* [PATCH] drm/i915: Align power domain names with port names
@ 2019-08-23 10:07 Imre Deak
2019-08-23 17:11 ` ✓ Fi.CI.BAT: success for drm/i915: Align power domain names with port names (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Imre Deak @ 2019-08-23 10:07 UTC (permalink / raw)
To: intel-gfx
There is a difference in BSpec's and the driver's designation of DDI
ports. BSpec uses the following names:
- before GEN11:
BSpec/driver:
port A/B/C/D etc
- GEN11:
BSpec/driver:
port A-F
- GEN12:
BSpec:
port A/B/C for combo PHY ports
port TC1-6 for Type C PHY ports
driver:
port A-I.
The driver's port D name matches BSpec's TC1 port name.
So far power domains were named according to the BSpec designation, to
make it easier to match the code against the specification. That however
can be confusing when a power domain needs to be matched to a port on
GEN12+. To resolve that use the driver's port A-I designation for power
domain names too and rename the corresponding power wells so that they
reflect the mapping from the driver's to BSpec's port name.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../drm/i915/display/intel_display_power.c | 361 +++++++++---------
.../drm/i915/display/intel_display_power.h | 40 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
4 files changed, 198 insertions(+), 216 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b51d1ceb8739..a3cba6efbf71 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6737,16 +6737,16 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
dig_port->tc_mode == TC_PORT_TBT_ALT) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
- return POWER_DOMAIN_AUX_TBT1;
+ return POWER_DOMAIN_AUX_C_TBT;
case AUX_CH_D:
- return POWER_DOMAIN_AUX_TBT2;
+ return POWER_DOMAIN_AUX_D_TBT;
case AUX_CH_E:
- return POWER_DOMAIN_AUX_TBT3;
+ return POWER_DOMAIN_AUX_E_TBT;
case AUX_CH_F:
- return POWER_DOMAIN_AUX_TBT4;
+ return POWER_DOMAIN_AUX_F_TBT;
default:
MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_TBT1;
+ return POWER_DOMAIN_AUX_C_TBT;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 12099760d99e..ce88a27229ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -24,11 +24,8 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(struct drm_i915_private *i915,
- enum intel_display_power_domain domain)
+intel_display_power_domain_str(enum intel_display_power_domain domain)
{
- bool ddi_tc_ports = IS_GEN(i915, 12);
-
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -71,23 +68,17 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
- POWER_DOMAIN_PORT_DDI_TC1_LANES);
- return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
+ return "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
- POWER_DOMAIN_PORT_DDI_TC2_LANES);
- return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
+ return "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
- POWER_DOMAIN_PORT_DDI_TC3_LANES);
- return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
- case POWER_DOMAIN_PORT_DDI_TC4_LANES:
- return "PORT_DDI_TC4_LANES";
- case POWER_DOMAIN_PORT_DDI_TC5_LANES:
- return "PORT_DDI_TC5_LANES";
- case POWER_DOMAIN_PORT_DDI_TC6_LANES:
- return "PORT_DDI_TC6_LANES";
+ return "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_G_LANES:
+ return "PORT_DDI_G_LANES";
+ case POWER_DOMAIN_PORT_DDI_H_LANES:
+ return "PORT_DDI_H_LANES";
+ case POWER_DOMAIN_PORT_DDI_I_LANES:
+ return "PORT_DDI_I_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -95,23 +86,17 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
- POWER_DOMAIN_PORT_DDI_TC1_IO);
- return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
+ return "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
- POWER_DOMAIN_PORT_DDI_TC2_IO);
- return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
+ return "PORT_DDI_E_IO";
case POWER_DOMAIN_PORT_DDI_F_IO:
- BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
- POWER_DOMAIN_PORT_DDI_TC3_IO);
- return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
- case POWER_DOMAIN_PORT_DDI_TC4_IO:
- return "PORT_DDI_TC4_IO";
- case POWER_DOMAIN_PORT_DDI_TC5_IO:
- return "PORT_DDI_TC5_IO";
- case POWER_DOMAIN_PORT_DDI_TC6_IO:
- return "PORT_DDI_TC6_IO";
+ return "PORT_DDI_F_IO";
+ case POWER_DOMAIN_PORT_DDI_G_IO:
+ return "PORT_DDI_G_IO";
+ case POWER_DOMAIN_PORT_DDI_H_IO:
+ return "PORT_DDI_H_IO";
+ case POWER_DOMAIN_PORT_DDI_I_IO:
+ return "PORT_DDI_I_IO";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -129,34 +114,33 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
case POWER_DOMAIN_AUX_C:
return "AUX_C";
case POWER_DOMAIN_AUX_D:
- BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
- return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
+ return "AUX_D";
case POWER_DOMAIN_AUX_E:
- BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
- return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
+ return "AUX_E";
case POWER_DOMAIN_AUX_F:
- BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
- return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
- case POWER_DOMAIN_AUX_TC4:
- return "AUX_TC4";
- case POWER_DOMAIN_AUX_TC5:
- return "AUX_TC5";
- case POWER_DOMAIN_AUX_TC6:
- return "AUX_TC6";
+ return "AUX_F";
+ case POWER_DOMAIN_AUX_G:
+ return "AUX_G";
+ case POWER_DOMAIN_AUX_H:
+ return "AUX_H";
+ case POWER_DOMAIN_AUX_I:
+ return "AUX_I";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_TBT1:
- return "AUX_TBT1";
- case POWER_DOMAIN_AUX_TBT2:
- return "AUX_TBT2";
- case POWER_DOMAIN_AUX_TBT3:
- return "AUX_TBT3";
- case POWER_DOMAIN_AUX_TBT4:
- return "AUX_TBT4";
- case POWER_DOMAIN_AUX_TBT5:
- return "AUX_TBT5";
- case POWER_DOMAIN_AUX_TBT6:
- return "AUX_TBT6";
+ case POWER_DOMAIN_AUX_C_TBT:
+ return "AUX_C_TBT";
+ case POWER_DOMAIN_AUX_D_TBT:
+ return "AUX_D_TBT";
+ case POWER_DOMAIN_AUX_E_TBT:
+ return "AUX_E_TBT";
+ case POWER_DOMAIN_AUX_F_TBT:
+ return "AUX_F_TBT";
+ case POWER_DOMAIN_AUX_G_TBT:
+ return "AUX_G_TBT";
+ case POWER_DOMAIN_AUX_H_TBT:
+ return "AUX_H_TBT";
+ case POWER_DOMAIN_AUX_I_TBT:
+ return "AUX_I_TBT";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1718,15 +1702,12 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
static void print_power_domains(struct i915_power_domains *power_domains,
const char *prefix, u64 mask)
{
- struct drm_i915_private *i915 =
- container_of(power_domains, struct drm_i915_private,
- power_domains);
enum intel_display_power_domain domain;
DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
for_each_power_domain(domain, mask)
DRM_DEBUG_DRIVER("%s use_count %d\n",
- intel_display_power_domain_str(i915, domain),
+ intel_display_power_domain_str(domain),
power_domains->domain_use_count[domain]);
}
@@ -1896,7 +1877,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
{
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
- const char *name = intel_display_power_domain_str(dev_priv, domain);
+ const char *name = intel_display_power_domain_str(domain);
power_domains = &dev_priv->power_domains;
@@ -2487,10 +2468,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_AUX_E) | \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2530,22 +2511,22 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_A))
#define ICL_AUX_B_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_B))
-#define ICL_AUX_C_IO_POWER_DOMAINS ( \
+#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_C))
-#define ICL_AUX_D_IO_POWER_DOMAINS ( \
+#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_D))
-#define ICL_AUX_E_IO_POWER_DOMAINS ( \
+#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_E))
-#define ICL_AUX_F_IO_POWER_DOMAINS ( \
+#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_F))
-#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1))
-#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2))
-#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3))
-#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
#define TGL_PW_5_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
@@ -2565,24 +2546,24 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2598,35 +2579,50 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
-#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
-#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
-#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
-#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
-#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
-
-#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC1))
-#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC2))
-#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC3))
-#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC4))
-#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC5))
-#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TC6))
-#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5))
-#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6))
+#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
+#define TGL_DDI_IO_E_TC2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
+#define TGL_DDI_IO_F_TC3_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
+#define TGL_DDI_IO_G_TC4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
+#define TGL_DDI_IO_H_TC5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
+#define TGL_DDI_IO_I_TC6_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
+
+#define TGL_AUX_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A))
+#define TGL_AUX_B_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_B))
+#define TGL_AUX_C_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C))
+#define TGL_AUX_D_TC1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D))
+#define TGL_AUX_E_TC2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_E))
+#define TGL_AUX_F_TC3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F))
+#define TGL_AUX_G_TC4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_G))
+#define TGL_AUX_H_TC5_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_H))
+#define TGL_AUX_I_TC6_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_I))
+#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
+#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
+#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
+#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
+#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
+#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
@@ -3484,8 +3480,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX C",
- .domains = ICL_AUX_C_IO_POWER_DOMAINS,
+ .name = "AUX C TC1",
+ .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3495,8 +3491,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX D",
- .domains = ICL_AUX_D_IO_POWER_DOMAINS,
+ .name = "AUX D TC2",
+ .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3506,8 +3502,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX E",
- .domains = ICL_AUX_E_IO_POWER_DOMAINS,
+ .name = "AUX E TC3",
+ .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3517,8 +3513,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX F",
- .domains = ICL_AUX_F_IO_POWER_DOMAINS,
+ .name = "AUX F TC4",
+ .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3528,8 +3524,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX TBT1",
- .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+ .name = "AUX C TBT1",
+ .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3539,8 +3535,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX TBT2",
- .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+ .name = "AUX D TBT2",
+ .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3550,8 +3546,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX TBT3",
- .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+ .name = "AUX E TBT3",
+ .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3561,8 +3557,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
},
{
- .name = "AUX TBT4",
- .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+ .name = "AUX F TBT4",
+ .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3667,8 +3663,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
},
{
- .name = "DDI TC1 IO",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .name = "DDI D TC1 IO",
+ .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3677,8 +3673,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DDI TC2 IO",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .name = "DDI E TC2 IO",
+ .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3687,8 +3683,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DDI TC3 IO",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .name = "DDI F TC3 IO",
+ .domains = TGL_DDI_IO_F_TC3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3697,8 +3693,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DDI TC4 IO",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .name = "DDI G TC4 IO",
+ .domains = TGL_DDI_IO_G_TC4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3707,8 +3703,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DDI TC5 IO",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .name = "DDI H TC5 IO",
+ .domains = TGL_DDI_IO_H_TC5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3717,8 +3713,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DDI TC6 IO",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .name = "DDI I TC6 IO",
+ .domains = TGL_DDI_IO_I_TC6_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3728,7 +3724,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
{
.name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3738,7 +3734,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
{
.name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3748,7 +3744,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
{
.name = "AUX C",
- .domains = ICL_AUX_C_IO_POWER_DOMAINS,
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3757,8 +3753,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC1",
- .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
+ .name = "AUX D TC1",
+ .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3768,8 +3764,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC2",
- .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
+ .name = "AUX E TC2",
+ .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3779,8 +3775,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC3",
- .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
+ .name = "AUX F TC3",
+ .domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3790,8 +3786,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC4",
- .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
+ .name = "AUX G TC4",
+ .domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3801,8 +3797,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC5",
- .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
+ .name = "AUX H TC5",
+ .domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3812,8 +3808,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TC6",
- .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
+ .name = "AUX I TC6",
+ .domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
.ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3823,8 +3819,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT1",
- .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+ .name = "AUX D TBT1",
+ .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3834,8 +3830,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT2",
- .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+ .name = "AUX E TBT2",
+ .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3845,8 +3841,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT3",
- .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+ .name = "AUX F TBT3",
+ .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3856,8 +3852,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT4",
- .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+ .name = "AUX G TBT4",
+ .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3867,8 +3863,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT5",
- .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
+ .name = "AUX H TBT5",
+ .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3878,8 +3874,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "AUX TBT6",
- .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
+ .name = "AUX I TBT6",
+ .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -5104,8 +5100,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
for_each_power_domain(domain, power_well->desc->domains)
DRM_DEBUG_DRIVER(" %-23s %d\n",
- intel_display_power_domain_str(i915,
- domain),
+ intel_display_power_domain_str(domain),
power_domains->domain_use_count[domain]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index a50605b8b1ad..737b5def7fc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -36,29 +36,20 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_B_LANES,
POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES,
- POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES,
- POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
POWER_DOMAIN_PORT_DDI_F_LANES,
- POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
- POWER_DOMAIN_PORT_DDI_TC4_LANES,
- POWER_DOMAIN_PORT_DDI_TC5_LANES,
- POWER_DOMAIN_PORT_DDI_TC6_LANES,
+ POWER_DOMAIN_PORT_DDI_G_LANES,
+ POWER_DOMAIN_PORT_DDI_H_LANES,
+ POWER_DOMAIN_PORT_DDI_I_LANES,
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO,
- POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO,
- POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
POWER_DOMAIN_PORT_DDI_F_IO,
- POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DDI_G_IO,
- POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
POWER_DOMAIN_PORT_DDI_H_IO,
- POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
POWER_DOMAIN_PORT_DDI_I_IO,
- POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -68,21 +59,19 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
- POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E,
- POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
- POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
- POWER_DOMAIN_AUX_TC4,
- POWER_DOMAIN_AUX_TC5,
- POWER_DOMAIN_AUX_TC6,
+ POWER_DOMAIN_AUX_G,
+ POWER_DOMAIN_AUX_H,
+ POWER_DOMAIN_AUX_I,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_TBT1,
- POWER_DOMAIN_AUX_TBT2,
- POWER_DOMAIN_AUX_TBT3,
- POWER_DOMAIN_AUX_TBT4,
- POWER_DOMAIN_AUX_TBT5,
- POWER_DOMAIN_AUX_TBT6,
+ POWER_DOMAIN_AUX_C_TBT,
+ POWER_DOMAIN_AUX_D_TBT,
+ POWER_DOMAIN_AUX_E_TBT,
+ POWER_DOMAIN_AUX_F_TBT,
+ POWER_DOMAIN_AUX_G_TBT,
+ POWER_DOMAIN_AUX_H_TBT,
+ POWER_DOMAIN_AUX_I_TBT,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
@@ -269,8 +258,7 @@ void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
const char *
-intel_display_power_domain_str(struct drm_i915_private *i915,
- enum intel_display_power_domain domain);
+intel_display_power_domain_str(enum intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b39226d7f8d2..67c63705a494 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2359,8 +2359,7 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
for_each_power_domain(power_domain, power_well->desc->domains)
seq_printf(m, " %-23s %d\n",
- intel_display_power_domain_str(dev_priv,
- power_domain),
+ intel_display_power_domain_str(power_domain),
power_domains->domain_use_count[power_domain]);
}
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Align power domain names with port names (rev2)
2019-08-23 10:07 [PATCH] drm/i915: Align power domain names with port names Imre Deak
@ 2019-08-23 17:11 ` Patchwork
2019-08-24 16:27 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-08-23 17:11 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Align power domain names with port names (rev2)
URL : https://patchwork.freedesktop.org/series/65682/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6777 -> Patchwork_14167
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/
Known issues
------------
Here are the changes found in Patchwork_14167 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-cml-u2/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/fi-cml-u2/igt@gem_close_race@basic-threads.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-blb-e6850/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
#### Possible fixes ####
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927] / [fdo#111381]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-hsw-4770r: [DMESG-WARN][9] ([fdo#107732]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 47)
------------------------------
Additional (2): fi-icl-u2 fi-gdg-551
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6777 -> Patchwork_14167
CI-20190529: 20190529
CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14167: 4df65a42a6b52d92c155cc52c5ac1dec1af5fde7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4df65a42a6b5 drm/i915: Align power domain names with port names
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Align power domain names with port names (rev2)
2019-08-23 10:07 [PATCH] drm/i915: Align power domain names with port names Imre Deak
2019-08-23 17:11 ` ✓ Fi.CI.BAT: success for drm/i915: Align power domain names with port names (rev2) Patchwork
@ 2019-08-24 16:27 ` Patchwork
2019-08-28 16:39 ` Imre Deak
2019-08-27 13:42 ` [PATCH] drm/i915: Align power domain names with port names Lisovskiy, Stanislav
2019-08-27 14:14 ` Lisovskiy, Stanislav
3 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2019-08-24 16:27 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Align power domain names with port names (rev2)
URL : https://patchwork.freedesktop.org/series/65682/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6777_full -> Patchwork_14167_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14167_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_exec_balancer@semaphore:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@gem_exec_balancer@semaphore.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl5/igt@gem_exec_balancer@semaphore.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@gem_tiled_swapping@non-threaded.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-skl: [PASS][9] -> [DMESG-WARN][10] ([fdo#106107])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl9/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +9 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@i915_suspend@fence-restore-tiled2untiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_flip@flip-vs-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl9/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713] / [fdo#110042])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#99912])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl2/igt@kms_setmode@basic.html
* igt@prime_busy@after-bsd2:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +19 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@prime_busy@after-bsd2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@prime_busy@after-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +11 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-apl: [INCOMPLETE][35] ([fdo#103927]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl3/igt@gem_exec_schedule@preempt-queue-contexts-render.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][37] ([fdo#111325]) -> [PASS][38] +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [SKIP][39] ([fdo#109271]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [INCOMPLETE][41] ([fdo#103540]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-iclb: [FAIL][43] ([fdo#103167]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [FAIL][45] ([fdo#103375]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-skl: [DMESG-WARN][49] ([fdo#106885]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl7/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_psr@psr2_basic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][53] ([fdo#99912]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl8/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl6/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][55] ([fdo#111329]) -> [SKIP][56] ([fdo#109276])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@gem_tiled_swapping@non-threaded:
- shard-skl: [FAIL][61] ([fdo#108686]) -> [SKIP][62] ([fdo#109271])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-skl: [FAIL][63] ([fdo#108040]) -> [FAIL][64] ([fdo#103167] / [fdo#110378])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: [FAIL][65] ([fdo#103167]) -> [FAIL][66] ([fdo#108040])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
[fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (8 -> 9)
------------------------------
Additional (1): pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6777 -> Patchwork_14167
CI-20190529: 20190529
CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14167: 4df65a42a6b52d92c155cc52c5ac1dec1af5fde7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Align power domain names with port names
2019-08-23 10:07 [PATCH] drm/i915: Align power domain names with port names Imre Deak
2019-08-23 17:11 ` ✓ Fi.CI.BAT: success for drm/i915: Align power domain names with port names (rev2) Patchwork
2019-08-24 16:27 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-27 13:42 ` Lisovskiy, Stanislav
2019-08-27 13:57 ` Imre Deak
2019-08-27 14:14 ` Lisovskiy, Stanislav
3 siblings, 1 reply; 7+ messages in thread
From: Lisovskiy, Stanislav @ 2019-08-27 13:42 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> There is a difference in BSpec's and the driver's designation of DDI
> ports. BSpec uses the following names:
> - before GEN11:
> BSpec/driver:
> port A/B/C/D etc
> - GEN11:
> BSpec/driver:
> port A-F
> - GEN12:
> BSpec:
> port A/B/C for combo PHY ports
> port TC1-6 for Type C PHY ports
> driver:
> port A-I.
> The driver's port D name matches BSpec's TC1 port name.
>
> So far power domains were named according to the BSpec designation,
> to
> make it easier to match the code against the specification. That
> however
> can be confusing when a power domain needs to be matched to a port on
> GEN12+. To resolve that use the driver's port A-I designation for
> power
> domain names too and rename the corresponding power wells so that
> they
> reflect the mapping from the driver's to BSpec's port name.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> .../drm/i915/display/intel_display_power.c | 361 +++++++++-------
> --
> .../drm/i915/display/intel_display_power.h | 40 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> 4 files changed, 198 insertions(+), 216 deletions(-)
For Tigerlake power domains we have this change:
+#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
+#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
+#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
+#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
+#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
+#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
and TGL_PW_5_POWER_DOMAINS:
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
For ICL_PW_3_POWER_DOMAINS:
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
However in intel_aux_power_domain:
- return POWER_DOMAIN_AUX_TBT1;
+ return POWER_DOMAIN_AUX_C_TBT;
case AUX_CH_D:
- return POWER_DOMAIN_AUX_TBT2;
+ return POWER_DOMAIN_AUX_D_TBT;
case AUX_CH_E:
- return POWER_DOMAIN_AUX_TBT3;
+ return POWER_DOMAIN_AUX_E_TBT;
case AUX_CH_F:
- return POWER_DOMAIN_AUX_TBT4;
+ return POWER_DOMAIN_AUX_F_TBT;
default:
MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_TBT1;
+ return POWER_DOMAIN_AUX_C_TBT;
While for Icelake power domains definition is still TBT1->AUX_C:
-#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1))
-#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2))
-#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3))
-#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
So does POWER_DOMAIN_AUX_TBT1 correspond now to POWER_DOMAIN_AUX_C_TBT
for ICL and POWER_DOMAIN_AUX_D_TBT for TGL?
Should we then change intel_aux_power_domain so that for Icl it returns
POWER_DOMAIN_AUX_C_TBT and POWER_DOMAIN_AUX_D_TBT for Tgl instead of
POWER_DOMAIN_AUX_TBT1?
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b51d1ceb8739..a3cba6efbf71 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6737,16 +6737,16 @@ intel_aux_power_domain(struct
> intel_digital_port *dig_port)
> dig_port->tc_mode == TC_PORT_TBT_ALT) {
> switch (dig_port->aux_ch) {
> case AUX_CH_C:
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> case AUX_CH_D:
> - return POWER_DOMAIN_AUX_TBT2;
> + return POWER_DOMAIN_AUX_D_TBT;
> case AUX_CH_E:
> - return POWER_DOMAIN_AUX_TBT3;
> + return POWER_DOMAIN_AUX_E_TBT;
> case AUX_CH_F:
> - return POWER_DOMAIN_AUX_TBT4;
> + return POWER_DOMAIN_AUX_F_TBT;
> default:
> MISSING_CASE(dig_port->aux_ch);
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12099760d99e..ce88a27229ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -24,11 +24,8 @@ bool intel_display_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
> enum i915_power_well_id
> power_well_id);
>
> const char *
> -intel_display_power_domain_str(struct drm_i915_private *i915,
> - enum intel_display_power_domain domain)
> +intel_display_power_domain_str(enum intel_display_power_domain
> domain)
> {
> - bool ddi_tc_ports = IS_GEN(i915, 12);
> -
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -71,23 +68,17 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC1_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
> "PORT_DDI_D_LANES";
> + return "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC2_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
> "PORT_DDI_E_LANES";
> + return "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC3_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
> "PORT_DDI_F_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> - return "PORT_DDI_TC4_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> - return "PORT_DDI_TC5_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> - return "PORT_DDI_TC6_LANES";
> + return "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_G_LANES:
> + return "PORT_DDI_G_LANES";
> + case POWER_DOMAIN_PORT_DDI_H_LANES:
> + return "PORT_DDI_H_LANES";
> + case POWER_DOMAIN_PORT_DDI_I_LANES:
> + return "PORT_DDI_I_LANES";
> case POWER_DOMAIN_PORT_DDI_A_IO:
> return "PORT_DDI_A_IO";
> case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -95,23 +86,17 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_PORT_DDI_C_IO:
> return "PORT_DDI_C_IO";
> case POWER_DOMAIN_PORT_DDI_D_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> - POWER_DOMAIN_PORT_DDI_TC1_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
> "PORT_DDI_D_IO";
> + return "PORT_DDI_D_IO";
> case POWER_DOMAIN_PORT_DDI_E_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> - POWER_DOMAIN_PORT_DDI_TC2_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
> "PORT_DDI_E_IO";
> + return "PORT_DDI_E_IO";
> case POWER_DOMAIN_PORT_DDI_F_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> - POWER_DOMAIN_PORT_DDI_TC3_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
> "PORT_DDI_F_IO";
> - case POWER_DOMAIN_PORT_DDI_TC4_IO:
> - return "PORT_DDI_TC4_IO";
> - case POWER_DOMAIN_PORT_DDI_TC5_IO:
> - return "PORT_DDI_TC5_IO";
> - case POWER_DOMAIN_PORT_DDI_TC6_IO:
> - return "PORT_DDI_TC6_IO";
> + return "PORT_DDI_F_IO";
> + case POWER_DOMAIN_PORT_DDI_G_IO:
> + return "PORT_DDI_G_IO";
> + case POWER_DOMAIN_PORT_DDI_H_IO:
> + return "PORT_DDI_H_IO";
> + case POWER_DOMAIN_PORT_DDI_I_IO:
> + return "PORT_DDI_I_IO";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> @@ -129,34 +114,33 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_AUX_C:
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
> POWER_DOMAIN_AUX_TC1);
> - return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> + return "AUX_D";
> case POWER_DOMAIN_AUX_E:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
> POWER_DOMAIN_AUX_TC2);
> - return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> + return "AUX_E";
> case POWER_DOMAIN_AUX_F:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
> POWER_DOMAIN_AUX_TC3);
> - return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> - case POWER_DOMAIN_AUX_TC4:
> - return "AUX_TC4";
> - case POWER_DOMAIN_AUX_TC5:
> - return "AUX_TC5";
> - case POWER_DOMAIN_AUX_TC6:
> - return "AUX_TC6";
> + return "AUX_F";
> + case POWER_DOMAIN_AUX_G:
> + return "AUX_G";
> + case POWER_DOMAIN_AUX_H:
> + return "AUX_H";
> + case POWER_DOMAIN_AUX_I:
> + return "AUX_I";
> case POWER_DOMAIN_AUX_IO_A:
> return "AUX_IO_A";
> - case POWER_DOMAIN_AUX_TBT1:
> - return "AUX_TBT1";
> - case POWER_DOMAIN_AUX_TBT2:
> - return "AUX_TBT2";
> - case POWER_DOMAIN_AUX_TBT3:
> - return "AUX_TBT3";
> - case POWER_DOMAIN_AUX_TBT4:
> - return "AUX_TBT4";
> - case POWER_DOMAIN_AUX_TBT5:
> - return "AUX_TBT5";
> - case POWER_DOMAIN_AUX_TBT6:
> - return "AUX_TBT6";
> + case POWER_DOMAIN_AUX_C_TBT:
> + return "AUX_C_TBT";
> + case POWER_DOMAIN_AUX_D_TBT:
> + return "AUX_D_TBT";
> + case POWER_DOMAIN_AUX_E_TBT:
> + return "AUX_E_TBT";
> + case POWER_DOMAIN_AUX_F_TBT:
> + return "AUX_F_TBT";
> + case POWER_DOMAIN_AUX_G_TBT:
> + return "AUX_G_TBT";
> + case POWER_DOMAIN_AUX_H_TBT:
> + return "AUX_H_TBT";
> + case POWER_DOMAIN_AUX_I_TBT:
> + return "AUX_I_TBT";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> case POWER_DOMAIN_INIT:
> @@ -1718,15 +1702,12 @@ __async_put_domains_state_ok(struct
> i915_power_domains *power_domains)
> static void print_power_domains(struct i915_power_domains
> *power_domains,
> const char *prefix, u64 mask)
> {
> - struct drm_i915_private *i915 =
> - container_of(power_domains, struct drm_i915_private,
> - power_domains);
> enum intel_display_power_domain domain;
>
> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> for_each_power_domain(domain, mask)
> DRM_DEBUG_DRIVER("%s use_count %d\n",
> - intel_display_power_domain_str(i915,
> domain),
> + intel_display_power_domain_str(domain)
> ,
> power_domains-
> >domain_use_count[domain]);
> }
>
> @@ -1896,7 +1877,7 @@ __intel_display_power_put_domain(struct
> drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains;
> struct i915_power_well *power_well;
> - const char *name = intel_display_power_domain_str(dev_priv,
> domain);
> + const char *name = intel_display_power_domain_str(domain);
>
> power_domains = &dev_priv->power_domains;
>
> @@ -2487,10 +2468,10 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_AUX_E) | \
> BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2530,22 +2511,22 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_A))
> #define ICL_AUX_B_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_B))
> -#define ICL_AUX_C_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_C))
> -#define ICL_AUX_D_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D))
> -#define ICL_AUX_E_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_E))
> -#define ICL_AUX_F_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_F))
> -#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> -#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2))
> -#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> -#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
> +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
>
> #define TGL_PW_5_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> @@ -2565,24 +2546,24 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2598,35 +2579,50 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> -#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> -#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> -#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> -#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> -#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> -#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
> -
> -#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC1))
> -#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC2))
> -#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC3))
> -#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC4))
> -#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC5))
> -#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC6))
> -#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> -#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6))
> +#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> +#define TGL_DDI_IO_E_TC2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> +#define TGL_DDI_IO_F_TC3_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> +#define TGL_DDI_IO_G_TC4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
> +#define TGL_DDI_IO_H_TC5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
> +#define TGL_DDI_IO_I_TC6_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
> +
> +#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A))
> +#define TGL_AUX_B_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_B))
> +#define TGL_AUX_C_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C))
> +#define TGL_AUX_D_TC1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D))
> +#define TGL_AUX_E_TC2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E))
> +#define TGL_AUX_F_TC3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F))
> +#define TGL_AUX_G_TC4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_G))
> +#define TGL_AUX_H_TC5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_H))
> +#define TGL_AUX_I_TC6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_I))
> +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
> +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
> +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
>
> static const struct i915_power_well_ops
> i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -3484,8 +3480,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX C",
> - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .name = "AUX C TC1",
> + .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3495,8 +3491,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX D",
> - .domains = ICL_AUX_D_IO_POWER_DOMAINS,
> + .name = "AUX D TC2",
> + .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3506,8 +3502,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX E",
> - .domains = ICL_AUX_E_IO_POWER_DOMAINS,
> + .name = "AUX E TC3",
> + .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3517,8 +3513,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX F",
> - .domains = ICL_AUX_F_IO_POWER_DOMAINS,
> + .name = "AUX F TC4",
> + .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3528,8 +3524,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT1",
> - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .name = "AUX C TBT1",
> + .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3539,8 +3535,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT2",
> - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .name = "AUX D TBT2",
> + .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3550,8 +3546,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT3",
> - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .name = "AUX E TBT3",
> + .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3561,8 +3557,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT4",
> - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .name = "AUX F TBT4",
> + .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3667,8 +3663,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> }
> },
> {
> - .name = "DDI TC1 IO",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .name = "DDI D TC1 IO",
> + .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3677,8 +3673,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC2 IO",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .name = "DDI E TC2 IO",
> + .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3687,8 +3683,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC3 IO",
> - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .name = "DDI F TC3 IO",
> + .domains = TGL_DDI_IO_F_TC3_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3697,8 +3693,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC4 IO",
> - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .name = "DDI G TC4 IO",
> + .domains = TGL_DDI_IO_G_TC4_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3707,8 +3703,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC5 IO",
> - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .name = "DDI H TC5 IO",
> + .domains = TGL_DDI_IO_H_TC5_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3717,8 +3713,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC6 IO",
> - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .name = "DDI I TC6 IO",
> + .domains = TGL_DDI_IO_I_TC6_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3728,7 +3724,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3738,7 +3734,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3748,7 +3744,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX C",
> - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3757,8 +3753,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC1",
> - .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> + .name = "AUX D TC1",
> + .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3768,8 +3764,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC2",
> - .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> + .name = "AUX E TC2",
> + .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3779,8 +3775,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC3",
> - .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> + .name = "AUX F TC3",
> + .domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3790,8 +3786,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC4",
> - .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> + .name = "AUX G TC4",
> + .domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3801,8 +3797,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC5",
> - .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> + .name = "AUX H TC5",
> + .domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3812,8 +3808,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC6",
> - .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> + .name = "AUX I TC6",
> + .domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3823,8 +3819,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT1",
> - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .name = "AUX D TBT1",
> + .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3834,8 +3830,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT2",
> - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .name = "AUX E TBT2",
> + .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3845,8 +3841,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT3",
> - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .name = "AUX F TBT3",
> + .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3856,8 +3852,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT4",
> - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .name = "AUX G TBT4",
> + .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3867,8 +3863,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT5",
> - .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> + .name = "AUX H TBT5",
> + .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3878,8 +3874,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT6",
> - .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> + .name = "AUX I TBT6",
> + .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -5104,8 +5100,7 @@ static void
> intel_power_domains_dump_info(struct drm_i915_private *i915)
>
> for_each_power_domain(domain, power_well->desc-
> >domains)
> DRM_DEBUG_DRIVER(" %-23s %d\n",
> - intel_display_power_domain_str
> (i915,
> -
> domain),
> + intel_display_power_domain_str
> (domain),
> power_domains-
> >domain_use_count[domain]);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index a50605b8b1ad..737b5def7fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -36,29 +36,20 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_DDI_B_LANES,
> POWER_DOMAIN_PORT_DDI_C_LANES,
> POWER_DOMAIN_PORT_DDI_D_LANES,
> - POWER_DOMAIN_PORT_DDI_TC1_LANES =
> POWER_DOMAIN_PORT_DDI_D_LANES,
> POWER_DOMAIN_PORT_DDI_E_LANES,
> - POWER_DOMAIN_PORT_DDI_TC2_LANES =
> POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DDI_F_LANES,
> - POWER_DOMAIN_PORT_DDI_TC3_LANES =
> POWER_DOMAIN_PORT_DDI_F_LANES,
> - POWER_DOMAIN_PORT_DDI_TC4_LANES,
> - POWER_DOMAIN_PORT_DDI_TC5_LANES,
> - POWER_DOMAIN_PORT_DDI_TC6_LANES,
> + POWER_DOMAIN_PORT_DDI_G_LANES,
> + POWER_DOMAIN_PORT_DDI_H_LANES,
> + POWER_DOMAIN_PORT_DDI_I_LANES,
> POWER_DOMAIN_PORT_DDI_A_IO,
> POWER_DOMAIN_PORT_DDI_B_IO,
> POWER_DOMAIN_PORT_DDI_C_IO,
> POWER_DOMAIN_PORT_DDI_D_IO,
> - POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> POWER_DOMAIN_PORT_DDI_E_IO,
> - POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> POWER_DOMAIN_PORT_DDI_F_IO,
> - POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> POWER_DOMAIN_PORT_DDI_G_IO,
> - POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> POWER_DOMAIN_PORT_DDI_H_IO,
> - POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> POWER_DOMAIN_PORT_DDI_I_IO,
> - POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> @@ -68,21 +59,19 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> - POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_AUX_E,
> - POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> POWER_DOMAIN_AUX_F,
> - POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> - POWER_DOMAIN_AUX_TC4,
> - POWER_DOMAIN_AUX_TC5,
> - POWER_DOMAIN_AUX_TC6,
> + POWER_DOMAIN_AUX_G,
> + POWER_DOMAIN_AUX_H,
> + POWER_DOMAIN_AUX_I,
> POWER_DOMAIN_AUX_IO_A,
> - POWER_DOMAIN_AUX_TBT1,
> - POWER_DOMAIN_AUX_TBT2,
> - POWER_DOMAIN_AUX_TBT3,
> - POWER_DOMAIN_AUX_TBT4,
> - POWER_DOMAIN_AUX_TBT5,
> - POWER_DOMAIN_AUX_TBT6,
> + POWER_DOMAIN_AUX_C_TBT,
> + POWER_DOMAIN_AUX_D_TBT,
> + POWER_DOMAIN_AUX_E_TBT,
> + POWER_DOMAIN_AUX_F_TBT,
> + POWER_DOMAIN_AUX_G_TBT,
> + POWER_DOMAIN_AUX_H_TBT,
> + POWER_DOMAIN_AUX_I_TBT,
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> @@ -269,8 +258,7 @@ void intel_display_power_suspend(struct
> drm_i915_private *i915);
> void intel_display_power_resume(struct drm_i915_private *i915);
>
> const char *
> -intel_display_power_domain_str(struct drm_i915_private *i915,
> - enum intel_display_power_domain domain);
> +intel_display_power_domain_str(enum intel_display_power_domain
> domain);
>
> bool intel_display_power_is_enabled(struct drm_i915_private
> *dev_priv,
> enum intel_display_power_domain
> domain);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b39226d7f8d2..67c63705a494 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2359,8 +2359,7 @@ static int i915_power_domain_info(struct
> seq_file *m, void *unused)
>
> for_each_power_domain(power_domain, power_well->desc-
> >domains)
> seq_printf(m, " %-23s %d\n",
> - intel_display_power_domain_str(dev_pri
> v,
> - power_d
> omain),
> + intel_display_power_domain_str(power_d
> omain),
> power_domains-
> >domain_use_count[power_domain]);
> }
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Align power domain names with port names
2019-08-27 13:42 ` [PATCH] drm/i915: Align power domain names with port names Lisovskiy, Stanislav
@ 2019-08-27 13:57 ` Imre Deak
0 siblings, 0 replies; 7+ messages in thread
From: Imre Deak @ 2019-08-27 13:57 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Tue, Aug 27, 2019 at 04:42:12PM +0300, Lisovskiy, Stanislav wrote:
> On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> > There is a difference in BSpec's and the driver's designation of DDI
> > ports. BSpec uses the following names:
> > - before GEN11:
> > BSpec/driver:
> > port A/B/C/D etc
> > - GEN11:
> > BSpec/driver:
> > port A-F
> > - GEN12:
> > BSpec:
> > port A/B/C for combo PHY ports
> > port TC1-6 for Type C PHY ports
> > driver:
> > port A-I.
> > The driver's port D name matches BSpec's TC1 port name.
> >
> > So far power domains were named according to the BSpec designation,
> > to
> > make it easier to match the code against the specification. That
> > however
> > can be confusing when a power domain needs to be matched to a port on
> > GEN12+. To resolve that use the driver's port A-I designation for
> > power
> > domain names too and rename the corresponding power wells so that
> > they
> > reflect the mapping from the driver's to BSpec's port name.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > .../drm/i915/display/intel_display_power.c | 361 +++++++++-------
> > --
> > .../drm/i915/display/intel_display_power.h | 40 +-
> > drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> > 4 files changed, 198 insertions(+), 216 deletions(-)
>
>
>
> For Tigerlake power domains we have this change:
>
> +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
> +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
> +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
>
> and TGL_PW_5_POWER_DOMAINS:
>
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
>
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
>
> For ICL_PW_3_POWER_DOMAINS:
>
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
>
> However in intel_aux_power_domain:
>
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> case AUX_CH_D:
> - return POWER_DOMAIN_AUX_TBT2;
> + return POWER_DOMAIN_AUX_D_TBT;
> case AUX_CH_E:
> - return POWER_DOMAIN_AUX_TBT3;
> + return POWER_DOMAIN_AUX_E_TBT;
> case AUX_CH_F:
> - return POWER_DOMAIN_AUX_TBT4;
> + return POWER_DOMAIN_AUX_F_TBT;
> default:
> MISSING_CASE(dig_port->aux_ch);
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
>
> While for Icelake power domains definition is still TBT1->AUX_C:
>
> -#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> -#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2))
> -#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> -#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
> +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
>
> So does POWER_DOMAIN_AUX_TBT1 correspond now to POWER_DOMAIN_AUX_C_TBT
> for ICL and POWER_DOMAIN_AUX_D_TBT for TGL?
Both on ICL and TGL we need the AUX_x_TBT power domain for Port x.
> Should we then change intel_aux_power_domain so that for Icl it returns
> POWER_DOMAIN_AUX_C_TBT and POWER_DOMAIN_AUX_D_TBT for Tgl instead of
> POWER_DOMAIN_AUX_TBT1?
On ICL port C is the first TypeC port (where TBT) can be used and so we
should return the AUX_C_TBT power well for it.
On TGL port D is the first TypeC port and we should return the AUX_D_TBT
power well for it. On TGL we can't enable TBT on port C, so we could
actually add a WARN for that case to intel_aux_power_domain().
>
>
>
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index b51d1ceb8739..a3cba6efbf71 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6737,16 +6737,16 @@ intel_aux_power_domain(struct
> > intel_digital_port *dig_port)
> > dig_port->tc_mode == TC_PORT_TBT_ALT) {
> > switch (dig_port->aux_ch) {
> > case AUX_CH_C:
> > - return POWER_DOMAIN_AUX_TBT1;
> > + return POWER_DOMAIN_AUX_C_TBT;
> > case AUX_CH_D:
> > - return POWER_DOMAIN_AUX_TBT2;
> > + return POWER_DOMAIN_AUX_D_TBT;
> > case AUX_CH_E:
> > - return POWER_DOMAIN_AUX_TBT3;
> > + return POWER_DOMAIN_AUX_E_TBT;
> > case AUX_CH_F:
> > - return POWER_DOMAIN_AUX_TBT4;
> > + return POWER_DOMAIN_AUX_F_TBT;
> > default:
> > MISSING_CASE(dig_port->aux_ch);
> > - return POWER_DOMAIN_AUX_TBT1;
> > + return POWER_DOMAIN_AUX_C_TBT;
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 12099760d99e..ce88a27229ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -24,11 +24,8 @@ bool intel_display_power_well_is_enabled(struct
> > drm_i915_private *dev_priv,
> > enum i915_power_well_id
> > power_well_id);
> >
> > const char *
> > -intel_display_power_domain_str(struct drm_i915_private *i915,
> > - enum intel_display_power_domain domain)
> > +intel_display_power_domain_str(enum intel_display_power_domain
> > domain)
> > {
> > - bool ddi_tc_ports = IS_GEN(i915, 12);
> > -
> > switch (domain) {
> > case POWER_DOMAIN_DISPLAY_CORE:
> > return "DISPLAY_CORE";
> > @@ -71,23 +68,17 @@ intel_display_power_domain_str(struct
> > drm_i915_private *i915,
> > case POWER_DOMAIN_PORT_DDI_C_LANES:
> > return "PORT_DDI_C_LANES";
> > case POWER_DOMAIN_PORT_DDI_D_LANES:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> > - POWER_DOMAIN_PORT_DDI_TC1_LANES);
> > - return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
> > "PORT_DDI_D_LANES";
> > + return "PORT_DDI_D_LANES";
> > case POWER_DOMAIN_PORT_DDI_E_LANES:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> > - POWER_DOMAIN_PORT_DDI_TC2_LANES);
> > - return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
> > "PORT_DDI_E_LANES";
> > + return "PORT_DDI_E_LANES";
> > case POWER_DOMAIN_PORT_DDI_F_LANES:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> > - POWER_DOMAIN_PORT_DDI_TC3_LANES);
> > - return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
> > "PORT_DDI_F_LANES";
> > - case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> > - return "PORT_DDI_TC4_LANES";
> > - case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> > - return "PORT_DDI_TC5_LANES";
> > - case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> > - return "PORT_DDI_TC6_LANES";
> > + return "PORT_DDI_F_LANES";
> > + case POWER_DOMAIN_PORT_DDI_G_LANES:
> > + return "PORT_DDI_G_LANES";
> > + case POWER_DOMAIN_PORT_DDI_H_LANES:
> > + return "PORT_DDI_H_LANES";
> > + case POWER_DOMAIN_PORT_DDI_I_LANES:
> > + return "PORT_DDI_I_LANES";
> > case POWER_DOMAIN_PORT_DDI_A_IO:
> > return "PORT_DDI_A_IO";
> > case POWER_DOMAIN_PORT_DDI_B_IO:
> > @@ -95,23 +86,17 @@ intel_display_power_domain_str(struct
> > drm_i915_private *i915,
> > case POWER_DOMAIN_PORT_DDI_C_IO:
> > return "PORT_DDI_C_IO";
> > case POWER_DOMAIN_PORT_DDI_D_IO:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> > - POWER_DOMAIN_PORT_DDI_TC1_IO);
> > - return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
> > "PORT_DDI_D_IO";
> > + return "PORT_DDI_D_IO";
> > case POWER_DOMAIN_PORT_DDI_E_IO:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> > - POWER_DOMAIN_PORT_DDI_TC2_IO);
> > - return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
> > "PORT_DDI_E_IO";
> > + return "PORT_DDI_E_IO";
> > case POWER_DOMAIN_PORT_DDI_F_IO:
> > - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> > - POWER_DOMAIN_PORT_DDI_TC3_IO);
> > - return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
> > "PORT_DDI_F_IO";
> > - case POWER_DOMAIN_PORT_DDI_TC4_IO:
> > - return "PORT_DDI_TC4_IO";
> > - case POWER_DOMAIN_PORT_DDI_TC5_IO:
> > - return "PORT_DDI_TC5_IO";
> > - case POWER_DOMAIN_PORT_DDI_TC6_IO:
> > - return "PORT_DDI_TC6_IO";
> > + return "PORT_DDI_F_IO";
> > + case POWER_DOMAIN_PORT_DDI_G_IO:
> > + return "PORT_DDI_G_IO";
> > + case POWER_DOMAIN_PORT_DDI_H_IO:
> > + return "PORT_DDI_H_IO";
> > + case POWER_DOMAIN_PORT_DDI_I_IO:
> > + return "PORT_DDI_I_IO";
> > case POWER_DOMAIN_PORT_DSI:
> > return "PORT_DSI";
> > case POWER_DOMAIN_PORT_CRT:
> > @@ -129,34 +114,33 @@ intel_display_power_domain_str(struct
> > drm_i915_private *i915,
> > case POWER_DOMAIN_AUX_C:
> > return "AUX_C";
> > case POWER_DOMAIN_AUX_D:
> > - BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
> > POWER_DOMAIN_AUX_TC1);
> > - return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> > + return "AUX_D";
> > case POWER_DOMAIN_AUX_E:
> > - BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
> > POWER_DOMAIN_AUX_TC2);
> > - return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> > + return "AUX_E";
> > case POWER_DOMAIN_AUX_F:
> > - BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
> > POWER_DOMAIN_AUX_TC3);
> > - return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> > - case POWER_DOMAIN_AUX_TC4:
> > - return "AUX_TC4";
> > - case POWER_DOMAIN_AUX_TC5:
> > - return "AUX_TC5";
> > - case POWER_DOMAIN_AUX_TC6:
> > - return "AUX_TC6";
> > + return "AUX_F";
> > + case POWER_DOMAIN_AUX_G:
> > + return "AUX_G";
> > + case POWER_DOMAIN_AUX_H:
> > + return "AUX_H";
> > + case POWER_DOMAIN_AUX_I:
> > + return "AUX_I";
> > case POWER_DOMAIN_AUX_IO_A:
> > return "AUX_IO_A";
> > - case POWER_DOMAIN_AUX_TBT1:
> > - return "AUX_TBT1";
> > - case POWER_DOMAIN_AUX_TBT2:
> > - return "AUX_TBT2";
> > - case POWER_DOMAIN_AUX_TBT3:
> > - return "AUX_TBT3";
> > - case POWER_DOMAIN_AUX_TBT4:
> > - return "AUX_TBT4";
> > - case POWER_DOMAIN_AUX_TBT5:
> > - return "AUX_TBT5";
> > - case POWER_DOMAIN_AUX_TBT6:
> > - return "AUX_TBT6";
> > + case POWER_DOMAIN_AUX_C_TBT:
> > + return "AUX_C_TBT";
> > + case POWER_DOMAIN_AUX_D_TBT:
> > + return "AUX_D_TBT";
> > + case POWER_DOMAIN_AUX_E_TBT:
> > + return "AUX_E_TBT";
> > + case POWER_DOMAIN_AUX_F_TBT:
> > + return "AUX_F_TBT";
> > + case POWER_DOMAIN_AUX_G_TBT:
> > + return "AUX_G_TBT";
> > + case POWER_DOMAIN_AUX_H_TBT:
> > + return "AUX_H_TBT";
> > + case POWER_DOMAIN_AUX_I_TBT:
> > + return "AUX_I_TBT";
> > case POWER_DOMAIN_GMBUS:
> > return "GMBUS";
> > case POWER_DOMAIN_INIT:
> > @@ -1718,15 +1702,12 @@ __async_put_domains_state_ok(struct
> > i915_power_domains *power_domains)
> > static void print_power_domains(struct i915_power_domains
> > *power_domains,
> > const char *prefix, u64 mask)
> > {
> > - struct drm_i915_private *i915 =
> > - container_of(power_domains, struct drm_i915_private,
> > - power_domains);
> > enum intel_display_power_domain domain;
> >
> > DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> > for_each_power_domain(domain, mask)
> > DRM_DEBUG_DRIVER("%s use_count %d\n",
> > - intel_display_power_domain_str(i915,
> > domain),
> > + intel_display_power_domain_str(domain)
> > ,
> > power_domains-
> > >domain_use_count[domain]);
> > }
> >
> > @@ -1896,7 +1877,7 @@ __intel_display_power_put_domain(struct
> > drm_i915_private *dev_priv,
> > {
> > struct i915_power_domains *power_domains;
> > struct i915_power_well *power_well;
> > - const char *name = intel_display_power_domain_str(dev_priv,
> > domain);
> > + const char *name = intel_display_power_domain_str(domain);
> >
> > power_domains = &dev_priv->power_domains;
> >
> > @@ -2487,10 +2468,10 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > BIT_ULL(POWER_DOMAIN_AUX_E) | \
> > BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2530,22 +2511,22 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_A))
> > #define ICL_AUX_B_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_B))
> > -#define ICL_AUX_C_IO_POWER_DOMAINS ( \
> > +#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_C))
> > -#define ICL_AUX_D_IO_POWER_DOMAINS ( \
> > +#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_D))
> > -#define ICL_AUX_E_IO_POWER_DOMAINS ( \
> > +#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_E))
> > -#define ICL_AUX_F_IO_POWER_DOMAINS ( \
> > +#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_F))
> > -#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> > -#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2))
> > -#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> > -#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> > +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
> > +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> > +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> > +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> >
> > #define TGL_PW_5_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> > @@ -2565,24 +2546,24 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_G) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_H) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_I) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2598,35 +2579,50 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > -#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> > -#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> > -#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> > -#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> > -#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> > -#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
> > -
> > -#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC1))
> > -#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC2))
> > -#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC3))
> > -#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC4))
> > -#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC5))
> > -#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TC6))
> > -#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> > -#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
> > - BIT_ULL(POWER_DOMAIN_AUX_TBT6))
> > +#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> > +#define TGL_DDI_IO_E_TC2_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> > +#define TGL_DDI_IO_F_TC3_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> > +#define TGL_DDI_IO_G_TC4_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
> > +#define TGL_DDI_IO_H_TC5_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
> > +#define TGL_DDI_IO_I_TC6_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
> > +
> > +#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_A))
> > +#define TGL_AUX_B_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_B))
> > +#define TGL_AUX_C_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_C))
> > +#define TGL_AUX_D_TC1_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_D))
> > +#define TGL_AUX_E_TC2_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_E))
> > +#define TGL_AUX_F_TC3_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_F))
> > +#define TGL_AUX_G_TC4_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_G))
> > +#define TGL_AUX_H_TC5_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_H))
> > +#define TGL_AUX_I_TC6_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_I))
> > +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> > +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> > +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> > +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
> > +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
> > +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
> >
> > static const struct i915_power_well_ops
> > i9xx_always_on_power_well_ops = {
> > .sync_hw = i9xx_power_well_sync_hw_noop,
> > @@ -3484,8 +3480,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX C",
> > - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> > + .name = "AUX C TC1",
> > + .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3495,8 +3491,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX D",
> > - .domains = ICL_AUX_D_IO_POWER_DOMAINS,
> > + .name = "AUX D TC2",
> > + .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3506,8 +3502,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX E",
> > - .domains = ICL_AUX_E_IO_POWER_DOMAINS,
> > + .name = "AUX E TC3",
> > + .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3517,8 +3513,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX F",
> > - .domains = ICL_AUX_F_IO_POWER_DOMAINS,
> > + .name = "AUX F TC4",
> > + .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3528,8 +3524,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT1",
> > - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> > + .name = "AUX C TBT1",
> > + .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3539,8 +3535,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT2",
> > - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> > + .name = "AUX D TBT2",
> > + .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3550,8 +3546,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT3",
> > - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> > + .name = "AUX E TBT3",
> > + .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3561,8 +3557,8 @@ static const struct i915_power_well_desc
> > icl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT4",
> > - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> > + .name = "AUX F TBT4",
> > + .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3667,8 +3663,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > }
> > },
> > {
> > - .name = "DDI TC1 IO",
> > - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> > + .name = "DDI D TC1 IO",
> > + .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3677,8 +3673,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "DDI TC2 IO",
> > - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> > + .name = "DDI E TC2 IO",
> > + .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3687,8 +3683,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "DDI TC3 IO",
> > - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> > + .name = "DDI F TC3 IO",
> > + .domains = TGL_DDI_IO_F_TC3_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3697,8 +3693,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "DDI TC4 IO",
> > - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> > + .name = "DDI G TC4 IO",
> > + .domains = TGL_DDI_IO_G_TC4_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3707,8 +3703,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "DDI TC5 IO",
> > - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> > + .name = "DDI H TC5 IO",
> > + .domains = TGL_DDI_IO_H_TC5_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3717,8 +3713,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "DDI TC6 IO",
> > - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> > + .name = "DDI I TC6 IO",
> > + .domains = TGL_DDI_IO_I_TC6_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3728,7 +3724,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > {
> > .name = "AUX A",
> > - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> > .ops = &icl_combo_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3738,7 +3734,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > {
> > .name = "AUX B",
> > - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> > .ops = &icl_combo_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3748,7 +3744,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > {
> > .name = "AUX C",
> > - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> > + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> > .ops = &icl_combo_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3757,8 +3753,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC1",
> > - .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> > + .name = "AUX D TC1",
> > + .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3768,8 +3764,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC2",
> > - .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> > + .name = "AUX E TC2",
> > + .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3779,8 +3775,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC3",
> > - .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> > + .name = "AUX F TC3",
> > + .domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3790,8 +3786,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC4",
> > - .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> > + .name = "AUX G TC4",
> > + .domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3801,8 +3797,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC5",
> > - .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> > + .name = "AUX H TC5",
> > + .domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3812,8 +3808,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TC6",
> > - .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> > + .name = "AUX I TC6",
> > + .domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
> > .ops = &icl_tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3823,8 +3819,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT1",
> > - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> > + .name = "AUX D TBT1",
> > + .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3834,8 +3830,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT2",
> > - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> > + .name = "AUX E TBT2",
> > + .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3845,8 +3841,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT3",
> > - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> > + .name = "AUX F TBT3",
> > + .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3856,8 +3852,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT4",
> > - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> > + .name = "AUX G TBT4",
> > + .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3867,8 +3863,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT5",
> > - .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> > + .name = "AUX H TBT5",
> > + .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3878,8 +3874,8 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > },
> > },
> > {
> > - .name = "AUX TBT6",
> > - .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> > + .name = "AUX I TBT6",
> > + .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> > .ops = &hsw_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -5104,8 +5100,7 @@ static void
> > intel_power_domains_dump_info(struct drm_i915_private *i915)
> >
> > for_each_power_domain(domain, power_well->desc-
> > >domains)
> > DRM_DEBUG_DRIVER(" %-23s %d\n",
> > - intel_display_power_domain_str
> > (i915,
> > -
> > domain),
> > + intel_display_power_domain_str
> > (domain),
> > power_domains-
> > >domain_use_count[domain]);
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index a50605b8b1ad..737b5def7fc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -36,29 +36,20 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_PORT_DDI_B_LANES,
> > POWER_DOMAIN_PORT_DDI_C_LANES,
> > POWER_DOMAIN_PORT_DDI_D_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC1_LANES =
> > POWER_DOMAIN_PORT_DDI_D_LANES,
> > POWER_DOMAIN_PORT_DDI_E_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC2_LANES =
> > POWER_DOMAIN_PORT_DDI_E_LANES,
> > POWER_DOMAIN_PORT_DDI_F_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC3_LANES =
> > POWER_DOMAIN_PORT_DDI_F_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC4_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC5_LANES,
> > - POWER_DOMAIN_PORT_DDI_TC6_LANES,
> > + POWER_DOMAIN_PORT_DDI_G_LANES,
> > + POWER_DOMAIN_PORT_DDI_H_LANES,
> > + POWER_DOMAIN_PORT_DDI_I_LANES,
> > POWER_DOMAIN_PORT_DDI_A_IO,
> > POWER_DOMAIN_PORT_DDI_B_IO,
> > POWER_DOMAIN_PORT_DDI_C_IO,
> > POWER_DOMAIN_PORT_DDI_D_IO,
> > - POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> > POWER_DOMAIN_PORT_DDI_E_IO,
> > - POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> > POWER_DOMAIN_PORT_DDI_F_IO,
> > - POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> > POWER_DOMAIN_PORT_DDI_G_IO,
> > - POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> > POWER_DOMAIN_PORT_DDI_H_IO,
> > - POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> > POWER_DOMAIN_PORT_DDI_I_IO,
> > - POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> > POWER_DOMAIN_PORT_DSI,
> > POWER_DOMAIN_PORT_CRT,
> > POWER_DOMAIN_PORT_OTHER,
> > @@ -68,21 +59,19 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_AUX_B,
> > POWER_DOMAIN_AUX_C,
> > POWER_DOMAIN_AUX_D,
> > - POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> > POWER_DOMAIN_AUX_E,
> > - POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> > POWER_DOMAIN_AUX_F,
> > - POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> > - POWER_DOMAIN_AUX_TC4,
> > - POWER_DOMAIN_AUX_TC5,
> > - POWER_DOMAIN_AUX_TC6,
> > + POWER_DOMAIN_AUX_G,
> > + POWER_DOMAIN_AUX_H,
> > + POWER_DOMAIN_AUX_I,
> > POWER_DOMAIN_AUX_IO_A,
> > - POWER_DOMAIN_AUX_TBT1,
> > - POWER_DOMAIN_AUX_TBT2,
> > - POWER_DOMAIN_AUX_TBT3,
> > - POWER_DOMAIN_AUX_TBT4,
> > - POWER_DOMAIN_AUX_TBT5,
> > - POWER_DOMAIN_AUX_TBT6,
> > + POWER_DOMAIN_AUX_C_TBT,
> > + POWER_DOMAIN_AUX_D_TBT,
> > + POWER_DOMAIN_AUX_E_TBT,
> > + POWER_DOMAIN_AUX_F_TBT,
> > + POWER_DOMAIN_AUX_G_TBT,
> > + POWER_DOMAIN_AUX_H_TBT,
> > + POWER_DOMAIN_AUX_I_TBT,
> > POWER_DOMAIN_GMBUS,
> > POWER_DOMAIN_MODESET,
> > POWER_DOMAIN_GT_IRQ,
> > @@ -269,8 +258,7 @@ void intel_display_power_suspend(struct
> > drm_i915_private *i915);
> > void intel_display_power_resume(struct drm_i915_private *i915);
> >
> > const char *
> > -intel_display_power_domain_str(struct drm_i915_private *i915,
> > - enum intel_display_power_domain domain);
> > +intel_display_power_domain_str(enum intel_display_power_domain
> > domain);
> >
> > bool intel_display_power_is_enabled(struct drm_i915_private
> > *dev_priv,
> > enum intel_display_power_domain
> > domain);
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index b39226d7f8d2..67c63705a494 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2359,8 +2359,7 @@ static int i915_power_domain_info(struct
> > seq_file *m, void *unused)
> >
> > for_each_power_domain(power_domain, power_well->desc-
> > >domains)
> > seq_printf(m, " %-23s %d\n",
> > - intel_display_power_domain_str(dev_pri
> > v,
> > - power_d
> > omain),
> > + intel_display_power_domain_str(power_d
> > omain),
> > power_domains-
> > >domain_use_count[power_domain]);
> > }
> >
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Align power domain names with port names
2019-08-23 10:07 [PATCH] drm/i915: Align power domain names with port names Imre Deak
` (2 preceding siblings ...)
2019-08-27 13:42 ` [PATCH] drm/i915: Align power domain names with port names Lisovskiy, Stanislav
@ 2019-08-27 14:14 ` Lisovskiy, Stanislav
3 siblings, 0 replies; 7+ messages in thread
From: Lisovskiy, Stanislav @ 2019-08-27 14:14 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> There is a difference in BSpec's and the driver's designation of DDI
> ports. BSpec uses the following names:
> - before GEN11:
> BSpec/driver:
> port A/B/C/D etc
> - GEN11:
> BSpec/driver:
> port A-F
> - GEN12:
> BSpec:
> port A/B/C for combo PHY ports
> port TC1-6 for Type C PHY ports
> driver:
> port A-I.
> The driver's port D name matches BSpec's TC1 port name.
>
> So far power domains were named according to the BSpec designation,
> to
> make it easier to match the code against the specification. That
> however
> can be confusing when a power domain needs to be matched to a port on
> GEN12+. To resolve that use the driver's port A-I designation for
> power
> domain names too and rename the corresponding power wells so that
> they
> reflect the mapping from the driver's to BSpec's port name.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> .../drm/i915/display/intel_display_power.c | 361 +++++++++-------
> --
> .../drm/i915/display/intel_display_power.h | 40 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> 4 files changed, 198 insertions(+), 216 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b51d1ceb8739..a3cba6efbf71 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6737,16 +6737,16 @@ intel_aux_power_domain(struct
> intel_digital_port *dig_port)
> dig_port->tc_mode == TC_PORT_TBT_ALT) {
> switch (dig_port->aux_ch) {
> case AUX_CH_C:
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> case AUX_CH_D:
> - return POWER_DOMAIN_AUX_TBT2;
> + return POWER_DOMAIN_AUX_D_TBT;
> case AUX_CH_E:
> - return POWER_DOMAIN_AUX_TBT3;
> + return POWER_DOMAIN_AUX_E_TBT;
> case AUX_CH_F:
> - return POWER_DOMAIN_AUX_TBT4;
> + return POWER_DOMAIN_AUX_F_TBT;
> default:
> MISSING_CASE(dig_port->aux_ch);
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12099760d99e..ce88a27229ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -24,11 +24,8 @@ bool intel_display_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
> enum i915_power_well_id
> power_well_id);
>
> const char *
> -intel_display_power_domain_str(struct drm_i915_private *i915,
> - enum intel_display_power_domain domain)
> +intel_display_power_domain_str(enum intel_display_power_domain
> domain)
> {
> - bool ddi_tc_ports = IS_GEN(i915, 12);
> -
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -71,23 +68,17 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC1_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
> "PORT_DDI_D_LANES";
> + return "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC2_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
> "PORT_DDI_E_LANES";
> + return "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC3_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
> "PORT_DDI_F_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> - return "PORT_DDI_TC4_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> - return "PORT_DDI_TC5_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> - return "PORT_DDI_TC6_LANES";
> + return "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_G_LANES:
> + return "PORT_DDI_G_LANES";
> + case POWER_DOMAIN_PORT_DDI_H_LANES:
> + return "PORT_DDI_H_LANES";
> + case POWER_DOMAIN_PORT_DDI_I_LANES:
> + return "PORT_DDI_I_LANES";
> case POWER_DOMAIN_PORT_DDI_A_IO:
> return "PORT_DDI_A_IO";
> case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -95,23 +86,17 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_PORT_DDI_C_IO:
> return "PORT_DDI_C_IO";
> case POWER_DOMAIN_PORT_DDI_D_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> - POWER_DOMAIN_PORT_DDI_TC1_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
> "PORT_DDI_D_IO";
> + return "PORT_DDI_D_IO";
> case POWER_DOMAIN_PORT_DDI_E_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> - POWER_DOMAIN_PORT_DDI_TC2_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
> "PORT_DDI_E_IO";
> + return "PORT_DDI_E_IO";
> case POWER_DOMAIN_PORT_DDI_F_IO:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> - POWER_DOMAIN_PORT_DDI_TC3_IO);
> - return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
> "PORT_DDI_F_IO";
> - case POWER_DOMAIN_PORT_DDI_TC4_IO:
> - return "PORT_DDI_TC4_IO";
> - case POWER_DOMAIN_PORT_DDI_TC5_IO:
> - return "PORT_DDI_TC5_IO";
> - case POWER_DOMAIN_PORT_DDI_TC6_IO:
> - return "PORT_DDI_TC6_IO";
> + return "PORT_DDI_F_IO";
> + case POWER_DOMAIN_PORT_DDI_G_IO:
> + return "PORT_DDI_G_IO";
> + case POWER_DOMAIN_PORT_DDI_H_IO:
> + return "PORT_DDI_H_IO";
> + case POWER_DOMAIN_PORT_DDI_I_IO:
> + return "PORT_DDI_I_IO";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> @@ -129,34 +114,33 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_AUX_C:
> return "AUX_C";
> case POWER_DOMAIN_AUX_D:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
> POWER_DOMAIN_AUX_TC1);
> - return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> + return "AUX_D";
> case POWER_DOMAIN_AUX_E:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
> POWER_DOMAIN_AUX_TC2);
> - return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> + return "AUX_E";
> case POWER_DOMAIN_AUX_F:
> - BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
> POWER_DOMAIN_AUX_TC3);
> - return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> - case POWER_DOMAIN_AUX_TC4:
> - return "AUX_TC4";
> - case POWER_DOMAIN_AUX_TC5:
> - return "AUX_TC5";
> - case POWER_DOMAIN_AUX_TC6:
> - return "AUX_TC6";
> + return "AUX_F";
> + case POWER_DOMAIN_AUX_G:
> + return "AUX_G";
> + case POWER_DOMAIN_AUX_H:
> + return "AUX_H";
> + case POWER_DOMAIN_AUX_I:
> + return "AUX_I";
> case POWER_DOMAIN_AUX_IO_A:
> return "AUX_IO_A";
> - case POWER_DOMAIN_AUX_TBT1:
> - return "AUX_TBT1";
> - case POWER_DOMAIN_AUX_TBT2:
> - return "AUX_TBT2";
> - case POWER_DOMAIN_AUX_TBT3:
> - return "AUX_TBT3";
> - case POWER_DOMAIN_AUX_TBT4:
> - return "AUX_TBT4";
> - case POWER_DOMAIN_AUX_TBT5:
> - return "AUX_TBT5";
> - case POWER_DOMAIN_AUX_TBT6:
> - return "AUX_TBT6";
> + case POWER_DOMAIN_AUX_C_TBT:
> + return "AUX_C_TBT";
> + case POWER_DOMAIN_AUX_D_TBT:
> + return "AUX_D_TBT";
> + case POWER_DOMAIN_AUX_E_TBT:
> + return "AUX_E_TBT";
> + case POWER_DOMAIN_AUX_F_TBT:
> + return "AUX_F_TBT";
> + case POWER_DOMAIN_AUX_G_TBT:
> + return "AUX_G_TBT";
> + case POWER_DOMAIN_AUX_H_TBT:
> + return "AUX_H_TBT";
> + case POWER_DOMAIN_AUX_I_TBT:
> + return "AUX_I_TBT";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> case POWER_DOMAIN_INIT:
> @@ -1718,15 +1702,12 @@ __async_put_domains_state_ok(struct
> i915_power_domains *power_domains)
> static void print_power_domains(struct i915_power_domains
> *power_domains,
> const char *prefix, u64 mask)
> {
> - struct drm_i915_private *i915 =
> - container_of(power_domains, struct drm_i915_private,
> - power_domains);
> enum intel_display_power_domain domain;
>
> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> for_each_power_domain(domain, mask)
> DRM_DEBUG_DRIVER("%s use_count %d\n",
> - intel_display_power_domain_str(i915,
> domain),
> + intel_display_power_domain_str(domain)
> ,
> power_domains-
> >domain_use_count[domain]);
> }
>
> @@ -1896,7 +1877,7 @@ __intel_display_power_put_domain(struct
> drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains;
> struct i915_power_well *power_well;
> - const char *name = intel_display_power_domain_str(dev_priv,
> domain);
> + const char *name = intel_display_power_domain_str(domain);
>
> power_domains = &dev_priv->power_domains;
>
> @@ -2487,10 +2468,10 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_AUX_E) | \
> BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2530,22 +2511,22 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_A))
> #define ICL_AUX_B_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_B))
> -#define ICL_AUX_C_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_C))
> -#define ICL_AUX_D_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_D))
> -#define ICL_AUX_E_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_E))
> -#define ICL_AUX_F_IO_POWER_DOMAINS ( \
> +#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_AUX_F))
> -#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1))
> -#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2))
> -#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3))
> -#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
> +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
>
> #define TGL_PW_5_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> @@ -2565,24 +2546,24 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2598,35 +2579,50 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> -#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> -#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> -#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> -#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> -#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> -#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
> -
> -#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC1))
> -#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC2))
> -#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC3))
> -#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC4))
> -#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC5))
> -#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TC6))
> -#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> -#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6))
> +#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> +#define TGL_DDI_IO_E_TC2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> +#define TGL_DDI_IO_F_TC3_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> +#define TGL_DDI_IO_G_TC4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
> +#define TGL_DDI_IO_H_TC5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
> +#define TGL_DDI_IO_I_TC6_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
> +
> +#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A))
> +#define TGL_AUX_B_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_B))
> +#define TGL_AUX_C_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C))
> +#define TGL_AUX_D_TC1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D))
> +#define TGL_AUX_E_TC2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E))
> +#define TGL_AUX_F_TC3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F))
> +#define TGL_AUX_G_TC4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_G))
> +#define TGL_AUX_H_TC5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_H))
> +#define TGL_AUX_I_TC6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_I))
> +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
> +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
> +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
>
> static const struct i915_power_well_ops
> i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -3484,8 +3480,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX C",
> - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .name = "AUX C TC1",
> + .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3495,8 +3491,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX D",
> - .domains = ICL_AUX_D_IO_POWER_DOMAINS,
> + .name = "AUX D TC2",
> + .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3506,8 +3502,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX E",
> - .domains = ICL_AUX_E_IO_POWER_DOMAINS,
> + .name = "AUX E TC3",
> + .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3517,8 +3513,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX F",
> - .domains = ICL_AUX_F_IO_POWER_DOMAINS,
> + .name = "AUX F TC4",
> + .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3528,8 +3524,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT1",
> - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .name = "AUX C TBT1",
> + .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3539,8 +3535,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT2",
> - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .name = "AUX D TBT2",
> + .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3550,8 +3546,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT3",
> - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .name = "AUX E TBT3",
> + .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3561,8 +3557,8 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT4",
> - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .name = "AUX F TBT4",
> + .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3667,8 +3663,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> }
> },
> {
> - .name = "DDI TC1 IO",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .name = "DDI D TC1 IO",
> + .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3677,8 +3673,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC2 IO",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .name = "DDI E TC2 IO",
> + .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3687,8 +3683,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC3 IO",
> - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .name = "DDI F TC3 IO",
> + .domains = TGL_DDI_IO_F_TC3_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3697,8 +3693,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC4 IO",
> - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .name = "DDI G TC4 IO",
> + .domains = TGL_DDI_IO_G_TC4_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3707,8 +3703,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC5 IO",
> - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .name = "DDI H TC5 IO",
> + .domains = TGL_DDI_IO_H_TC5_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3717,8 +3713,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "DDI TC6 IO",
> - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .name = "DDI I TC6 IO",
> + .domains = TGL_DDI_IO_I_TC6_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3728,7 +3724,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3738,7 +3734,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3748,7 +3744,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> {
> .name = "AUX C",
> - .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3757,8 +3753,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC1",
> - .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> + .name = "AUX D TC1",
> + .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3768,8 +3764,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC2",
> - .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> + .name = "AUX E TC2",
> + .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3779,8 +3775,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC3",
> - .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> + .name = "AUX F TC3",
> + .domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3790,8 +3786,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC4",
> - .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> + .name = "AUX G TC4",
> + .domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3801,8 +3797,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC5",
> - .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> + .name = "AUX H TC5",
> + .domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3812,8 +3808,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TC6",
> - .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> + .name = "AUX I TC6",
> + .domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
> .ops = &icl_tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3823,8 +3819,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT1",
> - .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> + .name = "AUX D TBT1",
> + .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3834,8 +3830,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT2",
> - .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> + .name = "AUX E TBT2",
> + .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3845,8 +3841,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT3",
> - .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> + .name = "AUX F TBT3",
> + .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3856,8 +3852,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT4",
> - .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> + .name = "AUX G TBT4",
> + .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3867,8 +3863,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT5",
> - .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> + .name = "AUX H TBT5",
> + .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -3878,8 +3874,8 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> },
> {
> - .name = "AUX TBT6",
> - .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> + .name = "AUX I TBT6",
> + .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> @@ -5104,8 +5100,7 @@ static void
> intel_power_domains_dump_info(struct drm_i915_private *i915)
>
> for_each_power_domain(domain, power_well->desc-
> >domains)
> DRM_DEBUG_DRIVER(" %-23s %d\n",
> - intel_display_power_domain_str
> (i915,
> -
> domain),
> + intel_display_power_domain_str
> (domain),
> power_domains-
> >domain_use_count[domain]);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index a50605b8b1ad..737b5def7fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -36,29 +36,20 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_DDI_B_LANES,
> POWER_DOMAIN_PORT_DDI_C_LANES,
> POWER_DOMAIN_PORT_DDI_D_LANES,
> - POWER_DOMAIN_PORT_DDI_TC1_LANES =
> POWER_DOMAIN_PORT_DDI_D_LANES,
> POWER_DOMAIN_PORT_DDI_E_LANES,
> - POWER_DOMAIN_PORT_DDI_TC2_LANES =
> POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DDI_F_LANES,
> - POWER_DOMAIN_PORT_DDI_TC3_LANES =
> POWER_DOMAIN_PORT_DDI_F_LANES,
> - POWER_DOMAIN_PORT_DDI_TC4_LANES,
> - POWER_DOMAIN_PORT_DDI_TC5_LANES,
> - POWER_DOMAIN_PORT_DDI_TC6_LANES,
> + POWER_DOMAIN_PORT_DDI_G_LANES,
> + POWER_DOMAIN_PORT_DDI_H_LANES,
> + POWER_DOMAIN_PORT_DDI_I_LANES,
> POWER_DOMAIN_PORT_DDI_A_IO,
> POWER_DOMAIN_PORT_DDI_B_IO,
> POWER_DOMAIN_PORT_DDI_C_IO,
> POWER_DOMAIN_PORT_DDI_D_IO,
> - POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> POWER_DOMAIN_PORT_DDI_E_IO,
> - POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> POWER_DOMAIN_PORT_DDI_F_IO,
> - POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> POWER_DOMAIN_PORT_DDI_G_IO,
> - POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> POWER_DOMAIN_PORT_DDI_H_IO,
> - POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> POWER_DOMAIN_PORT_DDI_I_IO,
> - POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> @@ -68,21 +59,19 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> - POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_AUX_E,
> - POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> POWER_DOMAIN_AUX_F,
> - POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> - POWER_DOMAIN_AUX_TC4,
> - POWER_DOMAIN_AUX_TC5,
> - POWER_DOMAIN_AUX_TC6,
> + POWER_DOMAIN_AUX_G,
> + POWER_DOMAIN_AUX_H,
> + POWER_DOMAIN_AUX_I,
> POWER_DOMAIN_AUX_IO_A,
> - POWER_DOMAIN_AUX_TBT1,
> - POWER_DOMAIN_AUX_TBT2,
> - POWER_DOMAIN_AUX_TBT3,
> - POWER_DOMAIN_AUX_TBT4,
> - POWER_DOMAIN_AUX_TBT5,
> - POWER_DOMAIN_AUX_TBT6,
> + POWER_DOMAIN_AUX_C_TBT,
> + POWER_DOMAIN_AUX_D_TBT,
> + POWER_DOMAIN_AUX_E_TBT,
> + POWER_DOMAIN_AUX_F_TBT,
> + POWER_DOMAIN_AUX_G_TBT,
> + POWER_DOMAIN_AUX_H_TBT,
> + POWER_DOMAIN_AUX_I_TBT,
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> @@ -269,8 +258,7 @@ void intel_display_power_suspend(struct
> drm_i915_private *i915);
> void intel_display_power_resume(struct drm_i915_private *i915);
>
> const char *
> -intel_display_power_domain_str(struct drm_i915_private *i915,
> - enum intel_display_power_domain domain);
> +intel_display_power_domain_str(enum intel_display_power_domain
> domain);
>
> bool intel_display_power_is_enabled(struct drm_i915_private
> *dev_priv,
> enum intel_display_power_domain
> domain);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b39226d7f8d2..67c63705a494 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2359,8 +2359,7 @@ static int i915_power_domain_info(struct
> seq_file *m, void *unused)
>
> for_each_power_domain(power_domain, power_well->desc-
> >domains)
> seq_printf(m, " %-23s %d\n",
> - intel_display_power_domain_str(dev_pri
> v,
> - power_d
> omain),
> + intel_display_power_domain_str(power_d
> omain),
> power_domains-
> >domain_use_count[power_domain]);
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915: Align power domain names with port names (rev2)
2019-08-24 16:27 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-28 16:39 ` Imre Deak
0 siblings, 0 replies; 7+ messages in thread
From: Imre Deak @ 2019-08-28 16:39 UTC (permalink / raw)
To: intel-gfx, Stanislav Lisovskiy
On Sat, Aug 24, 2019 at 04:27:14PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Align power domain names with port names (rev2)
> URL : https://patchwork.freedesktop.org/series/65682/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6777_full -> Patchwork_14167_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_14167_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@bcs0-s3:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_ctx_isolation@bcs0-s3.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@gem_ctx_isolation@bcs0-s3.html
>
> * igt@gem_exec_balancer@semaphore:
> - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@gem_exec_balancer@semaphore.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl5/igt@gem_exec_balancer@semaphore.html
>
> * igt@gem_exec_schedule@preempt-other-chain-bsd:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@gem_tiled_swapping@non-threaded.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
>
> * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
> - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([fdo#106107])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl9/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
>
> * igt@i915_suspend@fence-restore-tiled2untiled:
> - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +9 similar issues
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html
> - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@i915_suspend@fence-restore-tiled2untiled.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb7/igt@i915_suspend@fence-restore-tiled2untiled.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_flip@flip-vs-suspend.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl9/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
> - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar issues
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
> - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713] / [fdo#110042])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
>
> * igt@kms_psr@psr2_primary_page_flip:
> - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][27] -> [FAIL][28] ([fdo#99912])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@kms_setmode@basic.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl2/igt@kms_setmode@basic.html
>
> * igt@prime_busy@after-bsd2:
> - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +19 similar issues
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@prime_busy@after-bsd2.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@prime_busy@after-bsd2.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_isolation@rcs0-s3:
> - shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
>
> * igt@gem_exec_schedule@preempt-queue-bsd1:
> - shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +11 similar issues
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
>
> * igt@gem_exec_schedule@preempt-queue-contexts-render:
> - shard-apl: [INCOMPLETE][35] ([fdo#103927]) -> [PASS][36]
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-apl3/igt@gem_exec_schedule@preempt-queue-contexts-render.html
>
> * igt@gem_exec_schedule@wide-bsd:
> - shard-iclb: [SKIP][37] ([fdo#111325]) -> [PASS][38] +4 similar issues
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
>
> * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-snb: [SKIP][39] ([fdo#109271]) -> [PASS][40]
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
>
> * igt@kms_flip@2x-flip-vs-suspend:
> - shard-hsw: [INCOMPLETE][41] ([fdo#103540]) -> [PASS][42]
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
> - shard-iclb: [FAIL][43] ([fdo#103167]) -> [PASS][44]
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-kbl: [FAIL][45] ([fdo#103375]) -> [PASS][46]
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
> - shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48]
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
>
> * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
> - shard-skl: [DMESG-WARN][49] ([fdo#106885]) -> [PASS][50]
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl7/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
>
> * igt@kms_psr@psr2_basic:
> - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_psr@psr2_basic.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@kms_psr@psr2_basic.html
>
> * igt@kms_setmode@basic:
> - shard-skl: [FAIL][53] ([fdo#99912]) -> [PASS][54]
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl8/igt@kms_setmode@basic.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl6/igt@kms_setmode@basic.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [FAIL][55] ([fdo#111329]) -> [SKIP][56] ([fdo#109276])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@gem_mocs_settings@mocs-reset-bsd2:
> - shard-iclb: [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276]) +1 similar issue
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb6/igt@gem_mocs_settings@mocs-reset-bsd2.html
>
> * igt@gem_mocs_settings@mocs-settings-bsd2:
> - shard-iclb: [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-skl: [FAIL][61] ([fdo#108686]) -> [SKIP][62] ([fdo#109271])
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-rte:
> - shard-skl: [FAIL][63] ([fdo#108040]) -> [FAIL][64] ([fdo#103167] / [fdo#110378])
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
> - shard-skl: [FAIL][65] ([fdo#103167]) -> [FAIL][66] ([fdo#108040])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
>
>
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
> [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
> [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
> [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
> [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
> [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
> [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> Participating hosts (8 -> 9)
> ------------------------------
>
> Additional (1): pig-hsw-4770r
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6777 -> Patchwork_14167
>
> CI-20190529: 20190529
> CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14167: 4df65a42a6b52d92c155cc52c5ac1dec1af5fde7 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14167/
_______________________________________________
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-08-28 16:40 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-23 10:07 [PATCH] drm/i915: Align power domain names with port names Imre Deak
2019-08-23 17:11 ` ✓ Fi.CI.BAT: success for drm/i915: Align power domain names with port names (rev2) Patchwork
2019-08-24 16:27 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-28 16:39 ` Imre Deak
2019-08-27 13:42 ` [PATCH] drm/i915: Align power domain names with port names Lisovskiy, Stanislav
2019-08-27 13:57 ` Imre Deak
2019-08-27 14:14 ` Lisovskiy, Stanislav
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