* ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
@ 2019-08-25 22:40 ` Patchwork
2019-08-25 23:03 ` ✓ Fi.CI.BAT: success " Patchwork
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-08-25 22:40 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service
URL : https://patchwork.freedesktop.org/series/65769/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add sysfs interface to control class-of-service
+drivers/gpu/drm/i915/i915_sysfs.c:261:9: warning: symbol 'closctrl_show' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_sysfs.c:281:9: warning: symbol 'closctrl_store' was not declared. Should it be static?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service
@ 2019-08-25 22:48 Prathap Kumar Valsan
2019-08-25 22:40 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
` (8 more replies)
0 siblings, 9 replies; 17+ messages in thread
From: Prathap Kumar Valsan @ 2019-08-25 22:48 UTC (permalink / raw)
To: intel-gfx
To provide shared last-level-cache isolation to cpu workloads running
concurrently with gpu workloads, the gpu allocation of cache lines needs
to be restricted to certain ways. Currently GPU hardware supports four
class-of-service(CLOS) levels and there is an associated way-mask for
each CLOS.
Hardware supports reading supported way-mask configuration for GPU using
a bios pcode interface. The supported way-masks and the one currently
active is communicated to userspace via a sysfs file--closctrl. Admin user
can then select a new mask by writing the mask value to the file.
Note of Caution: Restricting cache ways using this mechanism presents a
larger attack surface for side-channel attacks.
Example usage:
The active way-mask is highlighted within square brackets.
> cat /sys/class/drm/card0/closctrl
[0xffff] 0xff00 0xc000 0x8000
CLOS0 is currently active.
> echo 0x8000 > /sys/class/drm/card0/closctrl
> cat /sys/class/drm/card0/closctrl
0xffff 0xff00 0xc000 [0x8000]
CLOS3 is currently active
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 57 ++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 8 ++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 67 ++++++++++++++++++++++++++++
5 files changed, 129 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 728704bbbe18..dd13e61944fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -26,6 +26,7 @@
#include "intel_gt.h"
#include "intel_mocs.h"
#include "intel_lrc.h"
+#include "intel_sideband.h"
/* structures required */
struct drm_i915_mocs_entry {
@@ -51,6 +52,7 @@ struct drm_i915_mocs_table {
#define LE_SCF(value) ((value) << 14)
#define LE_COS(value) ((value) << 15)
#define LE_SSE(value) ((value) << 17)
+#define LE_COS_MASK GENMASK(16, 15)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -408,10 +410,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
-static void intel_mocs_init_global(struct intel_gt *gt)
+void intel_mocs_init_global(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
+ unsigned int active_clos;
+ u32 value, unused_value;
unsigned int index;
GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
@@ -422,20 +427,31 @@ static void intel_mocs_init_global(struct intel_gt *gt)
if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
return;
- for (index = 0; index < table.size; index++)
+ active_clos = atomic_read(&i915->clos.active_clos);
+
+ for (index = 0; index < table.size; index++) {
+ value = table.table[index].control_value;
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
+
intel_uncore_write(uncore,
GEN12_GLOBAL_MOCS(index),
- table.table[index].control_value);
+ value);
+ }
/*
* Ok, now set the unused entries to the invalid entry (index 0). These
* entries are officially undefined and no contract for the contents and
* settings is given for these entries.
*/
+ unused_value = table.table[0].control_value;
+ unused_value &= ~LE_COS_MASK;
+ unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
+
for (; index < table.n_entries; index++)
intel_uncore_write(uncore,
GEN12_GLOBAL_MOCS(index),
- table.table[0].control_value);
+ unused_value);
}
static int emit_mocs_control_table(struct i915_request *rq,
@@ -625,10 +641,41 @@ int intel_mocs_emit(struct i915_request *rq)
return 0;
}
+static void intel_read_clos_way_mask(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct drm_i915_mocs_table table;
+ int ret, i;
+ u32 val;
+
+ if (!get_mocs_settings(gt, &table))
+ return;
+
+ /* COS is same for all entries */
+ atomic_set(&i915->clos.active_clos,
+ FIELD_GET(LE_COS_MASK, get_entry_control(&table, 0)));
+ for (i = 0; i < NUM_OF_CLOS; i++) {
+ val = i;
+ ret = sandybridge_pcode_read(i915,
+ ICL_PCODE_LLC_COS_WAY_MASK_INFO,
+ &val, NULL);
+ if (ret) {
+ DRM_ERROR("Mailbox read error = %d\n", ret);
+ return;
+ }
+
+ i915->clos.way_mask[i] = val;
+ }
+
+ i915->clos.support_way_mask_read = true;
+}
+
void intel_mocs_init(struct intel_gt *gt)
{
intel_mocs_init_l3cc_table(gt);
- if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) {
+ intel_read_clos_way_mask(gt);
intel_mocs_init_global(gt);
+ }
}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 2ae816b7ca19..e64e1b104753 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -53,6 +53,7 @@ struct i915_request;
struct intel_engine_cs;
struct intel_gt;
+void intel_mocs_init_global(struct intel_gt *gt);
void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b42651a387d9..0e250416c5a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1621,6 +1621,14 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ /* Last Level Cache Class of Service */
+ struct {
+ bool support_way_mask_read;
+ atomic_t active_clos;
+#define NUM_OF_CLOS 4
+ u16 way_mask[NUM_OF_CLOS];
+ } clos;
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..399acb7a36d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8845,6 +8845,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_LLC_COS_WAY_MASK_INFO 0x1d
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d8a3b180c084..6e61bab95a30 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -34,6 +34,7 @@
#include "i915_sysfs.h"
#include "intel_pm.h"
#include "intel_sideband.h"
+#include "gt/intel_mocs.h"
static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
@@ -257,6 +258,62 @@ static const struct bin_attribute dpf_attrs_1 = {
.private = (void *)1
};
+ssize_t closctrl_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ ssize_t len = 0;
+ int i;
+
+ for (i = 0; i < NUM_OF_CLOS; i++) {
+ if (i == atomic_read(&dev_priv->clos.active_clos))
+ len += snprintf(buf + len, PAGE_SIZE, "%s0x%x%s ",
+ "[", dev_priv->clos.way_mask[i], "]");
+ else
+ len += snprintf(buf + len, PAGE_SIZE, "0x%x ",
+ dev_priv->clos.way_mask[i]);
+ }
+ len += snprintf(buf + len, PAGE_SIZE, "\n");
+
+ return len;
+}
+
+ssize_t closctrl_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ u8 active_clos, clos_index;
+ bool valid_mask = false;
+ ssize_t ret;
+ u16 way_mask;
+
+ ret = kstrtou16(buf, 0, &way_mask);
+ if (ret)
+ return ret;
+
+ active_clos = atomic_read(&dev_priv->clos.active_clos);
+
+ if (dev_priv->clos.way_mask[active_clos] == way_mask)
+ return count;
+
+ for (clos_index = 0; clos_index < NUM_OF_CLOS; clos_index++) {
+ if (dev_priv->clos.way_mask[clos_index] == way_mask) {
+ atomic_set(&dev_priv->clos.active_clos, clos_index);
+ valid_mask = true;
+ break;
+ }
+ }
+
+ if (!valid_mask)
+ return -EINVAL;
+
+ intel_mocs_init_global(&dev_priv->gt);
+
+ return count;
+}
+static DEVICE_ATTR_RW(closctrl);
+
static ssize_t gt_act_freq_mhz_show(struct device *kdev,
struct device_attribute *attr, char *buf)
{
@@ -576,6 +633,13 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
struct device *kdev = dev_priv->drm.primary->kdev;
int ret;
+ if (dev_priv->clos.support_way_mask_read) {
+ ret = sysfs_create_file(&kdev->kobj,
+ &dev_attr_closctrl.attr);
+ if (ret)
+ DRM_ERROR("LLC COS sysfs setup failed\n");
+ }
+
#ifdef CONFIG_PM
if (HAS_RC6(dev_priv)) {
ret = sysfs_merge_group(&kdev->kobj,
@@ -626,6 +690,9 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_teardown_error_capture(kdev);
+ if (dev_priv->clos.support_way_mask_read)
+ sysfs_remove_file(&kdev->kobj, &dev_attr_closctrl.attr);
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
sysfs_remove_files(&kdev->kobj, vlv_attrs);
else
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
2019-08-25 22:40 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2019-08-25 23:03 ` Patchwork
2019-08-25 23:35 ` [PATCH v2] " Prathap Kumar Valsan
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-08-25 23:03 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service
URL : https://patchwork.freedesktop.org/series/65769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783 -> Patchwork_14184
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/
Known issues
------------
Here are the changes found in Patchwork_14184 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-fd-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u3/igt@gem_basic@create-fd-close.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-icl-u3/igt@gem_basic@create-fd-close.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][5] -> [FAIL][6] ([fdo#108511])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u2/igt@kms_chamelium@hdmi-edid-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-icl-u2/igt@kms_chamelium@hdmi-edid-read.html
#### Possible fixes ####
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u3/igt@i915_module_load@reload-no-display.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-icl-u3/igt@i915_module_load@reload-no-display.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#109483])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (55 -> 47)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6783 -> Patchwork_14184
CI-20190529: 20190529
CI_DRM_6783: c8d316e9005aee1ae6c9f2214da1c95d9c65fd5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5149: 6756ede680ee12745393360d7cc87cc0eb733ff6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14184: df15c2b68ab298b0c7ab479f9a6ad01086488e65 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
df15c2b68ab2 drm/i915/tgl: Add sysfs interface to control class-of-service
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
2019-08-25 22:40 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
2019-08-25 23:03 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-25 23:35 ` Prathap Kumar Valsan
2019-08-26 8:39 ` Chris Wilson
2019-08-26 9:17 ` Chris Wilson
2019-08-25 23:52 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
` (5 subsequent siblings)
8 siblings, 2 replies; 17+ messages in thread
From: Prathap Kumar Valsan @ 2019-08-25 23:35 UTC (permalink / raw)
To: intel-gfx
To provide shared last-level-cache isolation to cpu workloads running
concurrently with gpu workloads, the gpu allocation of cache lines needs
to be restricted to certain ways. Currently GPU hardware supports four
class-of-service(CLOS) levels and there is an associated way-mask for
each CLOS.
Hardware supports reading supported way-mask configuration for GPU using
a bios pcode interface. The supported way-masks and the one currently
active is communicated to userspace via a sysfs file--closctrl. Admin user
can then select a new mask by writing the mask value to the file.
Note of Caution: Restricting cache ways using this mechanism presents a
larger attack surface for side-channel attacks.
Example usage:
The active way-mask is highlighted within square brackets.
> cat /sys/class/drm/card0/closctrl
[0xffff] 0xff00 0xc000 0x8000
CLOS0 is currently active.
> echo 0x8000 > /sys/class/drm/card0/closctrl
> cat /sys/class/drm/card0/closctrl
0xffff 0xff00 0xc000 [0x8000]
CLOS3 is currently active
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
Changes in v2:
Declare closctrl_show and closctrl_store as static functions.
drivers/gpu/drm/i915/gt/intel_mocs.c | 57 ++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 8 ++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 67 ++++++++++++++++++++++++++++
5 files changed, 129 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 728704bbbe18..dd13e61944fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -26,6 +26,7 @@
#include "intel_gt.h"
#include "intel_mocs.h"
#include "intel_lrc.h"
+#include "intel_sideband.h"
/* structures required */
struct drm_i915_mocs_entry {
@@ -51,6 +52,7 @@ struct drm_i915_mocs_table {
#define LE_SCF(value) ((value) << 14)
#define LE_COS(value) ((value) << 15)
#define LE_SSE(value) ((value) << 17)
+#define LE_COS_MASK GENMASK(16, 15)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -408,10 +410,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
-static void intel_mocs_init_global(struct intel_gt *gt)
+void intel_mocs_init_global(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
+ unsigned int active_clos;
+ u32 value, unused_value;
unsigned int index;
GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
@@ -422,20 +427,31 @@ static void intel_mocs_init_global(struct intel_gt *gt)
if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
return;
- for (index = 0; index < table.size; index++)
+ active_clos = atomic_read(&i915->clos.active_clos);
+
+ for (index = 0; index < table.size; index++) {
+ value = table.table[index].control_value;
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
+
intel_uncore_write(uncore,
GEN12_GLOBAL_MOCS(index),
- table.table[index].control_value);
+ value);
+ }
/*
* Ok, now set the unused entries to the invalid entry (index 0). These
* entries are officially undefined and no contract for the contents and
* settings is given for these entries.
*/
+ unused_value = table.table[0].control_value;
+ unused_value &= ~LE_COS_MASK;
+ unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
+
for (; index < table.n_entries; index++)
intel_uncore_write(uncore,
GEN12_GLOBAL_MOCS(index),
- table.table[0].control_value);
+ unused_value);
}
static int emit_mocs_control_table(struct i915_request *rq,
@@ -625,10 +641,41 @@ int intel_mocs_emit(struct i915_request *rq)
return 0;
}
+static void intel_read_clos_way_mask(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct drm_i915_mocs_table table;
+ int ret, i;
+ u32 val;
+
+ if (!get_mocs_settings(gt, &table))
+ return;
+
+ /* COS is same for all entries */
+ atomic_set(&i915->clos.active_clos,
+ FIELD_GET(LE_COS_MASK, get_entry_control(&table, 0)));
+ for (i = 0; i < NUM_OF_CLOS; i++) {
+ val = i;
+ ret = sandybridge_pcode_read(i915,
+ ICL_PCODE_LLC_COS_WAY_MASK_INFO,
+ &val, NULL);
+ if (ret) {
+ DRM_ERROR("Mailbox read error = %d\n", ret);
+ return;
+ }
+
+ i915->clos.way_mask[i] = val;
+ }
+
+ i915->clos.support_way_mask_read = true;
+}
+
void intel_mocs_init(struct intel_gt *gt)
{
intel_mocs_init_l3cc_table(gt);
- if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) {
+ intel_read_clos_way_mask(gt);
intel_mocs_init_global(gt);
+ }
}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 2ae816b7ca19..e64e1b104753 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -53,6 +53,7 @@ struct i915_request;
struct intel_engine_cs;
struct intel_gt;
+void intel_mocs_init_global(struct intel_gt *gt);
void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b42651a387d9..0e250416c5a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1621,6 +1621,14 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ /* Last Level Cache Class of Service */
+ struct {
+ bool support_way_mask_read;
+ atomic_t active_clos;
+#define NUM_OF_CLOS 4
+ u16 way_mask[NUM_OF_CLOS];
+ } clos;
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..399acb7a36d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8845,6 +8845,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_LLC_COS_WAY_MASK_INFO 0x1d
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d8a3b180c084..b53143416396 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -34,6 +34,7 @@
#include "i915_sysfs.h"
#include "intel_pm.h"
#include "intel_sideband.h"
+#include "gt/intel_mocs.h"
static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
@@ -257,6 +258,62 @@ static const struct bin_attribute dpf_attrs_1 = {
.private = (void *)1
};
+static ssize_t closctrl_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ ssize_t len = 0;
+ int i;
+
+ for (i = 0; i < NUM_OF_CLOS; i++) {
+ if (i == atomic_read(&dev_priv->clos.active_clos))
+ len += snprintf(buf + len, PAGE_SIZE, "%s0x%x%s ",
+ "[", dev_priv->clos.way_mask[i], "]");
+ else
+ len += snprintf(buf + len, PAGE_SIZE, "0x%x ",
+ dev_priv->clos.way_mask[i]);
+ }
+ len += snprintf(buf + len, PAGE_SIZE, "\n");
+
+ return len;
+}
+
+static ssize_t closctrl_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ u8 active_clos, clos_index;
+ bool valid_mask = false;
+ ssize_t ret;
+ u16 way_mask;
+
+ ret = kstrtou16(buf, 0, &way_mask);
+ if (ret)
+ return ret;
+
+ active_clos = atomic_read(&dev_priv->clos.active_clos);
+
+ if (dev_priv->clos.way_mask[active_clos] == way_mask)
+ return count;
+
+ for (clos_index = 0; clos_index < NUM_OF_CLOS; clos_index++) {
+ if (dev_priv->clos.way_mask[clos_index] == way_mask) {
+ atomic_set(&dev_priv->clos.active_clos, clos_index);
+ valid_mask = true;
+ break;
+ }
+ }
+
+ if (!valid_mask)
+ return -EINVAL;
+
+ intel_mocs_init_global(&dev_priv->gt);
+
+ return count;
+}
+static DEVICE_ATTR_RW(closctrl);
+
static ssize_t gt_act_freq_mhz_show(struct device *kdev,
struct device_attribute *attr, char *buf)
{
@@ -576,6 +633,13 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
struct device *kdev = dev_priv->drm.primary->kdev;
int ret;
+ if (dev_priv->clos.support_way_mask_read) {
+ ret = sysfs_create_file(&kdev->kobj,
+ &dev_attr_closctrl.attr);
+ if (ret)
+ DRM_ERROR("LLC COS sysfs setup failed\n");
+ }
+
#ifdef CONFIG_PM
if (HAS_RC6(dev_priv)) {
ret = sysfs_merge_group(&kdev->kobj,
@@ -626,6 +690,9 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_teardown_error_capture(kdev);
+ if (dev_priv->clos.support_way_mask_read)
+ sysfs_remove_file(&kdev->kobj, &dev_attr_closctrl.attr);
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
sysfs_remove_files(&kdev->kobj, vlv_attrs);
else
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2)
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (2 preceding siblings ...)
2019-08-25 23:35 ` [PATCH v2] " Prathap Kumar Valsan
@ 2019-08-25 23:52 ` Patchwork
2019-08-26 7:32 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Add sysfs interface to control class-of-service Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-08-25 23:52 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service (rev2)
URL : https://patchwork.freedesktop.org/series/65769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783 -> Patchwork_14185
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/
Known issues
------------
Here are the changes found in Patchwork_14185 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-fd-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u3/igt@gem_basic@create-fd-close.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/fi-icl-u3/igt@gem_basic@create-fd-close.html
#### Possible fixes ####
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/fi-icl-u3/igt@i915_module_load@reload-no-display.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/fi-icl-u3/igt@i915_module_load@reload-no-display.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (55 -> 47)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6783 -> Patchwork_14185
CI-20190529: 20190529
CI_DRM_6783: c8d316e9005aee1ae6c9f2214da1c95d9c65fd5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5149: 6756ede680ee12745393360d7cc87cc0eb733ff6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14185: 29cf27989458eb569358786a96e4062f98f59cc9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
29cf27989458 drm/i915/tgl: Add sysfs interface to control class-of-service
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (3 preceding siblings ...)
2019-08-25 23:52 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
@ 2019-08-26 7:32 ` Patchwork
2019-08-26 8:32 ` ✓ Fi.CI.IGT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-08-26 7:32 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service
URL : https://patchwork.freedesktop.org/series/65769/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6783_full -> Patchwork_14184_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14184_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14184_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14184_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@busy-idle-no-semaphores-vecs0:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl1/igt@perf_pmu@busy-idle-no-semaphores-vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl6/igt@perf_pmu@busy-idle-no-semaphores-vecs0.html
Known issues
------------
Here are the changes found in Patchwork_14184_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@q-smoketest-render:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl1/igt@gem_ctx_shared@q-smoketest-render.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl2/igt@gem_ctx_shared@q-smoketest-render.html
* igt@gem_eio@reset-stress:
- shard-apl: [PASS][5] -> [FAIL][6] ([fdo#109661])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl1/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl2/igt@gem_eio@reset-stress.html
- shard-kbl: [PASS][7] -> [FAIL][8] ([fdo#109661])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-kbl3/igt@gem_eio@reset-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-kbl4/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb6/igt@gem_exec_schedule@preempt-self-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103184] / [fdo#103232])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane@plane-panning-top-left-pipe-b-planes:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103166])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl10/igt@kms_plane@plane-panning-top-left-pipe-b-planes.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl3/igt@kms_plane@plane-panning-top-left-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][29] -> [FAIL][30] ([fdo#99912])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl8/igt@kms_setmode@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl6/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109276]) +12 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][35] ([fdo#110841]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][37] ([fdo#111325]) -> [PASS][38] +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_exec_async@concurrent-writes-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][39] ([fdo#110854]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb5/igt@gem_exec_balancer@smoke.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@gem_exec_balancer@smoke.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [FAIL][41] ([fdo#108682]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl10/igt@kms_color@pipe-b-ctm-0-25.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl3/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][43] ([fdo#103540]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +5 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][49] ([fdo#103166]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-query-busy:
- shard-iclb: [INCOMPLETE][53] ([fdo#107713]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb7/igt@kms_vblank@pipe-b-query-busy.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb7/igt@kms_vblank@pipe-b-query-busy.html
* igt@prime_busy@after-bsd2:
- shard-iclb: [SKIP][55] ([fdo#109276]) -> [PASS][56] +11 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb5/igt@prime_busy@after-bsd2.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@prime_busy@after-bsd2.html
* igt@vgem_basic@dmabuf-mmap:
- shard-apl: [INCOMPLETE][57] ([fdo#103927]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl5/igt@vgem_basic@dmabuf-mmap.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-apl1/igt@vgem_basic@dmabuf-mmap.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][59] ([fdo#111330]) -> [SKIP][60] ([fdo#109276])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb6/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][61] ([fdo#109349]) -> [DMESG-WARN][62] ([fdo#107724])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack:
- shard-skl: [FAIL][63] ([fdo#103167]) -> [FAIL][64] ([fdo#108040])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6783 -> Patchwork_14184
CI-20190529: 20190529
CI_DRM_6783: c8d316e9005aee1ae6c9f2214da1c95d9c65fd5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5149: 6756ede680ee12745393360d7cc87cc0eb733ff6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14184: df15c2b68ab298b0c7ab479f9a6ad01086488e65 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14184/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2)
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (4 preceding siblings ...)
2019-08-26 7:32 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Add sysfs interface to control class-of-service Patchwork
@ 2019-08-26 8:32 ` Patchwork
2019-09-09 11:50 ` [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Joonas Lahtinen
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-08-26 8:32 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service (rev2)
URL : https://patchwork.freedesktop.org/series/65769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783_full -> Patchwork_14185_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14185_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@q-smoketest-render:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb1/igt@gem_ctx_shared@q-smoketest-render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb7/igt@gem_ctx_shared@q-smoketest-render.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +12 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb1/igt@gem_exec_schedule@preempt-queue-contexts-bsd.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl1/igt@i915_suspend@sysfs-reader.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
* igt@kms_fbcon_fbt@fbc:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([fdo#106107])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl2/igt@kms_fbcon_fbt@fbc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl8/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#99912])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl8/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-apl3/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#110728])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl1/igt@perf@blocking.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl2/igt@perf@blocking.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-apl5/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][33] ([fdo#110841]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][35] ([fdo#111325]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_exec_async@concurrent-writes-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb8/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [SKIP][37] ([fdo#109276]) -> [PASS][38] +17 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [FAIL][39] ([fdo#108682]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl10/igt@kms_color@pipe-b-ctm-0-25.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl7/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][41] ([fdo#103167]) -> [PASS][42] +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][43] ([fdo#108145] / [fdo#110403]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][45] ([fdo#103166]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][47] ([fdo#109642] / [fdo#111068]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb6/igt@kms_psr2_su@page_flip.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][51] ([fdo#99912]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-hsw5/igt@kms_setmode@basic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-hsw1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-query-busy:
- shard-iclb: [INCOMPLETE][53] ([fdo#107713]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb7/igt@kms_vblank@pipe-b-query-busy.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb5/igt@kms_vblank@pipe-b-query-busy.html
* igt@vgem_basic@dmabuf-mmap:
- shard-apl: [INCOMPLETE][55] ([fdo#103927]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-apl5/igt@vgem_basic@dmabuf-mmap.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-apl3/igt@vgem_basic@dmabuf-mmap.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
- shard-skl: [FAIL][59] ([fdo#108040]) -> [FAIL][60] ([fdo#103167])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6783/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6783 -> Patchwork_14185
CI-20190529: 20190529
CI_DRM_6783: c8d316e9005aee1ae6c9f2214da1c95d9c65fd5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5149: 6756ede680ee12745393360d7cc87cc0eb733ff6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14185: 29cf27989458eb569358786a96e4062f98f59cc9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14185/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 23:35 ` [PATCH v2] " Prathap Kumar Valsan
@ 2019-08-26 8:39 ` Chris Wilson
2019-08-27 14:17 ` Kumar Valsan, Prathap
2019-08-26 9:17 ` Chris Wilson
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2019-08-26 8:39 UTC (permalink / raw)
To: Prathap Kumar Valsan, intel-gfx
Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> To provide shared last-level-cache isolation to cpu workloads running
> concurrently with gpu workloads, the gpu allocation of cache lines needs
> to be restricted to certain ways. Currently GPU hardware supports four
> class-of-service(CLOS) levels and there is an associated way-mask for
> each CLOS.
>
> Hardware supports reading supported way-mask configuration for GPU using
> a bios pcode interface. The supported way-masks and the one currently
> active is communicated to userspace via a sysfs file--closctrl. Admin user
> can then select a new mask by writing the mask value to the file.
>
> Note of Caution: Restricting cache ways using this mechanism presents a
> larger attack surface for side-channel attacks.
>
> Example usage:
> The active way-mask is highlighted within square brackets.
> > cat /sys/class/drm/card0/closctrl
> [0xffff] 0xff00 0xc000 0x8000
>
> CLOS0 is currently active.
>
> > echo 0x8000 > /sys/class/drm/card0/closctrl
> > cat /sys/class/drm/card0/closctrl
> 0xffff 0xff00 0xc000 [0x8000]
>
> CLOS3 is currently active
>
> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> ---
> Changes in v2:
> Declare closctrl_show and closctrl_store as static functions.
> drivers/gpu/drm/i915/gt/intel_mocs.c | 57 ++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 8 ++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/i915_sysfs.c | 67 ++++++++++++++++++++++++++++
> 5 files changed, 129 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 728704bbbe18..dd13e61944fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -26,6 +26,7 @@
> #include "intel_gt.h"
> #include "intel_mocs.h"
> #include "intel_lrc.h"
> +#include "intel_sideband.h"
>
> /* structures required */
> struct drm_i915_mocs_entry {
> @@ -51,6 +52,7 @@ struct drm_i915_mocs_table {
> #define LE_SCF(value) ((value) << 14)
> #define LE_COS(value) ((value) << 15)
> #define LE_SSE(value) ((value) << 17)
> +#define LE_COS_MASK GENMASK(16, 15)
>
> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> #define L3_ESC(value) ((value) << 0)
> @@ -408,10 +410,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
> unused_value);
> }
>
> -static void intel_mocs_init_global(struct intel_gt *gt)
> +void intel_mocs_init_global(struct intel_gt *gt)
> {
> + struct drm_i915_private *i915 = gt->i915;
> struct intel_uncore *uncore = gt->uncore;
> struct drm_i915_mocs_table table;
> + unsigned int active_clos;
> + u32 value, unused_value;
> unsigned int index;
>
> GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
> @@ -422,20 +427,31 @@ static void intel_mocs_init_global(struct intel_gt *gt)
> if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> return;
>
> - for (index = 0; index < table.size; index++)
> + active_clos = atomic_read(&i915->clos.active_clos);
> +
> + for (index = 0; index < table.size; index++) {
> + value = table.table[index].control_value;
> + value &= ~LE_COS_MASK;
> + value |= FIELD_PREP(LE_COS_MASK, active_clos);
> +
> intel_uncore_write(uncore,
> GEN12_GLOBAL_MOCS(index),
> - table.table[index].control_value);
> + value);
> + }
>
> /*
> * Ok, now set the unused entries to the invalid entry (index 0). These
> * entries are officially undefined and no contract for the contents and
> * settings is given for these entries.
> */
> + unused_value = table.table[0].control_value;
> + unused_value &= ~LE_COS_MASK;
> + unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
> +
> for (; index < table.n_entries; index++)
> intel_uncore_write(uncore,
> GEN12_GLOBAL_MOCS(index),
> - table.table[0].control_value);
> + unused_value);
> }
>
> static int emit_mocs_control_table(struct i915_request *rq,
> @@ -625,10 +641,41 @@ int intel_mocs_emit(struct i915_request *rq)
> return 0;
> }
>
> +static void intel_read_clos_way_mask(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct drm_i915_mocs_table table;
> + int ret, i;
> + u32 val;
> +
> + if (!get_mocs_settings(gt, &table))
> + return;
> +
> + /* COS is same for all entries */
> + atomic_set(&i915->clos.active_clos,
> + FIELD_GET(LE_COS_MASK, get_entry_control(&table, 0)));
> + for (i = 0; i < NUM_OF_CLOS; i++) {
> + val = i;
> + ret = sandybridge_pcode_read(i915,
> + ICL_PCODE_LLC_COS_WAY_MASK_INFO,
> + &val, NULL);
> + if (ret) {
> + DRM_ERROR("Mailbox read error = %d\n", ret);
> + return;
> + }
> +
> + i915->clos.way_mask[i] = val;
> + }
> +
> + i915->clos.support_way_mask_read = true;
> +}
> +
> void intel_mocs_init(struct intel_gt *gt)
> {
> intel_mocs_init_l3cc_table(gt);
>
> - if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) {
> + intel_read_clos_way_mask(gt);
> intel_mocs_init_global(gt);
> + }
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index 2ae816b7ca19..e64e1b104753 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -53,6 +53,7 @@ struct i915_request;
> struct intel_engine_cs;
> struct intel_gt;
>
> +void intel_mocs_init_global(struct intel_gt *gt);
> void intel_mocs_init(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b42651a387d9..0e250416c5a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1621,6 +1621,14 @@ struct drm_i915_private {
> bool distrust_bios_wm;
> } wm;
>
> + /* Last Level Cache Class of Service */
> + struct {
> + bool support_way_mask_read;
> + atomic_t active_clos;
> +#define NUM_OF_CLOS 4
> + u16 way_mask[NUM_OF_CLOS];
> + } clos;
> +
> struct dram_info {
> bool valid;
> bool is_16gb_dimm;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02e1ef10c47e..399acb7a36d8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8845,6 +8845,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> +#define ICL_PCODE_LLC_COS_WAY_MASK_INFO 0x1d
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index d8a3b180c084..b53143416396 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -34,6 +34,7 @@
> #include "i915_sysfs.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> +#include "gt/intel_mocs.h"
>
> static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
> {
> @@ -257,6 +258,62 @@ static const struct bin_attribute dpf_attrs_1 = {
> .private = (void *)1
> };
>
> +static ssize_t closctrl_show(struct device *kdev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> + ssize_t len = 0;
> + int i;
> +
> + for (i = 0; i < NUM_OF_CLOS; i++) {
> + if (i == atomic_read(&dev_priv->clos.active_clos))
Reading an atomic more than once is liable to give you different
answers.
> + len += snprintf(buf + len, PAGE_SIZE, "%s0x%x%s ",
> + "[", dev_priv->clos.way_mask[i], "]");
> + else
> + len += snprintf(buf + len, PAGE_SIZE, "0x%x ",
> + dev_priv->clos.way_mask[i]);
> + }
> + len += snprintf(buf + len, PAGE_SIZE, "\n");
> +
> + return len;
> +}
> +
> +static ssize_t closctrl_store(struct device *kdev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> + u8 active_clos, clos_index;
> + bool valid_mask = false;
> + ssize_t ret;
> + u16 way_mask;
> +
> + ret = kstrtou16(buf, 0, &way_mask);
> + if (ret)
> + return ret;
> +
> + active_clos = atomic_read(&dev_priv->clos.active_clos);
> +
> + if (dev_priv->clos.way_mask[active_clos] == way_mask)
> + return count;
> +
> + for (clos_index = 0; clos_index < NUM_OF_CLOS; clos_index++) {
> + if (dev_priv->clos.way_mask[clos_index] == way_mask) {
> + atomic_set(&dev_priv->clos.active_clos, clos_index);
> + valid_mask = true;
> + break;
> + }
> + }
How is this serialised against multiple users changing the setting?
This is not an atomic operation, atomic_t should have been a warning.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 23:35 ` [PATCH v2] " Prathap Kumar Valsan
2019-08-26 8:39 ` Chris Wilson
@ 2019-08-26 9:17 ` Chris Wilson
2019-08-27 14:17 ` Kumar Valsan, Prathap
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2019-08-26 9:17 UTC (permalink / raw)
To: Prathap Kumar Valsan, intel-gfx
Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> To provide shared last-level-cache isolation to cpu workloads running
> concurrently with gpu workloads, the gpu allocation of cache lines needs
> to be restricted to certain ways. Currently GPU hardware supports four
> class-of-service(CLOS) levels and there is an associated way-mask for
> each CLOS.
>
> Hardware supports reading supported way-mask configuration for GPU using
> a bios pcode interface. The supported way-masks and the one currently
> active is communicated to userspace via a sysfs file--closctrl. Admin user
> can then select a new mask by writing the mask value to the file.
What impact does this have on inflight work? Do you need to drain the
submission queue, change the global registers, force an invalidation and
then restart? Can it be done from inside the GPU so that it is
serialised with on-going submission?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-26 8:39 ` Chris Wilson
@ 2019-08-27 14:17 ` Kumar Valsan, Prathap
0 siblings, 0 replies; 17+ messages in thread
From: Kumar Valsan, Prathap @ 2019-08-27 14:17 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, Aug 26, 2019 at 09:39:48AM +0100, Chris Wilson wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain ways. Currently GPU hardware supports four
> > class-of-service(CLOS) levels and there is an associated way-mask for
> > each CLOS.
> >
> > Hardware supports reading supported way-mask configuration for GPU using
> > a bios pcode interface. The supported way-masks and the one currently
> > active is communicated to userspace via a sysfs file--closctrl. Admin user
> > can then select a new mask by writing the mask value to the file.
> >
> > Note of Caution: Restricting cache ways using this mechanism presents a
> > larger attack surface for side-channel attacks.
> >
> > Example usage:
> > The active way-mask is highlighted within square brackets.
> > > cat /sys/class/drm/card0/closctrl
> > [0xffff] 0xff00 0xc000 0x8000
> >
> > CLOS0 is currently active.
> >
> > > echo 0x8000 > /sys/class/drm/card0/closctrl
> > > cat /sys/class/drm/card0/closctrl
> > 0xffff 0xff00 0xc000 [0x8000]
> >
> > CLOS3 is currently active
> >
> > Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > ---
> > Changes in v2:
> > Declare closctrl_show and closctrl_store as static functions.
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 57 ++++++++++++++++++++---
> > drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 8 ++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/i915_sysfs.c | 67 ++++++++++++++++++++++++++++
> > 5 files changed, 129 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 728704bbbe18..dd13e61944fd 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -26,6 +26,7 @@
> > #include "intel_gt.h"
> > #include "intel_mocs.h"
> > #include "intel_lrc.h"
> > +#include "intel_sideband.h"
> >
> > /* structures required */
> > struct drm_i915_mocs_entry {
> > @@ -51,6 +52,7 @@ struct drm_i915_mocs_table {
> > #define LE_SCF(value) ((value) << 14)
> > #define LE_COS(value) ((value) << 15)
> > #define LE_SSE(value) ((value) << 17)
> > +#define LE_COS_MASK GENMASK(16, 15)
> >
> > /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> > #define L3_ESC(value) ((value) << 0)
> > @@ -408,10 +410,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
> > unused_value);
> > }
> >
> > -static void intel_mocs_init_global(struct intel_gt *gt)
> > +void intel_mocs_init_global(struct intel_gt *gt)
> > {
> > + struct drm_i915_private *i915 = gt->i915;
> > struct intel_uncore *uncore = gt->uncore;
> > struct drm_i915_mocs_table table;
> > + unsigned int active_clos;
> > + u32 value, unused_value;
> > unsigned int index;
> >
> > GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
> > @@ -422,20 +427,31 @@ static void intel_mocs_init_global(struct intel_gt *gt)
> > if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> > return;
> >
> > - for (index = 0; index < table.size; index++)
> > + active_clos = atomic_read(&i915->clos.active_clos);
> > +
> > + for (index = 0; index < table.size; index++) {
> > + value = table.table[index].control_value;
> > + value &= ~LE_COS_MASK;
> > + value |= FIELD_PREP(LE_COS_MASK, active_clos);
> > +
> > intel_uncore_write(uncore,
> > GEN12_GLOBAL_MOCS(index),
> > - table.table[index].control_value);
> > + value);
> > + }
> >
> > /*
> > * Ok, now set the unused entries to the invalid entry (index 0). These
> > * entries are officially undefined and no contract for the contents and
> > * settings is given for these entries.
> > */
> > + unused_value = table.table[0].control_value;
> > + unused_value &= ~LE_COS_MASK;
> > + unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
> > +
> > for (; index < table.n_entries; index++)
> > intel_uncore_write(uncore,
> > GEN12_GLOBAL_MOCS(index),
> > - table.table[0].control_value);
> > + unused_value);
> > }
> >
> > static int emit_mocs_control_table(struct i915_request *rq,
> > @@ -625,10 +641,41 @@ int intel_mocs_emit(struct i915_request *rq)
> > return 0;
> > }
> >
> > +static void intel_read_clos_way_mask(struct intel_gt *gt)
> > +{
> > + struct drm_i915_private *i915 = gt->i915;
> > + struct drm_i915_mocs_table table;
> > + int ret, i;
> > + u32 val;
> > +
> > + if (!get_mocs_settings(gt, &table))
> > + return;
> > +
> > + /* COS is same for all entries */
> > + atomic_set(&i915->clos.active_clos,
> > + FIELD_GET(LE_COS_MASK, get_entry_control(&table, 0)));
> > + for (i = 0; i < NUM_OF_CLOS; i++) {
> > + val = i;
> > + ret = sandybridge_pcode_read(i915,
> > + ICL_PCODE_LLC_COS_WAY_MASK_INFO,
> > + &val, NULL);
> > + if (ret) {
> > + DRM_ERROR("Mailbox read error = %d\n", ret);
> > + return;
> > + }
> > +
> > + i915->clos.way_mask[i] = val;
> > + }
> > +
> > + i915->clos.support_way_mask_read = true;
> > +}
> > +
> > void intel_mocs_init(struct intel_gt *gt)
> > {
> > intel_mocs_init_l3cc_table(gt);
> >
> > - if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> > + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) {
> > + intel_read_clos_way_mask(gt);
> > intel_mocs_init_global(gt);
> > + }
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> > index 2ae816b7ca19..e64e1b104753 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> > @@ -53,6 +53,7 @@ struct i915_request;
> > struct intel_engine_cs;
> > struct intel_gt;
> >
> > +void intel_mocs_init_global(struct intel_gt *gt);
> > void intel_mocs_init(struct intel_gt *gt);
> > void intel_mocs_init_engine(struct intel_engine_cs *engine);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b42651a387d9..0e250416c5a9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1621,6 +1621,14 @@ struct drm_i915_private {
> > bool distrust_bios_wm;
> > } wm;
> >
> > + /* Last Level Cache Class of Service */
> > + struct {
> > + bool support_way_mask_read;
> > + atomic_t active_clos;
> > +#define NUM_OF_CLOS 4
> > + u16 way_mask[NUM_OF_CLOS];
> > + } clos;
> > +
> > struct dram_info {
> > bool valid;
> > bool is_16gb_dimm;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 02e1ef10c47e..399acb7a36d8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8845,6 +8845,7 @@ enum {
> > #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> > #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> > #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> > +#define ICL_PCODE_LLC_COS_WAY_MASK_INFO 0x1d
> > #define GEN6_PCODE_READ_D_COMP 0x10
> > #define GEN6_PCODE_WRITE_D_COMP 0x11
> > #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> > index d8a3b180c084..b53143416396 100644
> > --- a/drivers/gpu/drm/i915/i915_sysfs.c
> > +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > @@ -34,6 +34,7 @@
> > #include "i915_sysfs.h"
> > #include "intel_pm.h"
> > #include "intel_sideband.h"
> > +#include "gt/intel_mocs.h"
> >
> > static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
> > {
> > @@ -257,6 +258,62 @@ static const struct bin_attribute dpf_attrs_1 = {
> > .private = (void *)1
> > };
> >
> > +static ssize_t closctrl_show(struct device *kdev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> > + ssize_t len = 0;
> > + int i;
> > +
> > + for (i = 0; i < NUM_OF_CLOS; i++) {
> > + if (i == atomic_read(&dev_priv->clos.active_clos))
>
> Reading an atomic more than once is liable to give you different
> answers.
>
> > + len += snprintf(buf + len, PAGE_SIZE, "%s0x%x%s ",
> > + "[", dev_priv->clos.way_mask[i], "]");
> > + else
> > + len += snprintf(buf + len, PAGE_SIZE, "0x%x ",
> > + dev_priv->clos.way_mask[i]);
> > + }
> > + len += snprintf(buf + len, PAGE_SIZE, "\n");
> > +
> > + return len;
> > +}
> > +
> > +static ssize_t closctrl_store(struct device *kdev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t count)
> > +{
> > + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> > + u8 active_clos, clos_index;
> > + bool valid_mask = false;
> > + ssize_t ret;
> > + u16 way_mask;
> > +
> > + ret = kstrtou16(buf, 0, &way_mask);
> > + if (ret)
> > + return ret;
> > +
> > + active_clos = atomic_read(&dev_priv->clos.active_clos);
> > +
> > + if (dev_priv->clos.way_mask[active_clos] == way_mask)
> > + return count;
> > +
> > + for (clos_index = 0; clos_index < NUM_OF_CLOS; clos_index++) {
> > + if (dev_priv->clos.way_mask[clos_index] == way_mask) {
> > + atomic_set(&dev_priv->clos.active_clos, clos_index);
> > + valid_mask = true;
> > + break;
> > + }
> > + }
>
> How is this serialised against multiple users changing the setting?
>
Should have been using mutex to serialize. Will fix.
> This is not an atomic operation, atomic_t should have been a warning.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-26 9:17 ` Chris Wilson
@ 2019-08-27 14:17 ` Kumar Valsan, Prathap
2019-08-27 14:35 ` Chris Wilson
0 siblings, 1 reply; 17+ messages in thread
From: Kumar Valsan, Prathap @ 2019-08-27 14:17 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, Aug 26, 2019 at 10:17:55AM +0100, Chris Wilson wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain ways. Currently GPU hardware supports four
> > class-of-service(CLOS) levels and there is an associated way-mask for
> > each CLOS.
> >
> > Hardware supports reading supported way-mask configuration for GPU using
> > a bios pcode interface. The supported way-masks and the one currently
> > active is communicated to userspace via a sysfs file--closctrl. Admin user
> > can then select a new mask by writing the mask value to the file.
>
> What impact does this have on inflight work? Do you need to drain the
> submission queue, change the global registers, force an invalidation and
> then restart? Can it be done from inside the GPU so that it is
> serialised with on-going submission?
I believe this should not be impacting the inflight work. Because, way mask
only influnece a new cache allocation on cache miss. Cache hits are not
restricted by way-mask. So even the way-mask is changed, in-flight
requests previously allocated cache lines from other ways will still be
a cache hit until thrashed.
We want to support this on Gen11 as well, where these registers
are context saved and restored and we prime the register values of new contexts
from recorded defaults. What could be the correct way to handle this, write to the
default object or should ask GPU to re-record after modifying the
registers.
Thanks,
Prathap
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-27 14:17 ` Kumar Valsan, Prathap
@ 2019-08-27 14:35 ` Chris Wilson
2019-08-27 14:59 ` Kumar Valsan, Prathap
0 siblings, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2019-08-27 14:35 UTC (permalink / raw)
To: Kumar Valsan, Prathap; +Cc: intel-gfx
Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51)
> We want to support this on Gen11 as well, where these registers
> are context saved and restored and we prime the register values of new contexts
> from recorded defaults. What could be the correct way to handle this, write to the
> default object or should ask GPU to re-record after modifying the
> registers.
That depends on whether you want to apply to existing or only to new.
For OA / sseu, we modify the context images so that existing contexts
are updated to reflect the new defaults, and we update the defaults.
E.g. gen8_configure_all_contexts()
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-27 14:35 ` Chris Wilson
@ 2019-08-27 14:59 ` Kumar Valsan, Prathap
0 siblings, 0 replies; 17+ messages in thread
From: Kumar Valsan, Prathap @ 2019-08-27 14:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Tue, Aug 27, 2019 at 03:35:14PM +0100, Chris Wilson wrote:
> Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51)
> > We want to support this on Gen11 as well, where these registers
> > are context saved and restored and we prime the register values of new contexts
> > from recorded defaults. What could be the correct way to handle this, write to the
> > default object or should ask GPU to re-record after modifying the
> > registers.
>
> That depends on whether you want to apply to existing or only to new.
> For OA / sseu, we modify the context images so that existing contexts
> are updated to reflect the new defaults, and we update the defaults.
> E.g. gen8_configure_all_contexts()
Applying to the existing contexts as well should be the right
thing to do. Thank you! I will look at the example.
Prathap
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (5 preceding siblings ...)
2019-08-26 8:32 ` ✓ Fi.CI.IGT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
@ 2019-09-09 11:50 ` Joonas Lahtinen
2019-09-09 22:52 ` Kumar Valsan, Prathap
2019-09-30 22:18 ` [PATCH v2] drm/i915/ehl: " Prathap Kumar Valsan
2019-09-30 22:58 ` ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Add sysfs interface to control class-of-service (rev3) Patchwork
8 siblings, 1 reply; 17+ messages in thread
From: Joonas Lahtinen @ 2019-09-09 11:50 UTC (permalink / raw)
To: Prathap Kumar Valsan, intel-gfx
Quoting Prathap Kumar Valsan (2019-08-26 01:48:01)
> To provide shared last-level-cache isolation to cpu workloads running
> concurrently with gpu workloads, the gpu allocation of cache lines needs
> to be restricted to certain ways. Currently GPU hardware supports four
> class-of-service(CLOS) levels and there is an associated way-mask for
> each CLOS.
>
> Hardware supports reading supported way-mask configuration for GPU using
> a bios pcode interface. The supported way-masks and the one currently
> active is communicated to userspace via a sysfs file--closctrl. Admin user
> can then select a new mask by writing the mask value to the file.
>
> Note of Caution: Restricting cache ways using this mechanism presents a
> larger attack surface for side-channel attacks.
I wonder if this is enough to justify some further protection before
enabling?
> Example usage:
> The active way-mask is highlighted within square brackets.
> > cat /sys/class/drm/card0/closctrl
> [0xffff] 0xff00 0xc000 0x8000
How about two files for easier scripting interface?
/sys/class/drm/card0/llc_clos
/sys/class/drm/card0/llc_clos_modes
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service
2019-09-09 11:50 ` [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Joonas Lahtinen
@ 2019-09-09 22:52 ` Kumar Valsan, Prathap
0 siblings, 0 replies; 17+ messages in thread
From: Kumar Valsan, Prathap @ 2019-09-09 22:52 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Mon, Sep 09, 2019 at 02:50:20PM +0300, Joonas Lahtinen wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 01:48:01)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain ways. Currently GPU hardware supports four
> > class-of-service(CLOS) levels and there is an associated way-mask for
> > each CLOS.
> >
> > Hardware supports reading supported way-mask configuration for GPU using
> > a bios pcode interface. The supported way-masks and the one currently
> > active is communicated to userspace via a sysfs file--closctrl. Admin user
> > can then select a new mask by writing the mask value to the file.
> >
> > Note of Caution: Restricting cache ways using this mechanism presents a
> > larger attack surface for side-channel attacks.
>
> I wonder if this is enough to justify some further protection before
> enabling?
Should there be a kernel warning message on enabling this or a commit
message is enough?
>
> > Example usage:
> > The active way-mask is highlighted within square brackets.
> > > cat /sys/class/drm/card0/closctrl
> > [0xffff] 0xff00 0xc000 0x8000
>
> How about two files for easier scripting interface?
>
> /sys/class/drm/card0/llc_clos
> /sys/class/drm/card0/llc_clos_modes
>
Agreed. A single file interface was suggested by Jon. Hope he is ok with having
two files :)
> Regards, Joonas
Thanks,
Prathap
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915/ehl: Add sysfs interface to control class-of-service
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (6 preceding siblings ...)
2019-09-09 11:50 ` [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Joonas Lahtinen
@ 2019-09-30 22:18 ` Prathap Kumar Valsan
2019-09-30 22:58 ` ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Add sysfs interface to control class-of-service (rev3) Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Prathap Kumar Valsan @ 2019-09-30 22:18 UTC (permalink / raw)
To: intel-gfx
To provide shared last-level-cache isolation to cpu workloads running
concurrently with gpu workloads, the gpu allocation of cache lines needs
to be restricted to certain ways. Currently GPU hardware supports four
class-of-service(CLOS) levels and there is an associated way-mask for
each CLOS. Each LLC MOCS register has a field to select the clos level.
So in-order to globally set the gpu to a clos level, driver needs
to program entire MOCS table.
Hardware supports reading supported way-mask configuration for GPU using
a bios pcode interface. This interface has two files--llc_clos_modes and
llc_clos. The file llc_clos_modes is read only file and will list the
available way masks. The file llc_clos is read/write and will show the
currently active way mask and writing a new way mask will update the
active way mask of the gpu.
Note of Caution: Restricting cache ways using this mechanism presents a
larger attack surface for side-channel attacks.
Example usage:
> cat /sys/class/drm/card0/llc_clos_modes
0xfff 0xfc0 0xc00 0x800
>cat /sys/class/drm/card0/llc_clos
0xfff
Update to new clos
echo "0x800" > /sys/class/drm/card0/llc_clos
v2: Updated the interface to use two sysfs files(Joonas)
- Gen12 PCode interface is not ready yet to read the way mask.
So removed TGL support and added support for Gen11.
- Updating MOCS in Gen 11 also require changing the context image of
existing contexts.
Referred to gen8_configure_all_contexts() as suggested by Chris.
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 215 +++++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 100 +++++++++++
7 files changed, 334 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index ab725a6ca0ac..82cbf9b97a55 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2114,6 +2114,13 @@ __execlists_update_reg_state(const struct intel_context *ce,
intel_sseu_make_rpcs(engine->i915, &ce->sseu);
i915_oa_init_reg_state(ce, engine);
+ /*
+ * Gen11 supports update of LLC class-of-service via
+ * sysfs interface. Also update the context register state
+ * of the new contexts.
+ */
+ if (IS_GEN(engine->i915, 11))
+ intel_mocs_init_reg_state(ce);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 06ab0276e10e..f07a6262217c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -28,6 +28,7 @@
#define CTX_R_PWR_CLK_STATE (0x42 + 1)
#define GEN9_CTX_RING_MI_MODE 0x54
+#define GEN11_CTX_GFX_MOCS_BASE 0x4F2
/* GEN12+ Reg State Context */
#define GEN12_CTX_BB_PER_CTX_PTR (0x12 + 1)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 728704bbbe18..5eb805b6ee23 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -26,6 +26,9 @@
#include "intel_gt.h"
#include "intel_mocs.h"
#include "intel_lrc.h"
+#include "intel_lrc_reg.h"
+#include "intel_sideband.h"
+#include "gem/i915_gem_context.h"
/* structures required */
struct drm_i915_mocs_entry {
@@ -40,6 +43,7 @@ struct drm_i915_mocs_table {
const struct drm_i915_mocs_entry *table;
};
+#define ctx_mocsN(N) (GEN11_CTX_GFX_MOCS_BASE + 2 * (N) + 1)
/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
#define _LE_CACHEABILITY(value) ((value) << 0)
#define _LE_TGT_CACHE(value) ((value) << 2)
@@ -51,6 +55,7 @@ struct drm_i915_mocs_table {
#define LE_SCF(value) ((value) << 14)
#define LE_COS(value) ((value) << 15)
#define LE_SSE(value) ((value) << 17)
+#define LE_COS_MASK GENMASK(16, 15)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -377,6 +382,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
struct intel_gt *gt = engine->gt;
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
+ unsigned int active_clos;
unsigned int index;
u32 unused_value;
@@ -390,11 +396,16 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
if (!get_mocs_settings(gt, &table))
return;
+ active_clos = engine->i915->clos.active_clos;
/* Set unused values to PTE */
unused_value = table.table[I915_MOCS_PTE].control_value;
+ unused_value &= ~LE_COS_MASK;
+ unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
for (index = 0; index < table.size; index++) {
u32 value = get_entry_control(&table, index);
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
intel_uncore_write_fw(uncore,
mocs_register(engine->id, index),
@@ -408,7 +419,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
-static void intel_mocs_init_global(struct intel_gt *gt)
+void intel_mocs_init_global(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
@@ -442,6 +453,7 @@ static int emit_mocs_control_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table)
{
enum intel_engine_id engine = rq->engine->id;
+ unsigned int active_clos;
unsigned int index;
u32 unused_value;
u32 *cs;
@@ -449,8 +461,11 @@ static int emit_mocs_control_table(struct i915_request *rq,
if (GEM_WARN_ON(table->size > table->n_entries))
return -ENODEV;
+ active_clos = rq->i915->clos.active_clos;
/* Set unused values to PTE */
unused_value = table->table[I915_MOCS_PTE].control_value;
+ unused_value &= ~LE_COS_MASK;
+ unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
if (IS_ERR(cs))
@@ -460,6 +475,8 @@ static int emit_mocs_control_table(struct i915_request *rq,
for (index = 0; index < table->size; index++) {
u32 value = get_entry_control(table, index);
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
*cs++ = value;
@@ -625,10 +642,206 @@ int intel_mocs_emit(struct i915_request *rq)
return 0;
}
+void intel_mocs_init_reg_state(const struct intel_context *ce)
+{
+ struct drm_i915_private *i915 = ce->engine->i915;
+ u32 *reg_state = ce->lrc_reg_state;
+ struct drm_i915_mocs_table t;
+ unsigned int active_clos;
+ u32 value;
+ int i;
+
+ get_mocs_settings(ce->engine->gt, &t);
+
+ active_clos = i915->clos.active_clos;
+
+ if (active_clos == FIELD_GET(LE_COS_MASK, get_entry_control(&t, 0)))
+ return;
+
+ for (i = 0; i < t.n_entries; i++) {
+ value = reg_state[ctx_mocsN(i)];
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
+ reg_state[ctx_mocsN(i)] = value;
+ }
+}
+
+static int
+mocs_store_clos(struct i915_request *rq,
+ struct intel_context *ce)
+{
+ struct drm_i915_mocs_table t;
+ unsigned int count, active_clos, index;
+ u32 offset;
+ u32 value;
+ u32 *cs;
+
+ if (!get_mocs_settings(rq->engine->gt, &t))
+ return -ENODEV;
+
+ count = t.n_entries;
+ active_clos = rq->i915->clos.active_clos;
+ cs = intel_ring_begin(rq, 4 * count);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
+
+ for (index = 0; index < count; index++) {
+ value = ce->lrc_reg_state[ctx_mocsN(index)];
+ value &= ~LE_COS_MASK;
+ value |= FIELD_PREP(LE_COS_MASK, active_clos);
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset + ctx_mocsN(index) * sizeof(uint32_t);
+ *cs++ = 0;
+ *cs++ = value;
+ }
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int modify_context_mocs(struct intel_context *ce)
+{
+ struct i915_request *rq;
+ int err;
+
+ lockdep_assert_held(&ce->pin_mutex);
+
+ rq = i915_request_create(ce->engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ /* Serialise with the remote context */
+ err = intel_context_prepare_remote_request(ce, rq);
+ if (err == 0)
+ err = mocs_store_clos(rq, ce);
+
+ i915_request_add(rq);
+ return err;
+}
+
+static int intel_mocs_configure_context(struct i915_gem_context *ctx)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ int err = 0;
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ GEM_BUG_ON(ce == ce->engine->kernel_context);
+
+ if (ce->engine->class != RENDER_CLASS)
+ continue;
+
+ err = intel_context_lock_pinned(ce);
+ if (err)
+ break;
+
+ if (intel_context_is_pinned(ce))
+ err = modify_context_mocs(ce);
+
+ intel_context_unlock_pinned(ce);
+ if (err)
+ break;
+ }
+ i915_gem_context_unlock_engines(ctx);
+
+ return err;
+}
+
+static int intel_mocs_configure_all_contexts(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *ctx;
+ enum intel_engine_id id;
+ int err;
+
+ /*
+ * MOCS registers of render engine are context saved and restored to and
+ * from a context image.
+ * So for any MOCS update to reflect on the existing contexts requires
+ * updating the context image.
+ */
+ list_for_each_entry(ctx, &i915->contexts.list, link) {
+ if (ctx == i915->kernel_context)
+ continue;
+
+ err = intel_mocs_configure_context(ctx);
+ if (err)
+ return err;
+ }
+
+ /*
+ * After updating all other contexts, update render context image of
+ * kernel context. Also update the MOCS of non-render engines.
+ */
+
+ for_each_engine(engine, i915, id) {
+ struct i915_request *rq;
+ struct drm_i915_mocs_table t;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ get_mocs_settings(rq->engine->gt, &t);
+ err = emit_mocs_control_table(rq, &t);
+ if (err) {
+ i915_request_skip(rq, err);
+ i915_request_add(rq);
+ return err;
+ }
+
+ i915_request_add(rq);
+ }
+
+ return 0;
+}
+
+int intel_mocs_update_clos(struct intel_gt *gt)
+{
+ return intel_mocs_configure_all_contexts(gt);
+}
+
+static void intel_read_clos_way_mask(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct drm_i915_mocs_table table;
+ int ret, i;
+ u32 val;
+
+ if (!get_mocs_settings(gt, &table))
+ return;
+
+ /* CLOS is same for all entries. So its enough to read one*/
+ i915->clos.active_clos = FIELD_GET(LE_COS_MASK,
+ get_entry_control(&table, 0));
+ for (i = 0; i < NUM_OF_CLOS; i++) {
+ val = i;
+ ret = sandybridge_pcode_read(i915,
+ ICL_PCODE_LLC_COS_WAY_MASK_INFO,
+ &val, NULL);
+ if (ret) {
+ DRM_ERROR("Mailbox read error = %d\n", ret);
+ return;
+ }
+
+ i915->clos.way_mask[i] = val;
+ }
+
+ i915->clos.support_way_mask_read = true;
+}
+
void intel_mocs_init(struct intel_gt *gt)
{
intel_mocs_init_l3cc_table(gt);
+ if (IS_GEN(gt->i915, 11))
+ intel_read_clos_way_mask(gt);
+
if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
intel_mocs_init_global(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 2ae816b7ca19..af5450b209c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -57,5 +57,8 @@ void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
int intel_mocs_emit(struct i915_request *rq);
+int intel_mocs_update_clos(struct intel_gt *gt);
+
+void intel_mocs_init_reg_state(const struct intel_context *ce);
#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fcf7423075ef..7e4f6464d8c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1630,6 +1630,14 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ /* Last Level Cache Class of Service */
+ struct {
+ bool support_way_mask_read;
+ u8 active_clos;
+#define NUM_OF_CLOS 4
+ u16 way_mask[NUM_OF_CLOS];
+ } clos;
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..55dafde9c93c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8854,6 +8854,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_LLC_COS_WAY_MASK_INFO 0x1d
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d8a3b180c084..f313f559ffb4 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -34,6 +34,7 @@
#include "i915_sysfs.h"
#include "intel_pm.h"
#include "intel_sideband.h"
+#include "gt/intel_mocs.h"
static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
@@ -257,6 +258,88 @@ static const struct bin_attribute dpf_attrs_1 = {
.private = (void *)1
};
+static ssize_t llc_clos_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ ssize_t len = 0;
+ int active_clos;
+
+ active_clos = dev_priv->clos.active_clos;
+ len += snprintf(buf + len, PAGE_SIZE, "0x%x\n",
+ dev_priv->clos.way_mask[active_clos]);
+
+ return len;
+}
+
+static ssize_t llc_clos_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ struct drm_device *dev = &dev_priv->drm;
+ u8 active_clos, new_clos, clos_index;
+ bool valid_mask = false;
+ ssize_t ret;
+ u16 way_mask;
+
+ ret = kstrtou16(buf, 0, &way_mask);
+ if (ret)
+ return ret;
+
+ active_clos = dev_priv->clos.active_clos;
+
+ if (dev_priv->clos.way_mask[active_clos] == way_mask)
+ return count;
+
+ for (clos_index = 0; clos_index < NUM_OF_CLOS; clos_index++) {
+ if (dev_priv->clos.way_mask[clos_index] == way_mask) {
+ new_clos = clos_index;
+ valid_mask = true;
+ break;
+ }
+ }
+
+ if (!valid_mask)
+ return -EINVAL;
+
+ ret = i915_mutex_lock_interruptible(dev);
+ if (ret)
+ return ret;
+
+ dev_priv->clos.active_clos = new_clos;
+ ret = intel_mocs_update_clos(&dev_priv->gt);
+ if (ret) {
+ DRM_ERROR("Failed to update Class of service\n");
+ dev_priv->clos.active_clos = active_clos;
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+ }
+
+ mutex_unlock(&dev->struct_mutex);
+
+ return count;
+}
+
+static ssize_t llc_clos_modes_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ ssize_t len = 0;
+ int i;
+
+ for (i = 0; i < NUM_OF_CLOS; i++)
+ len += snprintf(buf + len, PAGE_SIZE, "0x%x ",
+ dev_priv->clos.way_mask[i]);
+
+ len += snprintf(buf + len, PAGE_SIZE, "\n");
+
+ return len;
+}
+
+static DEVICE_ATTR_RW(llc_clos);
+static DEVICE_ATTR_RO(llc_clos_modes);
+
static ssize_t gt_act_freq_mhz_show(struct device *kdev,
struct device_attribute *attr, char *buf)
{
@@ -576,6 +659,18 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
struct device *kdev = dev_priv->drm.primary->kdev;
int ret;
+ if (dev_priv->clos.support_way_mask_read) {
+ ret = sysfs_create_file(&kdev->kobj,
+ &dev_attr_llc_clos.attr);
+ if (ret)
+ DRM_ERROR("LLC COS sysfs setup failed\n");
+
+ ret = sysfs_create_file(&kdev->kobj,
+ &dev_attr_llc_clos_modes.attr);
+ if (ret)
+ DRM_ERROR("LLC COS sysfs setup failed\n");
+ }
+
#ifdef CONFIG_PM
if (HAS_RC6(dev_priv)) {
ret = sysfs_merge_group(&kdev->kobj,
@@ -626,6 +721,11 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_teardown_error_capture(kdev);
+ if (dev_priv->clos.support_way_mask_read) {
+ sysfs_remove_file(&kdev->kobj, &dev_attr_llc_clos.attr);
+ sysfs_remove_file(&kdev->kobj, &dev_attr_llc_clos_modes.attr);
+ }
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
sysfs_remove_files(&kdev->kobj, vlv_attrs);
else
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Add sysfs interface to control class-of-service (rev3)
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
` (7 preceding siblings ...)
2019-09-30 22:18 ` [PATCH v2] drm/i915/ehl: " Prathap Kumar Valsan
@ 2019-09-30 22:58 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-09-30 22:58 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service (rev3)
URL : https://patchwork.freedesktop.org/series/65769/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC drivers/gpu/drm/i915/gt/intel_mocs.h.s
In file included from <command-line>:0:0:
./drivers/gpu/drm/i915/gt/intel_mocs.h:62:45: error: ‘struct intel_context’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
void intel_mocs_init_reg_state(const struct intel_context *ce);
^~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/gt/intel_mocs.h.s' failed
make[5]: *** [drivers/gpu/drm/i915/gt/intel_mocs.h.s] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915/gt' failed
make[4]: *** [drivers/gpu/drm/i915/gt] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1670: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2019-09-30 22:58 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-25 22:48 [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Prathap Kumar Valsan
2019-08-25 22:40 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
2019-08-25 23:03 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-25 23:35 ` [PATCH v2] " Prathap Kumar Valsan
2019-08-26 8:39 ` Chris Wilson
2019-08-27 14:17 ` Kumar Valsan, Prathap
2019-08-26 9:17 ` Chris Wilson
2019-08-27 14:17 ` Kumar Valsan, Prathap
2019-08-27 14:35 ` Chris Wilson
2019-08-27 14:59 ` Kumar Valsan, Prathap
2019-08-25 23:52 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
2019-08-26 7:32 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Add sysfs interface to control class-of-service Patchwork
2019-08-26 8:32 ` ✓ Fi.CI.IGT: success for drm/i915/tgl: Add sysfs interface to control class-of-service (rev2) Patchwork
2019-09-09 11:50 ` [PATCH] drm/i915/tgl: Add sysfs interface to control class-of-service Joonas Lahtinen
2019-09-09 22:52 ` Kumar Valsan, Prathap
2019-09-30 22:18 ` [PATCH v2] drm/i915/ehl: " Prathap Kumar Valsan
2019-09-30 22:58 ` ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Add sysfs interface to control class-of-service (rev3) Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.