[PATCH v3 00/23] Tiger Lake batch 3

[PATCH v3 00/23] Tiger Lake batch 3

[Lucas De Marchi]

v3 of https://patchwork.freedesktop.org/series/65290/

Note that some patches were handled outside of the "batch series for
Tiger Lake". Compared to v2 several patches were merged. Anothe great
portion received comments and reviews. Unfortunately some people
commented/reviewed the wrong revision of the patch, making it difficult
to follow up on adding the R-b. Also, patchwork got pretty confused with
the patches sent by José to cover the review feedback. So, if I didn't
handle your comment, I will double check for the next version. If you
reviewed a patch and it does not show here, then please add your r-b
again.

2 patches to add perf support are dropped: one of them was missing
a userspace component and the other one depends on the first.

Patches that still need to handle the comments from previous versions
are prefixed with FIXME and are not meant to be merged.

For the patches that already have a r-b tag: I was planning to merge
them and remove from this series, but in the end I felt more confortable
doing it in steps: add them here again and merge them later.

Lucas De Marchi

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (12):
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  FIXME: drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lucas De Marchi (1):
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (5):
  drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  FIXME: drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 199 +++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  | 105 ++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 179 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 200 +++++++++---------
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++++++-
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 156 ++++++++++----
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  30 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  10 +-
 drivers/gpu/drm/i915/i915_irq.c               |  52 ++++-
 drivers/gpu/drm/i915/i915_perf.c              |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  35 ++-
 drivers/gpu/drm/i915/intel_pm.c               |  18 +-
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 22 files changed, 1011 insertions(+), 209 deletions(-)

-- 
2.23.0

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[PATCH v3 01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.

v2: Rename register and bitfield to its new name (suggested by Mika)

HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 3 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 8 +++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..bea0c49d3e32 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -83,6 +83,9 @@
 #define GEN8_GTCR			_MMIO(0x4274)
 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
 
+#define GEN12_GUC_TLB_INV_CR		_MMIO(0xcee8)
+#define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1<<0)
+
 #define GUC_ARAT_C6DIS			_MMIO(0xA178)
 
 #define GUC_SHIM_CONTROL		_MMIO(0xc064)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0b81e0b64393..2a425db1cfd8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -132,9 +132,15 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 
 	gen6_ggtt_invalidate(ggtt);
-	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	if (INTEL_GEN(i915) >= 12)
+		intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
+				      GEN12_GUC_TLB_INV_CR_INVALIDATE);
+	else
+		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-- 
2.23.0

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[PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.

During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.

BSpec: 14214
HSDES: 1209977827
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tony Ye <tony.ye@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  4 ++++
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a092b34c269d..02e1ef10c47e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8615,6 +8615,10 @@ enum {
 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
 #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
 
+#define POWERGATE_ENABLE			_MMIO(0xa210)
+#define    VDN_HCP_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 3)
+#define    VDN_MFX_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 4)
+
 #define  GTFIFODBG				_MMIO(0x120000)
 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75ee027abb80..d3ea193cd093 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9078,6 +9078,22 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
 }
 
+static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	u32 vd_pg_enable = 0;
+	unsigned int i;
+
+	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
+	for (i = 0; i < I915_MAX_VCS; i++) {
+		if (HAS_ENGINE(dev_priv, _VCS(i)))
+			vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
+					VDN_MFX_POWERGATE_ENABLE(i);
+	}
+
+	I915_WRITE(POWERGATE_ENABLE,
+		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_PCH_CNP(dev_priv))
@@ -9598,7 +9614,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_GEN(dev_priv, 12))
-		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+		dev_priv->display.init_clock_gating = tgl_init_clock_gating;
 	else if (IS_GEN(dev_priv, 11))
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
 	else if (IS_CANNONLAKE(dev_priv))
-- 
2.23.0

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[PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.

This also already prepares for future when more than one PSR instance
will be allowed.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
 drivers/gpu/drm/i915/i915_reg.h          |  13 +--
 2 files changed, 59 insertions(+), 94 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 28b62e587204..81e3619cd905 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
 	}
 }
 
-static int edp_psr_shift(enum transcoder cpu_transcoder)
+static void psr_irq_control(struct drm_i915_private *dev_priv)
 {
-	switch (cpu_transcoder) {
-	case TRANSCODER_A:
-		return EDP_PSR_TRANSCODER_A_SHIFT;
-	case TRANSCODER_B:
-		return EDP_PSR_TRANSCODER_B_SHIFT;
-	case TRANSCODER_C:
-		return EDP_PSR_TRANSCODER_C_SHIFT;
-	default:
-		MISSING_CASE(cpu_transcoder);
-		/* fallthrough */
-	case TRANSCODER_EDP:
-		return EDP_PSR_TRANSCODER_EDP_SHIFT;
-	}
-}
+	enum transcoder trans = dev_priv->psr.transcoder;
+	u32 val, mask;
 
-static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
-{
-	u32 debug_mask, mask;
-	enum transcoder cpu_transcoder;
-	u32 transcoders = BIT(TRANSCODER_EDP);
-
-	if (INTEL_GEN(dev_priv) >= 8)
-		transcoders |= BIT(TRANSCODER_A) |
-			       BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C);
-
-	debug_mask = 0;
-	mask = 0;
-	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
-		int shift = edp_psr_shift(cpu_transcoder);
-
-		mask |= EDP_PSR_ERROR(shift);
-		debug_mask |= EDP_PSR_POST_EXIT(shift) |
-			      EDP_PSR_PRE_ENTRY(shift);
-	}
+	mask = EDP_PSR_ERROR(trans);
+	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
 
-	if (debug & I915_PSR_DEBUG_IRQ)
-		mask |= debug_mask;
-
-	I915_WRITE(EDP_PSR_IMR, ~mask);
+	/*
+	 * TODO: when handling multiple PSR instances a global spinlock will be
+	 * needed to synchronize the value of shared register
+	 */
+	val = I915_READ(EDP_PSR_IMR);
+	val &= ~EDP_PSR_TRANS_MASK(trans);
+	val |= ~mask;
+	I915_WRITE(EDP_PSR_IMR, val);
 }
 
 static void psr_event_print(u32 val, bool psr2_enabled)
@@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
 
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 {
-	u32 transcoders = BIT(TRANSCODER_EDP);
-	enum transcoder cpu_transcoder;
+	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
 	ktime_t time_ns =  ktime_get();
-	u32 mask = 0;
 
-	if (INTEL_GEN(dev_priv) >= 8)
-		transcoders |= BIT(TRANSCODER_A) |
-			       BIT(TRANSCODER_B) |
-			       BIT(TRANSCODER_C);
+	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+		u32 val;
 
-	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
-		int shift = edp_psr_shift(cpu_transcoder);
+		DRM_WARN("[transcoder %s] PSR aux error\n",
+			 transcoder_name(cpu_transcoder));
 
-		if (psr_iir & EDP_PSR_ERROR(shift)) {
-			DRM_WARN("[transcoder %s] PSR aux error\n",
-				 transcoder_name(cpu_transcoder));
+		dev_priv->psr.irq_aux_error = true;
 
-			dev_priv->psr.irq_aux_error = true;
+		/*
+		 * If this interruption is not masked it will keep
+		 * interrupting so fast that it prevents the scheduled
+		 * work to run.
+		 * Also after a PSR error, we don't want to arm PSR
+		 * again so we don't care about unmask the interruption
+		 * or unset irq_aux_error.
+		 *
+		 * TODO: when handling multiple PSR instances a global spinlock
+		 * will be needed to synchronize the value of shared register
+		 */
+		val = I915_READ(EDP_PSR_IMR);
+		val |= EDP_PSR_ERROR(cpu_transcoder);
+		I915_WRITE(EDP_PSR_IMR, val);
 
-			/*
-			 * If this interruption is not masked it will keep
-			 * interrupting so fast that it prevents the scheduled
-			 * work to run.
-			 * Also after a PSR error, we don't want to arm PSR
-			 * again so we don't care about unmask the interruption
-			 * or unset irq_aux_error.
-			 */
-			mask |= EDP_PSR_ERROR(shift);
-		}
+		schedule_work(&dev_priv->psr.work);
+	}
 
-		if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
-			dev_priv->psr.last_entry_attempt = time_ns;
-			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
-				      transcoder_name(cpu_transcoder));
-		}
+	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+		dev_priv->psr.last_entry_attempt = time_ns;
+		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
+			      transcoder_name(cpu_transcoder));
+	}
 
-		if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
-			dev_priv->psr.last_exit = time_ns;
-			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
-				      transcoder_name(cpu_transcoder));
+	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+		dev_priv->psr.last_exit = time_ns;
+		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
+			      transcoder_name(cpu_transcoder));
 
-			if (INTEL_GEN(dev_priv) >= 9) {
-				u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
-				bool psr2_enabled = dev_priv->psr.psr2_enabled;
+		if (INTEL_GEN(dev_priv) >= 9) {
+			u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
+			bool psr2_enabled = dev_priv->psr.psr2_enabled;
 
-				I915_WRITE(PSR_EVENT(cpu_transcoder), val);
-				psr_event_print(val, psr2_enabled);
-			}
+			I915_WRITE(PSR_EVENT(cpu_transcoder), val);
+			psr_event_print(val, psr2_enabled);
 		}
 	}
-
-	if (mask) {
-		mask |= I915_READ(EDP_PSR_IMR);
-		I915_WRITE(EDP_PSR_IMR, mask);
-
-		schedule_work(&dev_priv->psr.work);
-	}
 }
 
 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
@@ -737,7 +703,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
 
-	psr_irq_control(dev_priv, dev_priv->psr.debug);
+	psr_irq_control(dev_priv);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
@@ -762,7 +728,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 	 * to avoid any rendering problems.
 	 */
 	val = I915_READ(EDP_PSR_IIR);
-	val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
+	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
 	if (val) {
 		dev_priv->psr.sink_not_reliable = true;
 		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
@@ -1110,7 +1076,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
 
 	old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
 	dev_priv->psr.debug = val;
-	psr_irq_control(dev_priv, dev_priv->psr.debug);
+	psr_irq_control(dev_priv);
 
 	mutex_unlock(&dev_priv->psr.lock);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..1c6d99944630 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4225,13 +4225,12 @@ enum {
 /* Bspec claims those aren't shifted but stay at 0x64800 */
 #define EDP_PSR_IMR				_MMIO(0x64834)
 #define EDP_PSR_IIR				_MMIO(0x64838)
-#define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
-#define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
-#define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
-#define   EDP_PSR_TRANSCODER_C_SHIFT		24
-#define   EDP_PSR_TRANSCODER_B_SHIFT		16
-#define   EDP_PSR_TRANSCODER_A_SHIFT		8
-#define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)
+#define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
+#define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
+#define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
+#define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
 
 #define _SRD_AUX_CTL_A				0x60810
 #define _SRD_AUX_CTL_EDP			0x6f810
-- 
2.23.0

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[PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this
limitation.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 81e3619cd905..0172b82858d9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 
 	/*
 	 * HSW spec explicitly says PSR is tied to port A.
-	 * BDW+ platforms have a instance of PSR registers per transcoder but
-	 * for now it only supports one instance of PSR, so lets keep it
-	 * hardcoded to PORT_A
+	 * BDW+ platforms have a instance of PSR registers per transcoder.
 	 */
-	if (dig_port->base.port != PORT_A) {
+	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
 		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 		return;
 	}
-- 
2.23.0

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[PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

Now that is allowed to have PSR enabled in any port from BDW+, lets
guard intel_psr_init_dpcd() against multiple eDP panels and warn about
it.

For now we will keep just one instance of PSR.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0172b82858d9..cf07ab3d9280 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -249,6 +249,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv =
 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 
+	if (dev_priv->psr.dp) {
+		DRM_WARN("More than one eDP panel found, PSR support should be extend\n");
+		return;
+	}
+
 	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 			 sizeof(intel_dp->psr_dpcd));
 
@@ -271,7 +276,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	dev_priv->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
-	WARN_ON(dev_priv->psr.dp);
 	dev_priv->psr.dp = intel_dp;
 
 	if (INTEL_GEN(dev_priv) >= 9 &&
-- 
2.23.0

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[PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

This fix unclaimed access warnings:

[  245.525788] ------------[ cut here ]------------
[  245.525884] Unclaimed read from register 0x62900
[  245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[  245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915]
[  245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915
[  245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019
[  245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915]
[  245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55
[  245.526288] RSP: 0018:ffffc900006bf7d8 EFLAGS: 00010086
[  245.526297] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
[  245.526304] RDX: 0000000000000007 RSI: 0000000000000000 RDI: 00000000ffffffff
[  245.526310] RBP: 0000000000061900 R08: 0000000000000000 R09: 0000000000000001
[  245.526317] R10: 0000000000000006 R11: 0000000000000000 R12: 0000000000000001
[  245.526324] R13: 0000000000000000 R14: ffff8882914f0d58 R15: 0000000000000206
[  245.526332] FS:  00007fed2a3c39c0(0000) GS:ffff8882a8600000(0000) knlGS:0000000000000000
[  245.526340] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  245.526347] CR2: 00007fed28dff000 CR3: 00000002a086c006 CR4: 0000000000760ef0
[  245.526354] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  245.526361] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  245.526367] PKRU: 55555554
[  245.526373] Call Trace:
[  245.526454]  gen11_fwtable_read32+0x219/0x250 [i915]
[  245.526576]  intel_psr_activate+0x57/0x400 [i915]
[  245.526697]  intel_psr_enable_locked+0x367/0x4b0 [i915]
[  245.526828]  intel_psr_enable+0xa4/0xd0 [i915]
[  245.526946]  intel_enable_ddi+0x127/0x2f0 [i915]
[  245.527075]  intel_encoders_enable.isra.79+0x62/0x90 [i915]
[  245.527202]  haswell_crtc_enable+0x2a2/0x850 [i915]
[  245.527337]  intel_update_crtc+0x51/0x360 [i915]
[  245.527466]  skl_update_crtcs+0x26c/0x300 [i915]
[  245.527603]  intel_atomic_commit_tail+0x3e5/0x13c0 [i915]
[  245.527757]  intel_atomic_commit+0x24d/0x2d0 [i915]
[  245.527782]  drm_atomic_helper_set_config+0x7b/0x90
[  245.527799]  drm_mode_setcrtc+0x1b4/0x6f0
[  245.527856]  ? drm_mode_getcrtc+0x180/0x180
[  245.527867]  drm_ioctl_kernel+0xad/0xf0
[  245.527886]  drm_ioctl+0x2f4/0x3b0
[  245.527902]  ? drm_mode_getcrtc+0x180/0x180
[  245.527935]  ? rcu_read_lock_sched_held+0x6f/0x80
[  245.527956]  do_vfs_ioctl+0xa0/0x6d0
[  245.527970]  ? __task_pid_nr_ns+0xb6/0x200
[  245.527991]  ksys_ioctl+0x35/0x70
[  245.528009]  __x64_sys_ioctl+0x11/0x20
[  245.528020]  do_syscall_64+0x55/0x180
[  245.528034]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
[  245.528042] RIP: 0033:0x7fed2cc7c3c7
[  245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48
[  245.528057] RSP: 002b:00007ffe36944378 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
[  245.528067] RAX: ffffffffffffffda RBX: 00007ffe369443b0 RCX: 00007fed2cc7c3c7
[  245.528074] RDX: 00007ffe369443b0 RSI: 00000000c06864a2 RDI: 0000000000000003
[  245.528081] RBP: 00007ffe369443b0 R08: 0000000000000000 R09: 0000564c0173ae98
[  245.528088] R10: 0000564c0173aeb8 R11: 0000000000000246 R12: 00000000c06864a2
[  245.528095] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
[  245.528128] irq event stamp: 140866
[  245.528138] hardirqs last  enabled at (140865): [<ffffffff819a63dc>] _raw_spin_unlock_irqrestore+0x4c/0x60
[  245.528148] hardirqs last disabled at (140866): [<ffffffff819a624d>] _raw_spin_lock_irqsave+0xd/0x50
[  245.528158] softirqs last  enabled at (140860): [<ffffffff81c0038c>] __do_softirq+0x38c/0x499
[  245.528170] softirqs last disabled at (140853): [<ffffffff810b4a09>] irq_exit+0xa9/0xc0
[  245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[  245.528254] ---[ end trace 366069676e98a410 ]---

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cf07ab3d9280..4e6b3ae8a872 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -631,7 +631,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (INTEL_GEN(dev_priv) >= 9 &&
+	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
 		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
 	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
@@ -785,7 +786,8 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	if (!dev_priv->psr.active) {
-		if (INTEL_GEN(dev_priv) >= 9) {
+		if (INTEL_GEN(dev_priv) >= 9 &&
+		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
 			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
 			WARN_ON(val & EDP_PSR2_ENABLE);
 		}
-- 
2.23.0

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[PATCH v3 07/23] drm/i915/tgl: PSR link standby is not supported anymore

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

According to BSpc if link standby is set on TGL+, PSR will not be
enabled. Vendors should not use panels that requires link standby and
even if they do, panel should assert a PSR error that will cause PSR to
be disabled.

BSpec: 50434
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e6b3ae8a872..2429328f963e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1243,8 +1243,8 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		/* HSW and BDW require workarounds that we don't implement. */
 		dev_priv->psr.link_standby = false;
-	else
-		/* For new platforms let's respect VBT back again */
+	else if (INTEL_GEN(dev_priv) < 12)
+		/* For new platforms up to TGL let's respect VBT back again */
 		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 
 	INIT_WORK(&dev_priv->psr.work, intel_psr_work);
-- 
2.23.0

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[PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

For older gens PSR IIR and IMR had a fixed address that was not
relative to anything, but from TGL those registers moved to each
transcoder offset.

So here adding a new macro and a new PSR irq handler with the
transcoder parameter.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h |  1 +
 drivers/gpu/drm/i915/i915_irq.c          | 52 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h          | 10 +++-
 4 files changed, 107 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2429328f963e..c33aa16ed038 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,20 +91,33 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
 static void psr_irq_control(struct drm_i915_private *dev_priv)
 {
 	enum transcoder trans = dev_priv->psr.transcoder;
-	u32 val, mask;
+	u32 psr_error, psr_entry, psr_exit, mask, val;
+	i915_reg_t mask_reg;
+
+	if (INTEL_GEN(dev_priv) >= 12) {
+		psr_error = TRANS_PSR_ERROR;
+		psr_entry = TRANS_PSR_PRE_ENTRY;
+		psr_exit = TRANS_PSR_POST_EXIT;
+		mask_reg = TRANS_PSR_IMR(trans);
+	} else {
+		psr_error = EDP_PSR_ERROR(trans);
+		psr_entry = EDP_PSR_PRE_ENTRY(trans);
+		psr_exit = EDP_PSR_POST_EXIT(trans);
+		mask_reg = EDP_PSR_IMR;
+	}
 
-	mask = EDP_PSR_ERROR(trans);
+	mask = psr_error;
 	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
-		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
+		mask |= psr_exit | psr_entry;
 
 	/*
 	 * TODO: when handling multiple PSR instances a global spinlock will be
 	 * needed to synchronize the value of shared register
 	 */
-	val = I915_READ(EDP_PSR_IMR);
-	val &= ~EDP_PSR_TRANS_MASK(trans);
+	val = I915_READ(mask_reg);
+	val &= ~(psr_error | psr_entry | psr_exit);
 	val |= ~mask;
-	I915_WRITE(EDP_PSR_IMR, val);
+	I915_WRITE(mask_reg, val);
 }
 
 static void psr_event_print(u32 val, bool psr2_enabled)
@@ -147,9 +160,21 @@ static void psr_event_print(u32 val, bool psr2_enabled)
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 {
 	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
+	u32 psr_error, psr_entry, psr_exit;
 	ktime_t time_ns =  ktime_get();
 
-	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		psr_error = TRANS_PSR_ERROR;
+		psr_entry = TRANS_PSR_PRE_ENTRY;
+		psr_exit = TRANS_PSR_POST_EXIT;
+	} else {
+		psr_error = EDP_PSR_ERROR(cpu_transcoder);
+		psr_entry = EDP_PSR_PRE_ENTRY(cpu_transcoder);
+		psr_exit = EDP_PSR_POST_EXIT(cpu_transcoder);
+	}
+
+	if (psr_iir & psr_error) {
+		i915_reg_t mask_reg;
 		u32 val;
 
 		DRM_WARN("[transcoder %s] PSR aux error\n",
@@ -168,20 +193,25 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 		 * TODO: when handling multiple PSR instances a global spinlock
 		 * will be needed to synchronize the value of shared register
 		 */
-		val = I915_READ(EDP_PSR_IMR);
-		val |= EDP_PSR_ERROR(cpu_transcoder);
-		I915_WRITE(EDP_PSR_IMR, val);
+		if (INTEL_GEN(dev_priv) >= 12)
+			mask_reg = TRANS_PSR_IMR(cpu_transcoder);
+		else
+			mask_reg = EDP_PSR_IMR;
+
+		val = I915_READ(mask_reg);
+		val |= psr_error;
+		I915_WRITE(mask_reg, val);
 
 		schedule_work(&dev_priv->psr.work);
 	}
 
-	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+	if (psr_iir & psr_entry) {
 		dev_priv->psr.last_entry_attempt = time_ns;
 		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
 			      transcoder_name(cpu_transcoder));
 	}
 
-	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+	if (psr_iir & psr_exit) {
 		dev_priv->psr.last_exit = time_ns;
 		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
 			      transcoder_name(cpu_transcoder));
@@ -632,7 +662,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	if (INTEL_GEN(dev_priv) >= 9 &&
-	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
+	    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
 		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
 	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
@@ -730,8 +760,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 	 * first time that PSR HW tries to activate so lets keep PSR disabled
 	 * to avoid any rendering problems.
 	 */
-	val = I915_READ(EDP_PSR_IIR);
-	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+	if (INTEL_GEN(dev_priv) >= 12) {
+		val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
+		val &= TRANS_PSR_ERROR;
+	} else {
+		val = I915_READ(EDP_PSR_IIR);
+		val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+	}
 	if (val) {
 		dev_priv->psr.sink_not_reliable = true;
 		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
@@ -787,7 +822,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 
 	if (!dev_priv->psr.active) {
 		if (INTEL_GEN(dev_priv) >= 9 &&
-		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
+		    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
 			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
 			WARN_ON(val & EDP_PSR2_ENABLE);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 46e4de8b8cd5..6570a23a68b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -6,6 +6,7 @@
 #ifndef __INTEL_PSR_H__
 #define __INTEL_PSR_H__
 
+#include "intel_display.h"
 #include "intel_frontbuffer.h"
 
 struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77391d8325bf..6024a6ef1c76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2655,11 +2655,22 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 	}
 
 	if (iir & GEN8_DE_EDP_PSR) {
-		u32 psr_iir = I915_READ(EDP_PSR_IIR);
+		u32 psr_iir;
+
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder trans = dev_priv->psr.transcoder;
+
+			psr_iir = I915_READ(TRANS_PSR_IIR(trans));
+			I915_WRITE(TRANS_PSR_IIR(trans), psr_iir);
+		} else {
+			psr_iir = I915_READ(EDP_PSR_IIR);
+			I915_WRITE(EDP_PSR_IIR, psr_iir);
+		}
+
+		if (psr_iir)
+			found = true;
 
 		intel_psr_irq_handler(dev_priv, psr_iir);
-		I915_WRITE(EDP_PSR_IIR, psr_iir);
-		found = true;
 	}
 
 	if (!found)
@@ -3279,8 +3290,23 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
 
 	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
 
-	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
-	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+	if (INTEL_GEN(dev_priv) >= 12) {
+		enum transcoder trans;
+
+		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+			enum intel_display_power_domain domain;
+
+			domain = POWER_DOMAIN_TRANSCODER(trans);
+			if (!intel_display_power_is_enabled(dev_priv, domain))
+				continue;
+
+			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
+			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
+		}
+	} else {
+		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
+		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+	}
 
 	for_each_pipe(dev_priv, pipe)
 		if (intel_display_power_is_enabled(dev_priv,
@@ -3793,7 +3819,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	else if (IS_BROADWELL(dev_priv))
 		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
 
-	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+	if (INTEL_GEN(dev_priv) >= 12) {
+		enum transcoder trans;
+
+		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+			enum intel_display_power_domain domain;
+
+			domain = POWER_DOMAIN_TRANSCODER(trans);
+			if (!intel_display_power_is_enabled(dev_priv, domain))
+				continue;
+
+			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
+		}
+	} else {
+		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+	}
 
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c6d99944630..3de02683d856 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4222,7 +4222,7 @@ enum {
 #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
-/* Bspec claims those aren't shifted but stay at 0x64800 */
+/* Bspec claims those aren't shifted but stay at 0x64800 until TGL */
 #define EDP_PSR_IMR				_MMIO(0x64834)
 #define EDP_PSR_IIR				_MMIO(0x64838)
 #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
@@ -4232,6 +4232,14 @@ enum {
 #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
 #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
 
+#define _PSR_IMR_A				0x60814
+#define _PSR_IIR_A				0x60818
+#define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(tran, _PSR_IMR_A) /* TGL+ */
+#define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(tran, _PSR_IIR_A) /* TGL+ */
+#define   TRANS_PSR_ERROR			(1 << 2)
+#define   TRANS_PSR_POST_EXIT			(1 << 1)
+#define   TRANS_PSR_PRE_ENTRY			(1 << 0)
+
 #define _SRD_AUX_CTL_A				0x60810
 #define _SRD_AUX_CTL_EDP			0x6f810
 #define EDP_PSR_AUX_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
-- 
2.23.0

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[PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

TGL PSR2 HW supports a bigger resolution, so lets add it

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c33aa16ed038..5d24f1c47a2b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		psr_max_h = 5120;
+		psr_max_v = 3200;
+	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		psr_max_h = 4096;
 		psr_max_v = 2304;
 	} else if (IS_GEN(dev_priv, 9)) {
-- 
2.23.0

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[PATCH v3 10/23] drm/i915: Add for_each_new_intel_connector_in_state()

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e57e6969051d..fd3043e77b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -411,6 +411,14 @@ enum phy_fia {
 	     (__i)++) \
 		for_each_if(crtc)
 
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-- 
2.23.0

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[PATCH v3 11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
order.

v2: Fix additional blank line

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index fd3043e77b50..b63fb7a4599e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -419,6 +419,15 @@ enum phy_fia {
 			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)
+
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-- 
2.23.0

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[PATCH v3 12/23] drm/i915: Disable pipes in reverse order

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

Disable CRTC/pipes in reverse order because some features (MST in
TGL+) requires master and slave relationship between pipes, so it
should always pick the lowest pipe as master as it will be enabled
first and disable in the reverse order so the master will be the last
one to be disabled.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b51d1ceb8739..ddb8436e2208 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13908,7 +13908,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset)
 		wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
 
-	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+	/*
+	 * Disable CRTC/pipes in reverse order because some features(MST in
+	 * TGL+) requires master and slave relationship between pipes, so it
+	 * should always pick the lowest pipe as master as it will be enabled
+	 * first and disable in the reverse order so the master will be the
+	 * last one to be disabled.
+	 */
+	for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
+						    new_crtc_state, i) {
 		if (needs_modeset(new_crtc_state) ||
 		    new_crtc_state->update_pipe) {
 
-- 
2.23.0

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[PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.

So here it is picking the lowest pipe/transcoder as it will be
enabled first and disabled last.
BSpec: 50493
BSpec: 49190

v2: Missed set mst_master_trans to TRANSCODER_INVALID when computing HSW
    encoder config. HSW CRT hw state readout calls
    hsw_crt_get_config()->intel_ddi_get_config() that will set
    mst_master_trans to TRANSCODER_INVALID causing the mismatch when
    verifying CRTC state after a modeset. (José)

v3: Add WARN_ON() requested by Jani.
    Add FIXME. From Jani: double check PIPE_CONF_CHECK_I(mst_master_trans) - it's
    now checking for all platforms and MST and non-MST alike.
    Perhaps in general I'd like the approach of only doing the readout when
    it's relevant, and only checking the value when it's relevant.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  18 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  15 ++
 drivers/gpu/drm/i915/display/intel_display.h  |   3 +
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 159 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   3 +
 8 files changed, 202 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index e6e8d4a82044..503135200cb3 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -416,6 +416,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
 	/* FDI must always be 2.7 GHz */
 	pipe_config->port_clock = 135000 * 2;
 
+	pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8eb2b3ec01ed..f4cb6bd74421 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1840,6 +1840,13 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder master = crtc_state->mst_master_trans;
+
+			WARN_ON(master == TRANSCODER_INVALID);
+			temp |= TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(master);
+		}
 	} else {
 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
@@ -3861,6 +3868,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		break;
 	}
 
+	pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
 	case TRANS_DDI_MODE_SELECT_HDMI:
 		pipe_config->has_hdmi_sink = true;
@@ -3896,6 +3905,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
 		pipe_config->lane_count =
 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+		if (INTEL_GEN(dev_priv) >= 12) {
+			temp = temp & TRANS_DDI_MST_TRANSPORT_SELECT_MASK;
+			temp = temp >> TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT;
+			pipe_config->mst_master_trans = temp;
+		}
+
 		intel_dp_get_m_n(intel_crtc, pipe_config);
 		break;
 	default:
@@ -3998,6 +4014,8 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
+	pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ddb8436e2208..109d4fd961c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -47,6 +47,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -12138,6 +12139,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 
 	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
 
+	if (INTEL_GEN(dev_priv) >= 12 &&
+	    intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+		enum transcoder master = pipe_config->mst_master_trans;
+
+		DRM_DEBUG_KMS("master mst cpu_transcoder: %s\n",
+			      transcoder_name(master));
+	}
+
 dump_planes:
 	if (!state)
 		return;
@@ -12821,6 +12830,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
 	PIPE_CONF_CHECK_INFOFRAME(drm);
 
+	PIPE_CONF_CHECK_I(mst_master_trans);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_BOOL
@@ -13597,6 +13608,10 @@ static int intel_atomic_check(struct drm_device *dev,
 	int ret, i;
 	bool any_ms = state->cdclk.force_min_cdclk_changed;
 
+	ret = intel_dp_mst_atomic_add_affected_crtcs(state);
+	if (ret)
+		return ret;
+
 	/* Catch I915_MODE_FLAG_INHERITED */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b63fb7a4599e..282e8d8f1cc1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -91,6 +91,8 @@ enum pipe {
 #define pipe_name(p) ((p) + 'A')
 
 enum transcoder {
+	TRANSCODER_INVALID = -1,
+
 	/*
 	 * The following transcoders have a 1:1 transcoder -> pipe mapping,
 	 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
@@ -132,6 +134,7 @@ static inline const char *transcoder_name(enum transcoder transcoder)
 		return "DSI A";
 	case TRANSCODER_DSI_C:
 		return "DSI C";
+	case TRANSCODER_INVALID:
 	default:
 		return "<invalid>";
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 449abaea619f..d84a66459daf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -984,6 +984,9 @@ struct intel_crtc_state {
 
 	/* Forward Error correction State */
 	bool fec_enable;
+
+	/* Master transcoder for all streams, only used on TGL+ */
+	enum transcoder mst_master_trans;
 };
 
 struct intel_crtc {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2c5ac3dd647f..8002dca9b734 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,50 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+/*
+ * Iterate over all the CRTCs and return the transcoder of the lowest CRTC that
+ * share the same MST connector.
+ */
+static enum transcoder
+mst_compute_master_trans(struct drm_atomic_state *state,
+			 struct drm_connector *mst_conn)
+{
+	struct intel_connector *intel_mst_conn = to_intel_connector(mst_conn);
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct intel_crtc_state *intel_crtc_state;
+	struct intel_crtc *intel_crtc;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return TRANSCODER_INVALID;
+
+	/* Iterate from the lowest to the highest pipe */
+	for_each_new_intel_crtc_in_state(intel_state, intel_crtc, intel_crtc_state, i) {
+		struct intel_digital_connector_state *intel_conn_state;
+		struct intel_connector *intel_conn;
+		int j;
+
+		if (!intel_crtc_state->base.active)
+			continue;
+
+		for_each_new_intel_connector_in_state(intel_state, intel_conn,
+						      intel_conn_state, j) {
+			/* Only care about connectors of this CRTC */
+			if (intel_conn_state->base.crtc !=
+			    intel_crtc_state->base.crtc)
+				continue;
+
+			if (intel_conn->mst_port != intel_mst_conn->mst_port)
+				continue;
+
+			return intel_crtc_state->cpu_transcoder;
+		}
+	}
+
+	return TRANSCODER_INVALID;
+}
+
 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 				       struct intel_crtc_state *pipe_config,
 				       struct drm_connector_state *conn_state)
@@ -94,14 +138,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
 	struct intel_dp *intel_dp = &intel_mst->primary->dp;
-	struct intel_connector *connector =
-		to_intel_connector(conn_state->connector);
+	struct drm_connector *connector = conn_state->connector;
+	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct intel_digital_connector_state *intel_conn_state =
 		to_intel_digital_connector_state(conn_state);
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->base.adjusted_mode;
-	void *port = connector->port;
+	void *port = intel_connector->port;
 	struct link_config_limits limits;
+	enum transcoder master;
 	int ret;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -146,6 +191,51 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
+	master = mst_compute_master_trans(conn_state->state, connector);
+	pipe_config->mst_master_trans = master;
+
+	return 0;
+}
+
+static int
+intel_dp_mst_master_trans_check(struct drm_connector *conn,
+				struct drm_connector_state *new_conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(conn->dev);
+	struct drm_atomic_state *state = new_conn_state->state;
+	struct drm_connector_state *old_conn_state =
+		drm_atomic_get_old_connector_state(state, conn);
+	struct drm_crtc *new_crtc = new_conn_state->crtc;
+	struct drm_crtc *old_crtc = old_conn_state->crtc;
+	enum transcoder old_master_trans = TRANSCODER_INVALID;
+	enum transcoder new_master_trans = TRANSCODER_INVALID;
+	struct drm_crtc_state *new_crtc_state, *old_crtc_state;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	if (old_crtc) {
+		struct intel_crtc_state *intel_crtc_state;
+
+		old_crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc);
+		intel_crtc_state = to_intel_crtc_state(old_crtc_state);
+		old_master_trans = intel_crtc_state->mst_master_trans;
+	}
+
+	if (new_crtc) {
+		struct intel_crtc_state *intel_crtc_state;
+
+		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
+		intel_crtc_state = to_intel_crtc_state(new_crtc_state);
+		new_master_trans = mst_compute_master_trans(state, conn);
+	}
+
+	if (old_crtc && old_master_trans != new_master_trans)
+		old_crtc_state->mode_changed = true;
+
+	if (new_crtc && old_master_trans != new_master_trans)
+		new_crtc_state->mode_changed = true;
+
 	return 0;
 }
 
@@ -168,6 +258,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	ret = intel_dp_mst_master_trans_check(connector, new_conn_state);
+	if (ret)
+		return ret;
+
 	if (!old_conn_state->crtc)
 		return 0;
 
@@ -674,3 +768,62 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
 	/* encoders will get killed by normal cleanup */
 }
+
+/**
+ * intel_dp_mst_atomic_add_affected_crtcs - Add all CRTCs that share the MST
+ * stream with the CRTCs in the current atomic state.
+ * @state: state to add CRTCs
+ *
+ * It is needed add the CRTCs trigger a call to atomic_check() to
+ * every connector attached to the CRTC in case a new master transcoder will
+ * be needed.
+ */
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_digital_connector_state *intel_conn_state;
+	struct drm_device *dev = state->base.dev;
+	struct intel_connector *intel_conn;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	for_each_new_intel_connector_in_state(state, intel_conn, intel_conn_state, i) {
+		struct drm_connector_list_iter conn_list_iter;
+		struct drm_connector *conn_iter;
+
+		if (!intel_conn->mst_port)
+			continue;
+
+		drm_connector_list_iter_begin(dev, &conn_list_iter);
+		drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+			struct drm_connector_state *conn_iter_state;
+			struct intel_connector *intel_conn_iter;
+			struct drm_crtc_state *crtc_state;
+
+			intel_conn_iter = to_intel_connector(conn_iter);
+
+			if (intel_conn_iter->mst_port != intel_conn->mst_port)
+				continue;
+
+			conn_iter_state = drm_atomic_get_connector_state(&state->base, conn_iter);
+			if (IS_ERR(conn_iter_state)) {
+				drm_connector_list_iter_end(&conn_list_iter);
+				return PTR_ERR(conn_iter_state);
+			}
+			if (!conn_iter_state->crtc)
+				continue;
+
+			crtc_state = drm_atomic_get_crtc_state(&state->base,
+							       conn_iter_state->crtc);
+			if (IS_ERR(crtc_state)) {
+				drm_connector_list_iter_end(&conn_list_iter);
+				return PTR_ERR(crtc_state);
+			}
+		}
+		drm_connector_list_iter_end(&conn_list_iter);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..173598aa81d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -6,10 +6,12 @@
 #ifndef __INTEL_DP_MST_H__
 #define __INTEL_DP_MST_H__
 
+struct intel_atomic_state;
 struct intel_digital_port;
 
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state);
 int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
 
 #endif /* __INTEL_DP_MST_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3de02683d856..bff9ee191832 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9424,6 +9424,9 @@ enum skl_power_gate {
 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
+#define  TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT		10 /* TGL+ */
+#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK		(0x3 << 10)
+#define  TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(trans)	((trans) << 10)
 #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder

[Lucas De Marchi]

Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 42 ++++++++----
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 66 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |  9 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 20 ++++--
 drivers/gpu/drm/i915/i915_reg.h               |  4 ++
 6 files changed, 119 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f4cb6bd74421..3eb73dbaf9fd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3136,17 +3136,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
+	i915_reg_t ctl, status;
 	u32 val;
 
 	if (!crtc_state->fec_enable)
 		return;
 
-	val = I915_READ(DP_TP_CTL(port));
+	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+	val = I915_READ(ctl);
 	val |= DP_TP_CTL_FEC_ENABLE;
-	I915_WRITE(DP_TP_CTL(port), val);
+	I915_WRITE(ctl, val);
 
-	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+	if (intel_de_wait_for_set(dev_priv, status,
 				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
 		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
 }
@@ -3155,16 +3160,19 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 					const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
+	i915_reg_t ctl;
 	u32 val;
 
 	if (!crtc_state->fec_enable)
 		return;
 
-	val = I915_READ(DP_TP_CTL(port));
+	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+	val = I915_READ(ctl);
 	val &= ~DP_TP_CTL_FEC_ENABLE;
-	I915_WRITE(DP_TP_CTL(port), val);
-	POSTING_READ(DP_TP_CTL(port));
+	I915_WRITE(ctl, val);
+	POSTING_READ(ctl);
 }
 
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3326,7 +3334,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
+	i915_reg_t ctl;
 	bool wait = false;
 	u32 val;
 
@@ -3337,10 +3347,11 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 		wait = true;
 	}
 
-	val = I915_READ(DP_TP_CTL(port));
+	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+	val = I915_READ(ctl);
 	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-	I915_WRITE(DP_TP_CTL(port), val);
+	I915_WRITE(ctl, val);
 
 	/* Disable FEC in DP Sink */
 	intel_ddi_disable_fec_state(encoder, crtc_state);
@@ -3765,10 +3776,13 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv =
 		to_i915(intel_dig_port->base.base.dev);
 	enum port port = intel_dig_port->base.port;
+	i915_reg_t ctl;
 	u32 val;
 	bool wait = false;
+	enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
 
-	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+	if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
 		val = I915_READ(DDI_BUF_CTL(port));
 		if (val & DDI_BUF_CTL_ENABLE) {
 			val &= ~DDI_BUF_CTL_ENABLE;
@@ -3776,11 +3790,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 			wait = true;
 		}
 
-		val = I915_READ(DP_TP_CTL(port));
+		val = I915_READ(ctl);
 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		I915_WRITE(DP_TP_CTL(port), val);
-		POSTING_READ(DP_TP_CTL(port));
+		I915_WRITE(ctl, val);
+		POSTING_READ(ctl);
 
 		if (wait)
 			intel_wait_ddi_buf_idle(dev_priv, port);
@@ -3795,8 +3809,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
 	}
-	I915_WRITE(DP_TP_CTL(port), val);
-	POSTING_READ(DP_TP_CTL(port));
+	I915_WRITE(ctl, val);
+	POSTING_READ(ctl);
 
 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d84a66459daf..a87fa06994ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1214,6 +1214,7 @@ struct intel_dp {
 	bool can_mst; /* this port supports mst */
 	bool is_mst;
 	int active_mst_links;
+	enum transcoder mst_master_trans; /* Only valid on TGL+ */
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 23908da1cd5d..943392faaea2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3209,6 +3209,51 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
 	vlv_dpio_put(dev_priv);
 }
 
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+			       enum transcoder cpu_transcoder,
+			       enum port port)
+{
+	if (INTEL_GEN(dev_priv) >= 12) {
+		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+		return TGL_DP_TP_CTL(cpu_transcoder);
+	} else {
+		return DP_TP_CTL(port);
+	}
+}
+
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+				  enum transcoder cpu_transcoder,
+				  enum port port)
+{
+	if (INTEL_GEN(dev_priv) >= 12) {
+		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+		return TGL_DP_TP_STATUS(cpu_transcoder);
+	} else {
+		return DP_TP_STATUS(port);
+	}
+}
+
+/*
+ * Return the transcoder that this intel_dp port is driven.
+ * When in MST mode it will return the master transcoder of the MST so do not
+ * use it when reading or writing registers in the slave transcoders.
+ */
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp)
+{
+	struct intel_connector *connector;
+	struct drm_connector_state *conn_state;
+	struct intel_crtc_state *crtc_state;
+
+	if (intel_dp->is_mst)
+		return intel_dp->mst_master_trans;
+
+	connector = intel_dp->attached_connector;
+	conn_state = connector->base.state;
+	crtc_state = to_intel_crtc_state(conn_state->crtc->state);
+
+	return crtc_state->cpu_transcoder;
+}
+
 static void
 _intel_dp_set_link_train(struct intel_dp *intel_dp,
 			 u32 *DP,
@@ -3224,8 +3269,13 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
 			      dp_train_pat & train_pat_mask);
 
 	if (HAS_DDI(dev_priv)) {
-		u32 temp = I915_READ(DP_TP_CTL(port));
+		enum transcoder cpu_transcoder;
+		i915_reg_t ctl;
+		u32 temp;
 
+		cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+		ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+		temp = I915_READ(ctl);
 		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
 			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
 		else
@@ -3250,7 +3300,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
 			temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
 			break;
 		}
-		I915_WRITE(DP_TP_CTL(port), temp);
+		I915_WRITE(ctl, temp);
 
 	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
 		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -3943,15 +3993,21 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->base.port;
+	enum transcoder cpu_transcoder;
+	i915_reg_t ctl, status;
 	u32 val;
 
 	if (!HAS_DDI(dev_priv))
 		return;
 
-	val = I915_READ(DP_TP_CTL(port));
+	cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+	val = I915_READ(ctl);
 	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
 	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
-	I915_WRITE(DP_TP_CTL(port), val);
+	I915_WRITE(ctl, val);
 
 	/*
 	 * On PORT_A we can have only eDP in SST mode. There the only reason
@@ -3963,7 +4019,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 	if (port == PORT_A)
 		return;
 
-	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+	if (intel_de_wait_for_set(dev_priv, status,
 				  DP_TP_STATUS_IDLE_DONE, 1))
 		DRM_ERROR("Timed out waiting for DP idle patterns\n");
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..107129b5d9a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -11,6 +11,7 @@
 #include <drm/i915_drm.h>
 
 #include "i915_reg.h"
+#include "intel_display.h"
 
 enum pipe;
 struct drm_connector_state;
@@ -113,6 +114,14 @@ int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+			       enum transcoder cpu_transcoder,
+			       enum port port);
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+				  enum transcoder cpu_transcoder,
+				  enum port port);
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp);
+
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
 	return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8002dca9b734..630db2fadaca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -354,9 +354,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
 
-	if (intel_dp->active_mst_links == 0)
+	if (intel_dp->active_mst_links == 0) {
+		intel_dp->mst_master_trans = pipe_config->mst_master_trans;
 		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
 						    pipe_config, NULL);
+	}
 }
 
 static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
@@ -384,6 +386,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 	enum port port = intel_dig_port->base.port;
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
+	i915_reg_t status;
 	int ret;
 	u32 temp;
 
@@ -412,8 +415,12 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 		DRM_ERROR("failed to allocate vcpi\n");
 
 	intel_dp->active_mst_links++;
-	temp = I915_READ(DP_TP_STATUS(port));
-	I915_WRITE(DP_TP_STATUS(port), temp);
+
+	status = intel_dp_tp_status_reg(dev_priv,
+					pipe_config->mst_master_trans,
+					port);
+	temp = I915_READ(status);
+	I915_WRITE(status, temp);
 
 	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
 
@@ -429,10 +436,15 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = intel_dig_port->base.port;
+	i915_reg_t status;
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+	status = intel_dp_tp_status_reg(dev_priv,
+					pipe_config->mst_master_trans,
+					port);
+
+	if (intel_de_wait_for_set(dev_priv, status,
 				  DP_TP_STATUS_ACT_SENT, 1))
 		DRM_ERROR("Timed out waiting for ACT sent\n");
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bff9ee191832..fffaed0ca3cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9454,7 +9454,9 @@ enum skl_power_gate {
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A			0x64040
 #define _DP_TP_CTL_B			0x64140
+#define _TGL_DP_TP_CTL_A		0x60540
 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
 #define  DP_TP_CTL_ENABLE			(1 << 31)
 #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
 #define  DP_TP_CTL_MODE_SST			(0 << 27)
@@ -9474,7 +9476,9 @@ enum skl_power_gate {
 /* DisplayPort Transport Status */
 #define _DP_TP_STATUS_A			0x64044
 #define _DP_TP_STATUS_B			0x64144
+#define _TGL_DP_TP_STATUS_A		0x60544
 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
 #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
-- 
2.23.0

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[PATCH v3 15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.

I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was added with comments of all steps. It's similar to ICL,
but different enough to deserve a new function.

The rest of DisplayPort enable and the whole disable sequences
remained the same.

v2: FEC and DSC should be enabled on sink side before start link
training(Maarten reported and Manasi confirmed the DSC part)

v3: Add call to enable FEC on step 7.l(Manasi)

BSpec: 49190
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 139 ++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c  |   8 +-
 2 files changed, 139 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3eb73dbaf9fd..60017a5f5fa8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1761,7 +1761,14 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
+/*
+ * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
+ *
+ * Only intended to be used by intel_ddi_enable_transcoder_func() and
+ * intel_ddi_config_transcoder_func().
+ */
+static u32
+intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
@@ -1852,6 +1859,33 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 	}
 
+	return temp;
+}
+
+void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 temp;
+
+	temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
+}
+
+/*
+ * Same as intel_ddi_enable_transcoder_func() but it do not set the enable bit
+ */
+static void
+intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 temp;
+
+	temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+	temp &= ~TRANS_DDI_FUNC_ENABLE;
 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
@@ -3175,9 +3209,94 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 	POSTING_READ(ctl);
 }
 
-static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *crtc_state,
-				    const struct drm_connector_state *conn_state)
+static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+	int level = intel_ddi_dp_level(intel_dp);
+
+	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
+				 crtc_state->lane_count, is_mst);
+
+	/* 1.a got on intel_atomic_commit_tail() */
+
+	/* 2. */
+	intel_edp_panel_on(intel_dp);
+
+	/*
+	 * 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by:
+	 * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
+	 * haswell_crtc_enable()->intel_enable_shared_dpll()
+	 */
+
+	/* 5. */
+	if (!intel_phy_is_tc(dev_priv, phy) ||
+	    dig_port->tc_mode != TC_PORT_TBT_ALT)
+		intel_display_power_get(dev_priv,
+					dig_port->ddi_io_power_domain);
+
+	/* 6. */
+	icl_program_mg_dp_mode(dig_port);
+
+	/*
+	 * 7.a - Steps in this function should only be executed over MST
+	 * master, what will be taken in care by MST hook
+	 * intel_mst_pre_enable_dp()
+	 */
+	intel_ddi_enable_pipe_clock(crtc_state);
+
+	/* 7.b */
+	intel_ddi_config_transcoder_func(crtc_state);
+
+	/* 7.d */
+	icl_disable_phy_clock_gating(dig_port);
+
+	/* 7.e */
+	icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
+				encoder->type);
+
+	/* 7.f */
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		bool lane_reversal =
+			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+
+		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
+					       crtc_state->lane_count,
+					       lane_reversal);
+	}
+
+	/* 7.g */
+	intel_ddi_init_dp_buf_reg(encoder);
+
+	if (!is_mst)
+		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
+	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+	/*
+	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
+	 * in the FEC_CONFIGURATION register to 1 before initiating link
+	 * training
+	 */
+	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+	/* 7.c, 7.h, 7.i, 7.j */
+	intel_dp_start_link_train(intel_dp);
+
+	/* 7.k */
+	intel_dp_stop_link_train(intel_dp);
+
+	/* 7.l */
+	intel_ddi_enable_fec(encoder, crtc_state);
+	intel_dsc_enable(encoder, crtc_state);
+}
+
+static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3243,6 +3362,18 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_dsc_enable(encoder, crtc_state);
 }
 
+static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+	else
+		hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+}
+
 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state,
 				      const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 943392faaea2..ece6375bf65d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4010,13 +4010,13 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 	I915_WRITE(ctl, val);
 
 	/*
-	 * On PORT_A we can have only eDP in SST mode. There the only reason
-	 * we need to set idle transmission mode is to work around a HW issue
-	 * where we enable the pipe while not in idle link-training mode.
+	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
+	 * reason we need to set idle transmission mode is to work around a HW
+	 * issue where we enable the pipe while not in idle link-training mode.
 	 * In this case there is requirement to wait for a minimum number of
 	 * idle patterns to be sent.
 	 */
-	if (port == PORT_A)
+	if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
 		return;
 
 	if (intel_de_wait_for_set(dev_priv, status,
-- 
2.23.0

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[PATCH v3 16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2a425db1cfd8..189b27bf33a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2027,7 +2027,7 @@ static void gtt_write_workarounds(struct intel_gt *gt)
 		intel_uncore_write(uncore,
 				   GEN8_L3_LRA_1_GPGPU,
 				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
-	else if (INTEL_GEN(i915) >= 9)
+	else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
 		intel_uncore_write(uncore,
 				   GEN8_L3_LRA_1_GPGPU,
 				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
-- 
2.23.0

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[PATCH v3 17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.

The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.

FIXME: https://patchwork.freedesktop.org/patch/324479/?series=65290&rev=4

Bspec: 46255
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c     | 156 +++++++++++++++++-------
 drivers/gpu/drm/i915/gt/intel_lrc.h     |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h |  30 ++++-
 3 files changed, 143 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d42584439f51..6b7c0a7f7ec3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3149,28 +3149,12 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
 	return indirect_ctx_offset;
 }
 
-static void execlists_init_reg_state(u32 *regs,
-				     struct intel_context *ce,
-				     struct intel_engine_cs *engine,
-				     struct intel_ring *ring)
+static void init_common_reg_state(u32 *regs,
+				  struct intel_engine_cs *engine,
+				  struct intel_ring *ring)
 {
-	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
-	bool rcs = engine->class == RENDER_CLASS;
 	u32 base = engine->mmio_base;
 
-	/*
-	 * A context is actually a big batch buffer with several
-	 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
-	 * values we are setting here are only for the first context restore:
-	 * on a subsequent save, the GPU will recreate this batchbuffer with new
-	 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
-	 * we are not initializing here).
-	 *
-	 * Must keep consistent with virtual_update_register_offsets().
-	 */
-	regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
-				 MI_LRI_FORCE_POSTED;
-
 	CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
 		_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
 		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
@@ -3187,38 +3171,44 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
 	CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
 	CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
-	CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
-	CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
-	CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
-	if (rcs) {
-		struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-
-		CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
-		CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
-			RING_INDIRECT_CTX_OFFSET(base), 0);
-		if (wa_ctx->indirect_ctx.size) {
-			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+}
 
-			regs[CTX_RCS_INDIRECT_CTX + 1] =
-				(ggtt_offset + wa_ctx->indirect_ctx.offset) |
-				(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+static void init_wa_bb_reg_state(u32 *regs,
+				 struct intel_engine_cs *engine,
+				 u32 pos_bb_per_ctx)
+{
+	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
+	u32 base = engine->mmio_base;
+	u32 pos_indirect_ctx = pos_bb_per_ctx + 2;
+	u32 pos_indirect_ctx_offset = pos_indirect_ctx + 2;
 
-			regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
-				intel_lr_indirect_ctx_offset(engine) << 6;
-		}
+	GEM_BUG_ON(engine->id != RCS0);
+	CTX_REG(regs, pos_indirect_ctx, RING_INDIRECT_CTX(base), 0);
+	CTX_REG(regs, pos_indirect_ctx_offset,
+		RING_INDIRECT_CTX_OFFSET(base), 0);
+	if (wa_ctx->indirect_ctx.size) {
+		u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
 
-		CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
-		if (wa_ctx->per_ctx.size) {
-			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+		regs[pos_indirect_ctx + 1] =
+			(ggtt_offset + wa_ctx->indirect_ctx.offset) |
+			(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
 
-			regs[CTX_BB_PER_CTX_PTR + 1] =
-				(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
-		}
+		regs[pos_indirect_ctx_offset + 1] =
+			intel_lr_indirect_ctx_offset(engine) << 6;
 	}
 
-	regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
+	CTX_REG(regs, pos_bb_per_ctx, RING_BB_PER_CTX_PTR(base), 0);
+	if (wa_ctx->per_ctx.size) {
+		u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
 
-	CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+		regs[pos_bb_per_ctx + 1] =
+			(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
+	}
+}
+
+static void init_ppgtt_reg_state(u32 *regs, u32 base,
+				 struct i915_ppgtt *ppgtt)
+{
 	/* PDP values well be assigned later if needed */
 	CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
 	CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
@@ -3241,6 +3231,32 @@ static void execlists_init_reg_state(u32 *regs,
 		ASSIGN_CTX_PDP(ppgtt, regs, 1);
 		ASSIGN_CTX_PDP(ppgtt, regs, 0);
 	}
+}
+
+static void gen8_init_reg_state(u32 *regs,
+				struct intel_context *ce,
+				struct intel_engine_cs *engine,
+				struct intel_ring *ring)
+{
+	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
+	bool rcs = engine->class == RENDER_CLASS;
+	u32 base = engine->mmio_base;
+
+	regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
+				 MI_LRI_FORCE_POSTED;
+
+	init_common_reg_state(regs, engine, ring);
+	CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
+	CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
+	CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
+	if (rcs)
+		init_wa_bb_reg_state(regs, engine, CTX_BB_PER_CTX_PTR);
+
+	regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
+
+	CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+
+	init_ppgtt_reg_state(regs, base, ppgtt);
 
 	if (rcs) {
 		regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
@@ -3252,6 +3268,58 @@ static void execlists_init_reg_state(u32 *regs,
 		regs[CTX_END] |= BIT(0);
 }
 
+static void gen12_init_reg_state(u32 *regs,
+				 struct intel_context *ce,
+				 struct intel_engine_cs *engine,
+				 struct intel_ring *ring)
+{
+	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
+	bool rcs = engine->class == RENDER_CLASS;
+	u32 base = engine->mmio_base;
+
+	GEM_DEBUG_EXEC(DRM_INFO_ONCE("Using GEN12 Register State Context\n"));
+
+	regs[GEN12_CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(13) |
+				       MI_LRI_FORCE_POSTED;
+
+	init_common_reg_state(regs, engine, ring);
+	if (rcs)
+		init_wa_bb_reg_state(regs, engine, GEN12_CTX_BB_PER_CTX_PTR);
+
+	regs[GEN12_CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) |
+				       MI_LRI_FORCE_POSTED;
+
+	CTX_REG(regs, GEN12_CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+
+	init_ppgtt_reg_state(regs, base, ppgtt);
+
+	if (rcs) {
+		regs[GEN12_CTX_LRI_HEADER_3] = MI_LOAD_REGISTER_IMM(1);
+		CTX_REG(regs, GEN12_CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+			0);
+
+		/* TODO: oa_init_reg_state ? */
+	}
+}
+
+static void execlists_init_reg_state(u32 *regs,
+				     struct intel_context *ce,
+				     struct intel_engine_cs *engine,
+				     struct intel_ring *ring)
+{
+	/* A context is actually a big batch buffer with several
+	 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
+	 * values we are setting here are only for the first context restore:
+	 * on a subsequent save, the GPU will recreate this batchbuffer with new
+	 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
+	 * we are not initializing here).
+	 */
+	if (INTEL_GEN(engine->i915) >= 12)
+		gen12_init_reg_state(regs, ce, engine, ring);
+	else
+		gen8_init_reg_state(regs, ce, engine, ring);
+}
+
 static int
 populate_lr_context(struct intel_context *ce,
 		    struct drm_i915_gem_object *ctx_obj,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index c2bba82bcc16..69285d354d9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -49,6 +49,8 @@ struct intel_engine_cs;
 
 #define	  EL_CTRL_LOAD				(1 << 0)
 
+#define GEN12_ENGINE_SEMAPHORE_TOKEN(engine)	_MMIO((engine)->mmio_base + 0x2b4)
+
 /* The docs specify that the write pointer wraps around after 5h, "After status
  * is written out to the last available status QW at offset 5h, this pointer
  * wraps to 0."
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index b8f20ad71169..b7695b96e484 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -9,7 +9,7 @@
 
 #include <linux/types.h>
 
-/* GEN8+ Reg State Context */
+/* GEN8 to GEN11 Reg State Context */
 #define CTX_LRI_HEADER_0		0x01
 #define CTX_CONTEXT_CONTROL		0x02
 #define CTX_RING_HEAD			0x04
@@ -39,6 +39,34 @@
 #define CTX_R_PWR_CLK_STATE		0x42
 #define CTX_END				0x44
 
+/* GEN12+ Reg State Context */
+#define GEN12_CTX_LRI_HEADER_0			CTX_LRI_HEADER_0
+#define GEN12_CTX_CONTEXT_CONTROL		CTX_CONTEXT_CONTROL
+#define GEN12_CTX_RING_HEAD			CTX_RING_HEAD
+#define GEN12_CTX_RING_TAIL			CTX_RING_TAIL
+#define GEN12_CTX_RING_BUFFER_START		CTX_RING_BUFFER_START
+#define GEN12_CTX_RING_BUFFER_CONTROL		CTX_RING_BUFFER_CONTROL
+#define GEN12_CTX_BB_HEAD_U			CTX_BB_HEAD_U
+#define GEN12_CTX_BB_HEAD_L			CTX_BB_HEAD_L
+#define GEN12_CTX_BB_STATE			CTX_BB_STATE
+#define GEN12_CTX_BB_PER_CTX_PTR		0x12
+#define GEN12_CTX_RCS_INDIRECT_CTX		0x14
+#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET	0x16
+#define GEN12_CTX_LRI_HEADER_1			CTX_LRI_HEADER_1
+#define GEN12_CTX_CTX_TIMESTAMP			CTX_CTX_TIMESTAMP
+#define GEN12_CTX_PDP3_UDW			CTX_PDP3_UDW
+#define GEN12_CTX_PDP3_LDW			CTX_PDP3_LDW
+#define GEN12_CTX_PDP2_UDW			CTX_PDP2_UDW
+#define GEN12_CTX_PDP2_LDW			CTX_PDP2_LDW
+#define GEN12_CTX_PDP1_UDW			CTX_PDP1_UDW
+#define GEN12_CTX_PDP1_LDW			CTX_PDP1_LDW
+#define GEN12_CTX_PDP0_UDW			CTX_PDP0_UDW
+#define GEN12_CTX_PDP0_LDW			CTX_PDP0_LDW
+#define GEN12_CTX_LRI_HEADER_2			0x34
+#define GEN12_CTX_LRI_HEADER_3			0x41
+#define GEN12_CTX_R_PWR_CLK_STATE		0x42
+#define GEN12_CTX_GPGPU_CSR_BASE_ADDRESS	0x44
+
 #define CTX_REG(reg_state, pos, reg, val) do { \
 	u32 *reg_state__ = (reg_state); \
 	const u32 pos__ = (pos); \
-- 
2.23.0

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[PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e42b86827d6b..2c9f46e12622 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 		}
 		break;
 
-	case 11: {
+	case 11:
+	case 12: {
 		stream->specific_ctx_id_mask =
 			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
 			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
-- 
2.23.0

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[PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support

[Lucas De Marchi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Yf tiling was removed in gen-12, make the necessary to changes to not
expose the modifier to user space. Gen-12 display also is incompatible with
pre-gen12 Y-tiled compression, so do not expose
I915_FORMAT_MOD_Y_TILED_CCS.

Bspec: 29650

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 73 +++++++++++++++++++--
 1 file changed, 67 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index dea63be1964f..71dae3c2f9db 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2157,6 +2157,13 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
+static const u64 gen12_plane_format_modifiers_noccs[] = {
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
 					    u32 format, u64 modifier)
 {
@@ -2305,6 +2312,42 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
+					     u32 format, u64 modifier)
+{
+	switch (modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+	case I915_FORMAT_MOD_X_TILED:
+	case I915_FORMAT_MOD_Y_TILED:
+		break;
+	default:
+		return false;
+	}
+
+	switch (format) {
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_ABGR8888:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_YUYV:
+	case DRM_FORMAT_YVYU:
+	case DRM_FORMAT_UYVY:
+	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_C8:
+		if (modifier == DRM_FORMAT_MOD_LINEAR ||
+		    modifier == I915_FORMAT_MOD_X_TILED ||
+		    modifier == I915_FORMAT_MOD_Y_TILED)
+			return true;
+		/* fall through */
+	default:
+		return false;
+	}
+}
+
 static const struct drm_plane_funcs g4x_sprite_funcs = {
 	.update_plane = drm_atomic_helper_update_plane,
 	.disable_plane = drm_atomic_helper_disable_plane,
@@ -2341,6 +2384,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
 	.format_mod_supported = skl_plane_format_mod_supported,
 };
 
+static const struct drm_plane_funcs gen12_plane_funcs = {
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane = drm_atomic_helper_disable_plane,
+	.destroy = intel_plane_destroy,
+	.atomic_duplicate_state = intel_plane_duplicate_state,
+	.atomic_destroy_state = intel_plane_destroy_state,
+	.format_mod_supported = gen12_plane_format_mod_supported,
+};
+
 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2429,6 +2481,7 @@ struct intel_plane *
 skl_universal_plane_create(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, enum plane_id plane_id)
 {
+	static const struct drm_plane_funcs *plane_funcs;
 	struct intel_plane *plane;
 	enum drm_plane_type plane_type;
 	unsigned int supported_rotations;
@@ -2471,11 +2524,19 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
-	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
-	if (plane->has_ccs)
-		modifiers = skl_plane_format_modifiers_ccs;
-	else
-		modifiers = skl_plane_format_modifiers_noccs;
+	if (INTEL_GEN(dev_priv) >= 12) {
+		/* TODO: Implement support for gen-12 CCS modifiers */
+		plane->has_ccs = false;
+		modifiers = gen12_plane_format_modifiers_noccs;
+		plane_funcs = &gen12_plane_funcs;
+	} else {
+		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
+		if (plane->has_ccs)
+			modifiers = skl_plane_format_modifiers_ccs;
+		else
+			modifiers = skl_plane_format_modifiers_noccs;
+		plane_funcs = &skl_plane_funcs;
+	}
 
 	if (plane_id == PLANE_PRIMARY)
 		plane_type = DRM_PLANE_TYPE_PRIMARY;
@@ -2485,7 +2546,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	possible_crtcs = BIT(pipe);
 
 	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
-				       possible_crtcs, &skl_plane_funcs,
+				       possible_crtcs, plane_funcs,
 				       formats, num_formats, modifiers,
 				       plane_type,
 				       "plane %d%c", plane_id + 1,
-- 
2.23.0

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[PATCH v3 20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression

[Lucas De Marchi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..fb7270bf9670 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,16 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.23.0

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[PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression

[Lucas De Marchi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modifier to identify
gen-12 compression. Another notable change is that decompression is
supported on all planes except cursor and on all pipes. This patch adds
decompression support for [A,X]BGR888 pixel formats.

Bspec: 18437

v2: Fix checkpatch warnings (Lucas)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++---
 2 files changed, 71 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 109d4fd961c6..190adbffe055 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (color_plane == 1)
+			return cpp;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 4 * 4 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return modifier == DRM_FORMAT_MOD_LINEAR ||
+	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2429,6 +2436,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2480,8 +2506,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2490,7 +2520,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2659,7 +2690,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			int main_x, main_y;
 			int ccs_x, ccs_y;
 
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
+			if (!is_surface_linear(fb->modifier, i)) {
+				intel_tile_dims(fb, i, &tile_width, &tile_height);
+			} else {
+				tile_width = 64 / cpp;
+				tile_height = 1;
+			}
+
 			tile_width *= hsub;
 			tile_height *= vsub;
 
@@ -4053,6 +4090,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
@@ -9828,7 +9867,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
@@ -15695,6 +15736,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		    is_ccs_modifier(fb->modifier))
 			stride_alignment *= 4;
 
+		/*
+		 * The main surface pitch must be paded to a multiple of four
+		 * tile widths.
+		 */
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+		    i == 0)
+			stride_alignment *= 4;
+
 		if (fb->pitches[i] & (stride_alignment - 1)) {
 			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 				      i, fb->pitches[i], stride_alignment);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 71dae3c2f9db..73d32017be89 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->base.dst.x1;
 	int crtc_y = plane_state->base.dst.y1;
@@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		u32 cus_ctl = 0;
@@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2524,13 +2533,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
-- 
2.23.0

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[PATCH v3 22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression

[Lucas De Marchi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fb7270bf9670..ec8351922265 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -420,6 +420,16 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.23.0

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[PATCH v3 23/23] drm/i915/tgl: Gen-12 media compression

[Lucas De Marchi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render compressed
buffers. Unlike render decompression, plane 6 and  plane 7 do not support
media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

Bspec: 29695

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_sprite.c  | 20 +++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 190adbffe055..18ff4631f873 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		if (color_plane == 1)
 			return cpp;
 		/* fall through */
@@ -2050,6 +2051,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return 4 * 4 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2248,8 +2250,15 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR ||
-	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+	switch (modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+		return true;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return color_plane == 1;
+	default:
+		return false;
+	}
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2437,6 +2446,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2510,6 +2520,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 					  ARRAY_SIZE(skl_ccs_formats),
 					  cmd->pixel_format);
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
@@ -2521,6 +2532,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -4093,6 +4105,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9870,6 +9884,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
@@ -15740,7 +15756,8 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		 * The main surface pitch must be paded to a multiple of four
 		 * tile widths.
 		 */
-		if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+		if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+		     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
 		    i == 0)
 			stride_alignment *= 4;
 
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 73d32017be89..5df3a899068e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1749,7 +1749,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2163,6 +2164,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 
 static const u64 gen12_plane_format_modifiers_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2320,7 +2322,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (plane->id >= PLANE_SPRITE4)
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2338,14 +2346,18 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
+	/* TODO: Media decompression does support NV12 */
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_C8:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fffaed0ca3cd..186ee8215f46 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6684,6 +6684,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.23.0

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Re: [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl

[Lionel Landwerlin]

On 23/08/2019 10:20, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
> since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
> will use the correct one.
>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>


> ---
>   drivers/gpu/drm/i915/i915_perf.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index e42b86827d6b..2c9f46e12622 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>   		}
>   		break;
>   
> -	case 11: {
> +	case 11:
> +	case 12: {
>   		stream->specific_ctx_id_mask =
>   			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
>   			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |


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Re: [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder

[Ville Syrjälä]

On Fri, Aug 23, 2019 at 01:20:46AM -0700, Lucas De Marchi wrote:
> Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
> than port-based. This add the new register address and changes the
> functions that are used with DDI on gen 12 to use the new registers. On
> MST the master transcoder is the one to be used.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 42 ++++++++----
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 66 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dp.h       |  9 +++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 20 ++++--
>  drivers/gpu/drm/i915/i915_reg.h               |  4 ++
>  6 files changed, 119 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index f4cb6bd74421..3eb73dbaf9fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3136,17 +3136,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
>  				 const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	enum port port = encoder->port;
> +	i915_reg_t ctl, status;
>  	u32 val;
>  
>  	if (!crtc_state->fec_enable)
>  		return;
>  
> -	val = I915_READ(DP_TP_CTL(port));
> +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
> +
> +	val = I915_READ(ctl);
>  	val |= DP_TP_CTL_FEC_ENABLE;
> -	I915_WRITE(DP_TP_CTL(port), val);
> +	I915_WRITE(ctl, val);
>  
> -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> +	if (intel_de_wait_for_set(dev_priv, status,
>  				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
>  		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
>  }
> @@ -3155,16 +3160,19 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
>  					const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	enum port port = encoder->port;
> +	i915_reg_t ctl;
>  	u32 val;
>  
>  	if (!crtc_state->fec_enable)
>  		return;
>  
> -	val = I915_READ(DP_TP_CTL(port));
> +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +	val = I915_READ(ctl);
>  	val &= ~DP_TP_CTL_FEC_ENABLE;
> -	I915_WRITE(DP_TP_CTL(port), val);
> -	POSTING_READ(DP_TP_CTL(port));
> +	I915_WRITE(ctl, val);
> +	POSTING_READ(ctl);
>  }
>  
>  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> @@ -3326,7 +3334,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	enum port port = encoder->port;
> +	i915_reg_t ctl;
>  	bool wait = false;
>  	u32 val;
>  
> @@ -3337,10 +3347,11 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
>  		wait = true;
>  	}
>  
> -	val = I915_READ(DP_TP_CTL(port));
> +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +	val = I915_READ(ctl);
>  	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>  	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -	I915_WRITE(DP_TP_CTL(port), val);
> +	I915_WRITE(ctl, val);
>  
>  	/* Disable FEC in DP Sink */
>  	intel_ddi_disable_fec_state(encoder, crtc_state);
> @@ -3765,10 +3776,13 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv =
>  		to_i915(intel_dig_port->base.base.dev);
>  	enum port port = intel_dig_port->base.port;
> +	i915_reg_t ctl;
>  	u32 val;
>  	bool wait = false;
> +	enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
>  
> -	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
> +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +	if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
>  		val = I915_READ(DDI_BUF_CTL(port));
>  		if (val & DDI_BUF_CTL_ENABLE) {
>  			val &= ~DDI_BUF_CTL_ENABLE;
> @@ -3776,11 +3790,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  			wait = true;
>  		}
>  
> -		val = I915_READ(DP_TP_CTL(port));
> +		val = I915_READ(ctl);
>  		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
>  		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -		I915_WRITE(DP_TP_CTL(port), val);
> -		POSTING_READ(DP_TP_CTL(port));
> +		I915_WRITE(ctl, val);
> +		POSTING_READ(ctl);
>  
>  		if (wait)
>  			intel_wait_ddi_buf_idle(dev_priv, port);
> @@ -3795,8 +3809,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
>  	}
> -	I915_WRITE(DP_TP_CTL(port), val);
> -	POSTING_READ(DP_TP_CTL(port));
> +	I915_WRITE(ctl, val);
> +	POSTING_READ(ctl);
>  
>  	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>  	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d84a66459daf..a87fa06994ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1214,6 +1214,7 @@ struct intel_dp {
>  	bool can_mst; /* this port supports mst */
>  	bool is_mst;
>  	int active_mst_links;
> +	enum transcoder mst_master_trans; /* Only valid on TGL+ */
>  	/* connector directly attached - won't be use for modeset in mst world */
>  	struct intel_connector *attached_connector;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23908da1cd5d..943392faaea2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3209,6 +3209,51 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
>  	vlv_dpio_put(dev_priv);
>  }
>  
> +i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
> +			       enum transcoder cpu_transcoder,
> +			       enum port port)
> +{
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
> +		return TGL_DP_TP_CTL(cpu_transcoder);
> +	} else {
> +		return DP_TP_CTL(port);
> +	}
> +}
> +
> +i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
> +				  enum transcoder cpu_transcoder,
> +				  enum port port)
> +{
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
> +		return TGL_DP_TP_STATUS(cpu_transcoder);
> +	} else {
> +		return DP_TP_STATUS(port);
> +	}
> +}
> +
> +/*
> + * Return the transcoder that this intel_dp port is driven.
> + * When in MST mode it will return the master transcoder of the MST so do not
> + * use it when reading or writing registers in the slave transcoders.
> + */
> +enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp)
> +{
> +	struct intel_connector *connector;
> +	struct drm_connector_state *conn_state;
> +	struct intel_crtc_state *crtc_state;
> +
> +	if (intel_dp->is_mst)
> +		return intel_dp->mst_master_trans;
> +
> +	connector = intel_dp->attached_connector;
> +	conn_state = connector->base.state;
> +	crtc_state = to_intel_crtc_state(conn_state->crtc->state);

That's illegal. Ideally we'd plumb the crtc state into the link training
stuff, but IIRC last time I tried that we still had at least one case
where that wasn't trivial. I can't remember right now where that case
was though.

I guess the alternative is to continue duplicating things in intel_dp.

> +
> +	return crtc_state->cpu_transcoder;
> +}
> +
>  static void
>  _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			 u32 *DP,
> @@ -3224,8 +3269,13 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			      dp_train_pat & train_pat_mask);
>  
>  	if (HAS_DDI(dev_priv)) {
> -		u32 temp = I915_READ(DP_TP_CTL(port));
> +		enum transcoder cpu_transcoder;
> +		i915_reg_t ctl;
> +		u32 temp;
>  
> +		cpu_transcoder = intel_dp_get_transcoder(intel_dp);
> +		ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +		temp = I915_READ(ctl);
>  		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
>  			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
>  		else
> @@ -3250,7 +3300,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
>  			break;
>  		}
> -		I915_WRITE(DP_TP_CTL(port), temp);
> +		I915_WRITE(ctl, temp);
>  
>  	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>  		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> @@ -3943,15 +3993,21 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	enum port port = intel_dig_port->base.port;
> +	enum transcoder cpu_transcoder;
> +	i915_reg_t ctl, status;
>  	u32 val;
>  
>  	if (!HAS_DDI(dev_priv))
>  		return;
>  
> -	val = I915_READ(DP_TP_CTL(port));
> +	cpu_transcoder = intel_dp_get_transcoder(intel_dp);
> +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> +	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
> +
> +	val = I915_READ(ctl);
>  	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
> -	I915_WRITE(DP_TP_CTL(port), val);
> +	I915_WRITE(ctl, val);
>  
>  	/*
>  	 * On PORT_A we can have only eDP in SST mode. There the only reason
> @@ -3963,7 +4019,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  	if (port == PORT_A)
>  		return;
>  
> -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> +	if (intel_de_wait_for_set(dev_priv, status,
>  				  DP_TP_STATUS_IDLE_DONE, 1))
>  		DRM_ERROR("Timed out waiting for DP idle patterns\n");
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 657bbb1f5ed0..107129b5d9a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -11,6 +11,7 @@
>  #include <drm/i915_drm.h>
>  
>  #include "i915_reg.h"
> +#include "intel_display.h"
>  
>  enum pipe;
>  struct drm_connector_state;
> @@ -113,6 +114,14 @@ int intel_dp_link_required(int pixel_clock, int bpp);
>  int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
>  bool intel_digital_port_connected(struct intel_encoder *encoder);
>  
> +i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
> +			       enum transcoder cpu_transcoder,
> +			       enum port port);
> +i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
> +				  enum transcoder cpu_transcoder,
> +				  enum port port);
> +enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp);
> +
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
>  	return ~((1 << lane_count) - 1) & 0xf;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8002dca9b734..630db2fadaca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -354,9 +354,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
>  	struct intel_digital_port *intel_dig_port = intel_mst->primary;
>  	struct intel_dp *intel_dp = &intel_dig_port->dp;
>  
> -	if (intel_dp->active_mst_links == 0)
> +	if (intel_dp->active_mst_links == 0) {
> +		intel_dp->mst_master_trans = pipe_config->mst_master_trans;
>  		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
>  						    pipe_config, NULL);
> +	}
>  }
>  
>  static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
> @@ -384,6 +386,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
>  	enum port port = intel_dig_port->base.port;
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> +	i915_reg_t status;
>  	int ret;
>  	u32 temp;
>  
> @@ -412,8 +415,12 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
>  		DRM_ERROR("failed to allocate vcpi\n");
>  
>  	intel_dp->active_mst_links++;
> -	temp = I915_READ(DP_TP_STATUS(port));
> -	I915_WRITE(DP_TP_STATUS(port), temp);
> +
> +	status = intel_dp_tp_status_reg(dev_priv,
> +					pipe_config->mst_master_trans,
> +					port);
> +	temp = I915_READ(status);
> +	I915_WRITE(status, temp);
>  
>  	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
>  
> @@ -429,10 +436,15 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = &intel_dig_port->dp;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = intel_dig_port->base.port;
> +	i915_reg_t status;
>  
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> +	status = intel_dp_tp_status_reg(dev_priv,
> +					pipe_config->mst_master_trans,
> +					port);
> +
> +	if (intel_de_wait_for_set(dev_priv, status,
>  				  DP_TP_STATUS_ACT_SENT, 1))
>  		DRM_ERROR("Timed out waiting for ACT sent\n");
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bff9ee191832..fffaed0ca3cd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9454,7 +9454,9 @@ enum skl_power_gate {
>  /* DisplayPort Transport Control */
>  #define _DP_TP_CTL_A			0x64040
>  #define _DP_TP_CTL_B			0x64140
> +#define _TGL_DP_TP_CTL_A		0x60540
>  #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> +#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
>  #define  DP_TP_CTL_ENABLE			(1 << 31)
>  #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
>  #define  DP_TP_CTL_MODE_SST			(0 << 27)
> @@ -9474,7 +9476,9 @@ enum skl_power_gate {
>  /* DisplayPort Transport Status */
>  #define _DP_TP_STATUS_A			0x64044
>  #define _DP_TP_STATUS_B			0x64144
> +#define _TGL_DP_TP_STATUS_A		0x60544
>  #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
> +#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
>  #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
>  #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
>  #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
> -- 
> 2.23.0

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder

[Ville Syrjälä]

On Fri, Aug 23, 2019 at 03:25:18PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 23, 2019 at 01:20:46AM -0700, Lucas De Marchi wrote:
> > Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
> > than port-based. This add the new register address and changes the
> > functions that are used with DDI on gen 12 to use the new registers. On
> > MST the master transcoder is the one to be used.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 42 ++++++++----
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 66 +++++++++++++++++--
> >  drivers/gpu/drm/i915/display/intel_dp.h       |  9 +++
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 20 ++++--
> >  drivers/gpu/drm/i915/i915_reg.h               |  4 ++
> >  6 files changed, 119 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index f4cb6bd74421..3eb73dbaf9fd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3136,17 +3136,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
> >  				 const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	enum port port = encoder->port;
> > +	i915_reg_t ctl, status;
> >  	u32 val;
> >  
> >  	if (!crtc_state->fec_enable)
> >  		return;
> >  
> > -	val = I915_READ(DP_TP_CTL(port));
> > +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
> > +
> > +	val = I915_READ(ctl);
> >  	val |= DP_TP_CTL_FEC_ENABLE;
> > -	I915_WRITE(DP_TP_CTL(port), val);
> > +	I915_WRITE(ctl, val);
> >  
> > -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> > +	if (intel_de_wait_for_set(dev_priv, status,
> >  				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
> >  		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
> >  }
> > @@ -3155,16 +3160,19 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
> >  					const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	enum port port = encoder->port;
> > +	i915_reg_t ctl;
> >  	u32 val;
> >  
> >  	if (!crtc_state->fec_enable)
> >  		return;
> >  
> > -	val = I915_READ(DP_TP_CTL(port));
> > +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +	val = I915_READ(ctl);
> >  	val &= ~DP_TP_CTL_FEC_ENABLE;
> > -	I915_WRITE(DP_TP_CTL(port), val);
> > -	POSTING_READ(DP_TP_CTL(port));
> > +	I915_WRITE(ctl, val);
> > +	POSTING_READ(ctl);
> >  }
> >  
> >  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > @@ -3326,7 +3334,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> >  				  const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	enum port port = encoder->port;
> > +	i915_reg_t ctl;
> >  	bool wait = false;
> >  	u32 val;
> >  
> > @@ -3337,10 +3347,11 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> >  		wait = true;
> >  	}
> >  
> > -	val = I915_READ(DP_TP_CTL(port));
> > +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +	val = I915_READ(ctl);
> >  	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> >  	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > -	I915_WRITE(DP_TP_CTL(port), val);
> > +	I915_WRITE(ctl, val);
> >  
> >  	/* Disable FEC in DP Sink */
> >  	intel_ddi_disable_fec_state(encoder, crtc_state);
> > @@ -3765,10 +3776,13 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> >  	struct drm_i915_private *dev_priv =
> >  		to_i915(intel_dig_port->base.base.dev);
> >  	enum port port = intel_dig_port->base.port;
> > +	i915_reg_t ctl;
> >  	u32 val;
> >  	bool wait = false;
> > +	enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
> >  
> > -	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
> > +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +	if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
> >  		val = I915_READ(DDI_BUF_CTL(port));
> >  		if (val & DDI_BUF_CTL_ENABLE) {
> >  			val &= ~DDI_BUF_CTL_ENABLE;
> > @@ -3776,11 +3790,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> >  			wait = true;
> >  		}
> >  
> > -		val = I915_READ(DP_TP_CTL(port));
> > +		val = I915_READ(ctl);
> >  		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> >  		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > -		I915_WRITE(DP_TP_CTL(port), val);
> > -		POSTING_READ(DP_TP_CTL(port));
> > +		I915_WRITE(ctl, val);
> > +		POSTING_READ(ctl);
> >  
> >  		if (wait)
> >  			intel_wait_ddi_buf_idle(dev_priv, port);
> > @@ -3795,8 +3809,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> >  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> >  			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> >  	}
> > -	I915_WRITE(DP_TP_CTL(port), val);
> > -	POSTING_READ(DP_TP_CTL(port));
> > +	I915_WRITE(ctl, val);
> > +	POSTING_READ(ctl);
> >  
> >  	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> >  	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d84a66459daf..a87fa06994ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1214,6 +1214,7 @@ struct intel_dp {
> >  	bool can_mst; /* this port supports mst */
> >  	bool is_mst;
> >  	int active_mst_links;
> > +	enum transcoder mst_master_trans; /* Only valid on TGL+ */

Hmm. So maybe just s/mst_master_trans/dp_tp_transcoder/ etc. and set
this unconditionally in eg. intel_dp_set_link_params().

> >  	/* connector directly attached - won't be use for modeset in mst world */
> >  	struct intel_connector *attached_connector;
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 23908da1cd5d..943392faaea2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3209,6 +3209,51 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
> >  	vlv_dpio_put(dev_priv);
> >  }
> >  
> > +i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
> > +			       enum transcoder cpu_transcoder,
> > +			       enum port port)
> > +{
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
> > +		return TGL_DP_TP_CTL(cpu_transcoder);
> > +	} else {
> > +		return DP_TP_CTL(port);
> > +	}
> > +}
> > +
> > +i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
> > +				  enum transcoder cpu_transcoder,
> > +				  enum port port)
> > +{
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
> > +		return TGL_DP_TP_STATUS(cpu_transcoder);
> > +	} else {
> > +		return DP_TP_STATUS(port);
> > +	}
> > +}
> > +
> > +/*
> > + * Return the transcoder that this intel_dp port is driven.
> > + * When in MST mode it will return the master transcoder of the MST so do not
> > + * use it when reading or writing registers in the slave transcoders.
> > + */
> > +enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_connector *connector;
> > +	struct drm_connector_state *conn_state;
> > +	struct intel_crtc_state *crtc_state;
> > +
> > +	if (intel_dp->is_mst)
> > +		return intel_dp->mst_master_trans;
> > +
> > +	connector = intel_dp->attached_connector;
> > +	conn_state = connector->base.state;
> > +	crtc_state = to_intel_crtc_state(conn_state->crtc->state);
> 
> That's illegal. Ideally we'd plumb the crtc state into the link training
> stuff, but IIRC last time I tried that we still had at least one case
> where that wasn't trivial. I can't remember right now where that case
> was though.
> 
> I guess the alternative is to continue duplicating things in intel_dp.
> 
> > +
> > +	return crtc_state->cpu_transcoder;
> > +}
> > +
> >  static void
> >  _intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  			 u32 *DP,
> > @@ -3224,8 +3269,13 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  			      dp_train_pat & train_pat_mask);
> >  
> >  	if (HAS_DDI(dev_priv)) {
> > -		u32 temp = I915_READ(DP_TP_CTL(port));
> > +		enum transcoder cpu_transcoder;
> > +		i915_reg_t ctl;
> > +		u32 temp;
> >  
> > +		cpu_transcoder = intel_dp_get_transcoder(intel_dp);
> > +		ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +		temp = I915_READ(ctl);
> >  		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> >  			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> >  		else
> > @@ -3250,7 +3300,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  			temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> >  			break;
> >  		}
> > -		I915_WRITE(DP_TP_CTL(port), temp);
> > +		I915_WRITE(ctl, temp);
> >  
> >  	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> >  		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> > @@ -3943,15 +3993,21 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >  	enum port port = intel_dig_port->base.port;
> > +	enum transcoder cpu_transcoder;
> > +	i915_reg_t ctl, status;
> >  	u32 val;
> >  
> >  	if (!HAS_DDI(dev_priv))
> >  		return;
> >  
> > -	val = I915_READ(DP_TP_CTL(port));
> > +	cpu_transcoder = intel_dp_get_transcoder(intel_dp);
> > +	ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
> > +	status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
> > +
> > +	val = I915_READ(ctl);
> >  	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> >  	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
> > -	I915_WRITE(DP_TP_CTL(port), val);
> > +	I915_WRITE(ctl, val);
> >  
> >  	/*
> >  	 * On PORT_A we can have only eDP in SST mode. There the only reason
> > @@ -3963,7 +4019,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> >  	if (port == PORT_A)
> >  		return;
> >  
> > -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> > +	if (intel_de_wait_for_set(dev_priv, status,
> >  				  DP_TP_STATUS_IDLE_DONE, 1))
> >  		DRM_ERROR("Timed out waiting for DP idle patterns\n");
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 657bbb1f5ed0..107129b5d9a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -11,6 +11,7 @@
> >  #include <drm/i915_drm.h>
> >  
> >  #include "i915_reg.h"
> > +#include "intel_display.h"
> >  
> >  enum pipe;
> >  struct drm_connector_state;
> > @@ -113,6 +114,14 @@ int intel_dp_link_required(int pixel_clock, int bpp);
> >  int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> >  bool intel_digital_port_connected(struct intel_encoder *encoder);
> >  
> > +i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
> > +			       enum transcoder cpu_transcoder,
> > +			       enum port port);
> > +i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
> > +				  enum transcoder cpu_transcoder,
> > +				  enum port port);
> > +enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp);
> > +
> >  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> >  {
> >  	return ~((1 << lane_count) - 1) & 0xf;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 8002dca9b734..630db2fadaca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -354,9 +354,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
> >  	struct intel_digital_port *intel_dig_port = intel_mst->primary;
> >  	struct intel_dp *intel_dp = &intel_dig_port->dp;
> >  
> > -	if (intel_dp->active_mst_links == 0)
> > +	if (intel_dp->active_mst_links == 0) {
> > +		intel_dp->mst_master_trans = pipe_config->mst_master_trans;

The current transcoder should be the master here, no?

Maybe sprinkle some

assert_is_master_transcoder(crtc_state)
{
	WARN(crtc_has_type(MST) &&
		crtc_state->cpu_trans != crtc_state->master_trans);
}

stuff into the ddi code?

> >  		intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
> >  						    pipe_config, NULL);
> > +	}
> >  }
> >  
> >  static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
> > @@ -384,6 +386,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> >  	enum port port = intel_dig_port->base.port;
> >  	struct intel_connector *connector =
> >  		to_intel_connector(conn_state->connector);
> > +	i915_reg_t status;
> >  	int ret;
> >  	u32 temp;
> >  
> > @@ -412,8 +415,12 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> >  		DRM_ERROR("failed to allocate vcpi\n");
> >  
> >  	intel_dp->active_mst_links++;
> > -	temp = I915_READ(DP_TP_STATUS(port));
> > -	I915_WRITE(DP_TP_STATUS(port), temp);
> > +
> > +	status = intel_dp_tp_status_reg(dev_priv,
> > +					pipe_config->mst_master_trans,
> > +					port);
> > +	temp = I915_READ(status);
> > +	I915_WRITE(status, temp);
> >  
> >  	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
> >  
> > @@ -429,10 +436,15 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
> >  	struct intel_dp *intel_dp = &intel_dig_port->dp;
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	enum port port = intel_dig_port->base.port;
> > +	i915_reg_t status;
> >  
> >  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> >  
> > -	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> > +	status = intel_dp_tp_status_reg(dev_priv,
> > +					pipe_config->mst_master_trans,
> > +					port);
> > +
> > +	if (intel_de_wait_for_set(dev_priv, status,
> >  				  DP_TP_STATUS_ACT_SENT, 1))
> >  		DRM_ERROR("Timed out waiting for ACT sent\n");
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index bff9ee191832..fffaed0ca3cd 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9454,7 +9454,9 @@ enum skl_power_gate {
> >  /* DisplayPort Transport Control */
> >  #define _DP_TP_CTL_A			0x64040
> >  #define _DP_TP_CTL_B			0x64140
> > +#define _TGL_DP_TP_CTL_A		0x60540
> >  #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> > +#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
> >  #define  DP_TP_CTL_ENABLE			(1 << 31)
> >  #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
> >  #define  DP_TP_CTL_MODE_SST			(0 << 27)
> > @@ -9474,7 +9476,9 @@ enum skl_power_gate {
> >  /* DisplayPort Transport Status */
> >  #define _DP_TP_STATUS_A			0x64044
> >  #define _DP_TP_STATUS_B			0x64144
> > +#define _TGL_DP_TP_STATUS_A		0x60544
> >  #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
> > +#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
> >  #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
> >  #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
> >  #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
> > -- 
> > 2.23.0
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST

[Ville Syrjälä]

On Fri, Aug 23, 2019 at 01:20:45AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port must
> send its stream to a master transcoder and master will send to DDI
> respecting the time slots.
> 
> So here it is picking the lowest pipe/transcoder as it will be
> enabled first and disabled last.
> BSpec: 50493
> BSpec: 49190
> 
> v2: Missed set mst_master_trans to TRANSCODER_INVALID when computing HSW
>     encoder config. HSW CRT hw state readout calls
>     hsw_crt_get_config()->intel_ddi_get_config() that will set
>     mst_master_trans to TRANSCODER_INVALID causing the mismatch when
>     verifying CRTC state after a modeset. (José)
> 
> v3: Add WARN_ON() requested by Jani.
>     Add FIXME. From Jani: double check PIPE_CONF_CHECK_I(mst_master_trans) - it's
>     now checking for all platforms and MST and non-MST alike.
>     Perhaps in general I'd like the approach of only doing the readout when
>     it's relevant, and only checking the value when it's relevant.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  18 ++
>  drivers/gpu/drm/i915/display/intel_display.c  |  15 ++
>  drivers/gpu/drm/i915/display/intel_display.h  |   3 +
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 159 +++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
>  drivers/gpu/drm/i915/i915_reg.h               |   3 +
>  8 files changed, 202 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index e6e8d4a82044..503135200cb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -416,6 +416,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
>  	/* FDI must always be 2.7 GHz */
>  	pipe_config->port_clock = 135000 * 2;
>  
> +	pipe_config->mst_master_trans = TRANSCODER_INVALID;
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8eb2b3ec01ed..f4cb6bd74421 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1840,6 +1840,13 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
>  		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			enum transcoder master = crtc_state->mst_master_trans;
> +
> +			WARN_ON(master == TRANSCODER_INVALID);
> +			temp |= TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(master);
> +		}
>  	} else {
>  		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> @@ -3861,6 +3868,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  		break;
>  	}
>  
> +	pipe_config->mst_master_trans = TRANSCODER_INVALID;
> +
>  	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
>  	case TRANS_DDI_MODE_SELECT_HDMI:
>  		pipe_config->has_hdmi_sink = true;
> @@ -3896,6 +3905,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
>  		pipe_config->lane_count =
>  			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
> +
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			temp = temp & TRANS_DDI_MST_TRANSPORT_SELECT_MASK;
> +			temp = temp >> TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT;
> +			pipe_config->mst_master_trans = temp;
> +		}
> +
>  		intel_dp_get_m_n(intel_crtc, pipe_config);
>  		break;
>  	default:
> @@ -3998,6 +4014,8 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
> +	pipe_config->mst_master_trans = TRANSCODER_INVALID;
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ddb8436e2208..109d4fd961c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -47,6 +47,7 @@
>  #include "display/intel_crt.h"
>  #include "display/intel_ddi.h"
>  #include "display/intel_dp.h"
> +#include "display/intel_dp_mst.h"
>  #include "display/intel_dsi.h"
>  #include "display/intel_dvo.h"
>  #include "display/intel_gmbus.h"
> @@ -12138,6 +12139,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  
>  	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
>  
> +	if (INTEL_GEN(dev_priv) >= 12 &&
> +	    intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> +		enum transcoder master = pipe_config->mst_master_trans;
> +
> +		DRM_DEBUG_KMS("master mst cpu_transcoder: %s\n",
> +			      transcoder_name(master));
> +	}
> +
>  dump_planes:
>  	if (!state)
>  		return;
> @@ -12821,6 +12830,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_INFOFRAME(hdmi);
>  	PIPE_CONF_CHECK_INFOFRAME(drm);
>  
> +	PIPE_CONF_CHECK_I(mst_master_trans);
> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_BOOL
> @@ -13597,6 +13608,10 @@ static int intel_atomic_check(struct drm_device *dev,
>  	int ret, i;
>  	bool any_ms = state->cdclk.force_min_cdclk_changed;
>  
> +	ret = intel_dp_mst_atomic_add_affected_crtcs(state);
> +	if (ret)
> +		return ret;

This feels too early. I think it should be after
drm_atomic_helper_check_modeset() at least.

> +
>  	/* Catch I915_MODE_FLAG_INHERITED */
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index b63fb7a4599e..282e8d8f1cc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -91,6 +91,8 @@ enum pipe {
>  #define pipe_name(p) ((p) + 'A')
>  
>  enum transcoder {
> +	TRANSCODER_INVALID = -1,
> +
>  	/*
>  	 * The following transcoders have a 1:1 transcoder -> pipe mapping,
>  	 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
> @@ -132,6 +134,7 @@ static inline const char *transcoder_name(enum transcoder transcoder)
>  		return "DSI A";
>  	case TRANSCODER_DSI_C:
>  		return "DSI C";
> +	case TRANSCODER_INVALID:
>  	default:
>  		return "<invalid>";
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 449abaea619f..d84a66459daf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -984,6 +984,9 @@ struct intel_crtc_state {
>  
>  	/* Forward Error correction State */
>  	bool fec_enable;
> +
> +	/* Master transcoder for all streams, only used on TGL+ */
> +	enum transcoder mst_master_trans;
>  };
>  
>  struct intel_crtc {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2c5ac3dd647f..8002dca9b734 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -87,6 +87,50 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>  	return 0;
>  }
>  
> +/*
> + * Iterate over all the CRTCs and return the transcoder of the lowest CRTC that
> + * share the same MST connector.
> + */
> +static enum transcoder
> +mst_compute_master_trans(struct drm_atomic_state *state,
> +			 struct drm_connector *mst_conn)
> +{
> +	struct intel_connector *intel_mst_conn = to_intel_connector(mst_conn);
> +	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> +	struct intel_crtc_state *intel_crtc_state;
> +	struct intel_crtc *intel_crtc;

Please switch to intel_ types fully and drop the intel_ prefix  from the
variables.

> +	int i;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		return TRANSCODER_INVALID;
> +
> +	/* Iterate from the lowest to the highest pipe */
> +	for_each_new_intel_crtc_in_state(intel_state, intel_crtc, intel_crtc_state, i) {
> +		struct intel_digital_connector_state *intel_conn_state;
> +		struct intel_connector *intel_conn;
> +		int j;
> +
> +		if (!intel_crtc_state->base.active)
> +			continue;
> +
> +		for_each_new_intel_connector_in_state(intel_state, intel_conn,
> +						      intel_conn_state, j) {
> +			/* Only care about connectors of this CRTC */
> +			if (intel_conn_state->base.crtc !=
> +			    intel_crtc_state->base.crtc)
> +				continue;
> +
> +			if (intel_conn->mst_port != intel_mst_conn->mst_port)
> +				continue;
> +
> +			return intel_crtc_state->cpu_transcoder;
> +		}
> +	}
> +
> +	return TRANSCODER_INVALID;
> +}
> +
>  static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  				       struct intel_crtc_state *pipe_config,
>  				       struct drm_connector_state *conn_state)
> @@ -94,14 +138,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
>  	struct intel_dp *intel_dp = &intel_mst->primary->dp;
> -	struct intel_connector *connector =
> -		to_intel_connector(conn_state->connector);
> +	struct drm_connector *connector = conn_state->connector;
> +	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
>  	const struct drm_display_mode *adjusted_mode =
>  		&pipe_config->base.adjusted_mode;
> -	void *port = connector->port;
> +	void *port = intel_connector->port;
>  	struct link_config_limits limits;
> +	enum transcoder master;
>  	int ret;
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> @@ -146,6 +191,51 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
> +	master = mst_compute_master_trans(conn_state->state, connector);
> +	pipe_config->mst_master_trans = master;
> +
> +	return 0;
> +}
> +
> +static int
> +intel_dp_mst_master_trans_check(struct drm_connector *conn,
> +				struct drm_connector_state *new_conn_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(conn->dev);
> +	struct drm_atomic_state *state = new_conn_state->state;
> +	struct drm_connector_state *old_conn_state =
> +		drm_atomic_get_old_connector_state(state, conn);
> +	struct drm_crtc *new_crtc = new_conn_state->crtc;
> +	struct drm_crtc *old_crtc = old_conn_state->crtc;
> +	enum transcoder old_master_trans = TRANSCODER_INVALID;
> +	enum transcoder new_master_trans = TRANSCODER_INVALID;
> +	struct drm_crtc_state *new_crtc_state, *old_crtc_state;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		return 0;
> +
> +	if (old_crtc) {
> +		struct intel_crtc_state *intel_crtc_state;

Same story with types and variable naming.

> +
> +		old_crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc);
> +		intel_crtc_state = to_intel_crtc_state(old_crtc_state);
> +		old_master_trans = intel_crtc_state->mst_master_trans;
> +	}
> +
> +	if (new_crtc) {
> +		struct intel_crtc_state *intel_crtc_state;
> +
> +		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
> +		intel_crtc_state = to_intel_crtc_state(new_crtc_state);
> +		new_master_trans = mst_compute_master_trans(state, conn);
> +	}
> +
> +	if (old_crtc && old_master_trans != new_master_trans)
> +		old_crtc_state->mode_changed = true;
> +
> +	if (new_crtc && old_master_trans != new_master_trans)
> +		new_crtc_state->mode_changed = true;
> +
>  	return 0;
>  }
>  
> @@ -168,6 +258,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
>  	if (ret)
>  		return ret;
>  
> +	ret = intel_dp_mst_master_trans_check(connector, new_conn_state);
> +	if (ret)
> +		return ret;
> +
>  	if (!old_conn_state->crtc)
>  		return 0;
>  
> @@ -674,3 +768,62 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
>  	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
>  	/* encoders will get killed by normal cleanup */
>  }
> +
> +/**
> + * intel_dp_mst_atomic_add_affected_crtcs - Add all CRTCs that share the MST
> + * stream with the CRTCs in the current atomic state.
> + * @state: state to add CRTCs
> + *
> + * It is needed add the CRTCs trigger a call to atomic_check() to
> + * every connector attached to the CRTC in case a new master transcoder will
> + * be needed.
> + */
> +int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_digital_connector_state *intel_conn_state;
> +	struct drm_device *dev = state->base.dev;
> +	struct intel_connector *intel_conn;
> +	int i;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		return 0;
> +
> +	for_each_new_intel_connector_in_state(state, intel_conn, intel_conn_state, i) {
> +		struct drm_connector_list_iter conn_list_iter;
> +		struct drm_connector *conn_iter;
> +
> +		if (!intel_conn->mst_port)
> +			continue;

I think we should be able to skip this unless a modeset is required.

> +
> +		drm_connector_list_iter_begin(dev, &conn_list_iter);
> +		drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
> +			struct drm_connector_state *conn_iter_state;
> +			struct intel_connector *intel_conn_iter;
> +			struct drm_crtc_state *crtc_state;
> +
> +			intel_conn_iter = to_intel_connector(conn_iter);
> +
> +			if (intel_conn_iter->mst_port != intel_conn->mst_port)
> +				continue;
> +
> +			conn_iter_state = drm_atomic_get_connector_state(&state->base, conn_iter);
> +			if (IS_ERR(conn_iter_state)) {
> +				drm_connector_list_iter_end(&conn_list_iter);
> +				return PTR_ERR(conn_iter_state);
> +			}
> +			if (!conn_iter_state->crtc)
> +				continue;
> +
> +			crtc_state = drm_atomic_get_crtc_state(&state->base,
> +							       conn_iter_state->crtc);
> +			if (IS_ERR(crtc_state)) {
> +				drm_connector_list_iter_end(&conn_list_iter);
> +				return PTR_ERR(crtc_state);
> +			}
> +		}
> +		drm_connector_list_iter_end(&conn_list_iter);
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> index f660ad80db04..173598aa81d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> @@ -6,10 +6,12 @@
>  #ifndef __INTEL_DP_MST_H__
>  #define __INTEL_DP_MST_H__
>  
> +struct intel_atomic_state;
>  struct intel_digital_port;
>  
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>  void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
> +int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state);
>  int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
>  
>  #endif /* __INTEL_DP_MST_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3de02683d856..bff9ee191832 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9424,6 +9424,9 @@ enum skl_power_gate {
>  #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
>  #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
>  #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
> +#define  TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT		10 /* TGL+ */
> +#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK		(0x3 << 10)
> +#define  TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(trans)	((trans) << 10)
>  #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
>  #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
>  #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> -- 
> 2.23.0

-- 
Ville Syrjälä
Intel
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✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev5)

[Patchwork]

== Series Details ==

Series: Tiger Lake batch 3 (rev5)
URL   : https://patchwork.freedesktop.org/series/65290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
385d0cea263f drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
-:28: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#28: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:87:
+#define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1<<0)
                                          	  ^

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
2f4032c673ce drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
01ce36bb2bfa drm/i915/psr: Only handle interruptions of the transcoder in use
-:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#230: FILE: drivers/gpu/drm/i915/i915_reg.h:4228:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
a2bf1ac1f4f0 drm/i915/bdw+: Enable PSR in any eDP port
2c444eefb88f drm/i915: Guard and warn if more than one eDP panel is present
04f3d0338d3f drm/i915: Do not read PSR2 register in transcoders without PSR2
c7a7a115467e drm/i915/tgl: PSR link standby is not supported anymore
6c29d1d87d2d drm/i915/tgl: Access the right register when handling PSR interruptions
4962b6d88797 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
04c9257c9791 drm/i915: Add for_each_new_intel_connector_in_state()
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:28: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
8ff0f4dfd8d7 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 3 checks, 15 lines checked
ac6110ed3d55 drm/i915: Disable pipes in reverse order
4e72fd9a7b1a FIXME: drm/i915/tgl: Select master transcoder in DP MST
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#26: 
    Add FIXME. From Jani: double check PIPE_CONF_CHECK_I(mst_master_trans) - it's

total: 0 errors, 1 warnings, 0 checks, 325 lines checked
2732c013a2e5 drm/i915/tgl: move DP_TP_* to transcoder
82a4ff669aa6 drm/i915/tgl: Implement TGL DisplayPort training sequence
e44fa908a435 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
5a65c5bddfa6 FIXME: drm/i915/tgl: Register state context definition for Gen12
53d10786309a drm/i915/tgl/perf: use the same oa ctx_id format as icl
6fd7e43b7477 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
32f171b41ca7 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
fca4dac975ee drm/i915/tgl: Gen-12 render decompression
fc2223c91ae2 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
62b7125d235e drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2523:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 1 warnings, 0 checks, 134 lines checked

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✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3 (rev5)

[Patchwork]

== Series Details ==

Series: Tiger Lake batch 3 (rev5)
URL   : https://patchwork.freedesktop.org/series/65290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

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✓ Fi.CI.BAT: success for Tiger Lake batch 3 (rev5)

[Patchwork]

== Series Details ==

Series: Tiger Lake batch 3 (rev5)
URL   : https://patchwork.freedesktop.org/series/65290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6777 -> Patchwork_14162
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14162:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - {fi-tgl-u}:         NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_render_linear_blits@basic:
    - {fi-tgl-u}:         NOTRUN -> [SKIP][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_render_linear_blits@basic.html

  * igt@gem_sync@basic-store-all:
    - {fi-tgl-u}:         NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_sync@basic-store-all.html

  
Known issues
------------

  Here are the changes found in Patchwork_14162 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-read-no-prefault:
    - fi-icl-u3:          [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [INCOMPLETE][6] ([fdo#103927] / [fdo#111381]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-hsw-4770r:       [DMESG-WARN][8] ([fdo#107732]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (53 -> 44)
------------------------------

  Additional (2): fi-icl-u2 fi-gdg-551 
  Missing    (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-bdw-samus fi-icl-dsi fi-skl-6600u fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6777 -> Patchwork_14162

  CI-20190529: 20190529
  CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14162: 62b7125d235edbae192a71d4337f9f389f6ef886 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

62b7125d235e drm/i915/tgl: Gen-12 media compression
fc2223c91ae2 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
fca4dac975ee drm/i915/tgl: Gen-12 render decompression
32f171b41ca7 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
6fd7e43b7477 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
53d10786309a drm/i915/tgl/perf: use the same oa ctx_id format as icl
5a65c5bddfa6 FIXME: drm/i915/tgl: Register state context definition for Gen12
e44fa908a435 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
82a4ff669aa6 drm/i915/tgl: Implement TGL DisplayPort training sequence
2732c013a2e5 drm/i915/tgl: move DP_TP_* to transcoder
4e72fd9a7b1a FIXME: drm/i915/tgl: Select master transcoder in DP MST
ac6110ed3d55 drm/i915: Disable pipes in reverse order
8ff0f4dfd8d7 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
04c9257c9791 drm/i915: Add for_each_new_intel_connector_in_state()
4962b6d88797 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
6c29d1d87d2d drm/i915/tgl: Access the right register when handling PSR interruptions
c7a7a115467e drm/i915/tgl: PSR link standby is not supported anymore
04f3d0338d3f drm/i915: Do not read PSR2 register in transcoders without PSR2
2c444eefb88f drm/i915: Guard and warn if more than one eDP panel is present
a2bf1ac1f4f0 drm/i915/bdw+: Enable PSR in any eDP port
01ce36bb2bfa drm/i915/psr: Only handle interruptions of the transcoder in use
2f4032c673ce drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
385d0cea263f drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/
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Re: [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl

[Umesh Nerlige Ramappa]

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

On Fri, Aug 23, 2019 at 01:20:50AM -0700, Lucas De Marchi wrote:
>From: Michel Thierry <michel.thierry@intel.com>
>
>Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
>since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
>will use the correct one.
>
>Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/i915_perf.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index e42b86827d6b..2c9f46e12622 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
> 		}
> 		break;
>
>-	case 11: {
>+	case 11:
>+	case 12: {
> 		stream->specific_ctx_id_mask =
> 			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
> 			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
>-- 
>2.23.0
>
>_______________________________________________
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Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Anshuman Gupta]

On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> TGL PSR2 HW supports a bigger resolution, so lets add it
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c33aa16ed038..5d24f1c47a2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
As per B.Specs:28692 on few Gen11 platform, PSR2 supports max resolution of 5120X3200.
Do we need to handle those Gen11 platform here? 
> +		psr_max_h = 5120;
> +		psr_max_v = 3200;
> +	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
>  	} else if (IS_GEN(dev_priv, 9)) {
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.IGT: success for Tiger Lake batch 3 (rev5)

[Patchwork]

== Series Details ==

Series: Tiger Lake batch 3 (rev5)
URL   : https://patchwork.freedesktop.org/series/65290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6777_full -> Patchwork_14162_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14162_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_rpm@i2c:
    - shard-hsw:          [PASS][5] -> [FAIL][6] ([fdo#104097])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw5/igt@i915_pm_rpm@i2c.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw2/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108840])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@i915_pm_rpm@pm-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@i915_pm_rpm@pm-tiling.html

  * igt@i915_selftest@live_gtt:
    - shard-glk:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103359] / [k.org#198133])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-glk7/igt@i915_selftest@live_gtt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-glk2/igt@i915_selftest@live_gtt.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#105363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@kms_psr@psr2_dpms.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([fdo#99912])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-apl:          [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  * igt@perf@polling:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl10/igt@perf@polling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl2/igt@perf@polling.html

  * igt@prime_busy@after-bsd2:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109276]) +16 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@prime_busy@after-bsd2.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@prime_busy@after-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preempt-queue-contexts-render:
    - shard-apl:          [INCOMPLETE][31] ([fdo#103927]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl8/igt@gem_exec_schedule@preempt-queue-contexts-render.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][33] ([fdo#111325]) -> [PASS][34] +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][37] ([fdo#103540]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][39] ([fdo#105363]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [FAIL][43] ([fdo#103375]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
    - shard-skl:          [DMESG-WARN][45] ([fdo#106885]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl7/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][47] ([fdo#109642] / [fdo#111068]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][49] ([fdo#109441]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][51] ([fdo#109276]) -> [PASS][52] +4 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][53] ([fdo#111329]) -> [SKIP][54] ([fdo#109276])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [FAIL][55] ([fdo#111330]) -> [SKIP][56] ([fdo#109276])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-skl:          [FAIL][57] ([fdo#108686]) -> [SKIP][58] ([fdo#109271])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl5/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-skl:          [FAIL][59] ([fdo#108040]) -> [FAIL][60] ([fdo#103167] / [fdo#110378])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111472]: https://bugs.freedesktop.org/show_bug.cgi?id=111472
  [fdo#111473 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111473 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (8 -> 9)
------------------------------

  Additional (1): pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6777 -> Patchwork_14162

  CI-20190529: 20190529
  CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14162: 62b7125d235edbae192a71d4337f9f389f6ef886 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/
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Re: [PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present

[Anshuman Gupta]

On 2019-08-23 at 01:20:37 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> Now that is allowed to have PSR enabled in any port from BDW+, lets
> guard intel_psr_init_dpcd() against multiple eDP panels and warn about
> it.
> 
> For now we will keep just one instance of PSR.
Looks good to me.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0172b82858d9..cf07ab3d9280 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -249,6 +249,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv =
>  		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
>  
> +	if (dev_priv->psr.dp) {
> +		DRM_WARN("More than one eDP panel found, PSR support should be extend\n");
> +		return;
> +	}
> +
>  	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>  			 sizeof(intel_dp->psr_dpcd));
>  
> @@ -271,7 +276,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	dev_priv->psr.sink_sync_latency =
>  		intel_dp_get_sink_sync_latency(intel_dp);
>  
> -	WARN_ON(dev_priv->psr.dp);
>  	dev_priv->psr.dp = intel_dp;
>  
>  	if (INTEL_GEN(dev_priv) >= 9 &&
> -- 
> 2.23.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions

[Anshuman Gupta]

On 2019-08-23 at 01:20:40 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> For older gens PSR IIR and IMR had a fixed address that was not
> relative to anything, but from TGL those registers moved to each
> transcoder offset.
> 
> So here adding a new macro and a new PSR irq handler with the
> transcoder parameter.
>
There are few minor comments below, apart from below comments
patch is looks ok to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>  
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++++++++------
>  drivers/gpu/drm/i915/display/intel_psr.h |  1 +
>  drivers/gpu/drm/i915/i915_irq.c          | 52 +++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h          | 10 +++-
>  4 files changed, 107 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2429328f963e..c33aa16ed038 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -91,20 +91,33 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>  static void psr_irq_control(struct drm_i915_private *dev_priv)
>  {
>  	enum transcoder trans = dev_priv->psr.transcoder;
> -	u32 val, mask;
> +	u32 psr_error, psr_entry, psr_exit, mask, val;
> +	i915_reg_t mask_reg;
> +
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		psr_error = TRANS_PSR_ERROR;
> +		psr_entry = TRANS_PSR_PRE_ENTRY;
> +		psr_exit = TRANS_PSR_POST_EXIT;
> +		mask_reg = TRANS_PSR_IMR(trans);
> +	} else {
> +		psr_error = EDP_PSR_ERROR(trans);
> +		psr_entry = EDP_PSR_PRE_ENTRY(trans);
> +		psr_exit = EDP_PSR_POST_EXIT(trans);
> +		mask_reg = EDP_PSR_IMR;
> +	}
>  
> -	mask = EDP_PSR_ERROR(trans);
> +	mask = psr_error;
>  	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
> -		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
> +		mask |= psr_exit | psr_entry;
>  
>  	/*
>  	 * TODO: when handling multiple PSR instances a global spinlock will be
>  	 * needed to synchronize the value of shared register
>  	 */
> -	val = I915_READ(EDP_PSR_IMR);
> -	val &= ~EDP_PSR_TRANS_MASK(trans);
> +	val = I915_READ(mask_reg);
> +	val &= ~(psr_error | psr_entry | psr_exit);
>  	val |= ~mask;
> -	I915_WRITE(EDP_PSR_IMR, val);
> +	I915_WRITE(mask_reg, val);
>  }
>  
>  static void psr_event_print(u32 val, bool psr2_enabled)
> @@ -147,9 +160,21 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>  {
>  	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
> +	u32 psr_error, psr_entry, psr_exit;
>  	ktime_t time_ns =  ktime_get();
>  
> -	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		psr_error = TRANS_PSR_ERROR;
> +		psr_entry = TRANS_PSR_PRE_ENTRY;
> +		psr_exit = TRANS_PSR_POST_EXIT;
> +	} else {
> +		psr_error = EDP_PSR_ERROR(cpu_transcoder);
> +		psr_entry = EDP_PSR_PRE_ENTRY(cpu_transcoder);
> +		psr_exit = EDP_PSR_POST_EXIT(cpu_transcoder);
> +	}
> +
> +	if (psr_iir & psr_error) {
> +		i915_reg_t mask_reg;
>  		u32 val;
>  
>  		DRM_WARN("[transcoder %s] PSR aux error\n",
> @@ -168,20 +193,25 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>  		 * TODO: when handling multiple PSR instances a global spinlock
>  		 * will be needed to synchronize the value of shared register
>  		 */
> -		val = I915_READ(EDP_PSR_IMR);
> -		val |= EDP_PSR_ERROR(cpu_transcoder);
> -		I915_WRITE(EDP_PSR_IMR, val);
> +		if (INTEL_GEN(dev_priv) >= 12)
> +			mask_reg = TRANS_PSR_IMR(cpu_transcoder);
> +		else
> +			mask_reg = EDP_PSR_IMR;
> +
> +		val = I915_READ(mask_reg);
> +		val |= psr_error;
> +		I915_WRITE(mask_reg, val);
>  
>  		schedule_work(&dev_priv->psr.work);
>  	}
>  
> -	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> +	if (psr_iir & psr_entry) {
>  		dev_priv->psr.last_entry_attempt = time_ns;
>  		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>  			      transcoder_name(cpu_transcoder));
>  	}
>  
> -	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
> +	if (psr_iir & psr_exit) {
>  		dev_priv->psr.last_exit = time_ns;
>  		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>  			      transcoder_name(cpu_transcoder));
> @@ -632,7 +662,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
>  	if (INTEL_GEN(dev_priv) >= 9 &&
> -	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
> +	    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
>  		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
>  	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
>  	WARN_ON(dev_priv->psr.active);
> @@ -730,8 +760,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>  	 * first time that PSR HW tries to activate so lets keep PSR disabled
>  	 * to avoid any rendering problems.
>  	 */
> -	val = I915_READ(EDP_PSR_IIR);
> -	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
> +		val &= TRANS_PSR_ERROR;
> +	} else {
> +		val = I915_READ(EDP_PSR_IIR);
> +		val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
> +	}
>  	if (val) {
>  		dev_priv->psr.sink_not_reliable = true;
>  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
> @@ -787,7 +822,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>  
>  	if (!dev_priv->psr.active) {
>  		if (INTEL_GEN(dev_priv) >= 9 &&
> -		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
> +		    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
>  			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>  			WARN_ON(val & EDP_PSR2_ENABLE);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 46e4de8b8cd5..6570a23a68b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -6,6 +6,7 @@
>  #ifndef __INTEL_PSR_H__
>  #define __INTEL_PSR_H__
>  
> +#include "intel_display.h"
IMO we don't need to include this header.
>  #include "intel_frontbuffer.h"
>  
>  struct drm_i915_private;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 77391d8325bf..6024a6ef1c76 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2655,11 +2655,22 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  	}
>  
>  	if (iir & GEN8_DE_EDP_PSR) {
> -		u32 psr_iir = I915_READ(EDP_PSR_IIR);
> +		u32 psr_iir;
> +
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			enum transcoder trans = dev_priv->psr.transcoder;
> +
> +			psr_iir = I915_READ(TRANS_PSR_IIR(trans));
> +			I915_WRITE(TRANS_PSR_IIR(trans), psr_iir);
> +		} else {
> +			psr_iir = I915_READ(EDP_PSR_IIR);
> +			I915_WRITE(EDP_PSR_IIR, psr_iir);
> +		}
> +
> +		if (psr_iir)
> +			found = true;
>  
>  		intel_psr_irq_handler(dev_priv, psr_iir);
> -		I915_WRITE(EDP_PSR_IIR, psr_iir);
> -		found = true;
>  	}
>  
>  	if (!found)
> @@ -3279,8 +3290,23 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
>  
>  	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
>  
> -	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
> -	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		enum transcoder trans;
> +
> +		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> +			enum intel_display_power_domain domain;
> +
> +			domain = POWER_DOMAIN_TRANSCODER(trans);
> +			if (!intel_display_power_is_enabled(dev_priv, domain))
> +				continue;
> +
> +			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
> +			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
Lines over 80 char.
> +		}
> +	} else {
> +		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
> +		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
> +	}
>  
>  	for_each_pipe(dev_priv, pipe)
>  		if (intel_display_power_is_enabled(dev_priv,
> @@ -3793,7 +3819,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	else if (IS_BROADWELL(dev_priv))
>  		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
>  
> -	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		enum transcoder trans;
> +
> +		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> +			enum intel_display_power_domain domain;
> +
> +			domain = POWER_DOMAIN_TRANSCODER(trans);
> +			if (!intel_display_power_is_enabled(dev_priv, domain))
> +				continue;
> +
> +			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
> +		}
> +	} else {
> +		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> +	}
>  
>  	for_each_pipe(dev_priv, pipe) {
>  		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c6d99944630..3de02683d856 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4222,7 +4222,7 @@ enum {
>  #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
> -/* Bspec claims those aren't shifted but stay at 0x64800 */
> +/* Bspec claims those aren't shifted but stay at 0x64800 until TGL */
>  #define EDP_PSR_IMR				_MMIO(0x64834)
>  #define EDP_PSR_IIR				_MMIO(0x64838)
>  #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
> @@ -4232,6 +4232,14 @@ enum {
>  #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
>  #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
>  
> +#define _PSR_IMR_A				0x60814
> +#define _PSR_IIR_A				0x60818
> +#define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(tran, _PSR_IMR_A) /* TGL+ */
> +#define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(tran, _PSR_IIR_A) /* TGL+ */
IMO if /* TGL+ */ comment shifted above, it will satisfy the 80 char limit.  
> +#define   TRANS_PSR_ERROR			(1 << 2)
> +#define   TRANS_PSR_POST_EXIT			(1 << 1)
> +#define   TRANS_PSR_PRE_ENTRY			(1 << 0)
> +
>  #define _SRD_AUX_CTL_A				0x60810
>  #define _SRD_AUX_CTL_EDP			0x6f810
>  #define EDP_PSR_AUX_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
> -- 
> 2.23.0
> 
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Re: [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port

[Imre Deak]

On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> From BDW+ the PSR registers moved from DDIA to transcoder, so any port
> with a eDP panel connected can have PSR, so lets remove this
> limitation.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 81e3619cd905..0172b82858d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  
>  	/*
>  	 * HSW spec explicitly says PSR is tied to port A.
> -	 * BDW+ platforms have a instance of PSR registers per transcoder but
> -	 * for now it only supports one instance of PSR, so lets keep it
> -	 * hardcoded to PORT_A
> +	 * BDW+ platforms have a instance of PSR registers per transcoder.
>  	 */
> -	if (dig_port->base.port != PORT_A) {
> +	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {

Based on an earlier discussion with Art, before TGL PSR is not supposed
to be used anywhere else than port A.

Art could you confirm that?

>  		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>  		return;
>  	}
> -- 
> 2.23.0
> 
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Re: [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2

[Imre Deak]

On Fri, Aug 23, 2019 at 01:20:38AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> This fix unclaimed access warnings:
> 
> [  245.525788] ------------[ cut here ]------------
> [  245.525884] Unclaimed read from register 0x62900
> [  245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
> [  245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915]
> [  245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915
> [  245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019
> [  245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915]
> [  245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55
> [  245.526288] RSP: 0018:ffffc900006bf7d8 EFLAGS: 00010086
> [  245.526297] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
> [  245.526304] RDX: 0000000000000007 RSI: 0000000000000000 RDI: 00000000ffffffff
> [  245.526310] RBP: 0000000000061900 R08: 0000000000000000 R09: 0000000000000001
> [  245.526317] R10: 0000000000000006 R11: 0000000000000000 R12: 0000000000000001
> [  245.526324] R13: 0000000000000000 R14: ffff8882914f0d58 R15: 0000000000000206
> [  245.526332] FS:  00007fed2a3c39c0(0000) GS:ffff8882a8600000(0000) knlGS:0000000000000000
> [  245.526340] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [  245.526347] CR2: 00007fed28dff000 CR3: 00000002a086c006 CR4: 0000000000760ef0
> [  245.526354] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> [  245.526361] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> [  245.526367] PKRU: 55555554
> [  245.526373] Call Trace:
> [  245.526454]  gen11_fwtable_read32+0x219/0x250 [i915]
> [  245.526576]  intel_psr_activate+0x57/0x400 [i915]
> [  245.526697]  intel_psr_enable_locked+0x367/0x4b0 [i915]
> [  245.526828]  intel_psr_enable+0xa4/0xd0 [i915]
> [  245.526946]  intel_enable_ddi+0x127/0x2f0 [i915]
> [  245.527075]  intel_encoders_enable.isra.79+0x62/0x90 [i915]
> [  245.527202]  haswell_crtc_enable+0x2a2/0x850 [i915]
> [  245.527337]  intel_update_crtc+0x51/0x360 [i915]
> [  245.527466]  skl_update_crtcs+0x26c/0x300 [i915]
> [  245.527603]  intel_atomic_commit_tail+0x3e5/0x13c0 [i915]
> [  245.527757]  intel_atomic_commit+0x24d/0x2d0 [i915]
> [  245.527782]  drm_atomic_helper_set_config+0x7b/0x90
> [  245.527799]  drm_mode_setcrtc+0x1b4/0x6f0
> [  245.527856]  ? drm_mode_getcrtc+0x180/0x180
> [  245.527867]  drm_ioctl_kernel+0xad/0xf0
> [  245.527886]  drm_ioctl+0x2f4/0x3b0
> [  245.527902]  ? drm_mode_getcrtc+0x180/0x180
> [  245.527935]  ? rcu_read_lock_sched_held+0x6f/0x80
> [  245.527956]  do_vfs_ioctl+0xa0/0x6d0
> [  245.527970]  ? __task_pid_nr_ns+0xb6/0x200
> [  245.527991]  ksys_ioctl+0x35/0x70
> [  245.528009]  __x64_sys_ioctl+0x11/0x20
> [  245.528020]  do_syscall_64+0x55/0x180
> [  245.528034]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
> [  245.528042] RIP: 0033:0x7fed2cc7c3c7
> [  245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48
> [  245.528057] RSP: 002b:00007ffe36944378 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
> [  245.528067] RAX: ffffffffffffffda RBX: 00007ffe369443b0 RCX: 00007fed2cc7c3c7
> [  245.528074] RDX: 00007ffe369443b0 RSI: 00000000c06864a2 RDI: 0000000000000003
> [  245.528081] RBP: 00007ffe369443b0 R08: 0000000000000000 R09: 0000564c0173ae98
> [  245.528088] R10: 0000564c0173aeb8 R11: 0000000000000246 R12: 00000000c06864a2
> [  245.528095] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
> [  245.528128] irq event stamp: 140866
> [  245.528138] hardirqs last  enabled at (140865): [<ffffffff819a63dc>] _raw_spin_unlock_irqrestore+0x4c/0x60
> [  245.528148] hardirqs last disabled at (140866): [<ffffffff819a624d>] _raw_spin_lock_irqsave+0xd/0x50
> [  245.528158] softirqs last  enabled at (140860): [<ffffffff81c0038c>] __do_softirq+0x38c/0x499
> [  245.528170] softirqs last disabled at (140853): [<ffffffff810b4a09>] irq_exit+0xa9/0xc0
> [  245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
> [  245.528254] ---[ end trace 366069676e98a410 ]---
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cf07ab3d9280..4e6b3ae8a872 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -631,7 +631,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9 &&
> +	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
	    ^transcoder_has_psr2()

nit: Move the GEN check to transcoder_has_psr2()?

Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
>  	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
>  	WARN_ON(dev_priv->psr.active);
> @@ -785,7 +786,8 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>  	u32 val;
>  
>  	if (!dev_priv->psr.active) {
> -		if (INTEL_GEN(dev_priv) >= 9) {
> +		if (INTEL_GEN(dev_priv) >= 9 &&
> +		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
>  			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>  			WARN_ON(val & EDP_PSR2_ENABLE);
>  		}
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2

[Lucas De Marchi]

On Mon, Aug 26, 2019 at 05:21:56PM +0300, Imre Deak wrote:
>On Fri, Aug 23, 2019 at 01:20:38AM -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> This fix unclaimed access warnings:
>>
>> [  245.525788] ------------[ cut here ]------------
>> [  245.525884] Unclaimed read from register 0x62900
>> [  245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
>> [  245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915]
>> [  245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915
>> [  245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019
>> [  245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915]
>> [  245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55
>> [  245.526288] RSP: 0018:ffffc900006bf7d8 EFLAGS: 00010086
>> [  245.526297] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
>> [  245.526304] RDX: 0000000000000007 RSI: 0000000000000000 RDI: 00000000ffffffff
>> [  245.526310] RBP: 0000000000061900 R08: 0000000000000000 R09: 0000000000000001
>> [  245.526317] R10: 0000000000000006 R11: 0000000000000000 R12: 0000000000000001
>> [  245.526324] R13: 0000000000000000 R14: ffff8882914f0d58 R15: 0000000000000206
>> [  245.526332] FS:  00007fed2a3c39c0(0000) GS:ffff8882a8600000(0000) knlGS:0000000000000000
>> [  245.526340] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [  245.526347] CR2: 00007fed28dff000 CR3: 00000002a086c006 CR4: 0000000000760ef0
>> [  245.526354] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>> [  245.526361] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>> [  245.526367] PKRU: 55555554
>> [  245.526373] Call Trace:
>> [  245.526454]  gen11_fwtable_read32+0x219/0x250 [i915]
>> [  245.526576]  intel_psr_activate+0x57/0x400 [i915]
>> [  245.526697]  intel_psr_enable_locked+0x367/0x4b0 [i915]
>> [  245.526828]  intel_psr_enable+0xa4/0xd0 [i915]
>> [  245.526946]  intel_enable_ddi+0x127/0x2f0 [i915]
>> [  245.527075]  intel_encoders_enable.isra.79+0x62/0x90 [i915]
>> [  245.527202]  haswell_crtc_enable+0x2a2/0x850 [i915]
>> [  245.527337]  intel_update_crtc+0x51/0x360 [i915]
>> [  245.527466]  skl_update_crtcs+0x26c/0x300 [i915]
>> [  245.527603]  intel_atomic_commit_tail+0x3e5/0x13c0 [i915]
>> [  245.527757]  intel_atomic_commit+0x24d/0x2d0 [i915]
>> [  245.527782]  drm_atomic_helper_set_config+0x7b/0x90
>> [  245.527799]  drm_mode_setcrtc+0x1b4/0x6f0
>> [  245.527856]  ? drm_mode_getcrtc+0x180/0x180
>> [  245.527867]  drm_ioctl_kernel+0xad/0xf0
>> [  245.527886]  drm_ioctl+0x2f4/0x3b0
>> [  245.527902]  ? drm_mode_getcrtc+0x180/0x180
>> [  245.527935]  ? rcu_read_lock_sched_held+0x6f/0x80
>> [  245.527956]  do_vfs_ioctl+0xa0/0x6d0
>> [  245.527970]  ? __task_pid_nr_ns+0xb6/0x200
>> [  245.527991]  ksys_ioctl+0x35/0x70
>> [  245.528009]  __x64_sys_ioctl+0x11/0x20
>> [  245.528020]  do_syscall_64+0x55/0x180
>> [  245.528034]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
>> [  245.528042] RIP: 0033:0x7fed2cc7c3c7
>> [  245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48
>> [  245.528057] RSP: 002b:00007ffe36944378 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
>> [  245.528067] RAX: ffffffffffffffda RBX: 00007ffe369443b0 RCX: 00007fed2cc7c3c7
>> [  245.528074] RDX: 00007ffe369443b0 RSI: 00000000c06864a2 RDI: 0000000000000003
>> [  245.528081] RBP: 00007ffe369443b0 R08: 0000000000000000 R09: 0000564c0173ae98
>> [  245.528088] R10: 0000564c0173aeb8 R11: 0000000000000246 R12: 00000000c06864a2
>> [  245.528095] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
>> [  245.528128] irq event stamp: 140866
>> [  245.528138] hardirqs last  enabled at (140865): [<ffffffff819a63dc>] _raw_spin_unlock_irqrestore+0x4c/0x60
>> [  245.528148] hardirqs last disabled at (140866): [<ffffffff819a624d>] _raw_spin_lock_irqsave+0xd/0x50
>> [  245.528158] softirqs last  enabled at (140860): [<ffffffff81c0038c>] __do_softirq+0x38c/0x499
>> [  245.528170] softirqs last disabled at (140853): [<ffffffff810b4a09>] irq_exit+0xa9/0xc0
>> [  245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
>> [  245.528254] ---[ end trace 366069676e98a410 ]---
>>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index cf07ab3d9280..4e6b3ae8a872 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -631,7 +631,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>>  {
>>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (INTEL_GEN(dev_priv) >= 9 &&
>> +	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
>	    ^transcoder_has_psr2()

yep, it diverged on patch that got applied.

>
>nit: Move the GEN check to transcoder_has_psr2()?

Done and queued for the next rev.

>
>Either way:
>Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks
Lucas De Marchi

>
>>  		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
>>  	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
>>  	WARN_ON(dev_priv->psr.active);
>> @@ -785,7 +786,8 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>>  	u32 val;
>>
>>  	if (!dev_priv->psr.active) {
>> -		if (INTEL_GEN(dev_priv) >= 9) {
>> +		if (INTEL_GEN(dev_priv) >= 9 &&
>> +		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
>>  			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>>  			WARN_ON(val & EDP_PSR2_ENABLE);
>>  		}
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions

[Lucas De Marchi]

On Mon, Aug 26, 2019 at 03:23:55PM +0530, Anshuman Gupta wrote:
>On 2019-08-23 at 01:20:40 -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> For older gens PSR IIR and IMR had a fixed address that was not
>> relative to anything, but from TGL those registers moved to each
>> transcoder offset.
>>
>> So here adding a new macro and a new PSR irq handler with the
>> transcoder parameter.
>>
>There are few minor comments below, apart from below comments
>patch is looks ok to me.

Those are fixed and queued for next revision.

>Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>

Thanks
Lucas De Marchi

>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++++++++------
>>  drivers/gpu/drm/i915/display/intel_psr.h |  1 +
>>  drivers/gpu/drm/i915/i915_irq.c          | 52 +++++++++++++++---
>>  drivers/gpu/drm/i915/i915_reg.h          | 10 +++-
>>  4 files changed, 107 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2429328f963e..c33aa16ed038 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -91,20 +91,33 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>>  static void psr_irq_control(struct drm_i915_private *dev_priv)
>>  {
>>  	enum transcoder trans = dev_priv->psr.transcoder;
>> -	u32 val, mask;
>> +	u32 psr_error, psr_entry, psr_exit, mask, val;
>> +	i915_reg_t mask_reg;
>> +
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		psr_error = TRANS_PSR_ERROR;
>> +		psr_entry = TRANS_PSR_PRE_ENTRY;
>> +		psr_exit = TRANS_PSR_POST_EXIT;
>> +		mask_reg = TRANS_PSR_IMR(trans);
>> +	} else {
>> +		psr_error = EDP_PSR_ERROR(trans);
>> +		psr_entry = EDP_PSR_PRE_ENTRY(trans);
>> +		psr_exit = EDP_PSR_POST_EXIT(trans);
>> +		mask_reg = EDP_PSR_IMR;
>> +	}
>>
>> -	mask = EDP_PSR_ERROR(trans);
>> +	mask = psr_error;
>>  	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
>> -		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
>> +		mask |= psr_exit | psr_entry;
>>
>>  	/*
>>  	 * TODO: when handling multiple PSR instances a global spinlock will be
>>  	 * needed to synchronize the value of shared register
>>  	 */
>> -	val = I915_READ(EDP_PSR_IMR);
>> -	val &= ~EDP_PSR_TRANS_MASK(trans);
>> +	val = I915_READ(mask_reg);
>> +	val &= ~(psr_error | psr_entry | psr_exit);
>>  	val |= ~mask;
>> -	I915_WRITE(EDP_PSR_IMR, val);
>> +	I915_WRITE(mask_reg, val);
>>  }
>>
>>  static void psr_event_print(u32 val, bool psr2_enabled)
>> @@ -147,9 +160,21 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>>  {
>>  	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
>> +	u32 psr_error, psr_entry, psr_exit;
>>  	ktime_t time_ns =  ktime_get();
>>
>> -	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		psr_error = TRANS_PSR_ERROR;
>> +		psr_entry = TRANS_PSR_PRE_ENTRY;
>> +		psr_exit = TRANS_PSR_POST_EXIT;
>> +	} else {
>> +		psr_error = EDP_PSR_ERROR(cpu_transcoder);
>> +		psr_entry = EDP_PSR_PRE_ENTRY(cpu_transcoder);
>> +		psr_exit = EDP_PSR_POST_EXIT(cpu_transcoder);
>> +	}
>> +
>> +	if (psr_iir & psr_error) {
>> +		i915_reg_t mask_reg;
>>  		u32 val;
>>
>>  		DRM_WARN("[transcoder %s] PSR aux error\n",
>> @@ -168,20 +193,25 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>>  		 * TODO: when handling multiple PSR instances a global spinlock
>>  		 * will be needed to synchronize the value of shared register
>>  		 */
>> -		val = I915_READ(EDP_PSR_IMR);
>> -		val |= EDP_PSR_ERROR(cpu_transcoder);
>> -		I915_WRITE(EDP_PSR_IMR, val);
>> +		if (INTEL_GEN(dev_priv) >= 12)
>> +			mask_reg = TRANS_PSR_IMR(cpu_transcoder);
>> +		else
>> +			mask_reg = EDP_PSR_IMR;
>> +
>> +		val = I915_READ(mask_reg);
>> +		val |= psr_error;
>> +		I915_WRITE(mask_reg, val);
>>
>>  		schedule_work(&dev_priv->psr.work);
>>  	}
>>
>> -	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
>> +	if (psr_iir & psr_entry) {
>>  		dev_priv->psr.last_entry_attempt = time_ns;
>>  		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>>  			      transcoder_name(cpu_transcoder));
>>  	}
>>
>> -	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
>> +	if (psr_iir & psr_exit) {
>>  		dev_priv->psr.last_exit = time_ns;
>>  		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>>  			      transcoder_name(cpu_transcoder));
>> @@ -632,7 +662,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>
>>  	if (INTEL_GEN(dev_priv) >= 9 &&
>> -	    psr2_supported(dev_priv, dev_priv->psr.transcoder))
>> +	    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
>>  		WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
>>  	WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
>>  	WARN_ON(dev_priv->psr.active);
>> @@ -730,8 +760,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>>  	 * first time that PSR HW tries to activate so lets keep PSR disabled
>>  	 * to avoid any rendering problems.
>>  	 */
>> -	val = I915_READ(EDP_PSR_IIR);
>> -	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
>> +		val &= TRANS_PSR_ERROR;
>> +	} else {
>> +		val = I915_READ(EDP_PSR_IIR);
>> +		val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
>> +	}
>>  	if (val) {
>>  		dev_priv->psr.sink_not_reliable = true;
>>  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
>> @@ -787,7 +822,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>>
>>  	if (!dev_priv->psr.active) {
>>  		if (INTEL_GEN(dev_priv) >= 9 &&
>> -		    psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
>> +		    transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
>>  			val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>>  			WARN_ON(val & EDP_PSR2_ENABLE);
>>  		}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 46e4de8b8cd5..6570a23a68b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -6,6 +6,7 @@
>>  #ifndef __INTEL_PSR_H__
>>  #define __INTEL_PSR_H__
>>
>> +#include "intel_display.h"
>IMO we don't need to include this header.
>>  #include "intel_frontbuffer.h"
>>
>>  struct drm_i915_private;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 77391d8325bf..6024a6ef1c76 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2655,11 +2655,22 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>>  	}
>>
>>  	if (iir & GEN8_DE_EDP_PSR) {
>> -		u32 psr_iir = I915_READ(EDP_PSR_IIR);
>> +		u32 psr_iir;
>> +
>> +		if (INTEL_GEN(dev_priv) >= 12) {
>> +			enum transcoder trans = dev_priv->psr.transcoder;
>> +
>> +			psr_iir = I915_READ(TRANS_PSR_IIR(trans));
>> +			I915_WRITE(TRANS_PSR_IIR(trans), psr_iir);
>> +		} else {
>> +			psr_iir = I915_READ(EDP_PSR_IIR);
>> +			I915_WRITE(EDP_PSR_IIR, psr_iir);
>> +		}
>> +
>> +		if (psr_iir)
>> +			found = true;
>>
>>  		intel_psr_irq_handler(dev_priv, psr_iir);
>> -		I915_WRITE(EDP_PSR_IIR, psr_iir);
>> -		found = true;
>>  	}
>>
>>  	if (!found)
>> @@ -3279,8 +3290,23 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
>>
>>  	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
>>
>> -	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>> -	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		enum transcoder trans;
>> +
>> +		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
>> +			enum intel_display_power_domain domain;
>> +
>> +			domain = POWER_DOMAIN_TRANSCODER(trans);
>> +			if (!intel_display_power_is_enabled(dev_priv, domain))
>> +				continue;
>> +
>> +			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
>> +			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
>Lines over 80 char.
>> +		}
>> +	} else {
>> +		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>> +		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
>> +	}
>>
>>  	for_each_pipe(dev_priv, pipe)
>>  		if (intel_display_power_is_enabled(dev_priv,
>> @@ -3793,7 +3819,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>  	else if (IS_BROADWELL(dev_priv))
>>  		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
>>
>> -	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		enum transcoder trans;
>> +
>> +		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
>> +			enum intel_display_power_domain domain;
>> +
>> +			domain = POWER_DOMAIN_TRANSCODER(trans);
>> +			if (!intel_display_power_is_enabled(dev_priv, domain))
>> +				continue;
>> +
>> +			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
>> +		}
>> +	} else {
>> +		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
>> +	}
>>
>>  	for_each_pipe(dev_priv, pipe) {
>>  		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1c6d99944630..3de02683d856 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4222,7 +4222,7 @@ enum {
>>  #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
>>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>>
>> -/* Bspec claims those aren't shifted but stay at 0x64800 */
>> +/* Bspec claims those aren't shifted but stay at 0x64800 until TGL */
>>  #define EDP_PSR_IMR				_MMIO(0x64834)
>>  #define EDP_PSR_IIR				_MMIO(0x64838)
>>  #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
>> @@ -4232,6 +4232,14 @@ enum {
>>  #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
>>  #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
>>
>> +#define _PSR_IMR_A				0x60814
>> +#define _PSR_IIR_A				0x60818
>> +#define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(tran, _PSR_IMR_A) /* TGL+ */
>> +#define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(tran, _PSR_IIR_A) /* TGL+ */
>IMO if /* TGL+ */ comment shifted above, it will satisfy the 80 char limit.
>> +#define   TRANS_PSR_ERROR			(1 << 2)
>> +#define   TRANS_PSR_POST_EXIT			(1 << 1)
>> +#define   TRANS_PSR_PRE_ENTRY			(1 << 0)
>> +
>>  #define _SRD_AUX_CTL_A				0x60810
>>  #define _SRD_AUX_CTL_EDP			0x6f810
>>  #define EDP_PSR_AUX_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
>> --
>> 2.23.0
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Lucas De Marchi]

On Sat, Aug 24, 2019 at 04:36:52PM +0530, Anshuman Gupta wrote:
>On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> TGL PSR2 HW supports a bigger resolution, so lets add it
>>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index c33aa16ed038..5d24f1c47a2b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  		return false;
>>  	}
>>
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>As per B.Specs:28692 on few Gen11 platform, PSR2 supports max resolution of 5120X3200.
>Do we need to handle those Gen11 platform here?

the only thing I see there for gen11 is:

	"PSR2 maximum pipe horizontal active size 4096 pixels."

Lucas De Marchi

>> +		psr_max_h = 5120;
>> +		psr_max_v = 3200;
>> +	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>  		psr_max_h = 4096;
>>  		psr_max_v = 2304;
>>  	} else if (IS_GEN(dev_priv, 9)) {
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Souza, Jose]

On Mon, 2019-08-26 at 10:10 -0700, Lucas De Marchi wrote:
> On Sat, Aug 24, 2019 at 04:36:52PM +0530, Anshuman Gupta wrote:
> > On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
> > > From: José Roberto de Souza <jose.souza@intel.com>
> > > 
> > > TGL PSR2 HW supports a bigger resolution, so lets add it
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index c33aa16ed038..5d24f1c47a2b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct
> > > intel_dp *intel_dp,
> > >  		return false;
> > >  	}
> > > 
> > > -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> > > +	if (INTEL_GEN(dev_priv) >= 12) {
> > As per B.Specs:28692 on few Gen11 platform, PSR2 supports max
> > resolution of 5120X3200.
> > Do we need to handle those Gen11 platform here?
> 
> the only thing I see there for gen11 is:
> 
> 	"PSR2 maximum pipe horizontal active size 4096 pixels."


We are following BSpec 7713

> 
> Lucas De Marchi
> 
> > > +		psr_max_h = 5120;
> > > +		psr_max_v = 3200;
> > > +	} else if (INTEL_GEN(dev_priv) >= 10 ||
> > > IS_GEMINILAKE(dev_priv)) {
> > >  		psr_max_h = 4096;
> > >  		psr_max_v = 2304;
> > >  	} else if (IS_GEN(dev_priv, 9)) {
> > > --
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use

[Imre Deak]

On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> It was enabling and checking PSR interruptions in every transcoder
> while it should keep the interruptions on the non-used transcoders
> masked.
> 
> This also already prepares for future when more than one PSR instance
> will be allowed.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
>  drivers/gpu/drm/i915/i915_reg.h          |  13 +--
>  2 files changed, 59 insertions(+), 94 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 28b62e587204..81e3619cd905 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> -static int edp_psr_shift(enum transcoder cpu_transcoder)
> +static void psr_irq_control(struct drm_i915_private *dev_priv)
>  {
> -	switch (cpu_transcoder) {
> -	case TRANSCODER_A:
> -		return EDP_PSR_TRANSCODER_A_SHIFT;
> -	case TRANSCODER_B:
> -		return EDP_PSR_TRANSCODER_B_SHIFT;
> -	case TRANSCODER_C:
> -		return EDP_PSR_TRANSCODER_C_SHIFT;
> -	default:
> -		MISSING_CASE(cpu_transcoder);
> -		/* fallthrough */
> -	case TRANSCODER_EDP:
> -		return EDP_PSR_TRANSCODER_EDP_SHIFT;
> -	}
> -}
> +	enum transcoder trans = dev_priv->psr.transcoder;

This is called from intel_psr_debug_set() where psr.transcoder may be
uninited.

> +	u32 val, mask;
>  
> -static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
> -{
> -	u32 debug_mask, mask;
> -	enum transcoder cpu_transcoder;
> -	u32 transcoders = BIT(TRANSCODER_EDP);
> -
> -	if (INTEL_GEN(dev_priv) >= 8)
> -		transcoders |= BIT(TRANSCODER_A) |
> -			       BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C);
> -
> -	debug_mask = 0;
> -	mask = 0;
> -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> -		int shift = edp_psr_shift(cpu_transcoder);
> -
> -		mask |= EDP_PSR_ERROR(shift);
> -		debug_mask |= EDP_PSR_POST_EXIT(shift) |
> -			      EDP_PSR_PRE_ENTRY(shift);
> -	}
> +	mask = EDP_PSR_ERROR(trans);
> +	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
> +		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
>  
> -	if (debug & I915_PSR_DEBUG_IRQ)
> -		mask |= debug_mask;
> -
> -	I915_WRITE(EDP_PSR_IMR, ~mask);
> +	/*
> +	 * TODO: when handling multiple PSR instances a global spinlock will be
> +	 * needed to synchronize the value of shared register
> +	 */
> +	val = I915_READ(EDP_PSR_IMR);
> +	val &= ~EDP_PSR_TRANS_MASK(trans);
> +	val |= ~mask;
> +	I915_WRITE(EDP_PSR_IMR, val);
>  }
>  
>  static void psr_event_print(u32 val, bool psr2_enabled)
> @@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>  
>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>  {
> -	u32 transcoders = BIT(TRANSCODER_EDP);
> -	enum transcoder cpu_transcoder;
> +	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
>  	ktime_t time_ns =  ktime_get();
> -	u32 mask = 0;
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> -		transcoders |= BIT(TRANSCODER_A) |
> -			       BIT(TRANSCODER_B) |
> -			       BIT(TRANSCODER_C);
> +	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
> +		u32 val;
>  
> -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {

I think we should still catch all interrupts, log the unexpected ones
and react only on the expected one in intel_psr_work().

> -		int shift = edp_psr_shift(cpu_transcoder);
> +		DRM_WARN("[transcoder %s] PSR aux error\n",
> +			 transcoder_name(cpu_transcoder));
>  
> -		if (psr_iir & EDP_PSR_ERROR(shift)) {
> -			DRM_WARN("[transcoder %s] PSR aux error\n",
> -				 transcoder_name(cpu_transcoder));
> +		dev_priv->psr.irq_aux_error = true;
>  
> -			dev_priv->psr.irq_aux_error = true;
> +		/*
> +		 * If this interruption is not masked it will keep
> +		 * interrupting so fast that it prevents the scheduled
> +		 * work to run.
> +		 * Also after a PSR error, we don't want to arm PSR
> +		 * again so we don't care about unmask the interruption
> +		 * or unset irq_aux_error.
> +		 *
> +		 * TODO: when handling multiple PSR instances a global spinlock
> +		 * will be needed to synchronize the value of shared register
> +		 */
> +		val = I915_READ(EDP_PSR_IMR);
> +		val |= EDP_PSR_ERROR(cpu_transcoder);
> +		I915_WRITE(EDP_PSR_IMR, val);
>  
> -			/*
> -			 * If this interruption is not masked it will keep
> -			 * interrupting so fast that it prevents the scheduled
> -			 * work to run.
> -			 * Also after a PSR error, we don't want to arm PSR
> -			 * again so we don't care about unmask the interruption
> -			 * or unset irq_aux_error.
> -			 */
> -			mask |= EDP_PSR_ERROR(shift);
> -		}
> +		schedule_work(&dev_priv->psr.work);

Would be better not to reorder intel_psr_work() and printing the events
below.

> +	}
>  
> -		if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
> -			dev_priv->psr.last_entry_attempt = time_ns;
> -			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> -				      transcoder_name(cpu_transcoder));
> -		}
> +	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> +		dev_priv->psr.last_entry_attempt = time_ns;
> +		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> +			      transcoder_name(cpu_transcoder));
> +	}
>  
> -		if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
> -			dev_priv->psr.last_exit = time_ns;
> -			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> -				      transcoder_name(cpu_transcoder));
> +	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
> +		dev_priv->psr.last_exit = time_ns;
> +		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> +			      transcoder_name(cpu_transcoder));
>  
> -			if (INTEL_GEN(dev_priv) >= 9) {
> -				u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
> -				bool psr2_enabled = dev_priv->psr.psr2_enabled;
> +		if (INTEL_GEN(dev_priv) >= 9) {
> +			u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
> +			bool psr2_enabled = dev_priv->psr.psr2_enabled;
>  
> -				I915_WRITE(PSR_EVENT(cpu_transcoder), val);
> -				psr_event_print(val, psr2_enabled);
> -			}
> +			I915_WRITE(PSR_EVENT(cpu_transcoder), val);
> +			psr_event_print(val, psr2_enabled);
>  		}
>  	}
> -
> -	if (mask) {
> -		mask |= I915_READ(EDP_PSR_IMR);
> -		I915_WRITE(EDP_PSR_IMR, mask);
> -
> -		schedule_work(&dev_priv->psr.work);
> -	}
>  }
>  
>  static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> @@ -737,7 +703,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  
>  	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
>  
> -	psr_irq_control(dev_priv, dev_priv->psr.debug);
> +	psr_irq_control(dev_priv);
>  }
>  
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> @@ -762,7 +728,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>  	 * to avoid any rendering problems.
>  	 */
>  	val = I915_READ(EDP_PSR_IIR);
> -	val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
> +	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
>  	if (val) {
>  		dev_priv->psr.sink_not_reliable = true;
>  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
> @@ -1110,7 +1076,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
>  
>  	old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
>  	dev_priv->psr.debug = val;
> -	psr_irq_control(dev_priv, dev_priv->psr.debug);
> +	psr_irq_control(dev_priv);
>  
>  	mutex_unlock(&dev_priv->psr.lock);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02e1ef10c47e..1c6d99944630 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4225,13 +4225,12 @@ enum {
>  /* Bspec claims those aren't shifted but stay at 0x64800 */
>  #define EDP_PSR_IMR				_MMIO(0x64834)
>  #define EDP_PSR_IIR				_MMIO(0x64838)
> -#define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
> -#define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
> -#define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
> -#define   EDP_PSR_TRANSCODER_C_SHIFT		24
> -#define   EDP_PSR_TRANSCODER_B_SHIFT		16
> -#define   EDP_PSR_TRANSCODER_A_SHIFT		8
> -#define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
> +#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
> +						 0 : ((trans) + 1) * 8)

(trans - TRANSCODER_A) + 1

to not depend on the enum value of TRANSCODER_A.

> +#define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
> +#define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
> +#define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
> +#define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
>  
>  #define _SRD_AUX_CTL_A				0x60810
>  #define _SRD_AUX_CTL_EDP			0x6f810
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Lucas De Marchi]

On Mon, Aug 26, 2019 at 10:17:40AM -0700, Jose Souza wrote:
>On Mon, 2019-08-26 at 10:10 -0700, Lucas De Marchi wrote:
>> On Sat, Aug 24, 2019 at 04:36:52PM +0530, Anshuman Gupta wrote:
>> > On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
>> > > From: José Roberto de Souza <jose.souza@intel.com>
>> > >
>> > > TGL PSR2 HW supports a bigger resolution, so lets add it
>> > >
>> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>> > >  1 file changed, 4 insertions(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> > > b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > index c33aa16ed038..5d24f1c47a2b 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct
>> > > intel_dp *intel_dp,
>> > >  		return false;
>> > >  	}
>> > >
>> > > -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>> > > +	if (INTEL_GEN(dev_priv) >= 12) {
>> > As per B.Specs:28692 on few Gen11 platform, PSR2 supports max
>> > resolution of 5120X3200.
>> > Do we need to handle those Gen11 platform here?
>>
>> the only thing I see there for gen11 is:
>>
>> 	"PSR2 maximum pipe horizontal active size 4096 pixels."
>
>
>We are following BSpec 7713

I think you meant 50422.

I will add "BSpec 50422, 49199" to the commit message.

Lucas De Marchi

>
>>
>> Lucas De Marchi
>>
>> > > +		psr_max_h = 5120;
>> > > +		psr_max_v = 3200;
>> > > +	} else if (INTEL_GEN(dev_priv) >= 10 ||
>> > > IS_GEMINILAKE(dev_priv)) {
>> > >  		psr_max_h = 4096;
>> > >  		psr_max_v = 2304;
>> > >  	} else if (IS_GEN(dev_priv, 9)) {
>> > > --
>> > > 2.23.0
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW

[Gupta, Anshuman]

Validated with respect to B.Specs:49199 and 50422.

On 8/26/2019 10:40 PM, Lucas De Marchi wrote:
> On Sat, Aug 24, 2019 at 04:36:52PM +0530, Anshuman Gupta wrote:
>> On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
>>> From: José Roberto de Souza <jose.souza@intel.com>
>>>
>>> TGL PSR2 HW supports a bigger resolution, so lets add it
>>>
>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index c33aa16ed038..5d24f1c47a2b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct 
>>> intel_dp *intel_dp,
>>>          return false;
>>>      }
>>>
>>> -    if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>> +    if (INTEL_GEN(dev_priv) >= 12) {
>> As per B.Specs:28692 on few Gen11 platform, PSR2 supports max 
>> resolution of 5120X3200.
>> Do we need to handle those Gen11 platform here?
> 
> the only thing I see there for gen11 is:
> 
>      "PSR2 maximum pipe horizontal active size 4096 pixels."
> 
> Lucas De Marchi
> 
>>> +        psr_max_h = 5120;
>>> +        psr_max_v = 3200;
>>> +    } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>>          psr_max_h = 4096;
>>>          psr_max_v = 2304;
>>>      } else if (IS_GEN(dev_priv, 9)) {
>>> -- 
>>> 2.23.0
>>>
>>> _______________________________________________
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>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port

[Runyan, Arthur J]

> -----Original Message-----
> From: Imre Deak <imre.deak@intel.com>
> Sent: Monday, 26 August, 2019 6:42 AM
> To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any
> eDP port
> 
> On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > From BDW+ the PSR registers moved from DDIA to transcoder, so any port
> > with a eDP panel connected can have PSR, so lets remove this
> > limitation.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 81e3619cd905..0172b82858d9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> >
> >  	/*
> >  	 * HSW spec explicitly says PSR is tied to port A.
> > -	 * BDW+ platforms have a instance of PSR registers per transcoder but
> > -	 * for now it only supports one instance of PSR, so lets keep it
> > -	 * hardcoded to PORT_A
> > +	 * BDW+ platforms have a instance of PSR registers per transcoder.
> >  	 */
> > -	if (dig_port->base.port != PORT_A) {
> > +	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
> 
> Based on an earlier discussion with Art, before TGL PSR is not supposed
> to be used anywhere else than port A.
> 
> Art could you confirm that?

Correct.  
PSR1 is limited to DDIA until Tigerlake.  There are registers for PSR on the other 
transcoders/ports because of reuse, but hardware isn't fully hooked up or validated.
PSR2 is still limited to DDIA on Tigerlake.

> 
> >  		DRM_DEBUG_KMS("PSR condition failed: Port not
> supported\n");
> >  		return;
> >  	}
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port

[Lucas De Marchi]

On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
>> -----Original Message-----
>> From: Imre Deak <imre.deak@intel.com>
>> Sent: Monday, 26 August, 2019 6:42 AM
>> To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>; Runyan, Arthur J <arthur.j.runyan@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
>> <dhinakaran.pandiyan@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any
>> eDP port
>>
>> On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
>> > From: José Roberto de Souza <jose.souza@intel.com>
>> >
>> > From BDW+ the PSR registers moved from DDIA to transcoder, so any port
>> > with a eDP panel connected can have PSR, so lets remove this
>> > limitation.
>> >
>> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++----
>> >  1 file changed, 2 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> > index 81e3619cd905..0172b82858d9 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp
>> *intel_dp,
>> >
>> >  	/*
>> >  	 * HSW spec explicitly says PSR is tied to port A.
>> > -	 * BDW+ platforms have a instance of PSR registers per transcoder but
>> > -	 * for now it only supports one instance of PSR, so lets keep it
>> > -	 * hardcoded to PORT_A
>> > +	 * BDW+ platforms have a instance of PSR registers per transcoder.
>> >  	 */
>> > -	if (dig_port->base.port != PORT_A) {
>> > +	if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
>>
>> Based on an earlier discussion with Art, before TGL PSR is not supposed
>> to be used anywhere else than port A.
>>
>> Art could you confirm that?
>
>Correct.
>PSR1 is limited to DDIA until Tigerlake.  There are registers for PSR on the other
>transcoders/ports because of reuse, but hardware isn't fully hooked up or validated.
>PSR2 is still limited to DDIA on Tigerlake.

thank you both for confirming. José, I think we need to drop this patch
and rebase the rest so we don't do anything before Tiger Lake. I will
work on it.

Lucas De Marchi

>
>>
>> >  		DRM_DEBUG_KMS("PSR condition failed: Port not
>> supported\n");
>> >  		return;
>> >  	}
>> > --
>> > 2.23.0
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use

[Lucas De Marchi]

On Mon, Aug 26, 2019 at 08:28:33PM +0300, Imre Deak wrote:
>On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> It was enabling and checking PSR interruptions in every transcoder
>> while it should keep the interruptions on the non-used transcoders
>> masked.
>>
>> This also already prepares for future when more than one PSR instance
>> will be allowed.
>>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
>>  drivers/gpu/drm/i915/i915_reg.h          |  13 +--
>>  2 files changed, 59 insertions(+), 94 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 28b62e587204..81e3619cd905 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>>  	}
>>  }
>>
>> -static int edp_psr_shift(enum transcoder cpu_transcoder)
>> +static void psr_irq_control(struct drm_i915_private *dev_priv)
>>  {
>> -	switch (cpu_transcoder) {
>> -	case TRANSCODER_A:
>> -		return EDP_PSR_TRANSCODER_A_SHIFT;
>> -	case TRANSCODER_B:
>> -		return EDP_PSR_TRANSCODER_B_SHIFT;
>> -	case TRANSCODER_C:
>> -		return EDP_PSR_TRANSCODER_C_SHIFT;
>> -	default:
>> -		MISSING_CASE(cpu_transcoder);
>> -		/* fallthrough */
>> -	case TRANSCODER_EDP:
>> -		return EDP_PSR_TRANSCODER_EDP_SHIFT;
>> -	}
>> -}
>> +	enum transcoder trans = dev_priv->psr.transcoder;
>
>This is called from intel_psr_debug_set() where psr.transcoder may be
>uninited.
>
>> +	u32 val, mask;
>>
>> -static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
>> -{
>> -	u32 debug_mask, mask;
>> -	enum transcoder cpu_transcoder;
>> -	u32 transcoders = BIT(TRANSCODER_EDP);
>> -
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> -		transcoders |= BIT(TRANSCODER_A) |
>> -			       BIT(TRANSCODER_B) |
>> -			       BIT(TRANSCODER_C);
>> -
>> -	debug_mask = 0;
>> -	mask = 0;
>> -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
>> -		int shift = edp_psr_shift(cpu_transcoder);
>> -
>> -		mask |= EDP_PSR_ERROR(shift);
>> -		debug_mask |= EDP_PSR_POST_EXIT(shift) |
>> -			      EDP_PSR_PRE_ENTRY(shift);
>> -	}
>> +	mask = EDP_PSR_ERROR(trans);
>> +	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
>> +		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
>>
>> -	if (debug & I915_PSR_DEBUG_IRQ)
>> -		mask |= debug_mask;
>> -
>> -	I915_WRITE(EDP_PSR_IMR, ~mask);
>> +	/*
>> +	 * TODO: when handling multiple PSR instances a global spinlock will be
>> +	 * needed to synchronize the value of shared register
>> +	 */
>> +	val = I915_READ(EDP_PSR_IMR);
>> +	val &= ~EDP_PSR_TRANS_MASK(trans);
>> +	val |= ~mask;
>> +	I915_WRITE(EDP_PSR_IMR, val);
>>  }
>>
>>  static void psr_event_print(u32 val, bool psr2_enabled)
>> @@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>>
>>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>>  {
>> -	u32 transcoders = BIT(TRANSCODER_EDP);
>> -	enum transcoder cpu_transcoder;
>> +	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
>>  	ktime_t time_ns =  ktime_get();
>> -	u32 mask = 0;
>>
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> -		transcoders |= BIT(TRANSCODER_A) |
>> -			       BIT(TRANSCODER_B) |
>> -			       BIT(TRANSCODER_C);
>> +	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
>> +		u32 val;
>>
>> -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
>
>I think we should still catch all interrupts, log the unexpected ones
>and react only on the expected one in intel_psr_work().

could you expand more on this? there is only one PSR instance hence only
one possible transcoder coming from dev_priv->psr.transcoder. Looping here just to
warn seems wasteful.

>
>> -		int shift = edp_psr_shift(cpu_transcoder);
>> +		DRM_WARN("[transcoder %s] PSR aux error\n",
>> +			 transcoder_name(cpu_transcoder));
>>
>> -		if (psr_iir & EDP_PSR_ERROR(shift)) {
>> -			DRM_WARN("[transcoder %s] PSR aux error\n",
>> -				 transcoder_name(cpu_transcoder));
>> +		dev_priv->psr.irq_aux_error = true;
>>
>> -			dev_priv->psr.irq_aux_error = true;
>> +		/*
>> +		 * If this interruption is not masked it will keep
>> +		 * interrupting so fast that it prevents the scheduled
>> +		 * work to run.
>> +		 * Also after a PSR error, we don't want to arm PSR
>> +		 * again so we don't care about unmask the interruption
>> +		 * or unset irq_aux_error.
>> +		 *
>> +		 * TODO: when handling multiple PSR instances a global spinlock
>> +		 * will be needed to synchronize the value of shared register

I'm not really a fan of these TODO for multiple PSR instances. When/if
we add them, we won't really be able to rely on these TODO comments and
will rather need to evaluate the whole scenario.

>> +		 */
>> +		val = I915_READ(EDP_PSR_IMR);
>> +		val |= EDP_PSR_ERROR(cpu_transcoder);
>> +		I915_WRITE(EDP_PSR_IMR, val);
>>
>> -			/*
>> -			 * If this interruption is not masked it will keep
>> -			 * interrupting so fast that it prevents the scheduled
>> -			 * work to run.
>> -			 * Also after a PSR error, we don't want to arm PSR
>> -			 * again so we don't care about unmask the interruption
>> -			 * or unset irq_aux_error.
>> -			 */
>> -			mask |= EDP_PSR_ERROR(shift);
>> -		}
>> +		schedule_work(&dev_priv->psr.work);
>
>Would be better not to reorder intel_psr_work() and printing the events
>below.
>
>> +	}
>>
>> -		if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
>> -			dev_priv->psr.last_entry_attempt = time_ns;
>> -			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>> -				      transcoder_name(cpu_transcoder));
>> -		}
>> +	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
>> +		dev_priv->psr.last_entry_attempt = time_ns;
>> +		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>> +			      transcoder_name(cpu_transcoder));
>> +	}
>>
>> -		if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
>> -			dev_priv->psr.last_exit = time_ns;
>> -			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>> -				      transcoder_name(cpu_transcoder));
>> +	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
>> +		dev_priv->psr.last_exit = time_ns;
>> +		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>> +			      transcoder_name(cpu_transcoder));
>>
>> -			if (INTEL_GEN(dev_priv) >= 9) {
>> -				u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
>> -				bool psr2_enabled = dev_priv->psr.psr2_enabled;
>> +		if (INTEL_GEN(dev_priv) >= 9) {
>> +			u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
>> +			bool psr2_enabled = dev_priv->psr.psr2_enabled;
>>
>> -				I915_WRITE(PSR_EVENT(cpu_transcoder), val);
>> -				psr_event_print(val, psr2_enabled);
>> -			}
>> +			I915_WRITE(PSR_EVENT(cpu_transcoder), val);
>> +			psr_event_print(val, psr2_enabled);
>>  		}
>>  	}
>> -
>> -	if (mask) {
>> -		mask |= I915_READ(EDP_PSR_IMR);
>> -		I915_WRITE(EDP_PSR_IMR, mask);
>> -
>> -		schedule_work(&dev_priv->psr.work);
>> -	}
>>  }
>>
>>  static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
>> @@ -737,7 +703,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>>
>>  	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
>>
>> -	psr_irq_control(dev_priv, dev_priv->psr.debug);
>> +	psr_irq_control(dev_priv);
>>  }
>>
>>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>> @@ -762,7 +728,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>>  	 * to avoid any rendering problems.
>>  	 */
>>  	val = I915_READ(EDP_PSR_IIR);
>> -	val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
>> +	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
>>  	if (val) {
>>  		dev_priv->psr.sink_not_reliable = true;
>>  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
>> @@ -1110,7 +1076,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
>>
>>  	old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
>>  	dev_priv->psr.debug = val;
>> -	psr_irq_control(dev_priv, dev_priv->psr.debug);
>> +	psr_irq_control(dev_priv);
>>
>>  	mutex_unlock(&dev_priv->psr.lock);
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 02e1ef10c47e..1c6d99944630 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4225,13 +4225,12 @@ enum {
>>  /* Bspec claims those aren't shifted but stay at 0x64800 */
>>  #define EDP_PSR_IMR				_MMIO(0x64834)
>>  #define EDP_PSR_IIR				_MMIO(0x64838)
>> -#define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
>> -#define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
>> -#define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
>> -#define   EDP_PSR_TRANSCODER_C_SHIFT		24
>> -#define   EDP_PSR_TRANSCODER_B_SHIFT		16
>> -#define   EDP_PSR_TRANSCODER_A_SHIFT		8
>> -#define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
>> +#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
>> +						 0 : ((trans) + 1) * 8)
>
>(trans - TRANSCODER_A) + 1
>
>to not depend on the enum value of TRANSCODER_A.

agreed

thanks
Lucas De Marchi

>
>> +#define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
>> +#define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
>> +#define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
>> +#define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
>>
>>  #define _SRD_AUX_CTL_A				0x60810
>>  #define _SRD_AUX_CTL_EDP			0x6f810
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port

[Souza, Jose]

On Tue, 2019-08-27 at 09:36 -0700, Lucas De Marchi wrote:
> On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
> > > -----Original Message-----
> > > From: Imre Deak <imre.deak@intel.com>
> > > Sent: Monday, 26 August, 2019 6:42 AM
> > > To: Souza, Jose <jose.souza@intel.com>; De Marchi, Lucas
> > > <lucas.demarchi@intel.com>; Runyan, Arthur J <
> > > arthur.j.runyan@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> > > <dhinakaran.pandiyan@intel.com>
> > > Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable
> > > PSR in any
> > > eDP port
> > > 
> > > On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
> > > > From: José Roberto de Souza <jose.souza@intel.com>
> > > > 
> > > > From BDW+ the PSR registers moved from DDIA to transcoder, so
> > > > any port
> > > > with a eDP panel connected can have PSR, so lets remove this
> > > > limitation.
> > > > 
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++----
> > > >  1 file changed, 2 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 81e3619cd905..0172b82858d9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct
> > > > intel_dp
> > > *intel_dp,
> > > >  	/*
> > > >  	 * HSW spec explicitly says PSR is tied to port A.
> > > > -	 * BDW+ platforms have a instance of PSR registers per
> > > > transcoder but
> > > > -	 * for now it only supports one instance of PSR, so
> > > > lets keep it
> > > > -	 * hardcoded to PORT_A
> > > > +	 * BDW+ platforms have a instance of PSR registers per
> > > > transcoder.
> > > >  	 */
> > > > -	if (dig_port->base.port != PORT_A) {
> > > > +	if (IS_HASWELL(dev_priv) && dig_port->base.port !=
> > > > PORT_A) {
> > > 
> > > Based on an earlier discussion with Art, before TGL PSR is not
> > > supposed
> > > to be used anywhere else than port A.
> > > 
> > > Art could you confirm that?
> > 
> > Correct.
> > PSR1 is limited to DDIA until Tigerlake.  There are registers for
> > PSR on the other
> > transcoders/ports because of reuse, but hardware isn't fully hooked
> > up or validated.
> > PSR2 is still limited to DDIA on Tigerlake.
> 
> thank you both for confirming. José, I think we need to drop this
> patch
> and rebase the rest so we don't do anything before Tiger Lake. I will
> work on it.

Thanks, maybe write a patch updating the comment above would be nice.
Otherwise I can do it latter.

> 
> Lucas De Marchi
> 
> > > >  		DRM_DEBUG_KMS("PSR condition failed: Port not
> > > supported\n");
> > > >  		return;
> > > >  	}
> > > > --
> > > > 2.23.0
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use

[Imre Deak]

On Tue, Aug 27, 2019 at 09:50:24AM -0700, Lucas De Marchi wrote:
> On Mon, Aug 26, 2019 at 08:28:33PM +0300, Imre Deak wrote:
> > On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
> > > From: José Roberto de Souza <jose.souza@intel.com>
> > > 
> > > It was enabling and checking PSR interruptions in every transcoder
> > > while it should keep the interruptions on the non-used transcoders
> > > masked.
> > > 
> > > This also already prepares for future when more than one PSR instance
> > > will be allowed.
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
> > >  drivers/gpu/drm/i915/i915_reg.h          |  13 +--
> > >  2 files changed, 59 insertions(+), 94 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 28b62e587204..81e3619cd905 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> > >  	}
> > >  }
> > > 
> > > -static int edp_psr_shift(enum transcoder cpu_transcoder)
> > > +static void psr_irq_control(struct drm_i915_private *dev_priv)
> > >  {
> > > -	switch (cpu_transcoder) {
> > > -	case TRANSCODER_A:
> > > -		return EDP_PSR_TRANSCODER_A_SHIFT;
> > > -	case TRANSCODER_B:
> > > -		return EDP_PSR_TRANSCODER_B_SHIFT;
> > > -	case TRANSCODER_C:
> > > -		return EDP_PSR_TRANSCODER_C_SHIFT;
> > > -	default:
> > > -		MISSING_CASE(cpu_transcoder);
> > > -		/* fallthrough */
> > > -	case TRANSCODER_EDP:
> > > -		return EDP_PSR_TRANSCODER_EDP_SHIFT;
> > > -	}
> > > -}
> > > +	enum transcoder trans = dev_priv->psr.transcoder;
> > 
> > This is called from intel_psr_debug_set() where psr.transcoder may be
> > uninited.
> > 
> > > +	u32 val, mask;
> > > 
> > > -static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
> > > -{
> > > -	u32 debug_mask, mask;
> > > -	enum transcoder cpu_transcoder;
> > > -	u32 transcoders = BIT(TRANSCODER_EDP);
> > > -
> > > -	if (INTEL_GEN(dev_priv) >= 8)
> > > -		transcoders |= BIT(TRANSCODER_A) |
> > > -			       BIT(TRANSCODER_B) |
> > > -			       BIT(TRANSCODER_C);
> > > -
> > > -	debug_mask = 0;
> > > -	mask = 0;
> > > -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> > > -		int shift = edp_psr_shift(cpu_transcoder);
> > > -
> > > -		mask |= EDP_PSR_ERROR(shift);
> > > -		debug_mask |= EDP_PSR_POST_EXIT(shift) |
> > > -			      EDP_PSR_PRE_ENTRY(shift);
> > > -	}
> > > +	mask = EDP_PSR_ERROR(trans);
> > > +	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
> > > +		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
> > > 
> > > -	if (debug & I915_PSR_DEBUG_IRQ)
> > > -		mask |= debug_mask;
> > > -
> > > -	I915_WRITE(EDP_PSR_IMR, ~mask);
> > > +	/*
> > > +	 * TODO: when handling multiple PSR instances a global spinlock will be
> > > +	 * needed to synchronize the value of shared register
> > > +	 */
> > > +	val = I915_READ(EDP_PSR_IMR);
> > > +	val &= ~EDP_PSR_TRANS_MASK(trans);
> > > +	val |= ~mask;
> > > +	I915_WRITE(EDP_PSR_IMR, val);
> > >  }
> > > 
> > >  static void psr_event_print(u32 val, bool psr2_enabled)
> > > @@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
> > > 
> > >  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> > >  {
> > > -	u32 transcoders = BIT(TRANSCODER_EDP);
> > > -	enum transcoder cpu_transcoder;
> > > +	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
> > >  	ktime_t time_ns =  ktime_get();
> > > -	u32 mask = 0;
> > > 
> > > -	if (INTEL_GEN(dev_priv) >= 8)
> > > -		transcoders |= BIT(TRANSCODER_A) |
> > > -			       BIT(TRANSCODER_B) |
> > > -			       BIT(TRANSCODER_C);
> > > +	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
> > > +		u32 val;
> > > 
> > > -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> > 
> > I think we should still catch all interrupts, log the unexpected ones
> > and react only on the expected one in intel_psr_work().
> 
> could you expand more on this? there is only one PSR instance hence only
> one possible transcoder coming from dev_priv->psr.transcoder. Looping here just to
> warn seems wasteful.

I think we should do what the HW tells us and make sure we clear all the
interrupts that may have happened rather than assume that the interrupt
that happened was the one corresponding to psr.transcoder.
psr.transcoder is also only protected by a mutex, so we can't use its
value in the interrupt handler.

It's weird that there is no per-PSR instance IIRs in the misc interrupt
register. Because of that we'd need a PSR software IRQ mask that could
be set from psr_irq_control(). We also have to make sure to clear/mask a
transcoder's PSR interupts and sync against the interrupt handler when
turning off the transcoder power well. It looks like the transcoder
power well is the same as that of the transcoder's pipe power well, so
we could do this in gen8_irq_power_well_pre_disable().

By doing the above (not use psr.transcoder in the interrupt handler,
rather use a separate psr_irq software mask) we could also keep the
interrupt handling independent of the modeset code (which is what sets
psr.transcoder).

> 
> > 
> > > -		int shift = edp_psr_shift(cpu_transcoder);
> > > +		DRM_WARN("[transcoder %s] PSR aux error\n",
> > > +			 transcoder_name(cpu_transcoder));
> > > 
> > > -		if (psr_iir & EDP_PSR_ERROR(shift)) {
> > > -			DRM_WARN("[transcoder %s] PSR aux error\n",
> > > -				 transcoder_name(cpu_transcoder));
> > > +		dev_priv->psr.irq_aux_error = true;
> > > 
> > > -			dev_priv->psr.irq_aux_error = true;
> > > +		/*
> > > +		 * If this interruption is not masked it will keep
> > > +		 * interrupting so fast that it prevents the scheduled
> > > +		 * work to run.
> > > +		 * Also after a PSR error, we don't want to arm PSR
> > > +		 * again so we don't care about unmask the interruption
> > > +		 * or unset irq_aux_error.
> > > +		 *
> > > +		 * TODO: when handling multiple PSR instances a global spinlock
> > > +		 * will be needed to synchronize the value of shared register
> 
> I'm not really a fan of these TODO for multiple PSR instances. When/if
> we add them, we won't really be able to rely on these TODO comments and
> will rather need to evaluate the whole scenario.
> 
> > > +		 */
> > > +		val = I915_READ(EDP_PSR_IMR);
> > > +		val |= EDP_PSR_ERROR(cpu_transcoder);
> > > +		I915_WRITE(EDP_PSR_IMR, val);
> > > 
> > > -			/*
> > > -			 * If this interruption is not masked it will keep
> > > -			 * interrupting so fast that it prevents the scheduled
> > > -			 * work to run.
> > > -			 * Also after a PSR error, we don't want to arm PSR
> > > -			 * again so we don't care about unmask the interruption
> > > -			 * or unset irq_aux_error.
> > > -			 */
> > > -			mask |= EDP_PSR_ERROR(shift);
> > > -		}
> > > +		schedule_work(&dev_priv->psr.work);
> > 
> > Would be better not to reorder intel_psr_work() and printing the events
> > below.
> > 
> > > +	}
> > > 
> > > -		if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
> > > -			dev_priv->psr.last_entry_attempt = time_ns;
> > > -			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> > > -				      transcoder_name(cpu_transcoder));
> > > -		}
> > > +	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> > > +		dev_priv->psr.last_entry_attempt = time_ns;
> > > +		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> > > +			      transcoder_name(cpu_transcoder));
> > > +	}
> > > 
> > > -		if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
> > > -			dev_priv->psr.last_exit = time_ns;
> > > -			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> > > -				      transcoder_name(cpu_transcoder));
> > > +	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
> > > +		dev_priv->psr.last_exit = time_ns;
> > > +		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> > > +			      transcoder_name(cpu_transcoder));
> > > 
> > > -			if (INTEL_GEN(dev_priv) >= 9) {
> > > -				u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
> > > -				bool psr2_enabled = dev_priv->psr.psr2_enabled;
> > > +		if (INTEL_GEN(dev_priv) >= 9) {
> > > +			u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
> > > +			bool psr2_enabled = dev_priv->psr.psr2_enabled;
> > > 
> > > -				I915_WRITE(PSR_EVENT(cpu_transcoder), val);
> > > -				psr_event_print(val, psr2_enabled);
> > > -			}
> > > +			I915_WRITE(PSR_EVENT(cpu_transcoder), val);
> > > +			psr_event_print(val, psr2_enabled);
> > >  		}
> > >  	}
> > > -
> > > -	if (mask) {
> > > -		mask |= I915_READ(EDP_PSR_IMR);
> > > -		I915_WRITE(EDP_PSR_IMR, mask);
> > > -
> > > -		schedule_work(&dev_priv->psr.work);
> > > -	}
> > >  }
> > > 
> > >  static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> > > @@ -737,7 +703,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > > 
> > >  	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
> > > 
> > > -	psr_irq_control(dev_priv, dev_priv->psr.debug);
> > > +	psr_irq_control(dev_priv);
> > >  }
> > > 
> > >  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> > > @@ -762,7 +728,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> > >  	 * to avoid any rendering problems.
> > >  	 */
> > >  	val = I915_READ(EDP_PSR_IIR);
> > > -	val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
> > > +	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
> > >  	if (val) {
> > >  		dev_priv->psr.sink_not_reliable = true;
> > >  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
> > > @@ -1110,7 +1076,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
> > > 
> > >  	old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> > >  	dev_priv->psr.debug = val;
> > > -	psr_irq_control(dev_priv, dev_priv->psr.debug);
> > > +	psr_irq_control(dev_priv);
> > > 
> > >  	mutex_unlock(&dev_priv->psr.lock);
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 02e1ef10c47e..1c6d99944630 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4225,13 +4225,12 @@ enum {
> > >  /* Bspec claims those aren't shifted but stay at 0x64800 */
> > >  #define EDP_PSR_IMR				_MMIO(0x64834)
> > >  #define EDP_PSR_IIR				_MMIO(0x64838)
> > > -#define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
> > > -#define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
> > > -#define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
> > > -#define   EDP_PSR_TRANSCODER_C_SHIFT		24
> > > -#define   EDP_PSR_TRANSCODER_B_SHIFT		16
> > > -#define   EDP_PSR_TRANSCODER_A_SHIFT		8
> > > -#define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
> > > +#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
> > > +						 0 : ((trans) + 1) * 8)
> > 
> > (trans - TRANSCODER_A) + 1
> > 
> > to not depend on the enum value of TRANSCODER_A.
> 
> agreed
> 
> thanks
> Lucas De Marchi
> 
> > 
> > > +#define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
> > > +#define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
> > > +#define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
> > > +#define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
> > > 
> > >  #define _SRD_AUX_CTL_A				0x60810
> > >  #define _SRD_AUX_CTL_EDP			0x6f810
> > > --
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use

[Lucas De Marchi]

On Wed, Aug 28, 2019 at 07:29:38PM +0300, Imre Deak wrote:
>On Tue, Aug 27, 2019 at 09:50:24AM -0700, Lucas De Marchi wrote:
>> On Mon, Aug 26, 2019 at 08:28:33PM +0300, Imre Deak wrote:
>> > On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
>> > > From: José Roberto de Souza <jose.souza@intel.com>
>> > >
>> > > It was enabling and checking PSR interruptions in every transcoder
>> > > while it should keep the interruptions on the non-used transcoders
>> > > masked.
>> > >
>> > > This also already prepares for future when more than one PSR instance
>> > > will be allowed.
>> > >
>> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
>> > >  drivers/gpu/drm/i915/i915_reg.h          |  13 +--
>> > >  2 files changed, 59 insertions(+), 94 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > index 28b62e587204..81e3619cd905 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > @@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
>> > >  	}
>> > >  }
>> > >
>> > > -static int edp_psr_shift(enum transcoder cpu_transcoder)
>> > > +static void psr_irq_control(struct drm_i915_private *dev_priv)
>> > >  {
>> > > -	switch (cpu_transcoder) {
>> > > -	case TRANSCODER_A:
>> > > -		return EDP_PSR_TRANSCODER_A_SHIFT;
>> > > -	case TRANSCODER_B:
>> > > -		return EDP_PSR_TRANSCODER_B_SHIFT;
>> > > -	case TRANSCODER_C:
>> > > -		return EDP_PSR_TRANSCODER_C_SHIFT;
>> > > -	default:
>> > > -		MISSING_CASE(cpu_transcoder);
>> > > -		/* fallthrough */
>> > > -	case TRANSCODER_EDP:
>> > > -		return EDP_PSR_TRANSCODER_EDP_SHIFT;
>> > > -	}
>> > > -}
>> > > +	enum transcoder trans = dev_priv->psr.transcoder;
>> >
>> > This is called from intel_psr_debug_set() where psr.transcoder may be
>> > uninited.
>> >
>> > > +	u32 val, mask;
>> > >
>> > > -static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
>> > > -{
>> > > -	u32 debug_mask, mask;
>> > > -	enum transcoder cpu_transcoder;
>> > > -	u32 transcoders = BIT(TRANSCODER_EDP);
>> > > -
>> > > -	if (INTEL_GEN(dev_priv) >= 8)
>> > > -		transcoders |= BIT(TRANSCODER_A) |
>> > > -			       BIT(TRANSCODER_B) |
>> > > -			       BIT(TRANSCODER_C);
>> > > -
>> > > -	debug_mask = 0;
>> > > -	mask = 0;
>> > > -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
>> > > -		int shift = edp_psr_shift(cpu_transcoder);
>> > > -
>> > > -		mask |= EDP_PSR_ERROR(shift);
>> > > -		debug_mask |= EDP_PSR_POST_EXIT(shift) |
>> > > -			      EDP_PSR_PRE_ENTRY(shift);
>> > > -	}
>> > > +	mask = EDP_PSR_ERROR(trans);
>> > > +	if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
>> > > +		mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
>> > >
>> > > -	if (debug & I915_PSR_DEBUG_IRQ)
>> > > -		mask |= debug_mask;
>> > > -
>> > > -	I915_WRITE(EDP_PSR_IMR, ~mask);
>> > > +	/*
>> > > +	 * TODO: when handling multiple PSR instances a global spinlock will be
>> > > +	 * needed to synchronize the value of shared register
>> > > +	 */
>> > > +	val = I915_READ(EDP_PSR_IMR);
>> > > +	val &= ~EDP_PSR_TRANS_MASK(trans);
>> > > +	val |= ~mask;
>> > > +	I915_WRITE(EDP_PSR_IMR, val);
>> > >  }
>> > >
>> > >  static void psr_event_print(u32 val, bool psr2_enabled)
>> > > @@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>> > >
>> > >  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
>> > >  {
>> > > -	u32 transcoders = BIT(TRANSCODER_EDP);
>> > > -	enum transcoder cpu_transcoder;
>> > > +	enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
>> > >  	ktime_t time_ns =  ktime_get();
>> > > -	u32 mask = 0;
>> > >
>> > > -	if (INTEL_GEN(dev_priv) >= 8)
>> > > -		transcoders |= BIT(TRANSCODER_A) |
>> > > -			       BIT(TRANSCODER_B) |
>> > > -			       BIT(TRANSCODER_C);
>> > > +	if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
>> > > +		u32 val;
>> > >
>> > > -	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
>> >
>> > I think we should still catch all interrupts, log the unexpected ones
>> > and react only on the expected one in intel_psr_work().
>>
>> could you expand more on this? there is only one PSR instance hence only
>> one possible transcoder coming from dev_priv->psr.transcoder. Looping here just to
>> warn seems wasteful.
>
>I think we should do what the HW tells us and make sure we clear all the
>interrupts that may have happened rather than assume that the interrupt
>that happened was the one corresponding to psr.transcoder.

if psr can only be enabled in a single transcoder, how the transcoder
could be any different for that interrupt?

>psr.transcoder is also only protected by a mutex, so we can't use its
>value in the interrupt handler.

psr.transcoder is only set before enabling the source hence should
remain the same for any interrupt received.

>
>It's weird that there is no per-PSR instance IIRs in the misc interrupt
>register. Because of that we'd need a PSR software IRQ mask that could
>be set from psr_irq_control(). We also have to make sure to clear/mask a
>transcoder's PSR interupts and sync against the interrupt handler when
>turning off the transcoder power well. It looks like the transcoder
>power well is the same as that of the transcoder's pipe power well, so
>we could do this in gen8_irq_power_well_pre_disable().
>
>By doing the above (not use psr.transcoder in the interrupt handler,
>rather use a separate psr_irq software mask) we could also keep the
>interrupt handling independent of the modeset code (which is what sets
>psr.transcoder).

I have another version that should fix the problem with psr.transcoder. After
that I don't see the issue with the current approach.

Lucas De Marchi

>
>>
>> >
>> > > -		int shift = edp_psr_shift(cpu_transcoder);
>> > > +		DRM_WARN("[transcoder %s] PSR aux error\n",
>> > > +			 transcoder_name(cpu_transcoder));
>> > >
>> > > -		if (psr_iir & EDP_PSR_ERROR(shift)) {
>> > > -			DRM_WARN("[transcoder %s] PSR aux error\n",
>> > > -				 transcoder_name(cpu_transcoder));
>> > > +		dev_priv->psr.irq_aux_error = true;
>> > >
>> > > -			dev_priv->psr.irq_aux_error = true;
>> > > +		/*
>> > > +		 * If this interruption is not masked it will keep
>> > > +		 * interrupting so fast that it prevents the scheduled
>> > > +		 * work to run.
>> > > +		 * Also after a PSR error, we don't want to arm PSR
>> > > +		 * again so we don't care about unmask the interruption
>> > > +		 * or unset irq_aux_error.
>> > > +		 *
>> > > +		 * TODO: when handling multiple PSR instances a global spinlock
>> > > +		 * will be needed to synchronize the value of shared register
>>
>> I'm not really a fan of these TODO for multiple PSR instances. When/if
>> we add them, we won't really be able to rely on these TODO comments and
>> will rather need to evaluate the whole scenario.
>>
>> > > +		 */
>> > > +		val = I915_READ(EDP_PSR_IMR);
>> > > +		val |= EDP_PSR_ERROR(cpu_transcoder);
>> > > +		I915_WRITE(EDP_PSR_IMR, val);
>> > >
>> > > -			/*
>> > > -			 * If this interruption is not masked it will keep
>> > > -			 * interrupting so fast that it prevents the scheduled
>> > > -			 * work to run.
>> > > -			 * Also after a PSR error, we don't want to arm PSR
>> > > -			 * again so we don't care about unmask the interruption
>> > > -			 * or unset irq_aux_error.
>> > > -			 */
>> > > -			mask |= EDP_PSR_ERROR(shift);
>> > > -		}
>> > > +		schedule_work(&dev_priv->psr.work);
>> >
>> > Would be better not to reorder intel_psr_work() and printing the events
>> > below.
>> >
>> > > +	}
>> > >
>> > > -		if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
>> > > -			dev_priv->psr.last_entry_attempt = time_ns;
>> > > -			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>> > > -				      transcoder_name(cpu_transcoder));
>> > > -		}
>> > > +	if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
>> > > +		dev_priv->psr.last_entry_attempt = time_ns;
>> > > +		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
>> > > +			      transcoder_name(cpu_transcoder));
>> > > +	}
>> > >
>> > > -		if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
>> > > -			dev_priv->psr.last_exit = time_ns;
>> > > -			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>> > > -				      transcoder_name(cpu_transcoder));
>> > > +	if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
>> > > +		dev_priv->psr.last_exit = time_ns;
>> > > +		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
>> > > +			      transcoder_name(cpu_transcoder));
>> > >
>> > > -			if (INTEL_GEN(dev_priv) >= 9) {
>> > > -				u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
>> > > -				bool psr2_enabled = dev_priv->psr.psr2_enabled;
>> > > +		if (INTEL_GEN(dev_priv) >= 9) {
>> > > +			u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
>> > > +			bool psr2_enabled = dev_priv->psr.psr2_enabled;
>> > >
>> > > -				I915_WRITE(PSR_EVENT(cpu_transcoder), val);
>> > > -				psr_event_print(val, psr2_enabled);
>> > > -			}
>> > > +			I915_WRITE(PSR_EVENT(cpu_transcoder), val);
>> > > +			psr_event_print(val, psr2_enabled);
>> > >  		}
>> > >  	}
>> > > -
>> > > -	if (mask) {
>> > > -		mask |= I915_READ(EDP_PSR_IMR);
>> > > -		I915_WRITE(EDP_PSR_IMR, mask);
>> > > -
>> > > -		schedule_work(&dev_priv->psr.work);
>> > > -	}
>> > >  }
>> > >
>> > >  static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
>> > > @@ -737,7 +703,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>> > >
>> > >  	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
>> > >
>> > > -	psr_irq_control(dev_priv, dev_priv->psr.debug);
>> > > +	psr_irq_control(dev_priv);
>> > >  }
>> > >
>> > >  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>> > > @@ -762,7 +728,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>> > >  	 * to avoid any rendering problems.
>> > >  	 */
>> > >  	val = I915_READ(EDP_PSR_IIR);
>> > > -	val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
>> > > +	val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
>> > >  	if (val) {
>> > >  		dev_priv->psr.sink_not_reliable = true;
>> > >  		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
>> > > @@ -1110,7 +1076,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
>> > >
>> > >  	old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
>> > >  	dev_priv->psr.debug = val;
>> > > -	psr_irq_control(dev_priv, dev_priv->psr.debug);
>> > > +	psr_irq_control(dev_priv);
>> > >
>> > >  	mutex_unlock(&dev_priv->psr.lock);
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > > index 02e1ef10c47e..1c6d99944630 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -4225,13 +4225,12 @@ enum {
>> > >  /* Bspec claims those aren't shifted but stay at 0x64800 */
>> > >  #define EDP_PSR_IMR				_MMIO(0x64834)
>> > >  #define EDP_PSR_IIR				_MMIO(0x64838)
>> > > -#define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
>> > > -#define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
>> > > -#define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
>> > > -#define   EDP_PSR_TRANSCODER_C_SHIFT		24
>> > > -#define   EDP_PSR_TRANSCODER_B_SHIFT		16
>> > > -#define   EDP_PSR_TRANSCODER_A_SHIFT		8
>> > > -#define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
>> > > +#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
>> > > +						 0 : ((trans) + 1) * 8)
>> >
>> > (trans - TRANSCODER_A) + 1
>> >
>> > to not depend on the enum value of TRANSCODER_A.
>>
>> agreed
>>
>> thanks
>> Lucas De Marchi
>>
>> >
>> > > +#define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
>> > > +#define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
>> > > +#define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
>> > > +#define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
>> > >
>> > >  #define _SRD_AUX_CTL_A				0x60810
>> > >  #define _SRD_AUX_CTL_EDP			0x6f810
>> > > --
>> > > 2.23.0
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support

[Matt Roper]

On Fri, Aug 23, 2019 at 01:20:51AM -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Yf tiling was removed in gen-12, make the necessary to changes to not
> expose the modifier to user space. Gen-12 display also is incompatible with
> pre-gen12 Y-tiled compression, so do not expose
> I915_FORMAT_MOD_Y_TILED_CCS.
> 
> Bspec: 29650
> 
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 73 +++++++++++++++++++--
>  1 file changed, 67 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index dea63be1964f..71dae3c2f9db 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2157,6 +2157,13 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> +static const u64 gen12_plane_format_modifiers_noccs[] = {
> +	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_X_TILED,
> +	DRM_FORMAT_MOD_LINEAR,
> +	DRM_FORMAT_MOD_INVALID
> +};
> +
>  static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
>  					    u32 format, u64 modifier)
>  {
> @@ -2305,6 +2312,42 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	}
>  }
>  
> +static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> +					     u32 format, u64 modifier)
> +{
> +	switch (modifier) {
> +	case DRM_FORMAT_MOD_LINEAR:
> +	case I915_FORMAT_MOD_X_TILED:
> +	case I915_FORMAT_MOD_Y_TILED:
> +		break;
> +	default:
> +		return false;
> +	}
> +
> +	switch (format) {
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_ABGR8888:
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_XRGB2101010:
> +	case DRM_FORMAT_XBGR2101010:
> +	case DRM_FORMAT_YUYV:
> +	case DRM_FORMAT_YVYU:
> +	case DRM_FORMAT_UYVY:
> +	case DRM_FORMAT_VYUY:
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_C8:

Shouldn't we also have the P01x and Y41x (DRM_FORMAT_XVYU*) formats
here?  Everything else in the patch looks correct.


Matt

> +		if (modifier == DRM_FORMAT_MOD_LINEAR ||
> +		    modifier == I915_FORMAT_MOD_X_TILED ||
> +		    modifier == I915_FORMAT_MOD_Y_TILED)
> +			return true;
> +		/* fall through */
> +	default:
> +		return false;
> +	}
> +}
> +
>  static const struct drm_plane_funcs g4x_sprite_funcs = {
>  	.update_plane = drm_atomic_helper_update_plane,
>  	.disable_plane = drm_atomic_helper_disable_plane,
> @@ -2341,6 +2384,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
>  	.format_mod_supported = skl_plane_format_mod_supported,
>  };
>  
> +static const struct drm_plane_funcs gen12_plane_funcs = {
> +	.update_plane = drm_atomic_helper_update_plane,
> +	.disable_plane = drm_atomic_helper_disable_plane,
> +	.destroy = intel_plane_destroy,
> +	.atomic_duplicate_state = intel_plane_duplicate_state,
> +	.atomic_destroy_state = intel_plane_destroy_state,
> +	.format_mod_supported = gen12_plane_format_mod_supported,
> +};
> +
>  static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
>  			      enum pipe pipe, enum plane_id plane_id)
>  {
> @@ -2429,6 +2481,7 @@ struct intel_plane *
>  skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  			   enum pipe pipe, enum plane_id plane_id)
>  {
> +	static const struct drm_plane_funcs *plane_funcs;
>  	struct intel_plane *plane;
>  	enum drm_plane_type plane_type;
>  	unsigned int supported_rotations;
> @@ -2471,11 +2524,19 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id, &num_formats);
>  
> -	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> -	if (plane->has_ccs)
> -		modifiers = skl_plane_format_modifiers_ccs;
> -	else
> -		modifiers = skl_plane_format_modifiers_noccs;
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		/* TODO: Implement support for gen-12 CCS modifiers */
> +		plane->has_ccs = false;
> +		modifiers = gen12_plane_format_modifiers_noccs;
> +		plane_funcs = &gen12_plane_funcs;
> +	} else {
> +		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> +		if (plane->has_ccs)
> +			modifiers = skl_plane_format_modifiers_ccs;
> +		else
> +			modifiers = skl_plane_format_modifiers_noccs;
> +		plane_funcs = &skl_plane_funcs;
> +	}
>  
>  	if (plane_id == PLANE_PRIMARY)
>  		plane_type = DRM_PLANE_TYPE_PRIMARY;
> @@ -2485,7 +2546,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	possible_crtcs = BIT(pipe);
>  
>  	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> -				       possible_crtcs, &skl_plane_funcs,
> +				       possible_crtcs, plane_funcs,
>  				       formats, num_formats, modifiers,
>  				       plane_type,
>  				       "plane %d%c", plane_id + 1,
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support

[Lucas De Marchi]

On Wed, Aug 28, 2019 at 04:04:01PM -0700, Matt Roper wrote:
>On Fri, Aug 23, 2019 at 01:20:51AM -0700, Lucas De Marchi wrote:
>> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>
>> Yf tiling was removed in gen-12, make the necessary to changes to not
>> expose the modifier to user space. Gen-12 display also is incompatible with
>> pre-gen12 Y-tiled compression, so do not expose
>> I915_FORMAT_MOD_Y_TILED_CCS.
>>
>> Bspec: 29650
>>
>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_sprite.c | 73 +++++++++++++++++++--
>>  1 file changed, 67 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index dea63be1964f..71dae3c2f9db 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -2157,6 +2157,13 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>>  	DRM_FORMAT_MOD_INVALID
>>  };
>>
>> +static const u64 gen12_plane_format_modifiers_noccs[] = {
>> +	I915_FORMAT_MOD_Y_TILED,
>> +	I915_FORMAT_MOD_X_TILED,
>> +	DRM_FORMAT_MOD_LINEAR,
>> +	DRM_FORMAT_MOD_INVALID
>> +};
>> +
>>  static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
>>  					    u32 format, u64 modifier)
>>  {
>> @@ -2305,6 +2312,42 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>>  	}
>>  }
>>
>> +static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>> +					     u32 format, u64 modifier)
>> +{
>> +	switch (modifier) {
>> +	case DRM_FORMAT_MOD_LINEAR:
>> +	case I915_FORMAT_MOD_X_TILED:
>> +	case I915_FORMAT_MOD_Y_TILED:
>> +		break;
>> +	default:
>> +		return false;
>> +	}
>> +
>> +	switch (format) {
>> +	case DRM_FORMAT_XRGB8888:
>> +	case DRM_FORMAT_XBGR8888:
>> +	case DRM_FORMAT_ARGB8888:
>> +	case DRM_FORMAT_ABGR8888:
>> +	case DRM_FORMAT_RGB565:
>> +	case DRM_FORMAT_XRGB2101010:
>> +	case DRM_FORMAT_XBGR2101010:
>> +	case DRM_FORMAT_YUYV:
>> +	case DRM_FORMAT_YVYU:
>> +	case DRM_FORMAT_UYVY:
>> +	case DRM_FORMAT_VYUY:
>> +	case DRM_FORMAT_NV12:
>> +	case DRM_FORMAT_C8:
>
>Shouldn't we also have the P01x and Y41x (DRM_FORMAT_XVYU*) formats
>here?  Everything else in the patch looks correct.

this patch is outdated. DK sent an updated one in
https://patchwork.freedesktop.org/series/65858/

Lucas De Marchi

>
>
>Matt
>
>> +		if (modifier == DRM_FORMAT_MOD_LINEAR ||
>> +		    modifier == I915_FORMAT_MOD_X_TILED ||
>> +		    modifier == I915_FORMAT_MOD_Y_TILED)
>> +			return true;
>> +		/* fall through */
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>>  static const struct drm_plane_funcs g4x_sprite_funcs = {
>>  	.update_plane = drm_atomic_helper_update_plane,
>>  	.disable_plane = drm_atomic_helper_disable_plane,
>> @@ -2341,6 +2384,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
>>  	.format_mod_supported = skl_plane_format_mod_supported,
>>  };
>>
>> +static const struct drm_plane_funcs gen12_plane_funcs = {
>> +	.update_plane = drm_atomic_helper_update_plane,
>> +	.disable_plane = drm_atomic_helper_disable_plane,
>> +	.destroy = intel_plane_destroy,
>> +	.atomic_duplicate_state = intel_plane_duplicate_state,
>> +	.atomic_destroy_state = intel_plane_destroy_state,
>> +	.format_mod_supported = gen12_plane_format_mod_supported,
>> +};
>> +
>>  static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
>>  			      enum pipe pipe, enum plane_id plane_id)
>>  {
>> @@ -2429,6 +2481,7 @@ struct intel_plane *
>>  skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>  			   enum pipe pipe, enum plane_id plane_id)
>>  {
>> +	static const struct drm_plane_funcs *plane_funcs;
>>  	struct intel_plane *plane;
>>  	enum drm_plane_type plane_type;
>>  	unsigned int supported_rotations;
>> @@ -2471,11 +2524,19 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>  		formats = skl_get_plane_formats(dev_priv, pipe,
>>  						plane_id, &num_formats);
>>
>> -	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>> -	if (plane->has_ccs)
>> -		modifiers = skl_plane_format_modifiers_ccs;
>> -	else
>> -		modifiers = skl_plane_format_modifiers_noccs;
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		/* TODO: Implement support for gen-12 CCS modifiers */
>> +		plane->has_ccs = false;
>> +		modifiers = gen12_plane_format_modifiers_noccs;
>> +		plane_funcs = &gen12_plane_funcs;
>> +	} else {
>> +		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>> +		if (plane->has_ccs)
>> +			modifiers = skl_plane_format_modifiers_ccs;
>> +		else
>> +			modifiers = skl_plane_format_modifiers_noccs;
>> +		plane_funcs = &skl_plane_funcs;
>> +	}
>>
>>  	if (plane_id == PLANE_PRIMARY)
>>  		plane_type = DRM_PLANE_TYPE_PRIMARY;
>> @@ -2485,7 +2546,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>  	possible_crtcs = BIT(pipe);
>>
>>  	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
>> -				       possible_crtcs, &skl_plane_funcs,
>> +				       possible_crtcs, plane_funcs,
>>  				       formats, num_formats, modifiers,
>>  				       plane_type,
>>  				       "plane %d%c", plane_id + 1,
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression

[Matt Roper]

On Fri, Aug 23, 2019 at 01:20:53AM -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
> 
> Bspec: 18437

For TGL I think you want to point at bspec #49252.

> 
> v2: Fix checkpatch warnings (Lucas)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++---
>  2 files changed, 71 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		if (color_plane == 1)
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (color_plane == 1)
> +			return cpp;

If the CCS itself is linear, is there a reason we don't treat this the
way we normally treat linear surfaces (i.e., return intel_tile_size())?

> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return 4 * 4 * 1024;

This is correct, but is there a reason we don't just write it as 16 *
1024?  The bspec says "must be 16KB aligned" so 16 * 1024 seems more
natural.

>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>  
>  static bool is_surface_linear(u64 modifier, int color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR;
> +	return modifier == DRM_FORMAT_MOD_LINEAR ||
> +	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2429,6 +2436,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  		return I915_TILING_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>   * us a ratio of one byte in the CCS for each 8x16 pixels in the
>   * main surface.
>   */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
>  	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
>  };
>  
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2480,8 +2506,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		return lookup_format_info(ccs_formats,
> -					  ARRAY_SIZE(ccs_formats),
> +		return lookup_format_info(skl_ccs_formats,
> +					  ARRAY_SIZE(skl_ccs_formats),
> +					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return lookup_format_info(gen12_ccs_formats,
> +					  ARRAY_SIZE(gen12_ccs_formats),
>  					  cmd->pixel_format);
>  	default:
>  		return NULL;
> @@ -2490,7 +2520,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  
>  bool is_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> @@ -2659,7 +2690,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  			int main_x, main_y;
>  			int ccs_x, ccs_y;
>  
> -			intel_tile_dims(fb, i, &tile_width, &tile_height);
> +			if (!is_surface_linear(fb->modifier, i)) {
> +				intel_tile_dims(fb, i, &tile_width, &tile_height);
> +			} else {
> +				tile_width = 64 / cpp;
> +				tile_height = 1;
> +			}
> +
>  			tile_width *= hsub;
>  			tile_height *= vsub;
>  
> @@ -4053,6 +4090,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
> @@ -9828,7 +9867,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  	case PLANE_CTL_TILED_Y:
>  		plane_config->tiling = I915_TILING_Y;
>  		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> +			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> +				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> +				I915_FORMAT_MOD_Y_TILED_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> @@ -15695,6 +15736,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		    is_ccs_modifier(fb->modifier))
>  			stride_alignment *= 4;
>  
> +		/*
> +		 * The main surface pitch must be paded to a multiple of four

s/paded/padded/

> +		 * tile widths.
> +		 */
> +		if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> +		    i == 0)
> +			stride_alignment *= 4;
> +

It might be worth moving this into intel_fb_stride_alignment itself.



Matt

>  		if (fb->pitches[i] & (stride_alignment - 1)) {
>  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
>  				      i, fb->pitches[i], stride_alignment);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 71dae3c2f9db..73d32017be89 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> +	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>  	int crtc_x = plane_state->base.dst.x1;
>  	int crtc_y = plane_state->base.dst.y1;
> @@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
>  	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		aux_dist |= aux_stride;
> +	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>  
>  	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>  		u32 cus_ctl = 0;
> @@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		break;
>  	default:
>  		return false;
> @@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (is_ccs_modifier(modifier))
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> @@ -2524,13 +2533,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id, &num_formats);
>  
> +	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/* TODO: Implement support for gen-12 CCS modifiers */
> -		plane->has_ccs = false;
> -		modifiers = gen12_plane_format_modifiers_noccs;
> +		modifiers = gen12_plane_format_modifiers_ccs;
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
> -		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  		if (plane->has_ccs)
>  			modifiers = skl_plane_format_modifiers_ccs;
>  		else
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression

[Sripada, Radhakrishna]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Lucas De Marchi
> Sent: Friday, August 23, 2019 1:21 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vetter, Daniel <daniel.vetter@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>
> Subject: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render
> decompression
> 
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a ratio of
> 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
> 
> Bspec: 18437
> 
> v2: Fix checkpatch warnings (Lucas)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++---
>  2 files changed, 71 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  		if (color_plane == 1)
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (color_plane == 1)
> +			return cpp;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return 4 * 4 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> 
>  static bool is_surface_linear(u64 modifier, int color_plane)  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR;
> +	return modifier == DRM_FORMAT_MOD_LINEAR ||
> +	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> +color_plane == 1);
>  }
> 
>  static u32 intel_adjust_aligned_offset(int *x, int *y, @@ -2429,6 +2436,7
> @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  		return I915_TILING_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
Shouldn’t this modifier be added to skl_max_plane_width as well?

Thanks,
Radhakrishna Sripada
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
>   * us a ratio of one byte in the CCS for each 8x16 pixels in the
>   * main surface.
>   */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
>  	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[]
> = {
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },  };
> 
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair
> +in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> +Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having
> +dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> +pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, };
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2480,8 +2506,12 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		return lookup_format_info(ccs_formats,
> -					  ARRAY_SIZE(ccs_formats),
> +		return lookup_format_info(skl_ccs_formats,
> +					  ARRAY_SIZE(skl_ccs_formats),
> +					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return lookup_format_info(gen12_ccs_formats,
> +					  ARRAY_SIZE(gen12_ccs_formats),
>  					  cmd->pixel_format);
>  	default:
>  		return NULL;
> @@ -2490,7 +2520,8 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
> 
>  bool is_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;  }
> 
> @@ -2659,7 +2690,13 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  			int main_x, main_y;
>  			int ccs_x, ccs_y;
> 
> -			intel_tile_dims(fb, i, &tile_width, &tile_height);
> +			if (!is_surface_linear(fb->modifier, i)) {
> +				intel_tile_dims(fb, i, &tile_width,
> &tile_height);
> +			} else {
> +				tile_width = 64 / cpp;
> +				tile_height = 1;
> +			}
> +
>  			tile_width *= hsub;
>  			tile_height *= vsub;
> 
> @@ -4053,6 +4090,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
> @@ -9828,7 +9867,9 @@ skylake_get_initial_plane_config(struct intel_crtc
> *crtc,
>  	case PLANE_CTL_TILED_Y:
>  		plane_config->tiling = I915_TILING_Y;
>  		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> +			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> +
> 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> +				I915_FORMAT_MOD_Y_TILED_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> @@ -15695,6 +15736,14 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
>  		    is_ccs_modifier(fb->modifier))
>  			stride_alignment *= 4;
> 
> +		/*
> +		 * The main surface pitch must be paded to a multiple of four
> +		 * tile widths.
> +		 */
> +		if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> +		    i == 0)
> +			stride_alignment *= 4;
> +
>  		if (fb->pitches[i] & (stride_alignment - 1)) {
>  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at
> least %u byte aligned\n",
>  				      i, fb->pitches[i], stride_alignment); diff --
> git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 71dae3c2f9db..73d32017be89 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> +	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>  	int crtc_x = plane_state->base.dst.x1;
>  	int crtc_y = plane_state->base.dst.y1; @@ -588,8 +589,10 @@
> skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
>  	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) |
> crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->color_plane[1].offset - surf_addr) |
> aux_stride);
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		aux_dist |= aux_stride;
> +	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> 
>  	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>  		u32 cus_ctl = 0;
> @@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
>  		return -EINVAL;
>  	}
> @@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[]
> = {
>  	DRM_FORMAT_MOD_INVALID
>  };
> 
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2319,6 +2324,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		break;
>  	default:
>  		return false;
> @@ -2329,6 +2335,9 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (is_ccs_modifier(modifier))
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> @@ -2524,13 +2533,11 @@ skl_universal_plane_create(struct
> drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id, &num_formats);
> 
> +	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/* TODO: Implement support for gen-12 CCS modifiers */
> -		plane->has_ccs = false;
> -		modifiers = gen12_plane_format_modifiers_noccs;
> +		modifiers = gen12_plane_format_modifiers_ccs;
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
> -		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> plane_id);
>  		if (plane->has_ccs)
>  			modifiers = skl_plane_format_modifiers_ccs;
>  		else
> --
> 2.23.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating

[Chris Wilson]

Quoting Lucas De Marchi (2019-08-23 09:20:34)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> HCP/MFX power gating is disabled by default, turn it on for the vd units
> available. User space will also issue a MI_FORCE_WAKEUP properly to
> wake up proper subwell.
> 
> During driver load, init_clock_gating happens after device_info_init_mmio
> read the vdbox disable fuse register, so only present vd units will have
> these enabled.
> 
> BSpec: 14214
> HSDES: 1209977827
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Tony Ye <tony.ye@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++++++-
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a092b34c269d..02e1ef10c47e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8615,6 +8615,10 @@ enum {
>  #define   GEN9_PWRGT_MEDIA_STATUS_MASK         (1 << 0)
>  #define   GEN9_PWRGT_RENDER_STATUS_MASK                (1 << 1)
>  
> +#define POWERGATE_ENABLE                       _MMIO(0xa210)
> +#define    VDN_HCP_POWERGATE_ENABLE(n)         BIT(((n) * 2) + 3)
> +#define    VDN_MFX_POWERGATE_ENABLE(n)         BIT(((n) * 2) + 4)
> +
>  #define  GTFIFODBG                             _MMIO(0x120000)
>  #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV   (0x1f << 20)
>  #define    GT_FIFO_FREE_ENTRIES_CHV            (0x7f << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 75ee027abb80..d3ea193cd093 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9078,6 +9078,22 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>                    _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
>  }
>  
> +static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +       u32 vd_pg_enable = 0;
> +       unsigned int i;
> +
> +       /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> +       for (i = 0; i < I915_MAX_VCS; i++) {
> +               if (HAS_ENGINE(dev_priv, _VCS(i)))
> +                       vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
> +                                       VDN_MFX_POWERGATE_ENABLE(i);
> +       }
> +
> +       I915_WRITE(POWERGATE_ENABLE,
> +                  I915_READ(POWERGATE_ENABLE) | vd_pg_enable);

Is this display related at all?
-Chris
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