* [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
@ 2019-08-28 16:42 Ramalingam C
2019-08-28 16:42 ` [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW Ramalingam C
` (9 more replies)
0 siblings, 10 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
from DDI into transcoder.
v12:
r-b and ack are collected.
few review comments are addressed.
Ramalingam C (6):
drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
drm: Move port definition back to i915 header
drm: Extend I915 mei interface for transcoder info
misc/mei/hdcp: Fill transcoder index in port info
drm/i915/hdcp: update current transcoder into intel_hdcp
drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
drivers/gpu/drm/i915/display/intel_bios.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.h | 20 +-
.../drm/i915/display/intel_display_types.h | 7 +
drivers/gpu/drm/i915/display/intel_dp.c | 3 +
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-
drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++--
drivers/misc/mei/hdcp/mei_hdcp.h | 17 +-
include/drm/i915_drm.h | 18 --
include/drm/i915_mei_hdcp_interface.h | 42 +++-
16 files changed, 389 insertions(+), 125 deletions(-)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 17:53 ` Winkler, Tomas
2019-08-28 16:42 ` [PATCH v12 2/6] drm: Move port definition back to i915 header Ramalingam C
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
Hence expose the enum mei_fw_ddi to I915 through
i915_mei_interface.h.
v2:
Copyright years are bumped [Tomas]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 17 +++++++++++-
drivers/misc/mei/hdcp/mei_hdcp.c | 34 ++++++++---------------
drivers/misc/mei/hdcp/mei_hdcp.h | 12 --------
include/drm/i915_mei_hdcp_interface.h | 18 ++++++++++--
4 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6ec5ceeab601..e8b04cc8fcb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 Google, Inc.
+ * Copyright _ 2017-2019, Intel Corporation.
*
* Authors:
* Sean Paul <seanpaul@chromium.org>
+ * Ramalingam C <ramalingam.c@intel.com>
*/
#include <linux/component.h>
@@ -1749,13 +1751,26 @@ static const struct component_ops i915_hdcp_component_ops = {
.unbind = i915_hdcp_component_unbind,
};
+static inline
+enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port)
+{
+ switch (port) {
+ case PORT_A:
+ return MEI_DDI_A;
+ case PORT_B ... PORT_F:
+ return (enum mei_fw_ddi)port;
+ default:
+ return MEI_DDI_INVALID_PORT;
+ }
+}
+
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
- data->port = connector->encoder->port;
+ data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port);
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index c681f6fab342..3638c77eba26 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -27,18 +27,6 @@
#include "mei_hdcp.h"
-static inline u8 mei_get_ddi_index(enum port port)
-{
- switch (port) {
- case PORT_A:
- return MEI_DDI_A;
- case PORT_B ... PORT_F:
- return (u8)port;
- default:
- return MEI_DDI_INVALID_PORT;
- }
-}
-
/**
* mei_hdcp_initiate_session() - Initiate a Wired HDCP2.2 Tx Session in ME FW
* @dev: device corresponding to the mei_cl_device
@@ -69,7 +57,7 @@ mei_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
session_init_in.port.integrated_port_type = data->port_type;
- session_init_in.port.physical_port = mei_get_ddi_index(data->port);
+ session_init_in.port.physical_port = (u8)data->fw_ddi;
session_init_in.protocol = data->protocol;
byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
@@ -138,7 +126,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
verify_rxcert_in.port.integrated_port_type = data->port_type;
- verify_rxcert_in.port.physical_port = mei_get_ddi_index(data->port);
+ verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
verify_rxcert_in.cert_rx = rx_cert->cert_rx;
memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
@@ -208,7 +196,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct hdcp_port_data *data,
send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
send_hprime_in.port.integrated_port_type = data->port_type;
- send_hprime_in.port.physical_port = mei_get_ddi_index(data->port);
+ send_hprime_in.port.physical_port = (u8)data->fw_ddi;
memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
HDCP_2_2_H_PRIME_LEN);
@@ -265,7 +253,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct hdcp_port_data *data,
WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
pairing_info_in.port.integrated_port_type = data->port_type;
- pairing_info_in.port.physical_port = mei_get_ddi_index(data->port);
+ pairing_info_in.port.physical_port = (u8)data->fw_ddi;
memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
HDCP_2_2_E_KH_KM_LEN);
@@ -323,7 +311,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
lc_init_in.port.integrated_port_type = data->port_type;
- lc_init_in.port.physical_port = mei_get_ddi_index(data->port);
+ lc_init_in.port.physical_port = (u8)data->fw_ddi;
byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
if (byte < 0) {
@@ -378,7 +366,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct hdcp_port_data *data,
WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
verify_lprime_in.port.integrated_port_type = data->port_type;
- verify_lprime_in.port.physical_port = mei_get_ddi_index(data->port);
+ verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
HDCP_2_2_L_PRIME_LEN);
@@ -435,7 +423,7 @@ static int mei_hdcp_get_session_key(struct device *dev,
get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
get_skey_in.port.integrated_port_type = data->port_type;
- get_skey_in.port.physical_port = mei_get_ddi_index(data->port);
+ get_skey_in.port.physical_port = (u8)data->fw_ddi;
byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
if (byte < 0) {
@@ -499,7 +487,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct device *dev,
WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
verify_repeater_in.port.integrated_port_type = data->port_type;
- verify_repeater_in.port.physical_port = mei_get_ddi_index(data->port);
+ verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
HDCP_2_2_RXINFO_LEN);
@@ -569,7 +557,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
verify_mprime_in.port.integrated_port_type = data->port_type;
- verify_mprime_in.port.physical_port = mei_get_ddi_index(data->port);
+ verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
HDCP_2_2_MPRIME_LEN);
@@ -630,7 +618,7 @@ static int mei_hdcp_enable_authentication(struct device *dev,
enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
enable_auth_in.port.integrated_port_type = data->port_type;
- enable_auth_in.port.physical_port = mei_get_ddi_index(data->port);
+ enable_auth_in.port.physical_port = (u8)data->fw_ddi;
enable_auth_in.stream_type = data->streams[0].stream_type;
byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in,
@@ -684,7 +672,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data *data)
WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
session_close_in.port.integrated_port_type = data->port_type;
- session_close_in.port.physical_port = mei_get_ddi_index(data->port);
+ session_close_in.port.physical_port = (u8)data->fw_ddi;
byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
sizeof(session_close_in));
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h b/drivers/misc/mei/hdcp/mei_hdcp.h
index e4b1cd54c853..e60282eb2d48 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.h
+++ b/drivers/misc/mei/hdcp/mei_hdcp.h
@@ -362,16 +362,4 @@ struct wired_cmd_repeater_auth_stream_req_out {
struct hdcp_cmd_header header;
struct hdcp_port_id port;
} __packed;
-
-enum mei_fw_ddi {
- MEI_DDI_INVALID_PORT = 0x0,
-
- MEI_DDI_B = 1,
- MEI_DDI_C,
- MEI_DDI_D,
- MEI_DDI_E,
- MEI_DDI_F,
- MEI_DDI_A = 7,
- MEI_DDI_RANGE_END = MEI_DDI_A,
-};
#endif /* __MEI_HDCP_H__ */
diff --git a/include/drm/i915_mei_hdcp_interface.h b/include/drm/i915_mei_hdcp_interface.h
index 8c344255146a..08670aa650d4 100644
--- a/include/drm/i915_mei_hdcp_interface.h
+++ b/include/drm/i915_mei_hdcp_interface.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+) */
/*
- * Copyright © 2017-2018 Intel Corporation
+ * Copyright © 2017-2019 Intel Corporation
*
* Authors:
* Ramalingam C <ramalingam.c@intel.com>
@@ -42,9 +42,21 @@ enum hdcp_wired_protocol {
HDCP_PROTOCOL_DP
};
+enum mei_fw_ddi {
+ MEI_DDI_INVALID_PORT = 0x0,
+
+ MEI_DDI_B = 1,
+ MEI_DDI_C,
+ MEI_DDI_D,
+ MEI_DDI_E,
+ MEI_DDI_F,
+ MEI_DDI_A = 7,
+ MEI_DDI_RANGE_END = MEI_DDI_A,
+};
+
/**
* struct hdcp_port_data - intel specific HDCP port data
- * @port: port index as per I915
+ * @fw_ddi: ddi index as per ME FW
* @port_type: HDCP port type as per ME FW classification
* @protocol: HDCP adaptation as per ME FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
@@ -56,7 +68,7 @@ enum hdcp_wired_protocol {
* streams
*/
struct hdcp_port_data {
- enum port port;
+ enum mei_fw_ddi fw_ddi;
u8 port_type;
u8 protocol;
u16 k;
--
2.20.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v12 2/6] drm: Move port definition back to i915 header
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-08-28 16:42 ` [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 16:42 ` [PATCH v12 3/6] drm: Extend I915 mei interface for transcoder info Ramalingam C
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
We dont need the definition of the enum port outside I915, anymore.
Hence move enum port definition into I915 driver itself.
v2:
intel_display.h is included in intel_hdcp.h
v3:
enum port is declared in headers.
v4:
commit msg is rephrased.
v5:
copyright year is updated [Tomas]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.h | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 20 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.h | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
include/drm/i915_drm.h | 18 ------------------
8 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 4969189e620f..98f064828a57 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -1,5 +1,5 @@
/*
- * Copyright © 2016 Intel Corporation
+ * Copyright © 2016-2019 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,7 @@
#include <drm/i915_drm.h>
struct drm_i915_private;
+enum port;
enum intel_backlight_type {
INTEL_BACKLIGHT_PMIC,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 03321fb4a703..33fd523c4622 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -1,5 +1,5 @@
/*
- * Copyright © 2006-2017 Intel Corporation
+ * Copyright © 2006-2019 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -182,6 +182,24 @@ enum plane_id {
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
+enum port {
+ PORT_NONE = -1,
+
+ PORT_A = 0,
+ PORT_B,
+ PORT_C,
+ PORT_D,
+ PORT_E,
+ PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
+
+ I915_MAX_PORTS
+};
+
+#define port_name(p) ((p) + 'A')
+
/*
* Ports identifier referenced from other drivers.
* Expected to remain stable over time
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..e01d1f89409d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -13,6 +13,7 @@
#include "i915_reg.h"
enum pipe;
+enum port;
struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 13555b054930..59a2b40405cc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -15,6 +15,7 @@ struct drm_connector_state;
struct drm_i915_private;
struct intel_connector;
struct intel_hdcp_shim;
+enum port;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 106c2e0bc3c9..cf1ea5427639 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -23,6 +23,7 @@ struct intel_crtc_state;
struct intel_hdmi;
struct drm_connector_state;
union hdmi_infoframe;
+enum port;
void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h
index b0cd447b7fbc..087b5f57b321 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -13,6 +13,7 @@
struct drm_i915_private;
struct intel_connector;
struct intel_encoder;
+enum port;
void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h
index c9e05bcdd141..a66f224aa17d 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.h
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
@@ -14,6 +14,7 @@
struct drm_i915_private;
enum pipe;
+enum port;
bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t sdvo_reg, enum pipe *pipe);
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 23274cf92712..6722005884db 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -100,22 +100,4 @@ extern struct resource intel_graphics_stolen_res;
#define INTEL_GEN11_BSM_DW1 0xc4
#define INTEL_BSM_MASK (-(1u << 20))
-enum port {
- PORT_NONE = -1,
-
- PORT_A = 0,
- PORT_B,
- PORT_C,
- PORT_D,
- PORT_E,
- PORT_F,
- PORT_G,
- PORT_H,
- PORT_I,
-
- I915_MAX_PORTS
-};
-
-#define port_name(p) ((p) + 'A')
-
#endif /* _I915_DRM_H_ */
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v12 3/6] drm: Extend I915 mei interface for transcoder info
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-08-28 16:42 ` [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW Ramalingam C
2019-08-28 16:42 ` [PATCH v12 2/6] drm: Move port definition back to i915 header Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 16:42 ` [PATCH v12 4/6] misc/mei/hdcp: Fill transcoder index in port info Ramalingam C
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_tc and add as a member into
the struct hdcp_port_data.
v2:
Typo in commit msg is fixed [Shashank]
v3:
kdoc is added for mei_fw_tc [Tomas]
s/MEI_TC_x/MEI_TRANSCODER_x
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
---
include/drm/i915_mei_hdcp_interface.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/include/drm/i915_mei_hdcp_interface.h b/include/drm/i915_mei_hdcp_interface.h
index 08670aa650d4..4d48de8890ca 100644
--- a/include/drm/i915_mei_hdcp_interface.h
+++ b/include/drm/i915_mei_hdcp_interface.h
@@ -54,9 +54,32 @@ enum mei_fw_ddi {
MEI_DDI_RANGE_END = MEI_DDI_A,
};
+/**
+ * enum mei_fw_tc - ME Firmware defined index for transcoders
+ * @MEI_INVALID_TRANSCODER: Index for Invalid transcoder
+ * @MEI_TRANSCODER_EDP: Index for EDP Transcoder
+ * @MEI_TRANSCODER_DSI0: Index for DSI0 Transcoder
+ * @MEI_TRANSCODER_DSI1: Index for DSI1 Transcoder
+ * @MEI_TRANSCODER_A: Index for Transcoder A
+ * @MEI_TRANSCODER_B: Index for Transcoder B
+ * @MEI_TRANSCODER_C: Index for Transcoder C
+ * @MEI_TRANSCODER_D: Index for Transcoder D
+ */
+enum mei_fw_tc {
+ MEI_INVALID_TRANSCODER = 0x00,
+ MEI_TRANSCODER_EDP,
+ MEI_TRANSCODER_DSI0,
+ MEI_TRANSCODER_DSI1,
+ MEI_TRANSCODER_A = 0x10,
+ MEI_TRANSCODER_B,
+ MEI_TRANSCODER_C,
+ MEI_TRANSCODER_D
+};
+
/**
* struct hdcp_port_data - intel specific HDCP port data
* @fw_ddi: ddi index as per ME FW
+ * @fw_tc: transcoder index as per ME FW
* @port_type: HDCP port type as per ME FW classification
* @protocol: HDCP adaptation as per ME FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
@@ -69,6 +92,7 @@ enum mei_fw_ddi {
*/
struct hdcp_port_data {
enum mei_fw_ddi fw_ddi;
+ enum mei_fw_tc fw_tc;
u8 port_type;
u8 protocol;
u16 k;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v12 4/6] misc/mei/hdcp: Fill transcoder index in port info
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (2 preceding siblings ...)
2019-08-28 16:42 ` [PATCH v12 3/6] drm: Extend I915 mei interface for transcoder info Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 16:42 ` [PATCH v12 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp Ramalingam C
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME FW from hdcp_port_data.
v2:
Doc is enhanced for physical_port and attached_transcoder [Tomas]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++++++++++
drivers/misc/mei/hdcp/mei_hdcp.h | 5 ++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 3638c77eba26..93027fd96c71 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
session_init_in.port.integrated_port_type = data->port_type;
session_init_in.port.physical_port = (u8)data->fw_ddi;
+ session_init_in.port.attached_transcoder = (u8)data->fw_tc;
session_init_in.protocol = data->protocol;
byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
@@ -127,6 +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
verify_rxcert_in.port.integrated_port_type = data->port_type;
verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
+ verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
verify_rxcert_in.cert_rx = rx_cert->cert_rx;
memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
@@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct hdcp_port_data *data,
send_hprime_in.port.integrated_port_type = data->port_type;
send_hprime_in.port.physical_port = (u8)data->fw_ddi;
+ send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
HDCP_2_2_H_PRIME_LEN);
@@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct hdcp_port_data *data,
pairing_info_in.port.integrated_port_type = data->port_type;
pairing_info_in.port.physical_port = (u8)data->fw_ddi;
+ pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
HDCP_2_2_E_KH_KM_LEN);
@@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
lc_init_in.port.integrated_port_type = data->port_type;
lc_init_in.port.physical_port = (u8)data->fw_ddi;
+ lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
if (byte < 0) {
@@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct hdcp_port_data *data,
verify_lprime_in.port.integrated_port_type = data->port_type;
verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
+ verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
HDCP_2_2_L_PRIME_LEN);
@@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct device *dev,
get_skey_in.port.integrated_port_type = data->port_type;
get_skey_in.port.physical_port = (u8)data->fw_ddi;
+ get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
if (byte < 0) {
@@ -488,6 +495,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct device *dev,
verify_repeater_in.port.integrated_port_type = data->port_type;
verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
+ verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
HDCP_2_2_RXINFO_LEN);
@@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in.port.integrated_port_type = data->port_type;
verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
+ verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
HDCP_2_2_MPRIME_LEN);
@@ -619,6 +628,7 @@ static int mei_hdcp_enable_authentication(struct device *dev,
enable_auth_in.port.integrated_port_type = data->port_type;
enable_auth_in.port.physical_port = (u8)data->fw_ddi;
+ enable_auth_in.port.attached_transcoder = (u8)data->fw_tc;
enable_auth_in.stream_type = data->streams[0].stream_type;
byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in,
@@ -673,6 +683,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data *data)
session_close_in.port.integrated_port_type = data->port_type;
session_close_in.port.physical_port = (u8)data->fw_ddi;
+ session_close_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
sizeof(session_close_in));
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h b/drivers/misc/mei/hdcp/mei_hdcp.h
index e60282eb2d48..18ffc773fa18 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.h
+++ b/drivers/misc/mei/hdcp/mei_hdcp.h
@@ -184,8 +184,11 @@ struct hdcp_cmd_no_data {
/* Uniquely identifies the hdcp port being addressed for a given command. */
struct hdcp_port_id {
u8 integrated_port_type;
+ /* physical_port is used until Gen11.5. Must be zero for Gen11.5+ */
u8 physical_port;
- u16 reserved;
+ /* attached_transcoder is for Gen11.5+. Set to zero for <Gen11.5 */
+ u8 attached_transcoder;
+ u8 reserved;
} __packed;
/*
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v12 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (3 preceding siblings ...)
2019-08-28 16:42 ` [PATCH v12 4/6] misc/mei/hdcp: Fill transcoder index in port info Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 16:42 ` [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
v3:
comment is added for fw_ddi init for gen12+ [Shashank]
only hdcp capable transcoder is translated into fw_tc [Shashank]
v4:
fw_tc initialization is kept for modeset. [Tomas]
few extra doc is added at port_data init [Tomas]
v5:
Few comments are improvised [Tomas]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
---
.../drm/i915/display/intel_display_types.h | 7 +++
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 47 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
5 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 96514dcc7812..61277a87dbe7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -388,6 +388,13 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ /*
+ * HDCP register access for gen12+ need the transcoder associated.
+ * Transcoder attached to the connector could be changed at modeset.
+ * Hence caching the transcoder here.
+ */
+ enum transcoder cpu_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 917f420d557c..11ae0f6f0307 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2248,6 +2248,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
+ intel_hdcp_transcoder_config(intel_connector,
+ pipe_config->cpu_transcoder);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e8b04cc8fcb1..edcec64a2c11 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1764,13 +1764,58 @@ enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port)
}
}
+static inline
+enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
+{
+ switch (cpu_transcoder) {
+ case TRANSCODER_A ... TRANSCODER_D:
+ return (enum mei_fw_tc)(cpu_transcoder | 0x10);
+ default: /* eDP, DSI TRANSCODERS are non HDCP capable */
+ return MEI_INVALID_TRANSCODER;
+ }
+}
+
+void intel_hdcp_transcoder_config(struct intel_connector *connector,
+ enum transcoder cpu_transcoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+
+ if (!hdcp->shim)
+ return;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ mutex_lock(&hdcp->mutex);
+ hdcp->cpu_transcoder = cpu_transcoder;
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ mutex_unlock(&hdcp->mutex);
+ }
+}
+
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
- data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port);
+ if (INTEL_GEN(dev_priv) < 12)
+ data->fw_ddi =
+ intel_get_mei_fw_ddi_index(connector->encoder->port);
+ else
+ /*
+ * As per ME FW API expectation, for GEN 12+, fw_ddi is filled
+ * with zero(INVALID PORT index).
+ */
+ data->fw_ddi = MEI_DDI_INVALID_PORT;
+
+ /*
+ * As associated transcoder is set and modified at modeset, here fw_tc
+ * is initialized to zero (invalid transcoder index). This will be
+ * retained for <Gen12 forever.
+ */
+ data->fw_tc = MEI_INVALID_TRANSCODER;
+
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 59a2b40405cc..41c1053d9e38 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -16,10 +16,13 @@ struct drm_i915_private;
struct intel_connector;
struct intel_hdcp_shim;
enum port;
+enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
+void intel_hdcp_transcoder_config(struct intel_connector *connector,
+ enum transcoder cpu_transcoder);
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0f5a0c618e46..a0e9cc35cc47 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2431,6 +2431,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
return -EINVAL;
}
+ intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
+ pipe_config->cpu_transcoder);
+
return 0;
}
--
2.20.1
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (4 preceding siblings ...)
2019-08-28 16:42 ` [PATCH v12 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp Ramalingam C
@ 2019-08-28 16:42 ` Ramalingam C
2019-08-28 18:50 ` Winkler, Tomas
2019-08-28 16:48 ` [PATCH v12 0/6] drm/i915: " Ramalingam C
` (3 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
>From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_data.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
v4:
Few optimizations in the coding [Shashank]
v5:
Fixed alignment in macro definition in i915_reg.h [Shashank]
unused variables "reg" is removed.
v6:
Configuring the transcoder at compute_config.
transcoder is used instead of pipe in macros.
Rebased.
v7:
transcoder is cached at intel_hdcp
hdcp_port_data is configured with transcoder index asper ME FW.
v8:
s/trans/cpu_transcoder
s/tc/cpu_transcoder
v9:
rep_ctl is prepared for TCD too.
return moved into deault of rep_ctl prepare function [Shashank]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 152 ++++++++++++++--------
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 124 ++++++++++++++++--
3 files changed, 221 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index edcec64a2c11..e69fa34528df 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -20,6 +20,7 @@
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -107,24 +108,20 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(PORT_HDCP_STATUS(port));
- return reg & HDCP_STATUS_ENC;
+ return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
+ HDCP_STATUS_ENC;
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(HDCP2_STATUS_DDI(port));
- return reg & LINK_ENCRYPTION_STATUS;
+ return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS;
}
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
@@ -255,9 +252,29 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- enum port port = intel_dig_port->base.port;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case TRANSCODER_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case TRANSCODER_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ case TRANSCODER_D:
+ return HDCP_TRANSD_REP_PRESENT |
+ HDCP_TRANSD_SHA1_M0;
+ default:
+ DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder);
+ return -EINVAL;
+ }
+ }
+
switch (port) {
case PORT_A:
return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
@@ -270,18 +287,20 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
case PORT_E:
return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
default:
- break;
+ DRM_ERROR("Unknown port %d\n", port);
+ return -EINVAL;
}
- DRM_ERROR("Unknown port %d\n", port);
- return -EINVAL;
}
static
-int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+int intel_hdcp_validate_v_prime(struct intel_connector *connector,
const struct intel_hdcp_shim *shim,
u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
struct drm_i915_private *dev_priv;
+ enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
+ enum port port = intel_dig_port->base.port;
u32 vprime, sha_text, sha_leftovers, rep_ctl;
int ret, i, j, sha_idx;
@@ -308,7 +327,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
sha_idx = 0;
sha_text = 0;
sha_leftovers = 0;
- rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
+ rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port);
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
for (i = 0; i < num_downstream; i++) {
unsigned int sha_empty;
@@ -550,7 +569,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
* V prime atleast twice.
*/
for (i = 0; i < tries; i++) {
- ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
+ ret = intel_hdcp_validate_v_prime(connector, shim,
ksv_fifo, num_downstream,
bstatus);
if (!ret)
@@ -578,6 +597,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
struct drm_device *dev = connector->base.dev;
const struct intel_hdcp_shim *shim = hdcp->shim;
struct drm_i915_private *dev_priv;
+ enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
enum port port;
unsigned long r0_prime_gen_start;
int ret, i, tries = 2;
@@ -617,18 +637,21 @@ static int intel_hdcp_auth(struct intel_connector *connector)
/* Initialize An with 2 random values and acquire it */
for (i = 0; i < 2; i++)
- I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
- I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
+ I915_WRITE(HDCP_ANINIT(dev_priv, cpu_transcoder, port),
+ get_random_u32());
+ I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
+ HDCP_CONF_CAPTURE_AN);
/* Wait for An to be acquired */
- if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv,
+ HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_AN_READY, 1)) {
DRM_ERROR("Timed out waiting for An\n");
return -ETIMEDOUT;
}
- an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
- an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
+ an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, cpu_transcoder, port));
+ an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, cpu_transcoder, port));
ret = shim->write_an_aksv(intel_dig_port, an.shim);
if (ret)
return ret;
@@ -646,24 +669,26 @@ static int intel_hdcp_auth(struct intel_connector *connector)
return -EPERM;
}
- I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
- I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
+ I915_WRITE(HDCP_BKSVLO(dev_priv, cpu_transcoder, port), bksv.reg[0]);
+ I915_WRITE(HDCP_BKSVHI(dev_priv, cpu_transcoder, port), bksv.reg[1]);
ret = shim->repeater_present(intel_dig_port, &repeater_present);
if (ret)
return ret;
if (repeater_present)
I915_WRITE(HDCP_REP_CTL,
- intel_hdcp_get_repeater_ctl(intel_dig_port));
+ intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
+ port));
ret = shim->toggle_signalling(intel_dig_port, true);
if (ret)
return ret;
- I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
+ I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
+ HDCP_CONF_AUTH_AND_ENC);
/* Wait for R0 ready */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
(HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Timed out waiting for R0 ready\n");
return -ETIMEDOUT;
@@ -691,22 +716,25 @@ static int intel_hdcp_auth(struct intel_connector *connector)
ret = shim->read_ri_prime(intel_dig_port, ri.shim);
if (ret)
return ret;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
/* Wait for Ri prime match */
- if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
+ port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
break;
}
if (i == tries) {
DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
+ port)));
return -ETIMEDOUT;
}
/* Wait for encryption confirmation */
- if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv,
+ HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Timed out waiting for encryption\n");
@@ -731,15 +759,17 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
hdcp->hdcp_encrypted = false;
- I915_WRITE(PORT_HDCP_CONF(port), 0);
- if (intel_de_wait_for_clear(dev_priv, PORT_HDCP_STATUS(port), ~0,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
+ if (intel_de_wait_for_clear(dev_priv,
+ HDCP_STATUS(dev_priv, cpu_transcoder, port),
+ ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
}
@@ -810,9 +840,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
+ enum transcoder cpu_transcoder;
int ret = 0;
mutex_lock(&hdcp->mutex);
+ cpu_transcoder = hdcp->cpu_transcoder;
/* Check_link valid only when HDCP1.4 is enabled */
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
@@ -821,10 +853,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp_in_use(connector))) {
+ if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
connector->base.name, connector->base.base.id,
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
+ port)));
ret = -ENXIO;
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
schedule_work(&hdcp->prop_work);
@@ -1495,10 +1528,11 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
-
+ WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS);
if (hdcp->shim->toggle_signalling) {
ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
if (ret) {
@@ -1508,14 +1542,18 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
}
}
- if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
+ if (I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_AUTH_STATUS) {
/* Link is Authenticated. Now set for Encryption */
- I915_WRITE(HDCP2_CTL_DDI(port),
- I915_READ(HDCP2_CTL_DDI(port)) |
+ I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
+ I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder,
+ port)) |
CTL_LINK_ENCRYPTION_REQ);
}
- ret = intel_de_wait_for_set(dev_priv, HDCP2_STATUS_DDI(port),
+ ret = intel_de_wait_for_set(dev_priv,
+ HDCP2_STATUS(dev_priv, cpu_transcoder,
+ port),
LINK_ENCRYPTION_STATUS,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
@@ -1528,14 +1566,19 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
+ WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS));
- I915_WRITE(HDCP2_CTL_DDI(port),
- I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
+ I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
+ I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder, port)) &
+ ~CTL_LINK_ENCRYPTION_REQ);
- ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS_DDI(port),
+ ret = intel_de_wait_for_clear(dev_priv,
+ HDCP2_STATUS(dev_priv, cpu_transcoder,
+ port),
LINK_ENCRYPTION_STATUS,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
@@ -1634,9 +1677,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = connector->encoder->port;
+ enum transcoder cpu_transcoder;
int ret = 0;
mutex_lock(&hdcp->mutex);
+ cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
@@ -1645,9 +1690,10 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp2_in_use(connector))) {
+ if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
- I915_READ(HDCP2_STATUS_DDI(port)));
+ I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder,
+ port)));
ret = -ENXIO;
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
schedule_work(&hdcp->prop_work);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a0e9cc35cc47..9710b85d1aef 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
{
struct drm_i915_private *dev_priv =
intel_dig_port->base.base.dev->dev_private;
+ struct intel_connector *connector =
+ intel_dig_port->hdmi.attached_connector;
enum port port = intel_dig_port->base.port;
+ enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
int ret;
union {
u32 reg;
@@ -1502,13 +1505,14 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
if (ret)
return false;
- I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+ I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
/* Wait for Ri prime match */
- if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+ if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
- I915_READ(PORT_HDCP_STATUS(port)));
+ I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
+ port)));
return false;
}
return true;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..3cfdab18c0cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9281,12 +9281,20 @@ enum skl_power_gate {
/* HDCP Repeater Registers */
#define HDCP_REP_CTL _MMIO(0x66d00)
+#define HDCP_TRANSA_REP_PRESENT BIT(31)
+#define HDCP_TRANSB_REP_PRESENT BIT(30)
+#define HDCP_TRANSC_REP_PRESENT BIT(29)
+#define HDCP_TRANSD_REP_PRESENT BIT(28)
#define HDCP_DDIB_REP_PRESENT BIT(30)
#define HDCP_DDIA_REP_PRESENT BIT(29)
#define HDCP_DDIC_REP_PRESENT BIT(28)
#define HDCP_DDID_REP_PRESENT BIT(27)
#define HDCP_DDIF_REP_PRESENT BIT(26)
#define HDCP_DDIE_REP_PRESENT BIT(25)
+#define HDCP_TRANSA_SHA1_M0 (1 << 20)
+#define HDCP_TRANSB_SHA1_M0 (2 << 20)
+#define HDCP_TRANSC_SHA1_M0 (3 << 20)
+#define HDCP_TRANSD_SHA1_M0 (4 << 20)
#define HDCP_DDIB_SHA1_M0 (1 << 20)
#define HDCP_DDIA_SHA1_M0 (2 << 20)
#define HDCP_DDIC_SHA1_M0 (3 << 20)
@@ -9326,15 +9334,92 @@ enum skl_power_gate {
_PORTE_HDCP_AUTHENC, \
_PORTF_HDCP_AUTHENC) + (x))
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
+#define _TRANSA_HDCP_CONF 0x66400
+#define _TRANSB_HDCP_CONF 0x66500
+#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
+ _TRANSB_HDCP_CONF)
+#define HDCP_CONF(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_CONF(trans) : \
+ PORT_HDCP_CONF(port))
+
#define HDCP_CONF_CAPTURE_AN BIT(0)
#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
+#define _TRANSA_HDCP_ANINIT 0x66404
+#define _TRANSB_HDCP_ANINIT 0x66504
+#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_ANINIT, \
+ _TRANSB_HDCP_ANINIT)
+#define HDCP_ANINIT(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANINIT(trans) : \
+ PORT_HDCP_ANINIT(port))
+
#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
+#define _TRANSA_HDCP_ANLO 0x66408
+#define _TRANSB_HDCP_ANLO 0x66508
+#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
+ _TRANSB_HDCP_ANLO)
+#define HDCP_ANLO(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANLO(trans) : \
+ PORT_HDCP_ANLO(port))
+
#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
+#define _TRANSA_HDCP_ANHI 0x6640C
+#define _TRANSB_HDCP_ANHI 0x6650C
+#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
+ _TRANSB_HDCP_ANHI)
+#define HDCP_ANHI(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_ANHI(trans) : \
+ PORT_HDCP_ANHI(port))
+
#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
+#define _TRANSA_HDCP_BKSVLO 0x66410
+#define _TRANSB_HDCP_BKSVLO 0x66510
+#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_BKSVLO, \
+ _TRANSB_HDCP_BKSVLO)
+#define HDCP_BKSVLO(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_BKSVLO(trans) : \
+ PORT_HDCP_BKSVLO(port))
+
#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
+#define _TRANSA_HDCP_BKSVHI 0x66414
+#define _TRANSB_HDCP_BKSVHI 0x66514
+#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_BKSVHI, \
+ _TRANSB_HDCP_BKSVHI)
+#define HDCP_BKSVHI(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_BKSVHI(trans) : \
+ PORT_HDCP_BKSVHI(port))
+
#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
+#define _TRANSA_HDCP_RPRIME 0x66418
+#define _TRANSB_HDCP_RPRIME 0x66518
+#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_RPRIME, \
+ _TRANSB_HDCP_RPRIME)
+#define HDCP_RPRIME(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_RPRIME(trans) : \
+ PORT_HDCP_RPRIME(port))
+
#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
+#define _TRANSA_HDCP_STATUS 0x6641C
+#define _TRANSB_HDCP_STATUS 0x6651C
+#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP_STATUS, \
+ _TRANSB_HDCP_STATUS)
+#define HDCP_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP_STATUS(trans) : \
+ PORT_HDCP_STATUS(port))
+
#define HDCP_STATUS_STREAM_A_ENC BIT(31)
#define HDCP_STATUS_STREAM_B_ENC BIT(30)
#define HDCP_STATUS_STREAM_C_ENC BIT(29)
@@ -9361,23 +9446,44 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
-
-#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
+#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
+#define _TRANSA_HDCP2_AUTH 0x66498
+#define _TRANSB_HDCP2_AUTH 0x66598
+#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
+ _TRANSB_HDCP2_AUTH)
#define AUTH_LINK_AUTHENTICATED BIT(31)
#define AUTH_LINK_TYPE BIT(30)
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
#define AUTH_CLR_KEYS BIT(18)
-
-#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
+#define HDCP2_AUTH(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_AUTH(trans) : \
+ PORT_HDCP2_AUTH(port))
+
+#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
+#define _TRANSA_HDCP2_CTL 0x664B0
+#define _TRANSB_HDCP2_CTL 0x665B0
+#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
+ _TRANSB_HDCP2_CTL)
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
-
-#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
-#define STREAM_ENCRYPTION_STATUS_A BIT(31)
-#define STREAM_ENCRYPTION_STATUS_B BIT(30)
-#define STREAM_ENCRYPTION_STATUS_C BIT(29)
+#define HDCP2_CTL(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_CTL(trans) : \
+ PORT_HDCP2_CTL(port))
+
+#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
+#define _TRANSA_HDCP2_STATUS 0x664B4
+#define _TRANSB_HDCP2_STATUS 0x665B4
+#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_STATUS, \
+ _TRANSB_HDCP2_STATUS)
#define LINK_TYPE_STATUS BIT(22)
#define LINK_AUTH_STATUS BIT(21)
#define LINK_ENCRYPTION_STATUS BIT(20)
+#define HDCP2_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_STATUS(trans) : \
+ PORT_HDCP2_STATUS(port))
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
--
2.20.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (5 preceding siblings ...)
2019-08-28 16:42 ` [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
@ 2019-08-28 16:48 ` Ramalingam C
2019-08-29 9:58 ` Winkler, Tomas
2019-08-29 10:28 ` ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10) Patchwork
` (2 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ramalingam C @ 2019-08-28 16:48 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Jani Nikula, tomas.winkler
On 2019-08-28 at 22:12:10 +0530, Ramalingam C wrote:
> Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
> from DDI into transcoder.
>
> v12:
> r-b and ack are collected.
> few review comments are addressed.
Tomas,
Thanks for reviewing the patches and providing the Ack/R-bes.
As we discussed offline, we need your ACK for submitting mei_hdcp
patches through dinq(drm-intel-next-queued). Please provide the same.
-Ram
>
> Ramalingam C (6):
> drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
> drm: Move port definition back to i915 header
> drm: Extend I915 mei interface for transcoder info
> misc/mei/hdcp: Fill transcoder index in port info
> drm/i915/hdcp: update current transcoder into intel_hdcp
> drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
>
> drivers/gpu/drm/i915/display/intel_bios.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.h | 20 +-
> .../drm/i915/display/intel_display_types.h | 7 +
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++++++++++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
> drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-
> drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++--
> drivers/misc/mei/hdcp/mei_hdcp.h | 17 +-
> include/drm/i915_drm.h | 18 --
> include/drm/i915_mei_hdcp_interface.h | 42 +++-
> 16 files changed, 389 insertions(+), 125 deletions(-)
>
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
2019-08-28 16:42 ` [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW Ramalingam C
@ 2019-08-28 17:53 ` Winkler, Tomas
2019-08-29 3:56 ` Ramalingam C
0 siblings, 1 reply; 16+ messages in thread
From: Winkler, Tomas @ 2019-08-28 17:53 UTC (permalink / raw)
To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Nikula, Jani
> FW
>
> I915 converts it's port value into ddi index defiend by ME FW and pass it as a
> member of hdcp_port_data structure.
>
> Hence expose the enum mei_fw_ddi to I915 through i915_mei_interface.h.
>
> v2:
> Copyright years are bumped [Tomas]
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Acked-by: Tomas Winkler <tomas.winkler@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 17 +++++++++++-
> drivers/misc/mei/hdcp/mei_hdcp.c | 34 ++++++++---------------
> drivers/misc/mei/hdcp/mei_hdcp.h | 12 --------
> include/drm/i915_mei_hdcp_interface.h | 18 ++++++++++--
> 4 files changed, 42 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 6ec5ceeab601..e8b04cc8fcb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1,9 +1,11 @@
> /* SPDX-License-Identifier: MIT */
> /*
> * Copyright (C) 2017 Google, Inc.
> + * Copyright _ 2017-2019, Intel Corporation.
Something happened here with (C) ?
> *
> * Authors:
> * Sean Paul <seanpaul@chromium.org>
> + * Ramalingam C <ramalingam.c@intel.com>
> */
>
> #include <linux/component.h>
> @@ -1749,13 +1751,26 @@ static const struct component_ops
> i915_hdcp_component_ops = {
> .unbind = i915_hdcp_component_unbind,
> };
>
> +static inline
> +enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port) {
> + switch (port) {
> + case PORT_A:
> + return MEI_DDI_A;
> + case PORT_B ... PORT_F:
> + return (enum mei_fw_ddi)port;
> + default:
> + return MEI_DDI_INVALID_PORT;
> + }
> +}
> +
> static inline int initialize_hdcp_port_data(struct intel_connector *connector,
> const struct intel_hdcp_shim *shim)
> {
> struct intel_hdcp *hdcp = &connector->hdcp;
> struct hdcp_port_data *data = &hdcp->port_data;
>
> - data->port = connector->encoder->port;
> + data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder-
> >port);
> data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
> data->protocol = (u8)shim->protocol;
>
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> b/drivers/misc/mei/hdcp/mei_hdcp.c
> index c681f6fab342..3638c77eba26 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -27,18 +27,6 @@
>
> #include "mei_hdcp.h"
>
> -static inline u8 mei_get_ddi_index(enum port port) -{
> - switch (port) {
> - case PORT_A:
> - return MEI_DDI_A;
> - case PORT_B ... PORT_F:
> - return (u8)port;
> - default:
> - return MEI_DDI_INVALID_PORT;
> - }
> -}
> -
> /**
> * mei_hdcp_initiate_session() - Initiate a Wired HDCP2.2 Tx Session in ME FW
> * @dev: device corresponding to the mei_cl_device @@ -69,7 +57,7 @@
> mei_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
>
> WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
>
> session_init_in.port.integrated_port_type = data->port_type;
> - session_init_in.port.physical_port = mei_get_ddi_index(data->port);
> + session_init_in.port.physical_port = (u8)data->fw_ddi;
> session_init_in.protocol = data->protocol;
>
> byte = mei_cldev_send(cldev, (u8 *)&session_init_in, @@ -138,7
> +126,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
>
> WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
>
> verify_rxcert_in.port.integrated_port_type = data->port_type;
> - verify_rxcert_in.port.physical_port = mei_get_ddi_index(data->port);
> + verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
>
> verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
> @@ -208,7 +196,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
> hdcp_port_data *data,
> send_hprime_in.header.buffer_len =
> WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
>
> send_hprime_in.port.integrated_port_type = data->port_type;
> - send_hprime_in.port.physical_port = mei_get_ddi_index(data->port);
> + send_hprime_in.port.physical_port = (u8)data->fw_ddi;
>
> memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> HDCP_2_2_H_PRIME_LEN);
> @@ -265,7 +253,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
> hdcp_port_data *data,
>
> WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
>
> pairing_info_in.port.integrated_port_type = data->port_type;
> - pairing_info_in.port.physical_port = mei_get_ddi_index(data->port);
> + pairing_info_in.port.physical_port = (u8)data->fw_ddi;
>
> memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> HDCP_2_2_E_KH_KM_LEN);
> @@ -323,7 +311,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
> lc_init_in.header.buffer_len =
> WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
>
> lc_init_in.port.integrated_port_type = data->port_type;
> - lc_init_in.port.physical_port = mei_get_ddi_index(data->port);
> + lc_init_in.port.physical_port = (u8)data->fw_ddi;
>
> byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
> if (byte < 0) {
> @@ -378,7 +366,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
> hdcp_port_data *data,
>
> WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
>
> verify_lprime_in.port.integrated_port_type = data->port_type;
> - verify_lprime_in.port.physical_port = mei_get_ddi_index(data->port);
> + verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
>
> memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> HDCP_2_2_L_PRIME_LEN);
> @@ -435,7 +423,7 @@ static int mei_hdcp_get_session_key(struct device
> *dev,
> get_skey_in.header.buffer_len =
> WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
>
> get_skey_in.port.integrated_port_type = data->port_type;
> - get_skey_in.port.physical_port = mei_get_ddi_index(data->port);
> + get_skey_in.port.physical_port = (u8)data->fw_ddi;
>
> byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
> if (byte < 0) {
> @@ -499,7 +487,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct
> device *dev,
>
> WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
>
> verify_repeater_in.port.integrated_port_type = data->port_type;
> - verify_repeater_in.port.physical_port = mei_get_ddi_index(data-
> >port);
> + verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
>
> memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> HDCP_2_2_RXINFO_LEN);
> @@ -569,7 +557,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
>
> WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
>
> verify_mprime_in.port.integrated_port_type = data->port_type;
> - verify_mprime_in.port.physical_port = mei_get_ddi_index(data->port);
> + verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
>
> memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> HDCP_2_2_MPRIME_LEN);
> @@ -630,7 +618,7 @@ static int mei_hdcp_enable_authentication(struct
> device *dev,
> enable_auth_in.header.buffer_len =
> WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
>
> enable_auth_in.port.integrated_port_type = data->port_type;
> - enable_auth_in.port.physical_port = mei_get_ddi_index(data->port);
> + enable_auth_in.port.physical_port = (u8)data->fw_ddi;
> enable_auth_in.stream_type = data->streams[0].stream_type;
>
> byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in, @@ -684,7
> +672,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data
> *data)
> WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
>
> session_close_in.port.integrated_port_type = data->port_type;
> - session_close_in.port.physical_port = mei_get_ddi_index(data->port);
> + session_close_in.port.physical_port = (u8)data->fw_ddi;
>
> byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
> sizeof(session_close_in));
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h
> b/drivers/misc/mei/hdcp/mei_hdcp.h
> index e4b1cd54c853..e60282eb2d48 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.h
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.h
> @@ -362,16 +362,4 @@ struct wired_cmd_repeater_auth_stream_req_out {
> struct hdcp_cmd_header header;
> struct hdcp_port_id port;
> } __packed;
> -
> -enum mei_fw_ddi {
> - MEI_DDI_INVALID_PORT = 0x0,
> -
> - MEI_DDI_B = 1,
> - MEI_DDI_C,
> - MEI_DDI_D,
> - MEI_DDI_E,
> - MEI_DDI_F,
> - MEI_DDI_A = 7,
> - MEI_DDI_RANGE_END = MEI_DDI_A,
> -};
> #endif /* __MEI_HDCP_H__ */
> diff --git a/include/drm/i915_mei_hdcp_interface.h
> b/include/drm/i915_mei_hdcp_interface.h
> index 8c344255146a..08670aa650d4 100644
> --- a/include/drm/i915_mei_hdcp_interface.h
> +++ b/include/drm/i915_mei_hdcp_interface.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: (GPL-2.0+) */
> /*
> - * Copyright © 2017-2018 Intel Corporation
> + * Copyright © 2017-2019 Intel Corporation
> *
> * Authors:
> * Ramalingam C <ramalingam.c@intel.com> @@ -42,9 +42,21 @@ enum
> hdcp_wired_protocol {
> HDCP_PROTOCOL_DP
> };
>
> +enum mei_fw_ddi {
> + MEI_DDI_INVALID_PORT = 0x0,
> +
> + MEI_DDI_B = 1,
> + MEI_DDI_C,
> + MEI_DDI_D,
> + MEI_DDI_E,
> + MEI_DDI_F,
> + MEI_DDI_A = 7,
> + MEI_DDI_RANGE_END = MEI_DDI_A,
> +};
> +
> /**
> * struct hdcp_port_data - intel specific HDCP port data
> - * @port: port index as per I915
> + * @fw_ddi: ddi index as per ME FW
> * @port_type: HDCP port type as per ME FW classification
> * @protocol: HDCP adaptation as per ME FW
> * @k: No of streams transmitted on a port. Only on DP MST this is != 1 @@ -
> 56,7 +68,7 @@ enum hdcp_wired_protocol {
> * streams
> */
> struct hdcp_port_data {
> - enum port port;
> + enum mei_fw_ddi fw_ddi;
> u8 port_type;
> u8 protocol;
> u16 k;
> --
> 2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-28 16:42 ` [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
@ 2019-08-28 18:50 ` Winkler, Tomas
0 siblings, 0 replies; 16+ messages in thread
From: Winkler, Tomas @ 2019-08-28 18:50 UTC (permalink / raw)
To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Nikula, Jani
Now I'm reading this other patch about DG1 ' drm/i915/dg1: Initialize DDI ports for DG1' , is this condition still correct here?
Is the condition 'INTEL_GEN(dev_priv) >= 12' sufficient ?
>
> >From Gen12 onwards, HDCP HW block is implemented within transcoders.
> Till Gen11 HDCP HW block was part of DDI.
>
> Hence required changes in HW programming is handled here.
>
> As ME FW needs the transcoder detail on which HDCP is enabled on Gen12+
> platform, we are populating the detail in hdcp_port_data.
>
> v2:
> _MMIO_TRANS is used [Lucas and Daniel]
> platform check is moved into the caller [Lucas]
> v3:
> platform check is moved into a macro [Shashank]
> v4:
> Few optimizations in the coding [Shashank]
> v5:
> Fixed alignment in macro definition in i915_reg.h [Shashank]
> unused variables "reg" is removed.
> v6:
> Configuring the transcoder at compute_config.
> transcoder is used instead of pipe in macros.
> Rebased.
> v7:
> transcoder is cached at intel_hdcp
> hdcp_port_data is configured with transcoder index asper ME FW.
> v8:
> s/trans/cpu_transcoder
> s/tc/cpu_transcoder
> v9:
> rep_ctl is prepared for TCD too.
> return moved into deault of rep_ctl prepare function [Shashank]
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 152 ++++++++++++++--------
> drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-
> drivers/gpu/drm/i915/i915_reg.h | 124 ++++++++++++++++--
> 3 files changed, 221 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index edcec64a2c11..e69fa34528df 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -20,6 +20,7 @@
> #include "intel_display_types.h"
> #include "intel_hdcp.h"
> #include "intel_sideband.h"
> +#include "intel_connector.h"
>
> #define KEY_LOAD_TRIES 5
> #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> @@ -107,24 +108,20 @@ bool intel_hdcp2_capable(struct intel_connector
> *connector)
> return capable;
> }
>
> -static inline bool intel_hdcp_in_use(struct intel_connector *connector)
> +static inline
> +bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder, enum port port)
> {
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - enum port port = connector->encoder->port;
> - u32 reg;
> -
> - reg = I915_READ(PORT_HDCP_STATUS(port));
> - return reg & HDCP_STATUS_ENC;
> + return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
> + HDCP_STATUS_ENC;
> }
>
> -static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
> +static inline
> +bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder, enum port port)
> {
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - enum port port = connector->encoder->port;
> - u32 reg;
> -
> - reg = I915_READ(HDCP2_STATUS_DDI(port));
> - return reg & LINK_ENCRYPTION_STATUS;
> + return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> + LINK_ENCRYPTION_STATUS;
> }
>
> static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
> @@ -255,9 +252,29 @@ static int intel_write_sha_text(struct
> drm_i915_private *dev_priv, u32 sha_text) }
>
> static
> -u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
> +u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder, enum port
> port)
> {
> - enum port port = intel_dig_port->base.port;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + return HDCP_TRANSA_REP_PRESENT |
> + HDCP_TRANSA_SHA1_M0;
> + case TRANSCODER_B:
> + return HDCP_TRANSB_REP_PRESENT |
> + HDCP_TRANSB_SHA1_M0;
> + case TRANSCODER_C:
> + return HDCP_TRANSC_REP_PRESENT |
> + HDCP_TRANSC_SHA1_M0;
> + case TRANSCODER_D:
> + return HDCP_TRANSD_REP_PRESENT |
> + HDCP_TRANSD_SHA1_M0;
> + default:
> + DRM_ERROR("Unknown transcoder %d\n",
> cpu_transcoder);
> + return -EINVAL;
> + }
> + }
> +
> switch (port) {
> case PORT_A:
> return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> @@ -270,18 +287,20 @@ u32 intel_hdcp_get_repeater_ctl(struct
> intel_digital_port *intel_dig_port)
> case PORT_E:
> return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> default:
> - break;
> + DRM_ERROR("Unknown port %d\n", port);
> + return -EINVAL;
> }
> - DRM_ERROR("Unknown port %d\n", port);
> - return -EINVAL;
> }
>
> static
> -int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> +int intel_hdcp_validate_v_prime(struct intel_connector *connector,
> const struct intel_hdcp_shim *shim,
> u8 *ksv_fifo, u8 num_downstream, u8
> *bstatus) {
> + struct intel_digital_port *intel_dig_port =
> +conn_to_dig_port(connector);
> struct drm_i915_private *dev_priv;
> + enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
> + enum port port = intel_dig_port->base.port;
> u32 vprime, sha_text, sha_leftovers, rep_ctl;
> int ret, i, j, sha_idx;
>
> @@ -308,7 +327,7 @@ int intel_hdcp_validate_v_prime(struct
> intel_digital_port *intel_dig_port,
> sha_idx = 0;
> sha_text = 0;
> sha_leftovers = 0;
> - rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
> + rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port);
> I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
> for (i = 0; i < num_downstream; i++) {
> unsigned int sha_empty;
> @@ -550,7 +569,7 @@ int intel_hdcp_auth_downstream(struct
> intel_connector *connector)
> * V prime atleast twice.
> */
> for (i = 0; i < tries; i++) {
> - ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> + ret = intel_hdcp_validate_v_prime(connector, shim,
> ksv_fifo, num_downstream,
> bstatus);
> if (!ret)
> @@ -578,6 +597,7 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> struct drm_device *dev = connector->base.dev;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> struct drm_i915_private *dev_priv;
> + enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
> enum port port;
> unsigned long r0_prime_gen_start;
> int ret, i, tries = 2;
> @@ -617,18 +637,21 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
>
> /* Initialize An with 2 random values and acquire it */
> for (i = 0; i < 2; i++)
> - I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
> - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
> + I915_WRITE(HDCP_ANINIT(dev_priv, cpu_transcoder, port),
> + get_random_u32());
> + I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
> + HDCP_CONF_CAPTURE_AN);
>
> /* Wait for An to be acquired */
> - if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
> + if (intel_de_wait_for_set(dev_priv,
> + HDCP_STATUS(dev_priv, cpu_transcoder,
> port),
> HDCP_STATUS_AN_READY, 1)) {
> DRM_ERROR("Timed out waiting for An\n");
> return -ETIMEDOUT;
> }
>
> - an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
> - an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
> + an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, cpu_transcoder, port));
> + an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, cpu_transcoder, port));
> ret = shim->write_an_aksv(intel_dig_port, an.shim);
> if (ret)
> return ret;
> @@ -646,24 +669,26 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> return -EPERM;
> }
>
> - I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
> - I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
> + I915_WRITE(HDCP_BKSVLO(dev_priv, cpu_transcoder, port),
> bksv.reg[0]);
> + I915_WRITE(HDCP_BKSVHI(dev_priv, cpu_transcoder, port),
> bksv.reg[1]);
>
> ret = shim->repeater_present(intel_dig_port, &repeater_present);
> if (ret)
> return ret;
> if (repeater_present)
> I915_WRITE(HDCP_REP_CTL,
> - intel_hdcp_get_repeater_ctl(intel_dig_port));
> + intel_hdcp_get_repeater_ctl(dev_priv,
> cpu_transcoder,
> + port));
>
> ret = shim->toggle_signalling(intel_dig_port, true);
> if (ret)
> return ret;
>
> - I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
> + I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
> + HDCP_CONF_AUTH_AND_ENC);
>
> /* Wait for R0 ready */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port))
> &
> (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
> DRM_ERROR("Timed out waiting for R0 ready\n");
> return -ETIMEDOUT;
> @@ -691,22 +716,25 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> if (ret)
> return ret;
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port),
> ri.reg);
>
> /* Wait for Ri prime match */
> - if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (!wait_for(I915_READ(HDCP_STATUS(dev_priv,
> cpu_transcoder,
> + port)) &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> break;
> }
>
> if (i == tries) {
> DRM_DEBUG_KMS("Timed out waiting for Ri prime match
> (%x)\n",
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv,
> cpu_transcoder,
> + port)));
> return -ETIMEDOUT;
> }
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
> + if (intel_de_wait_for_set(dev_priv,
> + HDCP_STATUS(dev_priv, cpu_transcoder,
> port),
> HDCP_STATUS_ENC,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
> {
> DRM_ERROR("Timed out waiting for encryption\n"); @@ -
> 731,15 +759,17 @@ static int _intel_hdcp_disable(struct intel_connector
> *connector)
> struct drm_i915_private *dev_priv = connector->base.dev-
> >dev_private;
> struct intel_digital_port *intel_dig_port =
> conn_to_dig_port(connector);
> enum port port = intel_dig_port->base.port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> int ret;
>
> DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> hdcp->hdcp_encrypted = false;
> - I915_WRITE(PORT_HDCP_CONF(port), 0);
> - if (intel_de_wait_for_clear(dev_priv, PORT_HDCP_STATUS(port), ~0,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
> {
> + I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> + if (intel_de_wait_for_clear(dev_priv,
> + HDCP_STATUS(dev_priv, cpu_transcoder,
> port),
> + ~0,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> DRM_ERROR("Failed to disable HDCP, timeout clearing
> status\n");
> return -ETIMEDOUT;
> }
> @@ -810,9 +840,11 @@ static int intel_hdcp_check_link(struct intel_connector
> *connector)
> struct drm_i915_private *dev_priv = connector->base.dev-
> >dev_private;
> struct intel_digital_port *intel_dig_port =
> conn_to_dig_port(connector);
> enum port port = intel_dig_port->base.port;
> + enum transcoder cpu_transcoder;
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + cpu_transcoder = hdcp->cpu_transcoder;
>
> /* Check_link valid only when HDCP1.4 is enabled */
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -821,10 +853,11 @@ static int intel_hdcp_check_link(struct
> intel_connector *connector)
> goto out;
> }
>
> - if (WARN_ON(!intel_hdcp_in_use(connector))) {
> + if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
> DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
> connector->base.name, connector->base.base.id,
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> + port)));
> ret = -ENXIO;
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> schedule_work(&hdcp->prop_work);
> @@ -1495,10 +1528,11 @@ static int hdcp2_enable_encryption(struct
> intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> int ret;
>
> - WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) &
> LINK_ENCRYPTION_STATUS);
> -
> + WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder,
> port)) &
> + LINK_ENCRYPTION_STATUS);
> if (hdcp->shim->toggle_signalling) {
> ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
> if (ret) {
> @@ -1508,14 +1542,18 @@ static int hdcp2_enable_encryption(struct
> intel_connector *connector)
> }
> }
>
> - if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
> + if (I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> + LINK_AUTH_STATUS) {
> /* Link is Authenticated. Now set for Encryption */
> - I915_WRITE(HDCP2_CTL_DDI(port),
> - I915_READ(HDCP2_CTL_DDI(port)) |
> + I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
> + I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder,
> + port)) |
> CTL_LINK_ENCRYPTION_REQ);
> }
>
> - ret = intel_de_wait_for_set(dev_priv, HDCP2_STATUS_DDI(port),
> + ret = intel_de_wait_for_set(dev_priv,
> + HDCP2_STATUS(dev_priv, cpu_transcoder,
> + port),
> LINK_ENCRYPTION_STATUS,
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
>
> @@ -1528,14 +1566,19 @@ static int hdcp2_disable_encryption(struct
> intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> int ret;
>
> - WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) &
> LINK_ENCRYPTION_STATUS));
> + WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder,
> port)) &
> + LINK_ENCRYPTION_STATUS));
>
> - I915_WRITE(HDCP2_CTL_DDI(port),
> - I915_READ(HDCP2_CTL_DDI(port)) &
> ~CTL_LINK_ENCRYPTION_REQ);
> + I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
> + I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder, port)) &
> + ~CTL_LINK_ENCRYPTION_REQ);
>
> - ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS_DDI(port),
> + ret = intel_de_wait_for_clear(dev_priv,
> + HDCP2_STATUS(dev_priv, cpu_transcoder,
> + port),
> LINK_ENCRYPTION_STATUS,
>
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> if (ret == -ETIMEDOUT)
> @@ -1634,9 +1677,11 @@ static int intel_hdcp2_check_link(struct
> intel_connector *connector)
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = connector->encoder->port;
> + enum transcoder cpu_transcoder;
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + cpu_transcoder = hdcp->cpu_transcoder;
>
> /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -1645,9 +1690,10 @@ static int intel_hdcp2_check_link(struct
> intel_connector *connector)
> goto out;
> }
>
> - if (WARN_ON(!intel_hdcp2_in_use(connector))) {
> + if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
> DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
> - I915_READ(HDCP2_STATUS_DDI(port)));
> + I915_READ(HDCP2_STATUS(dev_priv,
> cpu_transcoder,
> + port)));
> ret = -ENXIO;
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> schedule_work(&hdcp->prop_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index a0e9cc35cc47..9710b85d1aef 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct
> intel_digital_port *intel_dig_port) {
> struct drm_i915_private *dev_priv =
> intel_dig_port->base.base.dev->dev_private;
> + struct intel_connector *connector =
> + intel_dig_port->hdmi.attached_connector;
> enum port port = intel_dig_port->base.port;
> + enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
> int ret;
> union {
> u32 reg;
> @@ -1502,13 +1505,14 @@ bool intel_hdmi_hdcp_check_link(struct
> intel_digital_port *intel_dig_port)
> if (ret)
> return false;
>
> - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> + I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
>
> /* Wait for Ri prime match */
> - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> + if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port))
> &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
> - I915_READ(PORT_HDCP_STATUS(port)));
> + I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> + port)));
> return false;
> }
> return true;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 02e1ef10c47e..3cfdab18c0cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9281,12 +9281,20 @@ enum skl_power_gate {
>
> /* HDCP Repeater Registers */
> #define HDCP_REP_CTL _MMIO(0x66d00)
> +#define HDCP_TRANSA_REP_PRESENT BIT(31)
> +#define HDCP_TRANSB_REP_PRESENT BIT(30)
> +#define HDCP_TRANSC_REP_PRESENT BIT(29)
> +#define HDCP_TRANSD_REP_PRESENT BIT(28)
> #define HDCP_DDIB_REP_PRESENT BIT(30)
> #define HDCP_DDIA_REP_PRESENT BIT(29)
> #define HDCP_DDIC_REP_PRESENT BIT(28)
> #define HDCP_DDID_REP_PRESENT BIT(27)
> #define HDCP_DDIF_REP_PRESENT BIT(26)
> #define HDCP_DDIE_REP_PRESENT BIT(25)
> +#define HDCP_TRANSA_SHA1_M0 (1 << 20)
> +#define HDCP_TRANSB_SHA1_M0 (2 << 20)
> +#define HDCP_TRANSC_SHA1_M0 (3 << 20)
> +#define HDCP_TRANSD_SHA1_M0 (4 << 20)
> #define HDCP_DDIB_SHA1_M0 (1 << 20)
> #define HDCP_DDIA_SHA1_M0 (2 << 20)
> #define HDCP_DDIC_SHA1_M0 (3 << 20)
> @@ -9326,15 +9334,92 @@ enum skl_power_gate {
> _PORTE_HDCP_AUTHENC, \
> _PORTF_HDCP_AUTHENC) + (x))
> #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port,
> 0x0)
> +#define _TRANSA_HDCP_CONF 0x66400
> +#define _TRANSB_HDCP_CONF 0x66500
> +#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans,
> _TRANSA_HDCP_CONF, \
> + _TRANSB_HDCP_CONF)
> +#define HDCP_CONF(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_CONF(trans) : \
> + PORT_HDCP_CONF(port))
> +
> #define HDCP_CONF_CAPTURE_AN BIT(0)
> #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
> #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port,
> 0x4)
> +#define _TRANSA_HDCP_ANINIT 0x66404
> +#define _TRANSB_HDCP_ANINIT 0x66504
> +#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_ANINIT, \
> + _TRANSB_HDCP_ANINIT)
> +#define HDCP_ANINIT(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANINIT(trans) : \
> + PORT_HDCP_ANINIT(port))
> +
> #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port,
> 0x8)
> +#define _TRANSA_HDCP_ANLO 0x66408
> +#define _TRANSB_HDCP_ANLO 0x66508
> +#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans,
> _TRANSA_HDCP_ANLO, \
> + _TRANSB_HDCP_ANLO)
> +#define HDCP_ANLO(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANLO(trans) : \
> + PORT_HDCP_ANLO(port))
> +
> #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port,
> 0xC)
> +#define _TRANSA_HDCP_ANHI 0x6640C
> +#define _TRANSB_HDCP_ANHI 0x6650C
> +#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans,
> _TRANSA_HDCP_ANHI, \
> + _TRANSB_HDCP_ANHI)
> +#define HDCP_ANHI(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_ANHI(trans) : \
> + PORT_HDCP_ANHI(port))
> +
> #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port,
> 0x10)
> +#define _TRANSA_HDCP_BKSVLO 0x66410
> +#define _TRANSB_HDCP_BKSVLO 0x66510
> +#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_BKSVLO, \
> + _TRANSB_HDCP_BKSVLO)
> +#define HDCP_BKSVLO(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_BKSVLO(trans) : \
> + PORT_HDCP_BKSVLO(port))
> +
> #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port,
> 0x14)
> +#define _TRANSA_HDCP_BKSVHI 0x66414
> +#define _TRANSB_HDCP_BKSVHI 0x66514
> +#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_BKSVHI, \
> + _TRANSB_HDCP_BKSVHI)
> +#define HDCP_BKSVHI(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_BKSVHI(trans) : \
> + PORT_HDCP_BKSVHI(port))
> +
> #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port,
> 0x18)
> +#define _TRANSA_HDCP_RPRIME 0x66418
> +#define _TRANSB_HDCP_RPRIME 0x66518
> +#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_RPRIME, \
> + _TRANSB_HDCP_RPRIME)
> +#define HDCP_RPRIME(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_RPRIME(trans) : \
> + PORT_HDCP_RPRIME(port))
> +
> #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port,
> 0x1C)
> +#define _TRANSA_HDCP_STATUS 0x6641C
> +#define _TRANSB_HDCP_STATUS 0x6651C
> +#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP_STATUS, \
> + _TRANSB_HDCP_STATUS)
> +#define HDCP_STATUS(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP_STATUS(trans) : \
> + PORT_HDCP_STATUS(port))
> +
> #define HDCP_STATUS_STREAM_A_ENC BIT(31)
> #define HDCP_STATUS_STREAM_B_ENC BIT(30)
> #define HDCP_STATUS_STREAM_C_ENC BIT(29)
> @@ -9361,23 +9446,44 @@ enum skl_power_gate {
> _PORTD_HDCP2_BASE, \
> _PORTE_HDCP2_BASE, \
> _PORTF_HDCP2_BASE) + (x))
> -
> -#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port,
> 0x98)
> +#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port,
> 0x98)
> +#define _TRANSA_HDCP2_AUTH 0x66498
> +#define _TRANSB_HDCP2_AUTH 0x66598
> +#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans,
> _TRANSA_HDCP2_AUTH, \
> + _TRANSB_HDCP2_AUTH)
> #define AUTH_LINK_AUTHENTICATED BIT(31)
> #define AUTH_LINK_TYPE BIT(30)
> #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
> #define AUTH_CLR_KEYS BIT(18)
> -
> -#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
> +#define HDCP2_AUTH(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_AUTH(trans) : \
> + PORT_HDCP2_AUTH(port))
> +
> +#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port,
> 0xB0)
> +#define _TRANSA_HDCP2_CTL 0x664B0
> +#define _TRANSB_HDCP2_CTL 0x665B0
> +#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans,
> _TRANSA_HDCP2_CTL, \
> + _TRANSB_HDCP2_CTL)
> #define CTL_LINK_ENCRYPTION_REQ BIT(31)
> -
> -#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port,
> 0xB4)
> -#define STREAM_ENCRYPTION_STATUS_A BIT(31)
> -#define STREAM_ENCRYPTION_STATUS_B BIT(30)
> -#define STREAM_ENCRYPTION_STATUS_C BIT(29)
> +#define HDCP2_CTL(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_CTL(trans) : \
> + PORT_HDCP2_CTL(port))
> +
> +#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port,
> 0xB4)
> +#define _TRANSA_HDCP2_STATUS 0x664B4
> +#define _TRANSB_HDCP2_STATUS 0x665B4
> +#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_STATUS, \
> + _TRANSB_HDCP2_STATUS)
> #define LINK_TYPE_STATUS BIT(22)
> #define LINK_AUTH_STATUS BIT(21)
> #define LINK_ENCRYPTION_STATUS BIT(20)
> +#define HDCP2_STATUS(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_STATUS(trans) : \
> + PORT_HDCP2_STATUS(port))
>
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> --
> 2.20.1
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
2019-08-28 17:53 ` Winkler, Tomas
@ 2019-08-29 3:56 ` Ramalingam C
0 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-29 3:56 UTC (permalink / raw)
To: Winkler, Tomas; +Cc: Nikula, Jani, intel-gfx, dri-devel
On 2019-08-28 at 23:23:42 +0530, Winkler, Tomas wrote:
> > FW
> >
> > I915 converts it's port value into ddi index defiend by ME FW and pass it as a
> > member of hdcp_port_data structure.
> >
> > Hence expose the enum mei_fw_ddi to I915 through i915_mei_interface.h.
> >
> > v2:
> > Copyright years are bumped [Tomas]
> >
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > Acked-by: Jani Nikula <jani.nikula@intel.com>
> > Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> > Acked-by: Tomas Winkler <tomas.winkler@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 17 +++++++++++-
> > drivers/misc/mei/hdcp/mei_hdcp.c | 34 ++++++++---------------
> > drivers/misc/mei/hdcp/mei_hdcp.h | 12 --------
> > include/drm/i915_mei_hdcp_interface.h | 18 ++++++++++--
> > 4 files changed, 42 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 6ec5ceeab601..e8b04cc8fcb1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1,9 +1,11 @@
> > /* SPDX-License-Identifier: MIT */
> > /*
> > * Copyright (C) 2017 Google, Inc.
> > + * Copyright _ 2017-2019, Intel Corporation.
>
> Something happened here with (C) ?
In few I915 files I am seeing this format of copyright too. If this is not
right I could add (C) too.
-Ram
>
> > *
> > * Authors:
> > * Sean Paul <seanpaul@chromium.org>
> > + * Ramalingam C <ramalingam.c@intel.com>
> > */
> >
> > #include <linux/component.h>
> > @@ -1749,13 +1751,26 @@ static const struct component_ops
> > i915_hdcp_component_ops = {
> > .unbind = i915_hdcp_component_unbind,
> > };
> >
> > +static inline
> > +enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port) {
> > + switch (port) {
> > + case PORT_A:
> > + return MEI_DDI_A;
> > + case PORT_B ... PORT_F:
> > + return (enum mei_fw_ddi)port;
> > + default:
> > + return MEI_DDI_INVALID_PORT;
> > + }
> > +}
> > +
> > static inline int initialize_hdcp_port_data(struct intel_connector *connector,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > struct hdcp_port_data *data = &hdcp->port_data;
> >
> > - data->port = connector->encoder->port;
> > + data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder-
> > >port);
> > data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
> > data->protocol = (u8)shim->protocol;
> >
> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> > b/drivers/misc/mei/hdcp/mei_hdcp.c
> > index c681f6fab342..3638c77eba26 100644
> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> > @@ -27,18 +27,6 @@
> >
> > #include "mei_hdcp.h"
> >
> > -static inline u8 mei_get_ddi_index(enum port port) -{
> > - switch (port) {
> > - case PORT_A:
> > - return MEI_DDI_A;
> > - case PORT_B ... PORT_F:
> > - return (u8)port;
> > - default:
> > - return MEI_DDI_INVALID_PORT;
> > - }
> > -}
> > -
> > /**
> > * mei_hdcp_initiate_session() - Initiate a Wired HDCP2.2 Tx Session in ME FW
> > * @dev: device corresponding to the mei_cl_device @@ -69,7 +57,7 @@
> > mei_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
> >
> > WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
> >
> > session_init_in.port.integrated_port_type = data->port_type;
> > - session_init_in.port.physical_port = mei_get_ddi_index(data->port);
> > + session_init_in.port.physical_port = (u8)data->fw_ddi;
> > session_init_in.protocol = data->protocol;
> >
> > byte = mei_cldev_send(cldev, (u8 *)&session_init_in, @@ -138,7
> > +126,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
> >
> > WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
> >
> > verify_rxcert_in.port.integrated_port_type = data->port_type;
> > - verify_rxcert_in.port.physical_port = mei_get_ddi_index(data->port);
> > + verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
> >
> > verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> > memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
> > @@ -208,7 +196,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
> > hdcp_port_data *data,
> > send_hprime_in.header.buffer_len =
> > WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
> >
> > send_hprime_in.port.integrated_port_type = data->port_type;
> > - send_hprime_in.port.physical_port = mei_get_ddi_index(data->port);
> > + send_hprime_in.port.physical_port = (u8)data->fw_ddi;
> >
> > memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> > HDCP_2_2_H_PRIME_LEN);
> > @@ -265,7 +253,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
> >
> > pairing_info_in.port.integrated_port_type = data->port_type;
> > - pairing_info_in.port.physical_port = mei_get_ddi_index(data->port);
> > + pairing_info_in.port.physical_port = (u8)data->fw_ddi;
> >
> > memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> > HDCP_2_2_E_KH_KM_LEN);
> > @@ -323,7 +311,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
> > lc_init_in.header.buffer_len =
> > WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
> >
> > lc_init_in.port.integrated_port_type = data->port_type;
> > - lc_init_in.port.physical_port = mei_get_ddi_index(data->port);
> > + lc_init_in.port.physical_port = (u8)data->fw_ddi;
> >
> > byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
> > if (byte < 0) {
> > @@ -378,7 +366,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
> >
> > verify_lprime_in.port.integrated_port_type = data->port_type;
> > - verify_lprime_in.port.physical_port = mei_get_ddi_index(data->port);
> > + verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
> >
> > memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> > HDCP_2_2_L_PRIME_LEN);
> > @@ -435,7 +423,7 @@ static int mei_hdcp_get_session_key(struct device
> > *dev,
> > get_skey_in.header.buffer_len =
> > WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
> >
> > get_skey_in.port.integrated_port_type = data->port_type;
> > - get_skey_in.port.physical_port = mei_get_ddi_index(data->port);
> > + get_skey_in.port.physical_port = (u8)data->fw_ddi;
> >
> > byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
> > if (byte < 0) {
> > @@ -499,7 +487,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct
> > device *dev,
> >
> > WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
> >
> > verify_repeater_in.port.integrated_port_type = data->port_type;
> > - verify_repeater_in.port.physical_port = mei_get_ddi_index(data-
> > >port);
> > + verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
> >
> > memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> > HDCP_2_2_RXINFO_LEN);
> > @@ -569,7 +557,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> >
> > WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> >
> > verify_mprime_in.port.integrated_port_type = data->port_type;
> > - verify_mprime_in.port.physical_port = mei_get_ddi_index(data->port);
> > + verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
> >
> > memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> > HDCP_2_2_MPRIME_LEN);
> > @@ -630,7 +618,7 @@ static int mei_hdcp_enable_authentication(struct
> > device *dev,
> > enable_auth_in.header.buffer_len =
> > WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
> >
> > enable_auth_in.port.integrated_port_type = data->port_type;
> > - enable_auth_in.port.physical_port = mei_get_ddi_index(data->port);
> > + enable_auth_in.port.physical_port = (u8)data->fw_ddi;
> > enable_auth_in.stream_type = data->streams[0].stream_type;
> >
> > byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in, @@ -684,7
> > +672,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data
> > *data)
> > WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
> >
> > session_close_in.port.integrated_port_type = data->port_type;
> > - session_close_in.port.physical_port = mei_get_ddi_index(data->port);
> > + session_close_in.port.physical_port = (u8)data->fw_ddi;
> >
> > byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
> > sizeof(session_close_in));
> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h
> > b/drivers/misc/mei/hdcp/mei_hdcp.h
> > index e4b1cd54c853..e60282eb2d48 100644
> > --- a/drivers/misc/mei/hdcp/mei_hdcp.h
> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.h
> > @@ -362,16 +362,4 @@ struct wired_cmd_repeater_auth_stream_req_out {
> > struct hdcp_cmd_header header;
> > struct hdcp_port_id port;
> > } __packed;
> > -
> > -enum mei_fw_ddi {
> > - MEI_DDI_INVALID_PORT = 0x0,
> > -
> > - MEI_DDI_B = 1,
> > - MEI_DDI_C,
> > - MEI_DDI_D,
> > - MEI_DDI_E,
> > - MEI_DDI_F,
> > - MEI_DDI_A = 7,
> > - MEI_DDI_RANGE_END = MEI_DDI_A,
> > -};
> > #endif /* __MEI_HDCP_H__ */
> > diff --git a/include/drm/i915_mei_hdcp_interface.h
> > b/include/drm/i915_mei_hdcp_interface.h
> > index 8c344255146a..08670aa650d4 100644
> > --- a/include/drm/i915_mei_hdcp_interface.h
> > +++ b/include/drm/i915_mei_hdcp_interface.h
> > @@ -1,6 +1,6 @@
> > /* SPDX-License-Identifier: (GPL-2.0+) */
> > /*
> > - * Copyright © 2017-2018 Intel Corporation
> > + * Copyright © 2017-2019 Intel Corporation
> > *
> > * Authors:
> > * Ramalingam C <ramalingam.c@intel.com> @@ -42,9 +42,21 @@ enum
> > hdcp_wired_protocol {
> > HDCP_PROTOCOL_DP
> > };
> >
> > +enum mei_fw_ddi {
> > + MEI_DDI_INVALID_PORT = 0x0,
> > +
> > + MEI_DDI_B = 1,
> > + MEI_DDI_C,
> > + MEI_DDI_D,
> > + MEI_DDI_E,
> > + MEI_DDI_F,
> > + MEI_DDI_A = 7,
> > + MEI_DDI_RANGE_END = MEI_DDI_A,
> > +};
> > +
> > /**
> > * struct hdcp_port_data - intel specific HDCP port data
> > - * @port: port index as per I915
> > + * @fw_ddi: ddi index as per ME FW
> > * @port_type: HDCP port type as per ME FW classification
> > * @protocol: HDCP adaptation as per ME FW
> > * @k: No of streams transmitted on a port. Only on DP MST this is != 1 @@ -
> > 56,7 +68,7 @@ enum hdcp_wired_protocol {
> > * streams
> > */
> > struct hdcp_port_data {
> > - enum port port;
> > + enum mei_fw_ddi fw_ddi;
> > u8 port_type;
> > u8 protocol;
> > u16 k;
> > --
> > 2.20.1
>
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-28 16:48 ` [PATCH v12 0/6] drm/i915: " Ramalingam C
@ 2019-08-29 9:58 ` Winkler, Tomas
2019-08-29 10:07 ` Ramalingam C
0 siblings, 1 reply; 16+ messages in thread
From: Winkler, Tomas @ 2019-08-29 9:58 UTC (permalink / raw)
To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Nikula, Jani
> On 2019-08-28 at 22:12:10 +0530, Ramalingam C wrote:
> > Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block
> > movement from DDI into transcoder.
> >
> > v12:
> > r-b and ack are collected.
> > few review comments are addressed.
>
> Tomas,
>
> Thanks for reviewing the patches and providing the Ack/R-bes.
> As we discussed offline, we need your ACK for submitting mei_hdcp patches
> through dinq(drm-intel-next-queued). Please provide the same.
ACK
>
> -Ram
> >
> > Ramalingam C (6):
> > drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
> > drm: Move port definition back to i915 header
> > drm: Extend I915 mei interface for transcoder info
> > misc/mei/hdcp: Fill transcoder index in port info
> > drm/i915/hdcp: update current transcoder into intel_hdcp
> > drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
> >
> > drivers/gpu/drm/i915/display/intel_bios.h | 3 +-
> > drivers/gpu/drm/i915/display/intel_display.h | 20 +-
> > .../drm/i915/display/intel_display_types.h | 7 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++++++++++++-----
> > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
> > drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-
> > drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++--
> > drivers/misc/mei/hdcp/mei_hdcp.h | 17 +-
> > include/drm/i915_drm.h | 18 --
> > include/drm/i915_mei_hdcp_interface.h | 42 +++-
> > 16 files changed, 389 insertions(+), 125 deletions(-)
> >
> > --
> > 2.20.1
> >
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-29 9:58 ` Winkler, Tomas
@ 2019-08-29 10:07 ` Ramalingam C
0 siblings, 0 replies; 16+ messages in thread
From: Ramalingam C @ 2019-08-29 10:07 UTC (permalink / raw)
To: Winkler, Tomas; +Cc: Nikula, Jani, intel-gfx, dri-devel
On 2019-08-29 at 15:28:35 +0530, Winkler, Tomas wrote:
> > On 2019-08-28 at 22:12:10 +0530, Ramalingam C wrote:
> > > Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block
> > > movement from DDI into transcoder.
> > >
> > > v12:
> > > r-b and ack are collected.
> > > few review comments are addressed.
> >
> > Tomas,
> >
> > Thanks for reviewing the patches and providing the Ack/R-bes.
> > As we discussed offline, we need your ACK for submitting mei_hdcp patches
> > through dinq(drm-intel-next-queued). Please provide the same.
>
>
> ACK
Once again thanks Tomas for review.
-Ram
>
> >
> > -Ram
> > >
> > > Ramalingam C (6):
> > > drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
> > > drm: Move port definition back to i915 header
> > > drm: Extend I915 mei interface for transcoder info
> > > misc/mei/hdcp: Fill transcoder index in port info
> > > drm/i915/hdcp: update current transcoder into intel_hdcp
> > > drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
> > >
> > > drivers/gpu/drm/i915/display/intel_bios.h | 3 +-
> > > drivers/gpu/drm/i915/display/intel_display.h | 20 +-
> > > .../drm/i915/display/intel_display_types.h | 7 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> > > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++++++++++++-----
> > > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +-
> > > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-
> > > drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++--
> > > drivers/misc/mei/hdcp/mei_hdcp.h | 17 +-
> > > include/drm/i915_drm.h | 18 --
> > > include/drm/i915_mei_hdcp_interface.h | 42 +++-
> > > 16 files changed, 389 insertions(+), 125 deletions(-)
> > >
> > > --
> > > 2.20.1
> > >
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10)
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (6 preceding siblings ...)
2019-08-28 16:48 ` [PATCH v12 0/6] drm/i915: " Ramalingam C
@ 2019-08-29 10:28 ` Patchwork
2019-08-29 19:27 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-30 8:21 ` [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Shankar, Uma
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-08-29 10:28 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6798 -> Patchwork_14215
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/
Known issues
------------
Here are the changes found in Patchwork_14215 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-cml-u2/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-cml-u2/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] ([fdo#108744])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [INCOMPLETE][7] ([fdo#111514]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-skl-iommu: [INCOMPLETE][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-skl-iommu/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111096]) -> [FAIL][12] ([fdo#111407])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Participating hosts (52 -> 43)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-whl-u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6798 -> Patchwork_14215
CI-20190529: 20190529
CI_DRM_6798: 9c51d473851d23f32a0667e3f2b8ed5bda27bf42 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5152: f9d17c54c6946eb6391fce88687f9b071be9446b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14215: 52c7bcb498aa0f7ccc77b7718c53b8df904846e2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
52c7bcb498aa drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
975b516f515c drm/i915/hdcp: update current transcoder into intel_hdcp
cfe98ca3ed18 misc/mei/hdcp: Fill transcoder index in port info
87c019054d44 drm: Extend I915 mei interface for transcoder info
a35155b285d1 drm: Move port definition back to i915 header
97f82b42fa4f drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10)
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (7 preceding siblings ...)
2019-08-29 10:28 ` ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10) Patchwork
@ 2019-08-29 19:27 ` Patchwork
2019-08-30 8:21 ` [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Shankar, Uma
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-08-29 19:27 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6798_full -> Patchwork_14215_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14215_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb8/igt@gem_ctx_isolation@vcs1-none.html
* igt@gem_ctx_switch@legacy-bsd1-heavy-queue:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl7/igt@gem_ctx_switch@legacy-bsd1-heavy-queue.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl3/igt@gem_ctx_switch@legacy-bsd1-heavy-queue.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: ([PASS][5], [PASS][6]) -> [SKIP][7] ([fdo#110854])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@gem_exec_balancer@smoke.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb4/igt@gem_exec_balancer@smoke.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb3/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: ([PASS][8], [PASS][9]) -> [SKIP][10] ([fdo#109276]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb5/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: ([PASS][11], [PASS][12]) -> [SKIP][13] ([fdo#111325]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@gem_exec_schedule@preempt-bsd.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb2/igt@gem_exec_schedule@preempt-bsd.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: ([PASS][16], [PASS][17]) -> [DMESG-WARN][18] ([fdo#108566]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl2/igt@i915_suspend@debugfs-reader.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl5/igt@i915_suspend@debugfs-reader.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl7/igt@i915_suspend@debugfs-reader.html
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-iclb: ([PASS][19], [PASS][20]) -> [INCOMPLETE][21] ([fdo#107713])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb4/igt@kms_color@pipe-c-ctm-green-to-red.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@kms_color@pipe-c-ctm-green-to-red.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb7/igt@kms_color@pipe-c-ctm-green-to-red.html
* igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
- shard-apl: ([PASS][22], [PASS][23]) -> [INCOMPLETE][24] ([fdo#103927]) +4 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl2/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl8/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl4/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: ([PASS][25], [PASS][26]) -> [INCOMPLETE][27] ([fdo#104108])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl7/igt@kms_fbcon_fbt@fbc-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl8/igt@kms_fbcon_fbt@fbc-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][28] -> [FAIL][29] ([fdo#105363])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: ([PASS][30], [PASS][31]) -> [INCOMPLETE][32] ([fdo#109507])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl8/igt@kms_flip@flip-vs-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl2/igt@kms_flip@flip-vs-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: ([PASS][33], [PASS][34]) -> [FAIL][35] ([fdo#103167]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: ([PASS][36], [PASS][37]) -> [DMESG-WARN][38] ([fdo#108566]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-skl: ([PASS][41], [PASS][42]) -> [DMESG-WARN][43] ([fdo#106885])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl1/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl6/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl4/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][44] -> [SKIP][45] ([fdo#109441])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: ([PASS][46], [PASS][47]) -> [FAIL][48] ([fdo#99912])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl5/igt@kms_setmode@basic.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl4/igt@kms_setmode@basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl2/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#110728]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl5/igt@perf@blocking.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl2/igt@perf@blocking.html
* igt@prime_busy@wait-hang-bsd1:
- shard-iclb: [PASS][51] -> [INCOMPLETE][52] ([fdo#107713])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@prime_busy@wait-hang-bsd1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb7/igt@prime_busy@wait-hang-bsd1.html
* igt@tools_test@sysfs_l3_parity:
- shard-hsw: ([PASS][53], [PASS][54]) -> [SKIP][55] ([fdo#109271])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw8/igt@tools_test@sysfs_l3_parity.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw5/igt@tools_test@sysfs_l3_parity.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-hsw6/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: ([DMESG-WARN][56], [PASS][57]) ([fdo#108566]) -> [PASS][58] +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl5/igt@gem_ctx_isolation@bcs0-s3.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: ([SKIP][59], [PASS][60]) ([fdo#110841]) -> [PASS][61]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: ([PASS][62], [SKIP][63]) ([fdo#111325]) -> [PASS][64] +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: ([SKIP][65], [SKIP][66]) ([fdo#109276]) -> [PASS][67] +12 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@gem_exec_schedule@in-order-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb8/igt@gem_exec_schedule@in-order-bsd2.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb2/igt@gem_exec_schedule@in-order-bsd2.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: ([PASS][68], [SKIP][69]) ([fdo#109276]) -> [PASS][70] +12 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: ([SKIP][71], [SKIP][72]) ([fdo#111325]) -> [PASS][73]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-apl: ([PASS][74], [INCOMPLETE][75]) ([fdo#103927]) -> [PASS][76]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: ([PASS][77], [INCOMPLETE][78]) ([fdo#104108]) -> [PASS][79]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl1/igt@gem_softpin@noreloc-s3.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl9/igt@gem_softpin@noreloc-s3.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl4/igt@gem_softpin@noreloc-s3.html
- shard-kbl: ([DMESG-WARN][80], [PASS][81]) ([fdo#108566]) -> [PASS][82] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl6/igt@gem_softpin@noreloc-s3.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl3/igt@gem_softpin@noreloc-s3.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-kbl1/igt@gem_softpin@noreloc-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: ([PASS][83], [DMESG-WARN][84]) ([fdo#108686]) -> [PASS][85]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: ([DMESG-WARN][86], [DMESG-WARN][87]) ([fdo#108566]) -> [PASS][88] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl7/igt@i915_suspend@sysfs-reader.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-apl4/igt@i915_suspend@sysfs-reader.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-transition-fencing:
- shard-iclb: ([PASS][89], [INCOMPLETE][90]) ([fdo#107713]) -> [PASS][91]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb3/igt@kms_atomic_transition@plane-all-transition-fencing.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb7/igt@kms_atomic_transition@plane-all-transition-fencing.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb8/igt@kms_atomic_transition@plane-all-transition-fencing.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: ([FAIL][92], [PASS][93]) ([fdo#105767]) -> [PASS][94]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: ([PASS][95], [FAIL][96]) ([fdo#103355]) -> [PASS][97]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: ([FAIL][98], [FAIL][99]) ([fdo#103167]) -> [PASS][100]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: ([FAIL][101], [PASS][102]) ([fdo#103167]) -> [PASS][103] +6 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-farfromfence:
- shard-skl: ([FAIL][104], [FAIL][105]) ([fdo#103167]) -> [PASS][106]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl3/igt@kms_frontbuffer_tracking@psr-farfromfence.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl4/igt@kms_frontbuffer_tracking@psr-farfromfence.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl8/igt@kms_frontbuffer_tracking@psr-farfromfence.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: ([FAIL][107], [FAIL][108]) ([fdo#108145]) -> [PASS][109]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: ([SKIP][110], [SKIP][111]) ([fdo#109642] / [fdo#111068]) -> [PASS][112]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@kms_psr2_su@page_flip.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb8/igt@kms_psr2_su@page_flip.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: ([SKIP][113], [SKIP][114]) ([fdo#109441]) -> [PASS][115] +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: ([SKIP][116], [PASS][117]) ([fdo#109441]) -> [PASS][118]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb5/igt@kms_psr@psr2_suspend.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6798/shard-iclb2/igt@kms_psr@psr2_suspend.html
[11
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14215/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
` (8 preceding siblings ...)
2019-08-29 19:27 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-30 8:21 ` Shankar, Uma
9 siblings, 0 replies; 16+ messages in thread
From: Shankar, Uma @ 2019-08-30 8:21 UTC (permalink / raw)
To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Nikula, Jani, Winkler, Tomas
>-----Original Message-----
>From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ramalingam
>C
>Sent: Wednesday, August 28, 2019 10:12 PM
>To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
>devel@lists.freedesktop.org>
>Cc: Nikula, Jani <jani.nikula@intel.com>; Winkler, Tomas <tomas.winkler@intel.com>
>Subject: [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
>
>Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement from
>DDI into transcoder.
>
>v12:
> r-b and ack are collected.
> few review comments are addressed.
With the Acks from Tomas and Jani N, and RB from Shashank.
Pushed the series to dinq. Thanks for the patches and the reviews.
Regards,
Uma Shankar
>Ramalingam C (6):
> drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
> drm: Move port definition back to i915 header
> drm: Extend I915 mei interface for transcoder info
> misc/mei/hdcp: Fill transcoder index in port info
> drm/i915/hdcp: update current transcoder into intel_hdcp
> drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
>
> drivers/gpu/drm/i915/display/intel_bios.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.h | 20 +-
> .../drm/i915/display/intel_display_types.h | 7 +
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++++++++++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +-
> drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
> drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
> drivers/gpu/drm/i915/display/intel_sdvo.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-
> drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++--
> drivers/misc/mei/hdcp/mei_hdcp.h | 17 +-
> include/drm/i915_drm.h | 18 --
> include/drm/i915_mei_hdcp_interface.h | 42 +++-
> 16 files changed, 389 insertions(+), 125 deletions(-)
>
>--
>2.20.1
>
>_______________________________________________
>dri-devel mailing list
>dri-devel@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-08-30 8:21 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-28 16:42 [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-08-28 16:42 ` [PATCH v12 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW Ramalingam C
2019-08-28 17:53 ` Winkler, Tomas
2019-08-29 3:56 ` Ramalingam C
2019-08-28 16:42 ` [PATCH v12 2/6] drm: Move port definition back to i915 header Ramalingam C
2019-08-28 16:42 ` [PATCH v12 3/6] drm: Extend I915 mei interface for transcoder info Ramalingam C
2019-08-28 16:42 ` [PATCH v12 4/6] misc/mei/hdcp: Fill transcoder index in port info Ramalingam C
2019-08-28 16:42 ` [PATCH v12 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp Ramalingam C
2019-08-28 16:42 ` [PATCH v12 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ Ramalingam C
2019-08-28 18:50 ` Winkler, Tomas
2019-08-28 16:48 ` [PATCH v12 0/6] drm/i915: " Ramalingam C
2019-08-29 9:58 ` Winkler, Tomas
2019-08-29 10:07 ` Ramalingam C
2019-08-29 10:28 ` ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev10) Patchwork
2019-08-29 19:27 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-30 8:21 ` [PATCH v12 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ Shankar, Uma
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