[Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Alex Bennée]

Hi Peter,

Here are the ARM semi-hosting cleanup patches and a small selection of
miscellaneous TCG clean-ups. If your happy taking them all through
your tree please do otherwise I'll poke Richard. I'm just trying to
reduce the delta for my next iteration of the plugin series.

The following patches need review
   04 - target arm remove run time semihosting checks
   05 - includes remove stale smp max _cpus externs

The first is the result of review comments, moving CONFIG_TCG ifdefs
around and the second is pretty trivial.

Alex Bennée (7):
  target/arm: handle M-profile semihosting at translate time
  target/arm: handle A-profile T32 semihosting at translate time
  target/arm: handle A-profile A32 semihosting at translate time
  target/arm: remove run time semihosting checks
  includes: remove stale [smp|max]_cpus externs
  accel/stubs: reduce headers from tcg-stub
  include/exec/cpu-defs.h: fix typo

Emilio G. Cota (2):
  tcg/README: fix typo s/afterwise/afterwards/
  atomic_template: fix indentation in GEN_ATOMIC_HELPER

 accel/stubs/tcg-stub.c      |  2 -
 accel/tcg/atomic_template.h |  2 +-
 include/exec/cpu-defs.h     |  2 +-
 include/sysemu/sysemu.h     |  2 -
 target/arm/helper.c         | 96 +++++++++----------------------------
 target/arm/m_helper.c       | 18 +++----
 target/arm/translate.c      | 64 +++++++++++++++++++++----
 tcg/README                  |  2 +-
 8 files changed, 87 insertions(+), 101 deletions(-)

-- 
2.20.1

[Qemu-devel] [PATCH v1 1/9] target/arm: handle M-profile semihosting at translate time

[Alex Bennée]

We do this for other semihosting calls so we might as well do it for
M-profile as well.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/m_helper.c  | 18 ++++++------------
 target/arm/translate.c | 20 +++++++++++++++++++-
 2 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 884d35d2b02..27cd2f3f964 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
             break;
         }
         break;
+    case EXCP_SEMIHOST:
+        qemu_log_mask(CPU_LOG_INT,
+                      "...handling as semihosting call 0x%x\n",
+                      env->regs[0]);
+        env->regs[0] = do_arm_semihosting(env);
+        return;
     case EXCP_BKPT:
-        if (semihosting_enabled()) {
-            int nr;
-            nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
-            if (nr == 0xab) {
-                env->regs[15] += 2;
-                qemu_log_mask(CPU_LOG_INT,
-                              "...handling as semihosting call 0x%x\n",
-                              env->regs[0]);
-                env->regs[0] = do_arm_semihosting(env);
-                return;
-            }
-        }
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
         break;
     case EXCP_IRQ:
diff --git a/target/arm/translate.c b/target/arm/translate.c
index cbe19b7a625..259c4669b4c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10889,6 +10889,24 @@ illegal_op:
     unallocated_encoding(s);
 }
 
+/*
+ * Thumb BKPT. On M-profile CPUs this may be a semihosting call which
+ * we can process much the same way as gen_hlt() above.
+ */
+static inline void gen_thumb_bkpt(DisasContext *s, int imm8)
+{
+    if (arm_dc_feature(s, ARM_FEATURE_M) &&
+        semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+        s->current_el != 0 &&
+#endif
+        (imm8 == 0xab)) {
+        gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+        return;
+    }
+    gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
+}
+
 static void disas_thumb_insn(DisasContext *s, uint32_t insn)
 {
     uint32_t val, op, rm, rn, rd, shift, cond;
@@ -11511,7 +11529,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
         {
             int imm8 = extract32(insn, 0, 8);
             ARCH(5);
-            gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
+            gen_thumb_bkpt(s, imm8);
             break;
         }
 
-- 
2.20.1

[Qemu-devel] [PATCH v1 2/9] target/arm: handle A-profile T32 semihosting at translate time

[Alex Bennée]

As for the other semihosting calls we can resolve this at translate
time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 259c4669b4c..6157e9f52fc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10907,6 +10907,24 @@ static inline void gen_thumb_bkpt(DisasContext *s, int imm8)
     gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
 }
 
+/*
+ * Thumb SWI. On A-profile CPUs this may be a semihosting call.
+ */
+static inline void gen_thumb_swi(DisasContext *s, int imm8)
+{
+    if (semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+        s->current_el != 0 &&
+#endif
+        (imm8 == 0xab)) {
+        gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+        return;
+    }
+    gen_set_pc_im(s, s->base.pc_next);
+    s->svc_imm = imm8;
+    s->base.is_jmp = DISAS_SWI;
+}
+
 static void disas_thumb_insn(DisasContext *s, uint32_t insn)
 {
     uint32_t val, op, rm, rn, rd, shift, cond;
@@ -11658,10 +11676,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
             goto undef;
 
         if (cond == 0xf) {
-            /* swi */
-            gen_set_pc_im(s, s->base.pc_next);
-            s->svc_imm = extract32(insn, 0, 8);
-            s->base.is_jmp = DISAS_SWI;
+            /* swi/svc  */
+            gen_thumb_swi(s, extract32(insn, 0, 8));
             break;
         }
         /* generate a conditional jump to next instruction */
-- 
2.20.1

[Qemu-devel] [PATCH v1 3/9] target/arm: handle A-profile A32 semihosting at translate time

[Alex Bennée]

As for the other semihosting calls we can resolve this at translate
time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6157e9f52fc..9dc7ec78061 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7657,6 +7657,22 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
     arm_gen_test_cc(cond ^ 1, s->condlabel);
 }
 
+static inline void gen_arm_swi(DisasContext *s, int imm24)
+{
+    if (semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+        s->current_el != 0 &&
+#endif
+        (imm24 == 0x123456)) {
+        gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+        return;
+    }
+
+    gen_set_pc_im(s, s->base.pc_next);
+    s->svc_imm = imm24;
+    s->base.is_jmp = DISAS_SWI;
+}
+
 static void disas_arm_insn(DisasContext *s, unsigned int insn)
 {
     unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
@@ -9195,9 +9211,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             break;
         case 0xf:
             /* swi */
-            gen_set_pc_im(s, s->base.pc_next);
-            s->svc_imm = extract32(insn, 0, 24);
-            s->base.is_jmp = DISAS_SWI;
+            gen_arm_swi(s, extract32(insn, 0, 24));
             break;
         default:
         illegal_op:
-- 
2.20.1

[Qemu-devel] [PATCH v1 4/9] target/arm: remove run time semihosting checks

[Alex Bennée]

Now we do all our checking and use a common EXCP_SEMIHOST for
semihosting operations we can make helper code a lot simpler.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
v2
  - fix re-base conflicts
  - hoist EXCP_SEMIHOST check
  - comment cleanups
v5
  - move CONFIG_TCG ifdefs
---
 target/arm/helper.c | 96 +++++++++++----------------------------------
 1 file changed, 22 insertions(+), 74 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7e0d5398ab8..c54d4768e1d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8262,88 +8262,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
                   new_el, env->pc, pstate_read(env));
 }
 
-static inline bool check_for_semihosting(CPUState *cs)
-{
+/*
+ * Do semihosting call and set the appropriate return value. All the
+ * permission and validity checks have been done at translate time.
+ *
+ * We only see semihosting exceptions in TCG only as they are not
+ * trapped to the hypervisor in KVM.
+ */
 #ifdef CONFIG_TCG
-    /* Check whether this exception is a semihosting call; if so
-     * then handle it and return true; otherwise return false.
-     */
+static void handle_semihosting(CPUState *cs)
+{
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
 
     if (is_a64(env)) {
-        if (cs->exception_index == EXCP_SEMIHOST) {
-            /* This is always the 64-bit semihosting exception.
-             * The "is this usermode" and "is semihosting enabled"
-             * checks have been done at translate time.
-             */
-            qemu_log_mask(CPU_LOG_INT,
-                          "...handling as semihosting call 0x%" PRIx64 "\n",
-                          env->xregs[0]);
-            env->xregs[0] = do_arm_semihosting(env);
-            return true;
-        }
-        return false;
+        qemu_log_mask(CPU_LOG_INT,
+                      "...handling as semihosting call 0x%" PRIx64 "\n",
+                      env->xregs[0]);
+        env->xregs[0] = do_arm_semihosting(env);
     } else {
-        uint32_t imm;
-
-        /* Only intercept calls from privileged modes, to provide some
-         * semblance of security.
-         */
-        if (cs->exception_index != EXCP_SEMIHOST &&
-            (!semihosting_enabled() ||
-             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
-            return false;
-        }
-
-        switch (cs->exception_index) {
-        case EXCP_SEMIHOST:
-            /* This is always a semihosting call; the "is this usermode"
-             * and "is semihosting enabled" checks have been done at
-             * translate time.
-             */
-            break;
-        case EXCP_SWI:
-            /* Check for semihosting interrupt.  */
-            if (env->thumb) {
-                imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
-                    & 0xff;
-                if (imm == 0xab) {
-                    break;
-                }
-            } else {
-                imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
-                    & 0xffffff;
-                if (imm == 0x123456) {
-                    break;
-                }
-            }
-            return false;
-        case EXCP_BKPT:
-            /* See if this is a semihosting syscall.  */
-            if (env->thumb) {
-                imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
-                    & 0xff;
-                if (imm == 0xab) {
-                    env->regs[15] += 2;
-                    break;
-                }
-            }
-            return false;
-        default:
-            return false;
-        }
-
         qemu_log_mask(CPU_LOG_INT,
                       "...handling as semihosting call 0x%x\n",
                       env->regs[0]);
         env->regs[0] = do_arm_semihosting(env);
-        return true;
     }
-#else
-    return false;
-#endif
 }
+#endif
 
 /* Handle a CPU exception for A and R profile CPUs.
  * Do any appropriate logging, handle PSCI calls, and then hand off
@@ -8374,13 +8318,17 @@ void arm_cpu_do_interrupt(CPUState *cs)
         return;
     }
 
-    /* Semihosting semantics depend on the register width of the
-     * code that caused the exception, not the target exception level,
-     * so must be handled here.
+    /*
+     * Semihosting semantics depend on the register width of the code
+     * that caused the exception, not the target exception level, so
+     * must be handled here.
      */
-    if (check_for_semihosting(cs)) {
+#ifdef CONFIG_TCG
+    if (cs->exception_index == EXCP_SEMIHOST) {
+        handle_semihosting(cs);
         return;
     }
+#endif
 
     /* Hooks may change global state so BQL should be held, also the
      * BQL needs to be held for any modification of
-- 
2.20.1

Re: [Qemu-devel] [PATCH v1 4/9] target/arm: remove run time semihosting checks

[Richard Henderson]

On 8/28/19 9:53 AM, Alex Bennée wrote:
> Now we do all our checking and use a common EXCP_SEMIHOST for
> semihosting operations we can make helper code a lot simpler.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> 
> ---
> v2
>   - fix re-base conflicts
>   - hoist EXCP_SEMIHOST check
>   - comment cleanups
> v5
>   - move CONFIG_TCG ifdefs
> ---
>  target/arm/helper.c | 96 +++++++++++----------------------------------
>  1 file changed, 22 insertions(+), 74 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[Qemu-devel] [PATCH v1 5/9] includes: remove stale [smp|max]_cpus externs

[Alex Bennée]

Commit a5e0b3311 removed these in favour of querying machine
properties. Remove the extern declarations as well.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190711130546.18578-1-alex.bennee@linaro.org>
---
 include/sysemu/sysemu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index d2c38f611a3..44f18eb7394 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -42,8 +42,6 @@ extern const char *keyboard_layout;
 extern int win2k_install_hack;
 extern int alt_grab;
 extern int ctrl_grab;
-extern int smp_cpus;
-extern unsigned int max_cpus;
 extern int cursor_hide;
 extern int graphic_rotate;
 extern int no_quit;
-- 
2.20.1

Re: [Qemu-devel] [PATCH v1 5/9] includes: remove stale [smp|max]_cpus externs

[Richard Henderson]

On 8/28/19 9:53 AM, Alex Bennée wrote:
> Commit a5e0b3311 removed these in favour of querying machine
> properties. Remove the extern declarations as well.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Like Xu <like.xu@linux.intel.com>
> Message-Id: <20190711130546.18578-1-alex.bennee@linaro.org>
> ---
>  include/sysemu/sysemu.h | 2 --
>  1 file changed, 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[Qemu-devel] [PATCH v1 6/9] tcg/README: fix typo s/afterwise/afterwards/

[Alex Bennée]

From: "Emilio G. Cota" <cota@braap.org>

Afterwise is "wise after the fact", as in "hindsight".
Here we meant "afterwards" (as in "subsequently"). Fix it.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 tcg/README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/README b/tcg/README
index 21fcdf737ff..ef9be5ba90e 100644
--- a/tcg/README
+++ b/tcg/README
@@ -101,7 +101,7 @@ This can be overridden using the following function modifiers:
   canonical locations before calling the helper.
 - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
   They will only be saved to their canonical location before calling helpers,
-  but they won't be reloaded afterwise.
+  but they won't be reloaded afterwards.
 - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
   the return value is not used.
 
-- 
2.20.1

[Qemu-devel] [PATCH v1 7/9] atomic_template: fix indentation in GEN_ATOMIC_HELPER

[Alex Bennée]

From: "Emilio G. Cota" <cota@braap.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 accel/tcg/atomic_template.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 5aaf1862539..df9c8388178 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -284,7 +284,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
 
 #define GEN_ATOMIC_HELPER(X)                                        \
 ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
-                 ABI_TYPE val EXTRA_ARGS)                           \
+                        ABI_TYPE val EXTRA_ARGS)                    \
 {                                                                   \
     ATOMIC_MMU_DECLS;                                               \
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                           \
-- 
2.20.1

[Qemu-devel] [PATCH v1 8/9] accel/stubs: reduce headers from tcg-stub

[Alex Bennée]

We don't need much for these. However I do wonder why these aren't
just null inlines in exec-all.h

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/stubs/tcg-stub.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index e2d23edafe0..75b10ab54be 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -11,10 +11,8 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu-common.h"
 #include "cpu.h"
 #include "tcg/tcg.h"
-#include "exec/exec-all.h"
 
 void tb_flush(CPUState *cpu)
 {
-- 
2.20.1

Re: [Qemu-devel] [PATCH v1 8/9] accel/stubs: reduce headers from tcg-stub

[Alex Bennée]

Alex Bennée <alex.bennee@linaro.org> writes:

> We don't need much for these. However I do wonder why these aren't
> just null inlines in exec-all.h
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  accel/stubs/tcg-stub.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
> index e2d23edafe0..75b10ab54be 100644
> --- a/accel/stubs/tcg-stub.c
> +++ b/accel/stubs/tcg-stub.c
> @@ -11,10 +11,8 @@
>   */
>
>  #include "qemu/osdep.h"
> -#include "qemu-common.h"
>  #include "cpu.h"
>  #include "tcg/tcg.h"
> -#include "exec/exec-all.h"
>
>  void tb_flush(CPUState *cpu)
>  {

I'll drop this one as it doesn't merge build cleanly against master on
Travis (but oddly built on my machine).

--
Alex Bennée

[Qemu-devel] [PATCH v1 9/9] include/exec/cpu-defs.h: fix typo

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 189709b6deb..be946ba1ce5 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -231,7 +231,7 @@ typedef struct CPUTLB { } CPUTLB;
 #endif  /* !CONFIG_USER_ONLY && CONFIG_TCG */
 
 /*
- * This structure must be placed in ArchCPU immedately
+ * This structure must be placed in ArchCPU immediately
  * before CPUArchState, as a field named "neg".
  */
 typedef struct CPUNegativeOffsetState {
-- 
2.20.1

Re: [Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Philippe Mathieu-Daudé]

On 8/28/19 6:52 PM, Alex Bennée wrote:
> Hi Peter,
> 
> Here are the ARM semi-hosting cleanup patches and a small selection of
> miscellaneous TCG clean-ups. If your happy taking them all through
> your tree please do otherwise I'll poke Richard. I'm just trying to
> reduce the delta for my next iteration of the plugin series.
> 
> The following patches need review
>    04 - target arm remove run time semihosting checks
>    05 - includes remove stale smp max _cpus externs
> 
> The first is the result of review comments, moving CONFIG_TCG ifdefs
> around and the second is pretty trivial.
> 
> Alex Bennée (7):
>   target/arm: handle M-profile semihosting at translate time
>   target/arm: handle A-profile T32 semihosting at translate time
>   target/arm: handle A-profile A32 semihosting at translate time
>   target/arm: remove run time semihosting checks
>   includes: remove stale [smp|max]_cpus externs
>   accel/stubs: reduce headers from tcg-stub
>   include/exec/cpu-defs.h: fix typo
> 
> Emilio G. Cota (2):
>   tcg/README: fix typo s/afterwise/afterwards/
>   atomic_template: fix indentation in GEN_ATOMIC_HELPER

Thanks for cleaning this!

Series except patch #8 which you dropped:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Re: [Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Peter Maydell]

On Wed, 28 Aug 2019 at 18:08, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Hi Peter,
>
> Here are the ARM semi-hosting cleanup patches and a small selection of
> miscellaneous TCG clean-ups. If your happy taking them all through
> your tree please do otherwise I'll poke Richard. I'm just trying to
> reduce the delta for my next iteration of the plugin series.
>
> The following patches need review
>    04 - target arm remove run time semihosting checks
>    05 - includes remove stale smp max _cpus externs
>
> The first is the result of review comments, moving CONFIG_TCG ifdefs
> around and the second is pretty trivial.
>
> Alex Bennée (7):
>   target/arm: handle M-profile semihosting at translate time
>   target/arm: handle A-profile T32 semihosting at translate time
>   target/arm: handle A-profile A32 semihosting at translate time
>   target/arm: remove run time semihosting checks
>   includes: remove stale [smp|max]_cpus externs
>   accel/stubs: reduce headers from tcg-stub
>   include/exec/cpu-defs.h: fix typo
>
> Emilio G. Cota (2):
>   tcg/README: fix typo s/afterwise/afterwards/
>   atomic_template: fix indentation in GEN_ATOMIC_HELPER

Series, except for patch 8, applied to target-arm.next.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Peter Maydell]

On Wed, 28 Aug 2019 at 18:08, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Hi Peter,
>
> Here are the ARM semi-hosting cleanup patches and a small selection of
> miscellaneous TCG clean-ups. If your happy taking them all through
> your tree please do otherwise I'll poke Richard. I'm just trying to
> reduce the delta for my next iteration of the plugin series.
>
> The following patches need review
>    04 - target arm remove run time semihosting checks
>    05 - includes remove stale smp max _cpus externs
>
> The first is the result of review comments, moving CONFIG_TCG ifdefs
> around and the second is pretty trivial.
>
> Alex Bennée (7):
>   target/arm: handle M-profile semihosting at translate time
>   target/arm: handle A-profile T32 semihosting at translate time
>   target/arm: handle A-profile A32 semihosting at translate time

On closer testing, this patch breaks the semihosting test suite:

$ /home/petmay01/linaro/qemu-from-laptop/qemu/build/arm-clang//arm-linux-user/qemu-arm
 usertest-a32
hello world via semi_write0
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Segmentation fault (core dumped)

so I'm unqueueing the first 4 patches (but have kept the
misc unrelated other fixes).

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 0/9] arm semih-hosting cleanups and other misc cleanups

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> On Wed, 28 Aug 2019 at 18:08, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> Hi Peter,
>>
>> Here are the ARM semi-hosting cleanup patches and a small selection of
>> miscellaneous TCG clean-ups. If your happy taking them all through
>> your tree please do otherwise I'll poke Richard. I'm just trying to
>> reduce the delta for my next iteration of the plugin series.
>>
>> The following patches need review
>>    04 - target arm remove run time semihosting checks
>>    05 - includes remove stale smp max _cpus externs
>>
>> The first is the result of review comments, moving CONFIG_TCG ifdefs
>> around and the second is pretty trivial.
>>
>> Alex Bennée (7):
>>   target/arm: handle M-profile semihosting at translate time
>>   target/arm: handle A-profile T32 semihosting at translate time
>>   target/arm: handle A-profile A32 semihosting at translate time
>
> On closer testing, this patch breaks the semihosting test suite:
>
> $ /home/petmay01/linaro/qemu-from-laptop/qemu/build/arm-clang//arm-linux-user/qemu-arm
>  usertest-a32
> hello world via semi_write0
> qemu: uncaught target signal 11 (Segmentation fault) - core dumped
> Segmentation fault (core dumped)

That must of broken on re-base, I'll re-spin and fix.

>
> so I'm unqueueing the first 4 patches (but have kept the
> misc unrelated other fixes).
>
> thanks
> -- PMM


--
Alex Bennée