* [PATCH 1/4] drm/i915: parameterize south hpd macros
@ 2019-08-29 21:15 José Roberto de Souza
2019-08-29 21:15 ` [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling José Roberto de Souza
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-08-29 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
South, follow the north.
Instead of defining separate macros for each port, make them take port
as parameter as done for TC ports and for north engine. This will allow
us to easily extend this as needed.
tgp_ddi_port_hotplug_long_detect() is also removed as after the EHL
introduction the tgp variant is an exact copy of icp.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 22 ++++----------------
drivers/gpu/drm/i915/i915_reg.h | 36 +++++++++++----------------------
2 files changed, 16 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3f1b6ee157ba..084e322ec15b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1401,11 +1401,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_A:
- return val & ICP_DDIA_HPD_LONG_DETECT;
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
case HPD_PORT_B:
- return val & ICP_DDIB_HPD_LONG_DETECT;
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
case HPD_PORT_C:
- return val & TGP_DDIC_HPD_LONG_DETECT;
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
default:
return false;
}
@@ -1427,20 +1427,6 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
-static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
-{
- switch (pin) {
- case HPD_PORT_A:
- return val & ICP_DDIA_HPD_LONG_DETECT;
- case HPD_PORT_B:
- return val & ICP_DDIB_HPD_LONG_DETECT;
- case HPD_PORT_C:
- return val & TGP_DDIC_HPD_LONG_DETECT;
- default:
- return false;
- }
-}
-
static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -2318,7 +2304,7 @@ static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger,
dig_hotplug_reg, hpd_tgp,
- tgp_ddi_port_hotplug_long_detect);
+ icp_ddi_port_hotplug_long_detect);
}
if (tc_hotplug_trigger) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..a3f87115da0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7928,26 +7928,13 @@ enum {
* SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
*/
-#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
-#define TGP_DDIC_HPD_ENABLE (1 << 11)
-#define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
-#define TGP_DDIC_HPD_NO_DETECT (0 << 8)
-#define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
-#define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
-#define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
-#define ICP_DDIB_HPD_ENABLE (1 << 7)
-#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
-#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
-#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
-#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
-#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
-#define ICP_DDIA_HPD_ENABLE (1 << 3)
-#define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
-#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
-#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
-#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
-#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
-#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
+#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
+#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port)))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port)))
#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
@@ -8058,14 +8045,15 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
- ICP_DDIA_HPD_ENABLE)
+#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
ICP_TC_HPD_ENABLE(PORT_TC3) | \
ICP_TC_HPD_ENABLE(PORT_TC2) | \
ICP_TC_HPD_ENABLE(PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
- ICP_DDI_HPD_ENABLE_MASK)
+#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
ICP_TC_HPD_ENABLE(PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
--
2.23.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
@ 2019-08-29 21:15 ` José Roberto de Souza
2019-08-29 23:05 ` Matt Roper
2019-08-29 21:15 ` [PATCH 3/4] drm/i915: parameterize SDE hotplug registers José Roberto de Souza
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-08-29 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
The differences are only on the pins, trigger and long_detect function.
The MCC handling is already partially merged, so merge TGP as well.
Remove the pins argument from icp_irq_handler() so we have all the
differences between the 3 set in a common if ladder.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 65 ++++++++-------------------------
1 file changed, 16 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 084e322ec15b..5f590987dcd5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2243,19 +2243,27 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
cpt_serr_int_handler(dev_priv);
}
-static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
- const u32 *pins)
+static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
- u32 ddi_hotplug_trigger;
- u32 tc_hotplug_trigger;
+ u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
+ bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+ const u32 *pins;
- if (HAS_PCH_MCC(dev_priv)) {
+ if (HAS_PCH_TGP(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
+ tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
+ pins = hpd_tgp;
+ } else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
tc_hotplug_trigger = 0;
+ pins = hpd_mcc;
} else {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+ tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
+ pins = hpd_icp;
}
if (ddi_hotplug_trigger) {
@@ -2279,44 +2287,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
tc_hotplug_trigger,
dig_hotplug_reg, pins,
- icp_tc_port_hotplug_long_detect);
- }
-
- if (pin_mask)
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
-
- if (pch_iir & SDE_GMBUS_ICP)
- gmbus_irq_handler(dev_priv);
-}
-
-static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
-{
- u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
- u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
- u32 pin_mask = 0, long_mask = 0;
-
- if (ddi_hotplug_trigger) {
- u32 dig_hotplug_reg;
-
- dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
- I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
-
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- ddi_hotplug_trigger,
- dig_hotplug_reg, hpd_tgp,
- icp_ddi_port_hotplug_long_detect);
- }
-
- if (tc_hotplug_trigger) {
- u32 dig_hotplug_reg;
-
- dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
- I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
-
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- tc_hotplug_trigger,
- dig_hotplug_reg, hpd_tgp,
- tgp_tc_port_hotplug_long_detect);
+ tc_port_hotplug_long_detect);
}
if (pin_mask)
@@ -2767,12 +2738,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
I915_WRITE(SDEIIR, iir);
ret = IRQ_HANDLED;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
- tgp_irq_handler(dev_priv, iir);
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
- icp_irq_handler(dev_priv, iir, hpd_mcc);
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_irq_handler(dev_priv, iir, hpd_icp);
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_handler(dev_priv, iir);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
spt_irq_handler(dev_priv, iir);
else
--
2.23.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] drm/i915: parameterize SDE hotplug registers
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
2019-08-29 21:15 ` [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling José Roberto de Souza
@ 2019-08-29 21:15 ` José Roberto de Souza
2019-08-29 23:08 ` Matt Roper
2019-08-29 21:15 ` [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup José Roberto de Souza
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-08-29 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Ice Lake, Tiger Lake and Elkhart Lake all have different port
configurations and all of them can be parameterized the same way to form
the SDE hotplug bitmask. Avoid making them a special case an just use
the parameterized macros.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++-----------------
drivers/gpu/drm/i915/i915_reg.h | 35 ++++++++++++++------------------
2 files changed, 33 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5f590987dcd5..541382832126 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -149,30 +149,30 @@ static const u32 hpd_gen12[HPD_NUM_PINS] = {
};
static const u32 hpd_icp[HPD_NUM_PINS] = {
- [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
- [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
- [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
- [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
- [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
- [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+ [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
+ [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
+ [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
+ [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
};
static const u32 hpd_mcc[HPD_NUM_PINS] = {
- [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
- [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
- [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+ [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
};
static const u32 hpd_tgp[HPD_NUM_PINS] = {
- [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
- [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
- [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
- [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
- [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
- [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
- [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
- [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
- [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+ [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
+ [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
+ [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
+ [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
+ [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
+ [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a3f87115da0a..2ba25c18389b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7839,29 +7839,24 @@ enum {
SDE_FDI_RXA_CPT)
/* south display engine interrupt: ICP/TGP */
-#define SDE_TC6_HOTPLUG_TGP (1 << 29)
-#define SDE_TC5_HOTPLUG_TGP (1 << 28)
-#define SDE_TC4_HOTPLUG_ICP (1 << 27)
-#define SDE_TC3_HOTPLUG_ICP (1 << 26)
-#define SDE_TC2_HOTPLUG_ICP (1 << 25)
-#define SDE_TC1_HOTPLUG_ICP (1 << 24)
#define SDE_GMBUS_ICP (1 << 23)
-#define SDE_DDIC_HOTPLUG_TGP (1 << 18)
-#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
-#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
- SDE_DDIA_HOTPLUG_ICP)
-#define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
- SDE_TC3_HOTPLUG_ICP | \
- SDE_TC2_HOTPLUG_ICP | \
- SDE_TC1_HOTPLUG_ICP)
-#define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
- SDE_DDI_MASK_ICP)
-#define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
- SDE_TC5_HOTPLUG_TGP | \
- SDE_TC_MASK_ICP)
+#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(PORT_TC1))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
--
2.23.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
2019-08-29 21:15 ` [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling José Roberto de Souza
2019-08-29 21:15 ` [PATCH 3/4] drm/i915: parameterize SDE hotplug registers José Roberto de Souza
@ 2019-08-29 21:15 ` José Roberto de Souza
2019-08-29 23:15 ` Matt Roper
2019-08-29 22:47 ` [PATCH 1/4] drm/i915: parameterize south hpd macros Matt Roper
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-08-29 21:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Use a single function to setup the SDE irq and make MCC, ICP and TGP use
it, just like was done for the irq handler.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++-------------------
1 file changed, 21 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 541382832126..135c9ee55e07 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3385,42 +3385,31 @@ static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
}
}
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
+ u32 sde_ddi_mask, u32 sde_tc_mask,
+ u32 ddi_enable_mask, u32 tc_enable_mask,
+ const u32 *pins)
{
u32 hotplug_irqs, enabled_irqs;
- hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
+ hotplug_irqs = sde_ddi_mask | sde_tc_mask;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, pins);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
- ICP_TC_HPD_ENABLE_MASK);
+ icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
}
+/*
+ * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
+ * equivalent of SDE.
+ */
static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
- u32 hotplug_irqs, enabled_irqs;
-
- hotplug_irqs = SDE_DDI_MASK_TGP;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_mcc);
-
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
-
- icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
-}
-
-static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
- u32 hotplug_irqs, enabled_irqs;
-
- hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
-
- ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
-
- icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
- TGP_TC_HPD_ENABLE_MASK);
+ icp_hpd_irq_setup(dev_priv,
+ SDE_DDI_MASK_TGP, 0,
+ TGP_DDI_HPD_ENABLE_MASK, 0,
+ hpd_mcc);
}
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3460,9 +3449,13 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
gen11_hpd_detection_setup(dev_priv);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
- tgp_hpd_irq_setup(dev_priv);
+ icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP,
+ TGP_DDI_HPD_ENABLE_MASK,
+ TGP_TC_HPD_ENABLE_MASK, hpd_tgp);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_hpd_irq_setup(dev_priv);
+ icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP,
+ ICP_DDI_HPD_ENABLE_MASK,
+ ICP_TC_HPD_ENABLE_MASK, hpd_icp);
}
static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -4340,7 +4333,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
if (HAS_PCH_MCC(dev_priv))
- /* EHL doesn't need most of gen11_hpd_irq_setup */
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
else if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/4] drm/i915: parameterize south hpd macros
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
` (2 preceding siblings ...)
2019-08-29 21:15 ` [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup José Roberto de Souza
@ 2019-08-29 22:47 ` Matt Roper
2019-08-29 22:54 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2019-08-30 17:33 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-08-29 22:47 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Thu, Aug 29, 2019 at 02:15:23PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> South, follow the north.
>
> Instead of defining separate macros for each port, make them take port
> as parameter as done for TC ports and for north engine. This will allow
> us to easily extend this as needed.
>
> tgp_ddi_port_hotplug_long_detect() is also removed as after the EHL
> introduction the tgp variant is an exact copy of icp.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 22 ++++----------------
> drivers/gpu/drm/i915/i915_reg.h | 36 +++++++++++----------------------
> 2 files changed, 16 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3f1b6ee157ba..084e322ec15b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1401,11 +1401,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_A:
> - return val & ICP_DDIA_HPD_LONG_DETECT;
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
> case HPD_PORT_B:
> - return val & ICP_DDIB_HPD_LONG_DETECT;
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
> case HPD_PORT_C:
> - return val & TGP_DDIC_HPD_LONG_DETECT;
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
> default:
> return false;
> }
> @@ -1427,20 +1427,6 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> }
> }
>
> -static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> -{
> - switch (pin) {
> - case HPD_PORT_A:
> - return val & ICP_DDIA_HPD_LONG_DETECT;
> - case HPD_PORT_B:
> - return val & ICP_DDIB_HPD_LONG_DETECT;
> - case HPD_PORT_C:
> - return val & TGP_DDIC_HPD_LONG_DETECT;
> - default:
> - return false;
> - }
> -}
> -
> static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> @@ -2318,7 +2304,7 @@ static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> ddi_hotplug_trigger,
> dig_hotplug_reg, hpd_tgp,
> - tgp_ddi_port_hotplug_long_detect);
> + icp_ddi_port_hotplug_long_detect);
> }
>
> if (tc_hotplug_trigger) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02e1ef10c47e..a3f87115da0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7928,26 +7928,13 @@ enum {
> * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> */
>
> -#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> -#define TGP_DDIC_HPD_ENABLE (1 << 11)
> -#define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
> -#define TGP_DDIC_HPD_NO_DETECT (0 << 8)
> -#define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
> -#define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
> -#define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
> -#define ICP_DDIB_HPD_ENABLE (1 << 7)
> -#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
> -#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
> -#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
> -#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
> -#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
> -#define ICP_DDIA_HPD_ENABLE (1 << 3)
> -#define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
> -#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
> -#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
> -#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
> -#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
> -#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
> +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> +#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port)))
> +#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port)))
> +#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port)))
> +#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port)))
> +#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port)))
> +#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port)))
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
> @@ -8058,14 +8045,15 @@ enum {
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> -#define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
> - ICP_DDIA_HPD_ENABLE)
> +#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
> ICP_TC_HPD_ENABLE(PORT_TC3) | \
> ICP_TC_HPD_ENABLE(PORT_TC2) | \
> ICP_TC_HPD_ENABLE(PORT_TC1))
> -#define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
> - ICP_DDI_HPD_ENABLE_MASK)
> +#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
> ICP_TC_HPD_ENABLE(PORT_TC5) | \
> ICP_TC_HPD_ENABLE_MASK)
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: parameterize south hpd macros
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
` (3 preceding siblings ...)
2019-08-29 22:47 ` [PATCH 1/4] drm/i915: parameterize south hpd macros Matt Roper
@ 2019-08-29 22:54 ` Patchwork
2019-08-30 17:33 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-29 22:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: parameterize south hpd macros
URL : https://patchwork.freedesktop.org/series/66023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6804 -> Patchwork_14228
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/
Changes
-------
No changes found
Participating hosts (51 -> 45)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6804 -> Patchwork_14228
CI-20190529: 20190529
CI_DRM_6804: 317d4ca664ab65fbe571e15c59a39a1bcf58acd1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5157: 73d8d3ffccb6f0340e13bf006f56e3658673f345 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14228: 2018e0347fe6c5bea48c05e040dc1286d8a692df @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2018e0347fe6 drm/i915: unify icp, tgp and mcc irq setup
34e79f193e24 drm/i915: parameterize SDE hotplug registers
b1c6ac23df0e drm/i915: unify icp, tgp and mcc irq handling
b8992ddc9a39 drm/i915: parameterize south hpd macros
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling
2019-08-29 21:15 ` [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling José Roberto de Souza
@ 2019-08-29 23:05 ` Matt Roper
2019-08-30 18:06 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2019-08-29 23:05 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Thu, Aug 29, 2019 at 02:15:24PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> The differences are only on the pins, trigger and long_detect function.
> The MCC handling is already partially merged, so merge TGP as well.
> Remove the pins argument from icp_irq_handler() so we have all the
> differences between the 3 set in a common if ladder.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Now that everything is parameterized would it be worth unifying the tc
long detect functions too? E.g., something like
if (HAS_PCH_TGP(dev_priv))
return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1 + pin - HPD_PORT_D);
else if (HAS_PCH_ICP(dev_priv))
return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1 + pin - HPD_PORT_C);
else
MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
Even if you decide to keep it as is, this patch is
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 65 ++++++++-------------------------
> 1 file changed, 16 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 084e322ec15b..5f590987dcd5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2243,19 +2243,27 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> cpt_serr_int_handler(dev_priv);
> }
>
> -static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
> - const u32 *pins)
> +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> - u32 ddi_hotplug_trigger;
> - u32 tc_hotplug_trigger;
> + u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> u32 pin_mask = 0, long_mask = 0;
> + bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> + const u32 *pins;
>
> - if (HAS_PCH_MCC(dev_priv)) {
> + if (HAS_PCH_TGP(dev_priv)) {
> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> + tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
> + pins = hpd_tgp;
> + } else if (HAS_PCH_MCC(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> tc_hotplug_trigger = 0;
> + pins = hpd_mcc;
> } else {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> + tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
> + pins = hpd_icp;
> }
>
> if (ddi_hotplug_trigger) {
> @@ -2279,44 +2287,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> tc_hotplug_trigger,
> dig_hotplug_reg, pins,
> - icp_tc_port_hotplug_long_detect);
> - }
> -
> - if (pin_mask)
> - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> -
> - if (pch_iir & SDE_GMBUS_ICP)
> - gmbus_irq_handler(dev_priv);
> -}
> -
> -static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> -{
> - u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> - u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> - u32 pin_mask = 0, long_mask = 0;
> -
> - if (ddi_hotplug_trigger) {
> - u32 dig_hotplug_reg;
> -
> - dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> - I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> -
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> - ddi_hotplug_trigger,
> - dig_hotplug_reg, hpd_tgp,
> - icp_ddi_port_hotplug_long_detect);
> - }
> -
> - if (tc_hotplug_trigger) {
> - u32 dig_hotplug_reg;
> -
> - dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> - I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> -
> - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> - tc_hotplug_trigger,
> - dig_hotplug_reg, hpd_tgp,
> - tgp_tc_port_hotplug_long_detect);
> + tc_port_hotplug_long_detect);
> }
>
> if (pin_mask)
> @@ -2767,12 +2738,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> I915_WRITE(SDEIIR, iir);
> ret = IRQ_HANDLED;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
> - tgp_irq_handler(dev_priv, iir);
> - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
> - icp_irq_handler(dev_priv, iir, hpd_mcc);
> - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - icp_irq_handler(dev_priv, iir, hpd_icp);
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_handler(dev_priv, iir);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> spt_irq_handler(dev_priv, iir);
> else
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] drm/i915: parameterize SDE hotplug registers
2019-08-29 21:15 ` [PATCH 3/4] drm/i915: parameterize SDE hotplug registers José Roberto de Souza
@ 2019-08-29 23:08 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-08-29 23:08 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Thu, Aug 29, 2019 at 02:15:25PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Ice Lake, Tiger Lake and Elkhart Lake all have different port
> configurations and all of them can be parameterized the same way to form
> the SDE hotplug bitmask. Avoid making them a special case an just use
> the parameterized macros.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++-----------------
> drivers/gpu/drm/i915/i915_reg.h | 35 ++++++++++++++------------------
> 2 files changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5f590987dcd5..541382832126 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -149,30 +149,30 @@ static const u32 hpd_gen12[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
> - [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> - [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> - [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
> - [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
> - [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
> - [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> + [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
> + [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
> };
>
> static const u32 hpd_mcc[HPD_NUM_PINS] = {
> - [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> - [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> - [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> };
>
> static const u32 hpd_tgp[HPD_NUM_PINS] = {
> - [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> - [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> - [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
> - [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
> - [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
> - [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
> - [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
> - [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
> - [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> + [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
> + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
> + [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
> + [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
> + [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
> + [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
> + [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> };
>
> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a3f87115da0a..2ba25c18389b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7839,29 +7839,24 @@ enum {
> SDE_FDI_RXA_CPT)
>
> /* south display engine interrupt: ICP/TGP */
> -#define SDE_TC6_HOTPLUG_TGP (1 << 29)
> -#define SDE_TC5_HOTPLUG_TGP (1 << 28)
> -#define SDE_TC4_HOTPLUG_ICP (1 << 27)
> -#define SDE_TC3_HOTPLUG_ICP (1 << 26)
> -#define SDE_TC2_HOTPLUG_ICP (1 << 25)
> -#define SDE_TC1_HOTPLUG_ICP (1 << 24)
> #define SDE_GMBUS_ICP (1 << 23)
> -#define SDE_DDIC_HOTPLUG_TGP (1 << 18)
> -#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
> -#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
> #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
> #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
> -#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
> - SDE_DDIA_HOTPLUG_ICP)
> -#define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
> - SDE_TC3_HOTPLUG_ICP | \
> - SDE_TC2_HOTPLUG_ICP | \
> - SDE_TC1_HOTPLUG_ICP)
> -#define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
> - SDE_DDI_MASK_ICP)
> -#define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
> - SDE_TC5_HOTPLUG_TGP | \
> - SDE_TC_MASK_ICP)
> +#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_A))
> +#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC1))
> +#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_A))
> +#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> + SDE_TC_HOTPLUG_ICP(PORT_TC1))
>
> #define SDEISR _MMIO(0xc4000)
> #define SDEIMR _MMIO(0xc4004)
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup
2019-08-29 21:15 ` [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup José Roberto de Souza
@ 2019-08-29 23:15 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-08-29 23:15 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Thu, Aug 29, 2019 at 02:15:26PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Use a single function to setup the SDE irq and make MCC, ICP and TGP use
> it, just like was done for the irq handler.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++-------------------
> 1 file changed, 21 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 541382832126..135c9ee55e07 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3385,42 +3385,31 @@ static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
> + u32 sde_ddi_mask, u32 sde_tc_mask,
> + u32 ddi_enable_mask, u32 tc_enable_mask,
> + const u32 *pins)
> {
> u32 hotplug_irqs, enabled_irqs;
>
> - hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
> + hotplug_irqs = sde_ddi_mask | sde_tc_mask;
> + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, pins);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
> - icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
> - ICP_TC_HPD_ENABLE_MASK);
> + icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
> }
>
> +/*
> + * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
> + * equivalent of SDE.
> + */
> static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> - u32 hotplug_irqs, enabled_irqs;
> -
> - hotplug_irqs = SDE_DDI_MASK_TGP;
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_mcc);
> -
> - ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> -
> - icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
> -}
> -
> -static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> -{
> - u32 hotplug_irqs, enabled_irqs;
> -
> - hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
> - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
> -
> - ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> -
> - icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
> - TGP_TC_HPD_ENABLE_MASK);
> + icp_hpd_irq_setup(dev_priv,
> + SDE_DDI_MASK_TGP, 0,
> + TGP_DDI_HPD_ENABLE_MASK, 0,
> + hpd_mcc);
> }
>
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> @@ -3460,9 +3449,13 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> gen11_hpd_detection_setup(dev_priv);
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
> - tgp_hpd_irq_setup(dev_priv);
> + icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP,
> + TGP_DDI_HPD_ENABLE_MASK,
> + TGP_TC_HPD_ENABLE_MASK, hpd_tgp);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - icp_hpd_irq_setup(dev_priv);
> + icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP,
> + ICP_DDI_HPD_ENABLE_MASK,
> + ICP_TC_HPD_ENABLE_MASK, hpd_icp);
> }
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> @@ -4340,7 +4333,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> } else {
> if (HAS_PCH_MCC(dev_priv))
> - /* EHL doesn't need most of gen11_hpd_irq_setup */
> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
> else if (INTEL_GEN(dev_priv) >= 11)
> dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: parameterize south hpd macros
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
` (4 preceding siblings ...)
2019-08-29 22:54 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
@ 2019-08-30 17:33 ` Patchwork
2019-08-30 18:07 ` Souza, Jose
5 siblings, 1 reply; 12+ messages in thread
From: Patchwork @ 2019-08-30 17:33 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: parameterize south hpd macros
URL : https://patchwork.freedesktop.org/series/66023/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6804_full -> Patchwork_14228_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14228_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14228_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14228_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_persistent_relocs@forked:
- shard-skl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl9/igt@gem_persistent_relocs@forked.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl8/igt@gem_persistent_relocs@forked.html
Known issues
------------
Here are the changes found in Patchwork_14228_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-internal-10ms:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([fdo#106107])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl7/igt@gem_eio@in-flight-internal-10ms.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl5/igt@gem_eio@in-flight-internal-10ms.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110854])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb4/igt@gem_exec_balancer@smoke.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb8/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +18 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_psr@psr2_suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl6/igt@kms_setmode@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-skl: [DMESG-WARN][27] ([fdo#106107]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl2/igt@gem_eio@in-flight-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl9/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [SKIP][29] ([fdo#109276]) -> [PASS][30] +14 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][31] ([fdo#111325]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [DMESG-WARN][33] ([fdo#108686]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-glk8/igt@gem_tiled_swapping@non-threaded.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-glk5/igt@gem_tiled_swapping@non-threaded.html
- shard-hsw: [DMESG-WARN][35] ([fdo#108686]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw2/igt@gem_tiled_swapping@non-threaded.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][37] ([fdo#109507]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl2/igt@kms_flip@flip-vs-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl2/igt@kms_flip@flip-vs-suspend.html
- shard-kbl: [INCOMPLETE][39] ([fdo#103665]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-kbl7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][41] ([fdo#108566]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-ts-check:
- shard-skl: [FAIL][43] ([fdo#100368]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl5/igt@kms_flip@plain-flip-ts-check.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl8/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][49] ([fdo#103166]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@blocking:
- shard-skl: [FAIL][53] ([fdo#110728]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl8/igt@perf@blocking.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl2/igt@perf@blocking.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][57] ([fdo#109276]) -> [FAIL][58] ([fdo#111330])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@kms_setmode@basic:
- shard-hsw: [INCOMPLETE][59] ([fdo#103540]) -> [FAIL][60] ([fdo#99912])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw1/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw4/igt@kms_setmode@basic.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6804 -> Patchwork_14228
CI-20190529: 20190529
CI_DRM_6804: 317d4ca664ab65fbe571e15c59a39a1bcf58acd1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5157: 73d8d3ffccb6f0340e13bf006f56e3658673f345 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14228: 2018e0347fe6c5bea48c05e040dc1286d8a692df @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling
2019-08-29 23:05 ` Matt Roper
@ 2019-08-30 18:06 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-08-30 18:06 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx, De Marchi, Lucas
On Thu, 2019-08-29 at 16:05 -0700, Matt Roper wrote:
> On Thu, Aug 29, 2019 at 02:15:24PM -0700, José Roberto de Souza
> wrote:
> > From: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > The differences are only on the pins, trigger and long_detect
> > function.
> > The MCC handling is already partially merged, so merge TGP as well.
> > Remove the pins argument from icp_irq_handler() so we have all the
> > differences between the 3 set in a common if ladder.
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Now that everything is parameterized would it be worth unifying the
> tc
> long detect functions too? E.g., something like
>
> if (HAS_PCH_TGP(dev_priv))
> return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1 + pin -
> HPD_PORT_D);
> else if (HAS_PCH_ICP(dev_priv))
> return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1 + pin -
> HPD_PORT_C);
> else
> MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
>
> Even if you decide to keep it as is, this patch is
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
We can do it on top but I personally don't like keep this much detail
of register in .c files.
Thanks for the reviews.
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 65 ++++++++---------------------
> > ----
> > 1 file changed, 16 insertions(+), 49 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 084e322ec15b..5f590987dcd5 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2243,19 +2243,27 @@ static void cpt_irq_handler(struct
> > drm_i915_private *dev_priv, u32 pch_iir)
> > cpt_serr_int_handler(dev_priv);
> > }
> >
> > -static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir,
> > - const u32 *pins)
> > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > {
> > - u32 ddi_hotplug_trigger;
> > - u32 tc_hotplug_trigger;
> > + u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> > u32 pin_mask = 0, long_mask = 0;
> > + bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> > + const u32 *pins;
> >
> > - if (HAS_PCH_MCC(dev_priv)) {
> > + if (HAS_PCH_TGP(dev_priv)) {
> > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> > + tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> > + tc_port_hotplug_long_detect =
> > tgp_tc_port_hotplug_long_detect;
> > + pins = hpd_tgp;
> > + } else if (HAS_PCH_MCC(dev_priv)) {
> > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> > tc_hotplug_trigger = 0;
> > + pins = hpd_mcc;
> > } else {
> > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> > + tc_port_hotplug_long_detect =
> > icp_tc_port_hotplug_long_detect;
> > + pins = hpd_icp;
> > }
> >
> > if (ddi_hotplug_trigger) {
> > @@ -2279,44 +2287,7 @@ static void icp_irq_handler(struct
> > drm_i915_private *dev_priv, u32 pch_iir,
> > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > tc_hotplug_trigger,
> > dig_hotplug_reg, pins,
> > - icp_tc_port_hotplug_long_detect);
> > - }
> > -
> > - if (pin_mask)
> > - intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> > -
> > - if (pch_iir & SDE_GMBUS_ICP)
> > - gmbus_irq_handler(dev_priv);
> > -}
> > -
> > -static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > -{
> > - u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> > - u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> > - u32 pin_mask = 0, long_mask = 0;
> > -
> > - if (ddi_hotplug_trigger) {
> > - u32 dig_hotplug_reg;
> > -
> > - dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > - I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > -
> > - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > - ddi_hotplug_trigger,
> > - dig_hotplug_reg, hpd_tgp,
> > - icp_ddi_port_hotplug_long_detect);
> > - }
> > -
> > - if (tc_hotplug_trigger) {
> > - u32 dig_hotplug_reg;
> > -
> > - dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > - I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > -
> > - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> > - tc_hotplug_trigger,
> > - dig_hotplug_reg, hpd_tgp,
> > - tgp_tc_port_hotplug_long_detect);
> > + tc_port_hotplug_long_detect);
> > }
> >
> > if (pin_mask)
> > @@ -2767,12 +2738,8 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > I915_WRITE(SDEIIR, iir);
> > ret = IRQ_HANDLED;
> >
> > - if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
> > - tgp_irq_handler(dev_priv, iir);
> > - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
> > - icp_irq_handler(dev_priv, iir,
> > hpd_mcc);
> > - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > - icp_irq_handler(dev_priv, iir,
> > hpd_icp);
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_handler(dev_priv, iir);
> > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> > spt_irq_handler(dev_priv, iir);
> > else
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: parameterize south hpd macros
2019-08-30 17:33 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-08-30 18:07 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-08-30 18:07 UTC (permalink / raw)
To: intel-gfx
On Fri, 2019-08-30 at 17:33 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/4] drm/i915: parameterize south hpd
> macros
> URL : https://patchwork.freedesktop.org/series/66023/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6804_full -> Patchwork_14228_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14228_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the
> changes
> introduced in Patchwork_14228_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false
> positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14228_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-hsw: [PASS][1] -> [FAIL][2]
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
>
> * igt@gem_persistent_relocs@forked:
> - shard-skl: [PASS][3] -> [DMESG-WARN][4]
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl9/igt@gem_persistent_relocs@forked.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl8/igt@gem_persistent_relocs@forked.html
>
>
This patches are changing gen11 and hpd stuff so this is not related at
all.
Just pushed the patches to dinq, thanks again for the reviews Matt.
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_14228_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_eio@in-flight-internal-10ms:
> - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([fdo#106107])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl7/igt@gem_eio@in-flight-internal-10ms.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl5/igt@gem_eio@in-flight-internal-10ms.html
>
> * igt@gem_exec_async@concurrent-writes-bsd:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +5
> similar issues
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110854])
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb4/igt@gem_exec_balancer@smoke.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb8/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@preempt-queue-bsd1:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +18
> similar issues
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
> - shard-apl: [PASS][13] -> [INCOMPLETE][14]
> ([fdo#103927])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [PASS][15] -> [DMESG-WARN][16]
> ([fdo#108566]) +5 similar issues
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363])
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
> - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166])
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_psr@psr2_suspend:
> - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1
> similar issue
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_psr@psr2_suspend.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@kms_psr@psr2_suspend.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl6/igt@kms_setmode@basic.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl8/igt@kms_setmode@basic.html
>
>
> #### Possible fixes ####
>
> * igt@gem_eio@in-flight-suspend:
> - shard-skl: [DMESG-WARN][27] ([fdo#106107]) ->
> [PASS][28]
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl2/igt@gem_eio@in-flight-suspend.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl9/igt@gem_eio@in-flight-suspend.html
>
> * igt@gem_exec_schedule@out-order-bsd2:
> - shard-iclb: [SKIP][29] ([fdo#109276]) -> [PASS][30] +14
> similar issues
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
>
> * igt@gem_exec_schedule@wide-bsd:
> - shard-iclb: [SKIP][31] ([fdo#111325]) -> [PASS][32] +1
> similar issue
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-glk: [DMESG-WARN][33] ([fdo#108686]) ->
> [PASS][34]
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-glk8/igt@gem_tiled_swapping@non-threaded.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-glk5/igt@gem_tiled_swapping@non-threaded.html
> - shard-hsw: [DMESG-WARN][35] ([fdo#108686]) ->
> [PASS][36]
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw2/igt@gem_tiled_swapping@non-threaded.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
>
> * igt@kms_flip@flip-vs-suspend:
> - shard-skl: [INCOMPLETE][37] ([fdo#109507]) ->
> [PASS][38]
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl2/igt@kms_flip@flip-vs-suspend.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl2/igt@kms_flip@flip-vs-suspend.html
> - shard-kbl: [INCOMPLETE][39] ([fdo#103665]) ->
> [PASS][40]
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-kbl7/igt@kms_flip@flip-vs-suspend.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-apl: [DMESG-WARN][41] ([fdo#108566]) ->
> [PASS][42] +1 similar issue
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip@plain-flip-ts-check:
> - shard-skl: [FAIL][43] ([fdo#100368]) -> [PASS][44]
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl5/igt@kms_flip@plain-flip-ts-check.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl8/igt@kms_flip@plain-flip-ts-check.html
>
> * igt@kms
> _frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
> - shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +4
> similar issues
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>
> * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
> - shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48]
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-iclb: [FAIL][49] ([fdo#103166]) -> [PASS][50]
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
>
> * igt@kms_psr@psr2_no_drrs:
> - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1
> similar issue
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
>
> * igt@perf@blocking:
> - shard-skl: [FAIL][53] ([fdo#110728]) -> [PASS][54] +1
> similar issue
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-skl8/igt@perf@blocking.html
> [54]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-skl2/igt@perf@blocking.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [SKIP][55] ([fdo#109276]) -> [FAIL][56]
> ([fdo#111329])
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [56]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@gem_mocs_settings@mocs-isolation-bsd2:
> - shard-iclb: [SKIP][57] ([fdo#109276]) -> [FAIL][58]
> ([fdo#111330])
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> [58]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-iclb1/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>
> * igt@kms_setmode@basic:
> - shard-hsw: [INCOMPLETE][59] ([fdo#103540]) ->
> [FAIL][60] ([fdo#99912])
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6804/shard-hsw1/igt@kms_setmode@basic.html
> [60]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/shard-hsw4/igt@kms_setmode@basic.html
>
>
> [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
> [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6804 -> Patchwork_14228
>
> CI-20190529: 20190529
> CI_DRM_6804: 317d4ca664ab65fbe571e15c59a39a1bcf58acd1 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5157: 73d8d3ffccb6f0340e13bf006f56e3658673f345 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14228: 2018e0347fe6c5bea48c05e040dc1286d8a692df @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14228/
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-08-30 18:07 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-29 21:15 [PATCH 1/4] drm/i915: parameterize south hpd macros José Roberto de Souza
2019-08-29 21:15 ` [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling José Roberto de Souza
2019-08-29 23:05 ` Matt Roper
2019-08-30 18:06 ` Souza, Jose
2019-08-29 21:15 ` [PATCH 3/4] drm/i915: parameterize SDE hotplug registers José Roberto de Souza
2019-08-29 23:08 ` Matt Roper
2019-08-29 21:15 ` [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup José Roberto de Souza
2019-08-29 23:15 ` Matt Roper
2019-08-29 22:47 ` [PATCH 1/4] drm/i915: parameterize south hpd macros Matt Roper
2019-08-29 22:54 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2019-08-30 17:33 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-08-30 18:07 ` Souza, Jose
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