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* [PATCH] drm/mcde: Fix DSI transfers
@ 2019-08-30 13:06 ` Linus Walleij
  0 siblings, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2019-08-30 13:06 UTC (permalink / raw)
  To: dri-devel, Maarten Lankhorst, Maxime Ripard, Sean Paul
  Cc: Linus Walleij, Stephan Gerhold, linux-arm-kernel

There were bugs in the DSI transfer (read and write) function
as it was only tested with displays ever needing a single byte
to be written. Fixed it up and tested so we can now write
messages of up to 16 bytes and read up to 4 bytes from the
display.

Tested with a Sony ACX424AKP display: this display now self-
identifies and can control backlight in command mode.

Cc: Stephan Gerhold <stephan@gerhold.net>
Fixes: 5fc537bfd000 ("drm/mcde: Add new driver for ST-Ericsson MCDE")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/gpu/drm/mcde/mcde_dsi.c | 70 ++++++++++++++++++++++-----------
 1 file changed, 47 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c
index 07f7090d08b3..ad76a36e7bc1 100644
--- a/drivers/gpu/drm/mcde/mcde_dsi.c
+++ b/drivers/gpu/drm/mcde/mcde_dsi.c
@@ -178,22 +178,26 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	const u32 loop_delay_us = 10; /* us */
 	const u8 *tx = msg->tx_buf;
 	u32 loop_counter;
-	size_t txlen;
+	size_t txlen = msg->tx_len;
+	size_t rxlen = msg->rx_len;
 	u32 val;
 	int ret;
 	int i;
 
-	txlen = msg->tx_len;
-	if (txlen > 12) {
+	if (txlen > 16) {
 		dev_err(d->dev,
-			"dunno how to write more than 12 bytes yet\n");
+			"dunno how to write more than 16 bytes yet\n");
+		return -EIO;
+	}
+	if (rxlen > 4) {
+		dev_err(d->dev,
+			"dunno how to read more than 4 bytes yet\n");
 		return -EIO;
 	}
 
 	dev_dbg(d->dev,
-		"message to channel %d, %zd bytes",
-		msg->channel,
-		txlen);
+		"message to channel %d, write %zd bytes read %zd bytes\n",
+		msg->channel, txlen, rxlen);
 
 	/* Command "nature" */
 	if (MCDE_DSI_HOST_IS_READ(msg->type))
@@ -210,9 +214,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	if (mipi_dsi_packet_format_is_long(msg->type))
 		val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
 	val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
-	/* Add one to the length for the MIPI DCS command */
-	val |= txlen
-		<< DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
+	val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
 	val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
 	val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
 	writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
@@ -249,17 +251,36 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	writel(1, d->regs + DSI_DIRECT_CMD_SEND);
 
 	loop_counter = 1000 * 1000 / loop_delay_us;
-	while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
-		 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
-	       && --loop_counter)
-		usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
-
-	if (!loop_counter) {
-		dev_err(d->dev, "DSI write timeout!\n");
-		return -ETIME;
+	if (MCDE_DSI_HOST_IS_READ(msg->type)) {
+		/* Read command */
+		while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
+			 (DSI_DIRECT_CMD_STS_READ_COMPLETED |
+			  DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
+		       && --loop_counter)
+			usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
+		if (!loop_counter) {
+			dev_err(d->dev, "DSI write timeout!\n");
+			return -ETIME;
+		}
+	} else {
+		/* Writing only */
+		while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
+			 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
+		       && --loop_counter)
+			usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
+
+		if (!loop_counter) {
+			dev_err(d->dev, "DSI write timeout!\n");
+			return -ETIME;
+		}
 	}
 
 	val = readl(d->regs + DSI_DIRECT_CMD_STS);
+	if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
+		dev_err(d->dev, "read completed with error\n");
+		writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
+		return -EIO;
+	}
 	if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
 		val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
 		dev_err(d->dev, "error during transmission: %04x\n",
@@ -269,10 +290,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 
 	if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
 		/* Return number of bytes written */
-		if (mipi_dsi_packet_format_is_long(msg->type))
-			ret = 4 + txlen;
-		else
-			ret = 4;
+		ret = txlen;
 	} else {
 		/* OK this is a read command, get the response */
 		u32 rdsz;
@@ -282,7 +300,13 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 		rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
 		rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
 		rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
-		for (i = 0; i < 4 && i < rdsz; i++)
+		if (rdsz < rxlen) {
+			dev_err(d->dev, "read error, requested %d got %d\n",
+				msg->rx_len, rdsz);
+			return -EIO;
+		}
+		/* FIXME: read more than 4 bytes */
+		for (i = 0; i < 4 && i < rxlen; i++)
 			rx[i] = (rddat >> (i * 8)) & 0xff;
 		ret = rdsz;
 	}
-- 
2.21.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH] drm/mcde: Fix DSI transfers
@ 2019-08-30 13:06 ` Linus Walleij
  0 siblings, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2019-08-30 13:06 UTC (permalink / raw)
  To: dri-devel, Maarten Lankhorst, Maxime Ripard, Sean Paul
  Cc: Stephan Gerhold, linux-arm-kernel

There were bugs in the DSI transfer (read and write) function
as it was only tested with displays ever needing a single byte
to be written. Fixed it up and tested so we can now write
messages of up to 16 bytes and read up to 4 bytes from the
display.

Tested with a Sony ACX424AKP display: this display now self-
identifies and can control backlight in command mode.

Cc: Stephan Gerhold <stephan@gerhold.net>
Fixes: 5fc537bfd000 ("drm/mcde: Add new driver for ST-Ericsson MCDE")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/gpu/drm/mcde/mcde_dsi.c | 70 ++++++++++++++++++++++-----------
 1 file changed, 47 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c
index 07f7090d08b3..ad76a36e7bc1 100644
--- a/drivers/gpu/drm/mcde/mcde_dsi.c
+++ b/drivers/gpu/drm/mcde/mcde_dsi.c
@@ -178,22 +178,26 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	const u32 loop_delay_us = 10; /* us */
 	const u8 *tx = msg->tx_buf;
 	u32 loop_counter;
-	size_t txlen;
+	size_t txlen = msg->tx_len;
+	size_t rxlen = msg->rx_len;
 	u32 val;
 	int ret;
 	int i;
 
-	txlen = msg->tx_len;
-	if (txlen > 12) {
+	if (txlen > 16) {
 		dev_err(d->dev,
-			"dunno how to write more than 12 bytes yet\n");
+			"dunno how to write more than 16 bytes yet\n");
+		return -EIO;
+	}
+	if (rxlen > 4) {
+		dev_err(d->dev,
+			"dunno how to read more than 4 bytes yet\n");
 		return -EIO;
 	}
 
 	dev_dbg(d->dev,
-		"message to channel %d, %zd bytes",
-		msg->channel,
-		txlen);
+		"message to channel %d, write %zd bytes read %zd bytes\n",
+		msg->channel, txlen, rxlen);
 
 	/* Command "nature" */
 	if (MCDE_DSI_HOST_IS_READ(msg->type))
@@ -210,9 +214,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	if (mipi_dsi_packet_format_is_long(msg->type))
 		val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
 	val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
-	/* Add one to the length for the MIPI DCS command */
-	val |= txlen
-		<< DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
+	val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
 	val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
 	val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
 	writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
@@ -249,17 +251,36 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 	writel(1, d->regs + DSI_DIRECT_CMD_SEND);
 
 	loop_counter = 1000 * 1000 / loop_delay_us;
-	while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
-		 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
-	       && --loop_counter)
-		usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
-
-	if (!loop_counter) {
-		dev_err(d->dev, "DSI write timeout!\n");
-		return -ETIME;
+	if (MCDE_DSI_HOST_IS_READ(msg->type)) {
+		/* Read command */
+		while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
+			 (DSI_DIRECT_CMD_STS_READ_COMPLETED |
+			  DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
+		       && --loop_counter)
+			usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
+		if (!loop_counter) {
+			dev_err(d->dev, "DSI write timeout!\n");
+			return -ETIME;
+		}
+	} else {
+		/* Writing only */
+		while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
+			 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
+		       && --loop_counter)
+			usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
+
+		if (!loop_counter) {
+			dev_err(d->dev, "DSI write timeout!\n");
+			return -ETIME;
+		}
 	}
 
 	val = readl(d->regs + DSI_DIRECT_CMD_STS);
+	if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
+		dev_err(d->dev, "read completed with error\n");
+		writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
+		return -EIO;
+	}
 	if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
 		val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
 		dev_err(d->dev, "error during transmission: %04x\n",
@@ -269,10 +290,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 
 	if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
 		/* Return number of bytes written */
-		if (mipi_dsi_packet_format_is_long(msg->type))
-			ret = 4 + txlen;
-		else
-			ret = 4;
+		ret = txlen;
 	} else {
 		/* OK this is a read command, get the response */
 		u32 rdsz;
@@ -282,7 +300,13 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 		rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
 		rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
 		rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
-		for (i = 0; i < 4 && i < rdsz; i++)
+		if (rdsz < rxlen) {
+			dev_err(d->dev, "read error, requested %d got %d\n",
+				msg->rx_len, rdsz);
+			return -EIO;
+		}
+		/* FIXME: read more than 4 bytes */
+		for (i = 0; i < 4 && i < rxlen; i++)
 			rx[i] = (rddat >> (i * 8)) & 0xff;
 		ret = rdsz;
 	}
-- 
2.21.0

_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] drm/mcde: Fix DSI transfers
  2019-08-30 13:06 ` Linus Walleij
  (?)
@ 2019-08-30 22:38 ` kbuild test robot
  -1 siblings, 0 replies; 3+ messages in thread
From: kbuild test robot @ 2019-08-30 22:38 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Stephan Gerhold, Maxime Ripard, Maarten Lankhorst, dri-devel,
	kbuild-all, Sean Paul, linux-arm-kernel

[-- Attachment #1: Type: text/plain, Size: 7093 bytes --]

Hi Linus,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Linus-Walleij/drm-mcde-Fix-DSI-transfers/20190831-051121
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   In file included from include/linux/platform_device.h:13:0,
                    from drivers/gpu/drm/mcde/mcde_dsi.c:9:
   drivers/gpu/drm/mcde/mcde_dsi.c: In function 'mcde_dsi_host_transfer':
>> drivers/gpu/drm/mcde/mcde_dsi.c:304:20: warning: format '%d' expects argument of type 'int', but argument 3 has type 'size_t {aka const long unsigned int}' [-Wformat=]
       dev_err(d->dev, "read error, requested %d got %d\n",
                       ^
   include/linux/device.h:1416:22: note: in definition of macro 'dev_fmt'
    #define dev_fmt(fmt) fmt
                         ^~~
>> drivers/gpu/drm/mcde/mcde_dsi.c:304:4: note: in expansion of macro 'dev_err'
       dev_err(d->dev, "read error, requested %d got %d\n",
       ^~~~~~~

vim +304 drivers/gpu/drm/mcde/mcde_dsi.c

   167	
   168	#define MCDE_DSI_HOST_IS_READ(type)			    \
   169		((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
   170		 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
   171		 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
   172		 (type == MIPI_DSI_DCS_READ))
   173	
   174	static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
   175					      const struct mipi_dsi_msg *msg)
   176	{
   177		struct mcde_dsi *d = host_to_mcde_dsi(host);
   178		const u32 loop_delay_us = 10; /* us */
   179		const u8 *tx = msg->tx_buf;
   180		u32 loop_counter;
   181		size_t txlen = msg->tx_len;
   182		size_t rxlen = msg->rx_len;
   183		u32 val;
   184		int ret;
   185		int i;
   186	
   187		if (txlen > 16) {
   188			dev_err(d->dev,
   189				"dunno how to write more than 16 bytes yet\n");
   190			return -EIO;
   191		}
   192		if (rxlen > 4) {
   193			dev_err(d->dev,
   194				"dunno how to read more than 4 bytes yet\n");
   195			return -EIO;
   196		}
   197	
   198		dev_dbg(d->dev,
   199			"message to channel %d, write %zd bytes read %zd bytes\n",
   200			msg->channel, txlen, rxlen);
   201	
   202		/* Command "nature" */
   203		if (MCDE_DSI_HOST_IS_READ(msg->type))
   204			/* MCTL_MAIN_DATA_CTL already set up */
   205			val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;
   206		else
   207			val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;
   208		/*
   209		 * More than 2 bytes will not fit in a single packet, so it's
   210		 * time to set the "long not short" bit. One byte is used by
   211		 * the MIPI DCS command leaving just one byte for the payload
   212		 * in a short package.
   213		 */
   214		if (mipi_dsi_packet_format_is_long(msg->type))
   215			val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
   216		val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
   217		val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
   218		val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
   219		val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
   220		writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
   221	
   222		/* MIPI DCS command is part of the data */
   223		if (txlen > 0) {
   224			val = 0;
   225			for (i = 0; i < 4 && i < txlen; i++)
   226				val |= tx[i] << (i & 3) * 8;
   227		}
   228		writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
   229		if (txlen > 4) {
   230			val = 0;
   231			for (i = 0; i < 4 && (i + 4) < txlen; i++)
   232				val |= tx[i + 4] << (i & 3) * 8;
   233			writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
   234		}
   235		if (txlen > 8) {
   236			val = 0;
   237			for (i = 0; i < 4 && (i + 8) < txlen; i++)
   238				val |= tx[i + 8] << (i & 3) * 8;
   239			writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
   240		}
   241		if (txlen > 12) {
   242			val = 0;
   243			for (i = 0; i < 4 && (i + 12) < txlen; i++)
   244				val |= tx[i + 12] << (i & 3) * 8;
   245			writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
   246		}
   247	
   248		writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
   249		writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
   250		/* Send command */
   251		writel(1, d->regs + DSI_DIRECT_CMD_SEND);
   252	
   253		loop_counter = 1000 * 1000 / loop_delay_us;
   254		if (MCDE_DSI_HOST_IS_READ(msg->type)) {
   255			/* Read command */
   256			while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
   257				 (DSI_DIRECT_CMD_STS_READ_COMPLETED |
   258				  DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
   259			       && --loop_counter)
   260				usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
   261			if (!loop_counter) {
   262				dev_err(d->dev, "DSI write timeout!\n");
   263				return -ETIME;
   264			}
   265		} else {
   266			/* Writing only */
   267			while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
   268				 DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
   269			       && --loop_counter)
   270				usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
   271	
   272			if (!loop_counter) {
   273				dev_err(d->dev, "DSI write timeout!\n");
   274				return -ETIME;
   275			}
   276		}
   277	
   278		val = readl(d->regs + DSI_DIRECT_CMD_STS);
   279		if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
   280			dev_err(d->dev, "read completed with error\n");
   281			writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
   282			return -EIO;
   283		}
   284		if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
   285			val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
   286			dev_err(d->dev, "error during transmission: %04x\n",
   287				val);
   288			return -EIO;
   289		}
   290	
   291		if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
   292			/* Return number of bytes written */
   293			ret = txlen;
   294		} else {
   295			/* OK this is a read command, get the response */
   296			u32 rdsz;
   297			u32 rddat;
   298			u8 *rx = msg->rx_buf;
   299	
   300			rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
   301			rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
   302			rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
   303			if (rdsz < rxlen) {
 > 304				dev_err(d->dev, "read error, requested %d got %d\n",
   305					msg->rx_len, rdsz);
   306				return -EIO;
   307			}
   308			/* FIXME: read more than 4 bytes */
   309			for (i = 0; i < 4 && i < rxlen; i++)
   310				rx[i] = (rddat >> (i * 8)) & 0xff;
   311			ret = rdsz;
   312		}
   313	
   314		writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
   315		writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
   316	
   317		return ret;
   318	}
   319	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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2019-08-30 13:06 [PATCH] drm/mcde: Fix DSI transfers Linus Walleij
2019-08-30 13:06 ` Linus Walleij
2019-08-30 22:38 ` kbuild test robot

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