From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, jonathanh@nvidia.com, andrew.murray@arm.com,
kishon@ti.com, gustavo.pimentel@synopsys.com, digetx@gmail.com,
mperttunen@nvidia.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins
Date: Mon, 2 Sep 2019 13:38:59 +0200 [thread overview]
Message-ID: <20190902113859.GF19263@ulmo> (raw)
In-Reply-To: <20190828172850.19871-4-vidyas@nvidia.com>
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On Wed, Aug 28, 2019 at 10:58:47PM +0530, Vidya Sagar wrote:
> Add support to configure sideband signal pins when information is present
> in respective controller's device-tree node.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * Used 'dev' instead of 'pcie->dev'
>
> V2:
> * Addressed review comment from Andrew Murray
> * Handled failure case of pinctrl_pm_select_default_state() cleanly
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
mperttunen@nvidia.com, mmaddireddy@nvidia.com, kthota@nvidia.com,
gustavo.pimentel@synopsys.com, linux-kernel@vger.kernel.org,
kishon@ti.com, linux-tegra@vger.kernel.org, robh+dt@kernel.org,
linux-pci@vger.kernel.org, bhelgaas@google.com,
andrew.murray@arm.com, digetx@gmail.com, jonathanh@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins
Date: Mon, 2 Sep 2019 13:38:59 +0200 [thread overview]
Message-ID: <20190902113859.GF19263@ulmo> (raw)
In-Reply-To: <20190828172850.19871-4-vidyas@nvidia.com>
[-- Attachment #1.1: Type: text/plain, Size: 594 bytes --]
On Wed, Aug 28, 2019 at 10:58:47PM +0530, Vidya Sagar wrote:
> Add support to configure sideband signal pins when information is present
> in respective controller's device-tree node.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * Used 'dev' instead of 'pcie->dev'
>
> V2:
> * Addressed review comment from Andrew Murray
> * Handled failure case of pinctrl_pm_select_default_state() cleanly
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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next prev parent reply other threads:[~2019-09-02 11:38 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 17:28 [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` [PATCH V3 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-09-02 10:40 ` Andrew Murray
2019-09-02 10:40 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 2/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-29 12:03 ` Thierry Reding
2019-08-29 12:03 ` Thierry Reding
2019-08-29 15:18 ` Vidya Sagar
2019-08-29 15:18 ` Vidya Sagar
2019-08-29 15:18 ` Vidya Sagar
2019-08-29 16:41 ` Thierry Reding
2019-08-29 16:41 ` Thierry Reding
2019-09-02 10:41 ` Andrew Murray
2019-09-02 10:41 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding
2019-09-02 11:38 ` Thierry Reding
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:38 ` Rob Herring
2019-08-28 17:28 ` [PATCH V3 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-09-02 10:18 ` Andrew Murray
2019-09-02 10:18 ` Andrew Murray
2019-09-02 11:38 ` Thierry Reding [this message]
2019-09-02 11:38 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 4/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-09-02 10:29 ` Andrew Murray
2019-09-02 10:29 ` Andrew Murray
2019-09-02 11:40 ` Thierry Reding
2019-09-02 11:40 ` Thierry Reding
2019-08-28 17:28 ` [PATCH V3 5/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-09-02 10:45 ` Andrew Murray
2019-09-02 10:45 ` Andrew Murray
2019-08-28 17:28 ` [PATCH V3 6/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-08-28 17:28 ` Vidya Sagar
2019-09-02 10:47 ` Andrew Murray
2019-09-02 10:47 ` Andrew Murray
2019-09-05 8:14 ` [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 " Vidya Sagar
2019-09-05 8:14 ` Vidya Sagar
2019-09-05 8:14 ` Vidya Sagar
2019-09-05 9:34 ` Lorenzo Pieralisi
2019-09-05 9:34 ` Lorenzo Pieralisi
2019-09-05 10:50 ` Vidya Sagar
2019-09-05 10:50 ` Vidya Sagar
2019-09-05 10:50 ` Vidya Sagar
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