From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com> Subject: [PATCH 02/20] riscv: refactor the IPI code Date: Tue, 3 Sep 2019 11:32:21 +0200 [thread overview] Message-ID: <20190903093239.21278-3-hch@lst.de> (raw) In-Reply-To: <20190903093239.21278-1-hch@lst.de> This prepares for adding native non-SBI IPI code. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/kernel/smp.c | 55 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 5a9834503a2f..8cd730239613 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -78,13 +78,38 @@ static void ipi_stop(void) wait_for_interrupt(); } +static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) +{ + int cpuid, hartid; + struct cpumask hartid_mask; + + cpumask_clear(&hartid_mask); + mb(); + for_each_cpu(cpuid, mask) { + set_bit(op, &ipi_data[cpuid].bits); + hartid = cpuid_to_hartid_map(cpuid); + cpumask_set_cpu(hartid, &hartid_mask); + } + mb(); + sbi_send_ipi(cpumask_bits(&hartid_mask)); +} + +static void send_ipi_single(int cpu, enum ipi_message_type op) +{ + send_ipi_mask(cpumask_of(cpu), op); +} + +static inline void clear_ipi(void) +{ + csr_clear(CSR_SIP, SIE_SSIE); +} + void riscv_software_interrupt(void) { unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; unsigned long *stats = ipi_data[smp_processor_id()].stats; - /* Clear pending IPI */ - csr_clear(CSR_SIP, SIE_SSIE); + clear_ipi(); while (true) { unsigned long ops; @@ -118,23 +143,6 @@ void riscv_software_interrupt(void) } } -static void -send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation) -{ - int cpuid, hartid; - struct cpumask hartid_mask; - - cpumask_clear(&hartid_mask); - mb(); - for_each_cpu(cpuid, to_whom) { - set_bit(operation, &ipi_data[cpuid].bits); - hartid = cpuid_to_hartid_map(cpuid); - cpumask_set_cpu(hartid, &hartid_mask); - } - mb(); - sbi_send_ipi(cpumask_bits(&hartid_mask)); -} - static const char * const ipi_names[] = { [IPI_RESCHEDULE] = "Rescheduling interrupts", [IPI_CALL_FUNC] = "Function call interrupts", @@ -156,12 +164,12 @@ void show_ipi_stats(struct seq_file *p, int prec) void arch_send_call_function_ipi_mask(struct cpumask *mask) { - send_ipi_message(mask, IPI_CALL_FUNC); + send_ipi_mask(mask, IPI_CALL_FUNC); } void arch_send_call_function_single_ipi(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC); + send_ipi_single(cpu, IPI_CALL_FUNC); } void smp_send_stop(void) @@ -176,7 +184,7 @@ void smp_send_stop(void) if (system_state <= SYSTEM_RUNNING) pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_message(&mask, IPI_CPU_STOP); + send_ipi_mask(&mask, IPI_CPU_STOP); } /* Wait up to one second for other CPUs to stop */ @@ -191,6 +199,5 @@ void smp_send_stop(void) void smp_send_reschedule(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); + send_ipi_single(cpu, IPI_RESCHEDULE); } - -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Atish Patra <atish.patra@wdc.com>, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/20] riscv: refactor the IPI code Date: Tue, 3 Sep 2019 11:32:21 +0200 [thread overview] Message-ID: <20190903093239.21278-3-hch@lst.de> (raw) In-Reply-To: <20190903093239.21278-1-hch@lst.de> This prepares for adding native non-SBI IPI code. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/kernel/smp.c | 55 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 5a9834503a2f..8cd730239613 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -78,13 +78,38 @@ static void ipi_stop(void) wait_for_interrupt(); } +static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) +{ + int cpuid, hartid; + struct cpumask hartid_mask; + + cpumask_clear(&hartid_mask); + mb(); + for_each_cpu(cpuid, mask) { + set_bit(op, &ipi_data[cpuid].bits); + hartid = cpuid_to_hartid_map(cpuid); + cpumask_set_cpu(hartid, &hartid_mask); + } + mb(); + sbi_send_ipi(cpumask_bits(&hartid_mask)); +} + +static void send_ipi_single(int cpu, enum ipi_message_type op) +{ + send_ipi_mask(cpumask_of(cpu), op); +} + +static inline void clear_ipi(void) +{ + csr_clear(CSR_SIP, SIE_SSIE); +} + void riscv_software_interrupt(void) { unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; unsigned long *stats = ipi_data[smp_processor_id()].stats; - /* Clear pending IPI */ - csr_clear(CSR_SIP, SIE_SSIE); + clear_ipi(); while (true) { unsigned long ops; @@ -118,23 +143,6 @@ void riscv_software_interrupt(void) } } -static void -send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation) -{ - int cpuid, hartid; - struct cpumask hartid_mask; - - cpumask_clear(&hartid_mask); - mb(); - for_each_cpu(cpuid, to_whom) { - set_bit(operation, &ipi_data[cpuid].bits); - hartid = cpuid_to_hartid_map(cpuid); - cpumask_set_cpu(hartid, &hartid_mask); - } - mb(); - sbi_send_ipi(cpumask_bits(&hartid_mask)); -} - static const char * const ipi_names[] = { [IPI_RESCHEDULE] = "Rescheduling interrupts", [IPI_CALL_FUNC] = "Function call interrupts", @@ -156,12 +164,12 @@ void show_ipi_stats(struct seq_file *p, int prec) void arch_send_call_function_ipi_mask(struct cpumask *mask) { - send_ipi_message(mask, IPI_CALL_FUNC); + send_ipi_mask(mask, IPI_CALL_FUNC); } void arch_send_call_function_single_ipi(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC); + send_ipi_single(cpu, IPI_CALL_FUNC); } void smp_send_stop(void) @@ -176,7 +184,7 @@ void smp_send_stop(void) if (system_state <= SYSTEM_RUNNING) pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_message(&mask, IPI_CPU_STOP); + send_ipi_mask(&mask, IPI_CPU_STOP); } /* Wait up to one second for other CPUs to stop */ @@ -191,6 +199,5 @@ void smp_send_stop(void) void smp_send_reschedule(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); + send_ipi_single(cpu, IPI_RESCHEDULE); } - -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-09-03 9:34 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-03 9:32 RISC-V nommu support v4 Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig [this message] 2019-09-03 9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig 2019-09-03 9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-10-16 2:07 ` Paul Walmsley 2019-10-16 2:07 ` Paul Walmsley 2019-10-17 16:20 ` Christoph Hellwig 2019-10-17 16:20 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 11/20] riscv: cleanup the default power off implementation Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig 2019-09-03 9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig 2019-09-03 9:32 ` Christoph Hellwig
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