[Qemu-devel] [PATCH v2 0/5] Support disabling TCG on ARM (part 2)

[Qemu-devel] [PATCH v2 0/5] Support disabling TCG on ARM (part 2)

[Philippe Mathieu-Daudé]

Cover from Samuel Ortiz from (part 1) [1]:

  This patchset allows for building and running ARM targets with TCG
  disabled. [...]

  The rationale behind this work comes from the NEMU project where we're
  trying to only support x86 and ARM 64-bit architectures, without
  including the TCG code base. We can only do so if we can build and run
  ARM binaries with TCG disabled.

A preliminary patch expose the CONFIG_TCG to Kconfig.
2 patches disable non-KVM compatible cpus to the KVM build,
then 2 remove the boards using these cpus from this build.

v2: Addressed review comments from Richard and Thomas from v1 [2]
    (see comments in each patch).

Regards,

Phil.

[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
[2]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html

Philippe Mathieu-Daudé (5):
  Kconfig: Expose CONFIG_TCG to minikconf.py
  target/arm: Restrict pre-ARMv7 cpus to TCG
  hw/arm: Restrict pre-ARMv7 cpus to TCG
  target/arm: Restrict R and M profiles to TCG
  hw/arm: Restrict R and M profiles to TCG

 Kconfig.host     |  4 ++++
 hw/arm/Kconfig   | 37 ++++++++++++++++++++++++++++++++++---
 target/arm/cpu.c | 16 +++++++++++++++-
 3 files changed, 53 insertions(+), 4 deletions(-)

-- 
2.20.1

[Qemu-devel] [PATCH v2 1/5] Kconfig: Expose CONFIG_TCG to minikconf.py

[Philippe Mathieu-Daudé]

Expose the CONFIG_TCG selector to let minikconf.py uses it.

This is useful with the --disable-tcg build, to deselect
devices that are TCG-dependent.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 Kconfig.host | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Kconfig.host b/Kconfig.host
index bb6e116e2a..c7caa47dfb 100644
--- a/Kconfig.host
+++ b/Kconfig.host
@@ -2,6 +2,10 @@
 # down to Kconfig.  See also MINIKCONF_ARGS in the Makefile:
 # these two need to be kept in sync.
 
+config TCG
+    bool
+    default y
+
 config KVM
     bool
 
-- 
2.20.1

[Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG

[Philippe Mathieu-Daudé]

KVM requires a cpu based on (at least) the ARMv7 architecture.

The following CPUs are disabled:

* ARMv4

  - StrongARM (SA1100/1110)
  - OMAP1510 (TI925T)

* ARMv5

  - ARM926
  - ARM946
  - ARM1026
  - XScale (PXA250/255/260/261/262/270)

* ARMv6

  - ARM1136
  - ARM1176
  - ARM11MPCore
  - Cortex-M0

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: fixed misplaced #endif (rth), list cpus
---
 target/arm/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2399c14471..f69780147c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1678,6 +1678,8 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
+#ifdef CONFIG_TCG
+
 static void arm926_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -1900,6 +1902,8 @@ static void cortex_m0_initfn(Object *obj)
     cpu->midr = 0x410cc200;
 }
 
+#endif
+
 static void cortex_m3_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -2283,6 +2287,8 @@ static void cortex_a15_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 }
 
+#ifdef CONFIG_TCG
+
 static void ti925t_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -2451,6 +2457,8 @@ static void pxa270c5_initfn(Object *obj)
     cpu->reset_sctlr = 0x00000078;
 }
 
+#endif
+
 #ifndef TARGET_AARCH64
 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
  * otherwise, a CPU with as many features enabled as our emulation supports.
@@ -2523,6 +2531,7 @@ struct ARMCPUInfo {
 
 static const ARMCPUInfo arm_cpus[] = {
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifdef CONFIG_TCG
     { .name = "arm926",      .initfn = arm926_initfn },
     { .name = "arm946",      .initfn = arm946_initfn },
     { .name = "arm1026",     .initfn = arm1026_initfn },
@@ -2536,6 +2545,7 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
                              .class_init = arm_v7m_class_init },
+#endif
     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
@@ -2548,6 +2558,7 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
+#ifdef CONFIG_TCG
     { .name = "ti925t",      .initfn = ti925t_initfn },
     { .name = "sa1100",      .initfn = sa1100_initfn },
     { .name = "sa1110",      .initfn = sa1110_initfn },
@@ -2564,6 +2575,7 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
+#endif
 #ifndef TARGET_AARCH64
     { .name = "max",         .initfn = arm_max_initfn },
 #endif
-- 
2.20.1

[Qemu-devel] [PATCH v2 3/5] hw/arm: Restrict pre-ARMv7 cpus to TCG

[Philippe Mathieu-Daudé]

A KVM-only build won't be able to run pre-ARMv7 cpus, disable them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: - "depends on !KVM" -> "depends on TCG" (rth)
    - do not modify default-configs/arm-softmmu.mak (thuth)
---
 hw/arm/Kconfig | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 76a2a6bcbf..1c359a6f47 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,3 +1,15 @@
+config ARM_V4
+    depends on TCG
+    bool
+
+config ARM_V5
+    depends on TCG
+    bool
+
+config ARM_V6
+    depends on TCG
+    bool
+
 config ARM_VIRT
     bool
     imply PCI_DEVICES
@@ -23,6 +35,7 @@ config ARM_VIRT
 
 config CHEETAH
     bool
+    select ARM_V4
     select OMAP
     select TSC210X
 
@@ -32,6 +45,7 @@ config CUBIEBOARD
 
 config DIGIC
     bool
+    select ARM_V5
     select PTIMER
     select PFLASH_CFI02
 
@@ -61,6 +75,7 @@ config HIGHBANK
 
 config INTEGRATOR
     bool
+    select ARM_V5
     select ARM_TIMER
     select INTEGRATOR_DEBUG
     select PL011 # UART
@@ -86,6 +101,7 @@ config MUSCA
 
 config MUSICPAL
     bool
+    select ARM_V5
     select BITBANG_I2C
     select MARVELL_88W8618
     select PTIMER
@@ -99,6 +115,7 @@ config NETDUINO2
 
 config NSERIES
     bool
+    select ARM_V6
     select OMAP
     select TMP105   # tempature sensor
     select BLIZZARD # LCD/TV controller
@@ -121,6 +138,7 @@ config OMAP
 
 config PXA2XX
     bool
+    select ARM_V5
     select FRAMEBUFFER
     select I2C
     select SERIAL
@@ -232,10 +250,12 @@ config COLLIE
 
 config SX1
     bool
+    select ARM_V4
     select OMAP
 
 config VERSATILE
     bool
+    select ARM_V5
     select ARM_TIMER # sp804
     select PFLASH_CFI01
     select LSI_SCSI_PCI
@@ -327,6 +347,7 @@ config XLNX_VERSAL
 
 config FSL_IMX25
     bool
+    select ARM_V5
     select IMX
     select IMX_FEC
     select IMX_I2C
@@ -334,6 +355,7 @@ config FSL_IMX25
 
 config FSL_IMX31
     bool
+    select ARM_V6
     select SERIAL
     select IMX
     select IMX_I2C
@@ -349,6 +371,7 @@ config FSL_IMX6
 
 config ASPEED_SOC
     bool
+    select ARM_V5
     select DS1338
     select FTGMAC100
     select I2C
-- 
2.20.1

[Qemu-devel] [PATCH v2 4/5] target/arm: Restrict R and M profiles to TCG

[Philippe Mathieu-Daudé]

KVM is only able to run on CPUs based on the A-Profile architecture.

The following CPUs are disabled:

* M-Profile Architecture

  - Cortex-M3
  - Cortex-M4
  - Cortex-M33

* R-Profile Architecture

  - Cortex-R5
  - Cortex-R5F

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: list cpus
---
 target/arm/cpu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f69780147c..299c59fde4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -462,7 +462,9 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return ret;
 }
 
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if (!defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)) \
+    && defined(CONFIG_TCG)
 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
     CPUClass *cc = CPU_GET_CLASS(cs);
@@ -1902,8 +1904,6 @@ static void cortex_m0_initfn(Object *obj)
     cpu->midr = 0x410cc200;
 }
 
-#endif
-
 static void cortex_m3_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -2057,6 +2057,8 @@ static void cortex_r5f_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x00000011;
 }
 
+#endif
+
 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2545,7 +2547,6 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
                              .class_init = arm_v7m_class_init },
-#endif
     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
@@ -2554,6 +2555,7 @@ static const ARMCPUInfo arm_cpus[] = {
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
+#endif
     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
-- 
2.20.1

[Qemu-devel] [PATCH v2 5/5] hw/arm: Restrict R and M profiles to TCG

[Philippe Mathieu-Daudé]

A KVM-only build won't be able to run A or M-profile cpus,
disable them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: - "depends on !KVM" -> "depends on TCG" (rth)
    - do not modify default-configs/arm-softmmu.mak (thuth)
---
 hw/arm/Kconfig | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 1c359a6f47..8368666f5a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -10,6 +10,16 @@ config ARM_V6
     depends on TCG
     bool
 
+# ARM Microcontroller profile
+config ARM_V7M
+    depends on TCG
+    bool
+
+# ARM Realtime profile
+config ARM_V7R
+    depends on TCG
+    bool
+
 config ARM_VIRT
     bool
     imply PCI_DEVICES
@@ -295,9 +305,6 @@ config ZYNQ
     select XILINX_SPIPS
     select ZYNQ_DEVCFG
 
-config ARM_V7M
-    bool
-
 config ALLWINNER_A10
     bool
     select AHCI
@@ -325,6 +332,7 @@ config STM32F205_SOC
 
 config XLNX_ZYNQMP_ARM
     bool
+    select ARM_V7R
     select AHCI
     select ARM_GIC
     select CADENCE
-- 
2.20.1

Re: [Qemu-devel] [PATCH v2 1/5] Kconfig: Expose CONFIG_TCG to minikconf.py

[Thomas Huth]

On 03/09/2019 13.47, Philippe Mathieu-Daudé wrote:
> Expose the CONFIG_TCG selector to let minikconf.py uses it.
> 
> This is useful with the --disable-tcg build, to deselect
> devices that are TCG-dependent.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  Kconfig.host | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Kconfig.host b/Kconfig.host
> index bb6e116e2a..c7caa47dfb 100644
> --- a/Kconfig.host
> +++ b/Kconfig.host
> @@ -2,6 +2,10 @@
>  # down to Kconfig.  See also MINIKCONF_ARGS in the Makefile:
>  # these two need to be kept in sync.

Don't you also have to update ----^ MINIKCONF_ARGS in the Makefile?

> +config TCG
> +    bool
> +    default y
> +
>  config KVM
>      bool

 Thomas

Re: [Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG

[Thomas Huth]

On 03/09/2019 13.47, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
> 
> The following CPUs are disabled:
> 
> * ARMv4
> 
>   - StrongARM (SA1100/1110)
>   - OMAP1510 (TI925T)
> 
> * ARMv5
> 
>   - ARM926
>   - ARM946
>   - ARM1026
>   - XScale (PXA250/255/260/261/262/270)
> 
> * ARMv6
> 
>   - ARM1136
>   - ARM1176
>   - ARM11MPCore
>   - Cortex-M0
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> v2: fixed misplaced #endif (rth), list cpus
> ---
>  target/arm/cpu.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 2399c14471..f69780147c 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1678,6 +1678,8 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>  
> +#ifdef CONFIG_TCG
> +
>  static void arm926_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -1900,6 +1902,8 @@ static void cortex_m0_initfn(Object *obj)
>      cpu->midr = 0x410cc200;
>  }
>  
> +#endif
> +
>  static void cortex_m3_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -2283,6 +2287,8 @@ static void cortex_a15_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
>  }
>  
> +#ifdef CONFIG_TCG
> +
>  static void ti925t_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -2451,6 +2457,8 @@ static void pxa270c5_initfn(Object *obj)
>      cpu->reset_sctlr = 0x00000078;
>  }
>  
> +#endif
> +
>  #ifndef TARGET_AARCH64
>  /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
>   * otherwise, a CPU with as many features enabled as our emulation supports.
> @@ -2523,6 +2531,7 @@ struct ARMCPUInfo {
>  
>  static const ARMCPUInfo arm_cpus[] = {
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> +#ifdef CONFIG_TCG
>      { .name = "arm926",      .initfn = arm926_initfn },
>      { .name = "arm946",      .initfn = arm946_initfn },
>      { .name = "arm1026",     .initfn = arm1026_initfn },
> @@ -2536,6 +2545,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
>      { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
>                               .class_init = arm_v7m_class_init },
> +#endif
>      { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
>                               .class_init = arm_v7m_class_init },
>      { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
> @@ -2548,6 +2558,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
>      { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
>      { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
> +#ifdef CONFIG_TCG
>      { .name = "ti925t",      .initfn = ti925t_initfn },
>      { .name = "sa1100",      .initfn = sa1100_initfn },
>      { .name = "sa1110",      .initfn = sa1110_initfn },
> @@ -2564,6 +2575,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
>      { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
> +#endif
>  #ifndef TARGET_AARCH64
>      { .name = "max",         .initfn = arm_max_initfn },
>  #endif
> 

All that #ifdeffery is a little bit ugly. I wonder whether we could
solve this by moving the CPU registrations to separate files which then
only get compiled if the corresponding CONFIG_ARM_Vx switch is set.

That reminds me of a patch series of mine where I tried to make the code
compilable without CONFIG_ARM_V7M ... unfortunately, I never found
enough spare time to finish and publish it... I'll have a try to see
whether I can rebase it and send it as an RFC or so.

 Thomas

Re: [Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG

[Philippe Mathieu-Daudé]

On 9/3/19 2:10 PM, Thomas Huth wrote:
> On 03/09/2019 13.47, Philippe Mathieu-Daudé wrote:
>> KVM requires a cpu based on (at least) the ARMv7 architecture.
>>
>> The following CPUs are disabled:
>>
>> * ARMv4
>>
>>   - StrongARM (SA1100/1110)
>>   - OMAP1510 (TI925T)
>>
>> * ARMv5
>>
>>   - ARM926
>>   - ARM946
>>   - ARM1026
>>   - XScale (PXA250/255/260/261/262/270)
>>
>> * ARMv6
>>
>>   - ARM1136
>>   - ARM1176
>>   - ARM11MPCore
>>   - Cortex-M0
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> v2: fixed misplaced #endif (rth), list cpus
>> ---
>>  target/arm/cpu.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index 2399c14471..f69780147c 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -1678,6 +1678,8 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
>>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>>  
>> +#ifdef CONFIG_TCG
>> +
>>  static void arm926_initfn(Object *obj)
>>  {
>>      ARMCPU *cpu = ARM_CPU(obj);
>> @@ -1900,6 +1902,8 @@ static void cortex_m0_initfn(Object *obj)
>>      cpu->midr = 0x410cc200;
>>  }
>>  
>> +#endif
>> +
>>  static void cortex_m3_initfn(Object *obj)
>>  {
>>      ARMCPU *cpu = ARM_CPU(obj);
>> @@ -2283,6 +2287,8 @@ static void cortex_a15_initfn(Object *obj)
>>      define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
>>  }
>>  
>> +#ifdef CONFIG_TCG
>> +
>>  static void ti925t_initfn(Object *obj)
>>  {
>>      ARMCPU *cpu = ARM_CPU(obj);
>> @@ -2451,6 +2457,8 @@ static void pxa270c5_initfn(Object *obj)
>>      cpu->reset_sctlr = 0x00000078;
>>  }
>>  
>> +#endif
>> +
>>  #ifndef TARGET_AARCH64
>>  /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
>>   * otherwise, a CPU with as many features enabled as our emulation supports.
>> @@ -2523,6 +2531,7 @@ struct ARMCPUInfo {
>>  
>>  static const ARMCPUInfo arm_cpus[] = {
>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>> +#ifdef CONFIG_TCG
>>      { .name = "arm926",      .initfn = arm926_initfn },
>>      { .name = "arm946",      .initfn = arm946_initfn },
>>      { .name = "arm1026",     .initfn = arm1026_initfn },
>> @@ -2536,6 +2545,7 @@ static const ARMCPUInfo arm_cpus[] = {
>>      { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
>>      { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
>>                               .class_init = arm_v7m_class_init },
>> +#endif
>>      { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
>>                               .class_init = arm_v7m_class_init },
>>      { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
>> @@ -2548,6 +2558,7 @@ static const ARMCPUInfo arm_cpus[] = {
>>      { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
>>      { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
>>      { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
>> +#ifdef CONFIG_TCG
>>      { .name = "ti925t",      .initfn = ti925t_initfn },
>>      { .name = "sa1100",      .initfn = sa1100_initfn },
>>      { .name = "sa1110",      .initfn = sa1110_initfn },
>> @@ -2564,6 +2575,7 @@ static const ARMCPUInfo arm_cpus[] = {
>>      { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
>>      { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
>>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
>> +#endif
>>  #ifndef TARGET_AARCH64
>>      { .name = "max",         .initfn = arm_max_initfn },
>>  #endif
>>
> 
> All that #ifdeffery is a little bit ugly. I wonder whether we could
> solve this by moving the CPU registrations to separate files which then
> only get compiled if the corresponding CONFIG_ARM_Vx switch is set.

I tried splitting arm_cpus[] and move the ifdef in
arm_cpu_register_types(), but the resulting diff is much bigger and it
only reduces from 4 '#ifdef CONFIG_TCG' to 2...

I'll see what thinks Peter first.

> That reminds me of a patch series of mine where I tried to make the code
> compilable without CONFIG_ARM_V7M ... unfortunately, I never found
> enough spare time to finish and publish it... I'll have a try to see
> whether I can rebase it and send it as an RFC or so.

Well, this is the same goal of this series... So regarding on Peter's
comments I might wait on your work.

Regards,

Phil.

Re: [Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG

[Thomas Huth]

On 03/09/2019 15.37, Philippe Mathieu-Daudé wrote:
> On 9/3/19 2:10 PM, Thomas Huth wrote:
>> On 03/09/2019 13.47, Philippe Mathieu-Daudé wrote:
[...]
>> That reminds me of a patch series of mine where I tried to make the code
>> compilable without CONFIG_ARM_V7M ... unfortunately, I never found
>> enough spare time to finish and publish it... I'll have a try to see
>> whether I can rebase it and send it as an RFC or so.
> 
> Well, this is the same goal of this series... So regarding on Peter's
> comments I might wait on your work.

I noticed that you did most work of my old series with the new
m_helper.c file already :-) ... so I'll check whether I can re-do my
other work around these changes...

 Thomas

Re: [Qemu-devel] [PATCH v2 3/5] hw/arm: Restrict pre-ARMv7 cpus to TCG

[Alistair Francis]

On Tue, Sep 3, 2019 at 4:48 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> A KVM-only build won't be able to run pre-ARMv7 cpus, disable them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
> v2: - "depends on !KVM" -> "depends on TCG" (rth)
>     - do not modify default-configs/arm-softmmu.mak (thuth)
> ---
>  hw/arm/Kconfig | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 76a2a6bcbf..1c359a6f47 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,3 +1,15 @@
> +config ARM_V4
> +    depends on TCG
> +    bool
> +
> +config ARM_V5
> +    depends on TCG
> +    bool
> +
> +config ARM_V6
> +    depends on TCG
> +    bool
> +
>  config ARM_VIRT
>      bool
>      imply PCI_DEVICES
> @@ -23,6 +35,7 @@ config ARM_VIRT
>
>  config CHEETAH
>      bool
> +    select ARM_V4
>      select OMAP
>      select TSC210X
>
> @@ -32,6 +45,7 @@ config CUBIEBOARD
>
>  config DIGIC
>      bool
> +    select ARM_V5
>      select PTIMER
>      select PFLASH_CFI02
>
> @@ -61,6 +75,7 @@ config HIGHBANK
>
>  config INTEGRATOR
>      bool
> +    select ARM_V5
>      select ARM_TIMER
>      select INTEGRATOR_DEBUG
>      select PL011 # UART
> @@ -86,6 +101,7 @@ config MUSCA
>
>  config MUSICPAL
>      bool
> +    select ARM_V5
>      select BITBANG_I2C
>      select MARVELL_88W8618
>      select PTIMER
> @@ -99,6 +115,7 @@ config NETDUINO2
>
>  config NSERIES
>      bool
> +    select ARM_V6
>      select OMAP
>      select TMP105   # tempature sensor
>      select BLIZZARD # LCD/TV controller
> @@ -121,6 +138,7 @@ config OMAP
>
>  config PXA2XX
>      bool
> +    select ARM_V5
>      select FRAMEBUFFER
>      select I2C
>      select SERIAL
> @@ -232,10 +250,12 @@ config COLLIE
>
>  config SX1
>      bool
> +    select ARM_V4
>      select OMAP
>
>  config VERSATILE
>      bool
> +    select ARM_V5
>      select ARM_TIMER # sp804
>      select PFLASH_CFI01
>      select LSI_SCSI_PCI
> @@ -327,6 +347,7 @@ config XLNX_VERSAL
>
>  config FSL_IMX25
>      bool
> +    select ARM_V5
>      select IMX
>      select IMX_FEC
>      select IMX_I2C
> @@ -334,6 +355,7 @@ config FSL_IMX25
>
>  config FSL_IMX31
>      bool
> +    select ARM_V6
>      select SERIAL
>      select IMX
>      select IMX_I2C
> @@ -349,6 +371,7 @@ config FSL_IMX6
>
>  config ASPEED_SOC
>      bool
> +    select ARM_V5
>      select DS1338
>      select FTGMAC100
>      select I2C
> --
> 2.20.1
>
>