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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Apply FBC WA for TGL too
Date: Wed,  4 Sep 2019 16:02:40 -0700	[thread overview]
Message-ID: <20190904230241.20638-1-jose.souza@intel.com> (raw)

WA 1409120013 is also valid for TGL, so lets check for ">= 11".

BSpec: 52890

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16ed44bfd734..dc34b23e2320 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -343,8 +343,8 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 			   HSW_FBCQ_DIS);
 	}
 
-	if (IS_GEN(dev_priv, 11))
-		/* Wa_1409120013:icl,ehl */
+	if (INTEL_GEN(dev_priv) >= 11)
+		/* Wa_1409120013:icl,ehl,tgl */
 		I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-- 
2.23.0

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             reply	other threads:[~2019-09-04 23:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-04 23:02 José Roberto de Souza [this message]
2019-09-04 23:02 ` [PATCH 2/2] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect José Roberto de Souza
2019-09-05 10:51   ` Ville Syrjälä
2019-09-04 23:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Apply FBC WA for TGL too Patchwork
2019-09-04 23:27   ` Souza, Jose
2019-09-04 23:48 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-05  0:53 ` [PATCH 1/2] " Matt Roper
2019-09-05  0:56 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
2019-09-05 17:25   ` Souza, Jose

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