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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 2/2] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
Date: Wed,  4 Sep 2019 16:02:41 -0700	[thread overview]
Message-ID: <20190904230241.20638-2-jose.souza@intel.com> (raw)
In-Reply-To: <20190904230241.20638-1-jose.souza@intel.com>

Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
0x7. Do not hardcode the mask so it allows the fake MST encoders to
connect to all pipes no matter how many the platform has.

Iterating over all pipes to keep consistent with intel_ddi_init().

Initialy this patch was replaced by commit 4eaceea3a00f ("drm/i915:
Fix DP-MST crtc_mask") but userspace it not correctly using
encoder.possible_crtcs and it was reverted by
commit e838bfa8e170 ("Revert "drm/i915: Fix DP-MST crtc_mask"")

Userspace should be fixed but it might take a while, so bringing this
patch back for now.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 37366f81255b..792bcace3edf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -599,6 +599,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
 	struct intel_dp_mst_encoder *intel_mst;
 	struct intel_encoder *intel_encoder;
 	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum pipe pipe_iter;
 
 	intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
 
@@ -615,8 +617,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
 	intel_encoder->type = INTEL_OUTPUT_DP_MST;
 	intel_encoder->power_domain = intel_dig_port->base.power_domain;
 	intel_encoder->port = intel_dig_port->base.port;
-	intel_encoder->crtc_mask = 0x7;
 	intel_encoder->cloneable = 0;
+	for_each_pipe(dev_priv, pipe_iter)
+		intel_encoder->crtc_mask |= BIT(pipe_iter);
 
 	intel_encoder->compute_config = intel_dp_mst_compute_config;
 	intel_encoder->disable = intel_mst_disable_dp;
-- 
2.23.0

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  reply	other threads:[~2019-09-04 23:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-04 23:02 [PATCH 1/2] drm/i915: Apply FBC WA for TGL too José Roberto de Souza
2019-09-04 23:02 ` José Roberto de Souza [this message]
2019-09-05 10:51   ` [PATCH 2/2] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Ville Syrjälä
2019-09-04 23:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Apply FBC WA for TGL too Patchwork
2019-09-04 23:27   ` Souza, Jose
2019-09-04 23:48 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-05  0:53 ` [PATCH 1/2] " Matt Roper
2019-09-05  0:56 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
2019-09-05 17:25   ` Souza, Jose

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