[PATCH v4 0/6] drm/i915/dp: Support for DP HDR outputs

[PATCH v4 0/6] drm/i915/dp: Support for DP HDR outputs

[Gwan-gyeong Mun]

Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe SDP to the panel.
The HDR Metadata will be provided by userspace compositors, based on
blending policies and passed to the driver through a blob property.
And It refactors, renames and extends a function which handled vsc sdp
header and data block setup for supporting colorimetry format.
And It attaches the colorspace connector property and HDR metadata property
to a DisplayPort connector.

These patches tested on below test environment.
Test Environment:
 - Tested System: GLK and Gen11 platform.
 - Monitor: Dell UP2718Q 4K HDR Monitor.
 - In order to test DP HDR10, test environment uses patched Kodi-gbm,
   patched Media driver and HDR10 video.

   You can find these on below.
   [patched Kodi-gbm]
    - repo: https://github.com/Kwiboo/xbmc/tree/drmprime-hdr 
   [download 4K HDR video file]
    - link: https://4kmedia.org/lg-new-york-hdr-uhd-4k-demo/
   [Media Driver for GLK]
    - repo https://gitlab.freedesktop.org/emersion/intel-vaapi-driver
  	  master branch
   [Media Driver for ICL]
    - repo: https://github.com/harishkrupo/media-driver/tree/p010_composite

v2:
 - Add a missed blank line after function declaration.
 - Remove useless parentheses.
 - Minor style fix.

v3:
 - Remove not handled return values from
   intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]
 - Add handling of different register size for
   HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
   platforms [Uma]
 - Add new colorimetry options for DP 1.4a spec. [Ville]
 - Separate set of colorimetry enum values for DP. [Ville]
 - In order to checking output format and output colorspace on
   intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state stucture.[Ville]
 - Remove a pointless variable. [Ville]

v4:
 - Add additional comments to struct drm_prop_enum_list.
 - Polishing an enum string of struct drm_prop_enum_list.

Gwan-gyeong Mun (7):
  drm/i915/dp: Extend program of VSC Header and DB for Colorimetry
    Format
  drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA
  drm: Add DisplayPort colorspace property
  drm/i915/dp: Attach colorspace property
  drm/i915: Add new GMP register size for GEN11
  drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static
    Metadata
  drm/i915/dp: Attach HDR metadata property to DP connector

 drivers/gpu/drm/drm_connector.c               |  46 +++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   2 -
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 193 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |   7 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  10 +-
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 include/drm/drm_connector.h                   |   8 +
 9 files changed, 259 insertions(+), 21 deletions(-)

-- 
2.23.0

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[PATCH v4 1/7] drm/i915/dp: Extend program of VSC Header and DB for Colorimetry Format

[Gwan-gyeong Mun]

It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it adds an argument
of drm_connector_state type.

Setup VSC header and data block in function intel_dp_setup_vsc_sdp for
pixel encoding / colorimetry format as per dp 1.4a spec, section 2.2.5.7.1,
table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120: VSC SDP Payload for DB16 through DB18.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.h |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c      | 68 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h      |  3 +
 4 files changed, 60 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1fe0bf01e580..49c35af583f9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3610,7 +3610,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
-	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
+	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 33fd523c4622..8de63be75620 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -526,8 +526,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 		      enum link_m_n_set m_n);
-void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
-			       const struct intel_crtc_state *crtc_state);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 			struct dpll *best_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5673ed75e428..776be3e16ac6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4446,8 +4446,9 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 }
 
 static void
-intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
-			       const struct intel_crtc_state *crtc_state)
+intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
+		       const struct intel_crtc_state *crtc_state,
+		       const struct drm_connector_state *conn_state)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct dp_sdp vsc_sdp = {};
@@ -4468,13 +4469,55 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 	 */
 	vsc_sdp.sdp_header.HB3 = 0x13;
 
-	/*
-	 * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
-	 * DB16[3:0] DP 1.4a spec, Table 2-120
-	 */
-	vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
-	/* RGB->YCBCR color conversion uses the BT.709 color space. */
-	vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
+	/* DP 1.4a spec, Table 2-120 */
+	switch (crtc_state->output_format) {
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
+		break;
+	case INTEL_OUTPUT_FORMAT_RGB:
+	default:
+		/* RGB: DB16[7:4] = 0h */
+		break;
+	}
+
+	switch (conn_state->colorspace) {
+	case DRM_MODE_COLORIMETRY_BT709_YCC:
+		vsc_sdp.db[16] |= 0x1;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_601:
+		vsc_sdp.db[16] |= 0x2;
+		break;
+	case DRM_MODE_COLORIMETRY_XVYCC_709:
+		vsc_sdp.db[16] |= 0x3;
+		break;
+	case DRM_MODE_COLORIMETRY_SYCC_601:
+		vsc_sdp.db[16] |= 0x4;
+		break;
+	case DRM_MODE_COLORIMETRY_OPYCC_601:
+		vsc_sdp.db[16] |= 0x5;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+	case DRM_MODE_COLORIMETRY_BT2020_RGB:
+		vsc_sdp.db[16] |= 0x6;
+		break;
+	case DRM_MODE_COLORIMETRY_BT2020_YCC:
+		vsc_sdp.db[16] |= 0x7;
+		break;
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+		vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
+		break;
+	default:
+		/* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
+
+		/* RGB->YCBCR color conversion uses the BT.709 color space. */
+		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+			vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
+		break;
+	}
 
 	/*
 	 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
@@ -4526,13 +4569,14 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
 }
 
-void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
-			       const struct intel_crtc_state *crtc_state)
+void intel_dp_vsc_enable(struct intel_dp *intel_dp,
+			 const struct intel_crtc_state *crtc_state,
+			 const struct drm_connector_state *conn_state)
 {
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
 		return;
 
-	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
+	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
 }
 
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e01d1f89409d..be13cb395ef8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -112,6 +112,9 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+void intel_dp_vsc_enable(struct intel_dp *intel_dp,
+			 const struct intel_crtc_state *crtc_state,
+			 const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.23.0

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[PATCH v4 2/7] drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA

[Gwan-gyeong Mun]

When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp function.
If the output colorspace requires vsc sdp or output format is YCbCr 4:2:0,
it uses MSA with VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of
Color Encoding Format and Content Color Gamut] while sending
BT.2020 Colorimetry signals we should program MSA MISC1 fields which
indicate VSC SDP for the Pixel Encoding/Colorimetry Format.

v2: Remove useless parentheses
v3: Addressed review comments from Ville
    - In order to checking output format and output colorspace on
      intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state struct
      value.
    - Remove a pointless variable.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  7 +++--
 .../drm/i915/display/intel_display_types.h    |  3 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 29 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |  1 +
 4 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 49c35af583f9..87dc5a19cb7b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1737,11 +1737,12 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	/*
 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 	 * of Color Encoding Format and Content Color Gamut] while sending
-	 * YCBCR 420 signals we should program MSA MISC1 fields which
-	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
+	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 	 */
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (intel_dp_needs_vsc_sdp(crtc_state))
 		temp |= TRANS_MSA_USE_VSC_SDP;
+
 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 61277a87dbe7..c62bad369c8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -971,6 +971,9 @@ struct intel_crtc_state {
 	/* Output format RGB/YCBCR etc */
 	enum intel_output_format output_format;
 
+	/* Output colorspace sRGB/BT.2020 etc */
+	u32 output_colorspace;
+
 	/* Output down scaling is done in LSPCON device */
 	bool lspcon_downsampling;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 776be3e16ac6..6b7587c71e49 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2187,6 +2187,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		pipe_config->has_pch_encoder = true;
 
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->output_colorspace = intel_conn_state->base.colorspace;
+
 	if (lspcon->active)
 		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
 	else
@@ -4445,6 +4447,31 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+bool
+intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+	 * of Color Encoding Format and Content Color Gamut], in order to
+	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		return true;
+
+	switch (crtc_state->output_colorspace) {
+	case DRM_MODE_COLORIMETRY_SYCC_601:
+	case DRM_MODE_COLORIMETRY_OPYCC_601:
+	case DRM_MODE_COLORIMETRY_BT2020_YCC:
+	case DRM_MODE_COLORIMETRY_BT2020_RGB:
+	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+		return true;
+	default:
+		break;
+	}
+
+	return false;
+}
+
 static void
 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 		       const struct intel_crtc_state *crtc_state,
@@ -4573,7 +4600,7 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state)
 {
-	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (!intel_dp_needs_vsc_sdp(crtc_state))
 		return;
 
 	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index be13cb395ef8..87883d0d5977 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -112,6 +112,7 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state);
 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state);
-- 
2.23.0

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[PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Gwan-gyeong Mun]

In order to use colorspace property to Display Port connectors, it extends
DRM_MODE_CONNECTOR_DisplayPort connector_type on
drm_mode_create_colorspace_property function.

v3: Addressed review comments from Ville
    - Add new colorimetry options for DP 1.4a spec.
    - Separate set of colorimetry enum values for DP.
v4: Add additional comments to struct drm_prop_enum_list.
    Polishing an enum string of struct drm_prop_enum_list
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/drm_connector.c | 46 +++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h     |  8 ++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4c766624b20d..5834e6d330a0 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -882,6 +882,44 @@ static const struct drm_prop_enum_list hdmi_colorspaces[] = {
 	{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
 };
 
+/*
+ * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel Encoding/Colorimetry
+ * Format Table 2-120
+ */
+static const struct drm_prop_enum_list dp_colorspaces[] = {
+	/* For Default case, driver will set the colorspace */
+	{ DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
+	/* Colorimetry based on IEC 61966-2-1 */
+	{ DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
+	{ DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB, "wide_gamut_fixed_point_RGB" },
+	/* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB */
+	{ DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
+	{ DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
+	/* Colorimetry based on SMPTE RP 431-2 */
+	{ DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
+	/* Colorimetry based on ITU-R BT.2020 */
+	{ DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+	{ DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
+	{ DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
+	/* Standard Definition Colorimetry based on IEC 61966-2-4 */
+	{ DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
+	/* High Definition Colorimetry based on IEC 61966-2-4 */
+	{ DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
+	/* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+	{ DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
+	/* Colorimetry based on IEC 61966-2-5 [33] */
+	{ DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
+	/* Colorimetry based on ITU-R BT.2020 */
+	{ DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+	/* Colorimetry based on ITU-R BT.2020 */
+	{ DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+	/*
+	 * Colorumetry based on Digital Imaging and Communications in Medicine
+	 * (DICOM) Part 14: Grayscale Standard Display Function
+	 */
+	{ DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE, "DICOM_Part_14_Grayscale" },
+};
+
 /**
  * DOC: standard connector properties
  *
@@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct drm_connector *connector)
 						ARRAY_SIZE(hdmi_colorspaces));
 		if (!prop)
 			return -ENOMEM;
+	} else if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+		   connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+		prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
+						"Colorspace",
+						dp_colorspaces,
+						ARRAY_SIZE(dp_colorspaces));
+		if (!prop)
+			return -ENOMEM;
 	} else {
 		DRM_DEBUG_KMS("Colorspace property not supported\n");
 		return 0;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 681cb590f952..8848e5d6b0c4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -281,6 +281,14 @@ enum drm_panel_orientation {
 /* Additional Colorimetry extension added as part of CTA 861.G */
 #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65		11
 #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER		12
+/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
+#define DRM_MODE_COLORIMETRY_SRGB			13
+#define DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB	14
+#define DRM_MODE_COLORIMETRY_SCRGB			15
+#define DRM_MODE_COLORIMETRY_ADOBE_RGB			16
+#define DRM_MODE_COLORIMETRY_DCP_P3_RGB			17
+#define DRM_MODE_COLORIMETRY_BT601_YCC			18
+#define DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE	19
 
 /**
  * enum drm_bus_flags - bus_flags info for &drm_display_info
-- 
2.23.0

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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ilia Mirkin]

So how would this work with a DP++ connector? Should it list the HDMI
or DP properties? Or do we need a custom property checker which is
aware of what is currently plugged in to validate the values?

On Tue, Sep 3, 2019 at 5:12 AM Gwan-gyeong Mun
<gwan-gyeong.mun@intel.com> wrote:
>
> In order to use colorspace property to Display Port connectors, it extends
> DRM_MODE_CONNECTOR_DisplayPort connector_type on
> drm_mode_create_colorspace_property function.
>
> v3: Addressed review comments from Ville
>     - Add new colorimetry options for DP 1.4a spec.
>     - Separate set of colorimetry enum values for DP.
> v4: Add additional comments to struct drm_prop_enum_list.
>     Polishing an enum string of struct drm_prop_enum_list
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/drm_connector.c | 46 +++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h     |  8 ++++++
>  2 files changed, 54 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 4c766624b20d..5834e6d330a0 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -882,6 +882,44 @@ static const struct drm_prop_enum_list hdmi_colorspaces[] = {
>         { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
>  };
>
> +/*
> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel Encoding/Colorimetry
> + * Format Table 2-120
> + */
> +static const struct drm_prop_enum_list dp_colorspaces[] = {
> +       /* For Default case, driver will set the colorspace */
> +       { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> +       /* Colorimetry based on IEC 61966-2-1 */
> +       { DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
> +       { DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB, "wide_gamut_fixed_point_RGB" },
> +       /* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB */
> +       { DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
> +       { DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
> +       /* Colorimetry based on SMPTE RP 431-2 */
> +       { DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
> +       /* Colorimetry based on ITU-R BT.2020 */
> +       { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
> +       { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
> +       { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
> +       /* Standard Definition Colorimetry based on IEC 61966-2-4 */
> +       { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
> +       /* High Definition Colorimetry based on IEC 61966-2-4 */
> +       { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
> +       /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
> +       { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
> +       /* Colorimetry based on IEC 61966-2-5 [33] */
> +       { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
> +       /* Colorimetry based on ITU-R BT.2020 */
> +       { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
> +       /* Colorimetry based on ITU-R BT.2020 */
> +       { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
> +       /*
> +        * Colorumetry based on Digital Imaging and Communications in Medicine
> +        * (DICOM) Part 14: Grayscale Standard Display Function
> +        */
> +       { DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE, "DICOM_Part_14_Grayscale" },
> +};
> +
>  /**
>   * DOC: standard connector properties
>   *
> @@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct drm_connector *connector)
>                                                 ARRAY_SIZE(hdmi_colorspaces));
>                 if (!prop)
>                         return -ENOMEM;
> +       } else if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> +                  connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> +               prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
> +                                               "Colorspace",
> +                                               dp_colorspaces,
> +                                               ARRAY_SIZE(dp_colorspaces));
> +               if (!prop)
> +                       return -ENOMEM;
>         } else {
>                 DRM_DEBUG_KMS("Colorspace property not supported\n");
>                 return 0;
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 681cb590f952..8848e5d6b0c4 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -281,6 +281,14 @@ enum drm_panel_orientation {
>  /* Additional Colorimetry extension added as part of CTA 861.G */
>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65            11
>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER                12
> +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
> +#define DRM_MODE_COLORIMETRY_SRGB                      13
> +#define DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB        14
> +#define DRM_MODE_COLORIMETRY_SCRGB                     15
> +#define DRM_MODE_COLORIMETRY_ADOBE_RGB                 16
> +#define DRM_MODE_COLORIMETRY_DCP_P3_RGB                        17
> +#define DRM_MODE_COLORIMETRY_BT601_YCC                 18
> +#define DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE   19
>
>  /**
>   * enum drm_bus_flags - bus_flags info for &drm_display_info
> --
> 2.23.0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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RE: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Shankar, Uma]

>-----Original Message-----
>From: Ilia Mirkin <imirkin@alum.mit.edu>
>Sent: Tuesday, September 3, 2019 6:12 PM
>To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
>Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Shankar, Uma
><uma.shankar@intel.com>; dri-devel <dri-devel@lists.freedesktop.org>
>Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
>
>So how would this work with a DP++ connector? Should it list the HDMI or DP
>properties? Or do we need a custom property checker which is aware of what is
>currently plugged in to validate the values?

AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI (with a passive dongle).
Based on the type of sink detected, we should expose DP or HDMI colorspaces to userspace.

>On Tue, Sep 3, 2019 at 5:12 AM Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>wrote:
>>
>> In order to use colorspace property to Display Port connectors, it
>> extends DRM_MODE_CONNECTOR_DisplayPort connector_type on
>> drm_mode_create_colorspace_property function.
>>
>> v3: Addressed review comments from Ville
>>     - Add new colorimetry options for DP 1.4a spec.
>>     - Separate set of colorimetry enum values for DP.
>> v4: Add additional comments to struct drm_prop_enum_list.
>>     Polishing an enum string of struct drm_prop_enum_list
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/drm_connector.c | 46 +++++++++++++++++++++++++++++++++
>>  include/drm/drm_connector.h     |  8 ++++++
>>  2 files changed, 54 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_connector.c
>> b/drivers/gpu/drm/drm_connector.c index 4c766624b20d..5834e6d330a0
>> 100644
>> --- a/drivers/gpu/drm/drm_connector.c
>> +++ b/drivers/gpu/drm/drm_connector.c
>> @@ -882,6 +882,44 @@ static const struct drm_prop_enum_list
>hdmi_colorspaces[] = {
>>         { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER,
>> "DCI-P3_RGB_Theater" },  };
>>
>> +/*
>> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
>> +Encoding/Colorimetry
>> + * Format Table 2-120
>> + */
>> +static const struct drm_prop_enum_list dp_colorspaces[] = {
>> +       /* For Default case, driver will set the colorspace */
>> +       { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
>> +       /* Colorimetry based on IEC 61966-2-1 */
>> +       { DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
>> +       { DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB,
>"wide_gamut_fixed_point_RGB" },
>> +       /* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB */
>> +       { DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
>> +       { DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
>> +       /* Colorimetry based on SMPTE RP 431-2 */
>> +       { DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
>> +       /* Colorimetry based on ITU-R BT.2020 */
>> +       { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
>> +       { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
>> +       { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
>> +       /* Standard Definition Colorimetry based on IEC 61966-2-4 */
>> +       { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
>> +       /* High Definition Colorimetry based on IEC 61966-2-4 */
>> +       { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
>> +       /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
>> +       { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
>> +       /* Colorimetry based on IEC 61966-2-5 [33] */
>> +       { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
>> +       /* Colorimetry based on ITU-R BT.2020 */
>> +       { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
>> +       /* Colorimetry based on ITU-R BT.2020 */
>> +       { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
>> +       /*
>> +        * Colorumetry based on Digital Imaging and Communications in Medicine
>> +        * (DICOM) Part 14: Grayscale Standard Display Function
>> +        */
>> +       { DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE,
>> +"DICOM_Part_14_Grayscale" }, };
>> +
>>  /**
>>   * DOC: standard connector properties
>>   *
>> @@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct
>drm_connector *connector)
>>                                                 ARRAY_SIZE(hdmi_colorspaces));
>>                 if (!prop)
>>                         return -ENOMEM;
>> +       } else if (connector->connector_type ==
>DRM_MODE_CONNECTOR_DisplayPort ||
>> +                  connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>> +               prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
>> +                                               "Colorspace",
>> +                                               dp_colorspaces,
>> +                                               ARRAY_SIZE(dp_colorspaces));
>> +               if (!prop)
>> +                       return -ENOMEM;
>>         } else {
>>                 DRM_DEBUG_KMS("Colorspace property not supported\n");
>>                 return 0;
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
>> index 681cb590f952..8848e5d6b0c4 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -281,6 +281,14 @@ enum drm_panel_orientation {
>>  /* Additional Colorimetry extension added as part of CTA 861.G */
>>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65            11
>>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER                12
>> +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
>> +#define DRM_MODE_COLORIMETRY_SRGB                      13
>> +#define DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB        14
>> +#define DRM_MODE_COLORIMETRY_SCRGB                     15
>> +#define DRM_MODE_COLORIMETRY_ADOBE_RGB                 16
>> +#define DRM_MODE_COLORIMETRY_DCP_P3_RGB                        17
>> +#define DRM_MODE_COLORIMETRY_BT601_YCC                 18
>> +#define DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE   19
>>
>>  /**
>>   * enum drm_bus_flags - bus_flags info for &drm_display_info
>> --
>> 2.23.0
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ville Syrjälä]

On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ilia Mirkin <imirkin@alum.mit.edu>
> >Sent: Tuesday, September 3, 2019 6:12 PM
> >To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> >Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Shankar, Uma
> ><uma.shankar@intel.com>; dri-devel <dri-devel@lists.freedesktop.org>
> >Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
> >
> >So how would this work with a DP++ connector? Should it list the HDMI or DP
> >properties? Or do we need a custom property checker which is aware of what is
> >currently plugged in to validate the values?
> 
> AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI (with a passive dongle).
> Based on the type of sink detected, we should expose DP or HDMI colorspaces to userspace.

For i915 DP connector always drives DP mode, HDMI connector always drives
HDMI mode, even when the physical connector is DP++.

> 
> >On Tue, Sep 3, 2019 at 5:12 AM Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> >wrote:
> >>
> >> In order to use colorspace property to Display Port connectors, it
> >> extends DRM_MODE_CONNECTOR_DisplayPort connector_type on
> >> drm_mode_create_colorspace_property function.
> >>
> >> v3: Addressed review comments from Ville
> >>     - Add new colorimetry options for DP 1.4a spec.
> >>     - Separate set of colorimetry enum values for DP.
> >> v4: Add additional comments to struct drm_prop_enum_list.
> >>     Polishing an enum string of struct drm_prop_enum_list
> >> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> >> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >>  drivers/gpu/drm/drm_connector.c | 46 +++++++++++++++++++++++++++++++++
> >>  include/drm/drm_connector.h     |  8 ++++++
> >>  2 files changed, 54 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_connector.c
> >> b/drivers/gpu/drm/drm_connector.c index 4c766624b20d..5834e6d330a0
> >> 100644
> >> --- a/drivers/gpu/drm/drm_connector.c
> >> +++ b/drivers/gpu/drm/drm_connector.c
> >> @@ -882,6 +882,44 @@ static const struct drm_prop_enum_list
> >hdmi_colorspaces[] = {
> >>         { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER,
> >> "DCI-P3_RGB_Theater" },  };
> >>
> >> +/*
> >> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
> >> +Encoding/Colorimetry
> >> + * Format Table 2-120
> >> + */
> >> +static const struct drm_prop_enum_list dp_colorspaces[] = {
> >> +       /* For Default case, driver will set the colorspace */
> >> +       { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> >> +       /* Colorimetry based on IEC 61966-2-1 */
> >> +       { DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
> >> +       { DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB,
> >"wide_gamut_fixed_point_RGB" },
> >> +       /* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB */
> >> +       { DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
> >> +       { DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
> >> +       /* Colorimetry based on SMPTE RP 431-2 */
> >> +       { DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
> >> +       /* Colorimetry based on ITU-R BT.2020 */
> >> +       { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
> >> +       { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
> >> +       { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
> >> +       /* Standard Definition Colorimetry based on IEC 61966-2-4 */
> >> +       { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
> >> +       /* High Definition Colorimetry based on IEC 61966-2-4 */
> >> +       { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
> >> +       /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
> >> +       { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
> >> +       /* Colorimetry based on IEC 61966-2-5 [33] */
> >> +       { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
> >> +       /* Colorimetry based on ITU-R BT.2020 */
> >> +       { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
> >> +       /* Colorimetry based on ITU-R BT.2020 */
> >> +       { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
> >> +       /*
> >> +        * Colorumetry based on Digital Imaging and Communications in Medicine
> >> +        * (DICOM) Part 14: Grayscale Standard Display Function
> >> +        */
> >> +       { DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE,
> >> +"DICOM_Part_14_Grayscale" }, };
> >> +
> >>  /**
> >>   * DOC: standard connector properties
> >>   *
> >> @@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct
> >drm_connector *connector)
> >>                                                 ARRAY_SIZE(hdmi_colorspaces));
> >>                 if (!prop)
> >>                         return -ENOMEM;
> >> +       } else if (connector->connector_type ==
> >DRM_MODE_CONNECTOR_DisplayPort ||
> >> +                  connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> >> +               prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
> >> +                                               "Colorspace",
> >> +                                               dp_colorspaces,
> >> +                                               ARRAY_SIZE(dp_colorspaces));
> >> +               if (!prop)
> >> +                       return -ENOMEM;
> >>         } else {
> >>                 DRM_DEBUG_KMS("Colorspace property not supported\n");
> >>                 return 0;
> >> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> >> index 681cb590f952..8848e5d6b0c4 100644
> >> --- a/include/drm/drm_connector.h
> >> +++ b/include/drm/drm_connector.h
> >> @@ -281,6 +281,14 @@ enum drm_panel_orientation {
> >>  /* Additional Colorimetry extension added as part of CTA 861.G */
> >>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65            11
> >>  #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER                12
> >> +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
> >> +#define DRM_MODE_COLORIMETRY_SRGB                      13
> >> +#define DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB        14
> >> +#define DRM_MODE_COLORIMETRY_SCRGB                     15
> >> +#define DRM_MODE_COLORIMETRY_ADOBE_RGB                 16
> >> +#define DRM_MODE_COLORIMETRY_DCP_P3_RGB                        17
> >> +#define DRM_MODE_COLORIMETRY_BT601_YCC                 18
> >> +#define DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE   19
> >>
> >>  /**
> >>   * enum drm_bus_flags - bus_flags info for &drm_display_info
> >> --
> >> 2.23.0
> >>
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ilia Mirkin]

On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> >
> >
> > >-----Original Message-----
> > >From: Ilia Mirkin <imirkin@alum.mit.edu>
> > >Sent: Tuesday, September 3, 2019 6:12 PM
> > >To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > >Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Shankar, Uma
> > ><uma.shankar@intel.com>; dri-devel <dri-devel@lists.freedesktop.org>
> > >Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
> > >
> > >So how would this work with a DP++ connector? Should it list the HDMI or DP
> > >properties? Or do we need a custom property checker which is aware of what is
> > >currently plugged in to validate the values?
> >
> > AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI (with a passive dongle).
> > Based on the type of sink detected, we should expose DP or HDMI colorspaces to userspace.
>
> For i915 DP connector always drives DP mode, HDMI connector always drives
> HDMI mode, even when the physical connector is DP++.

Right, i915 creates 2 connectors, while nouveau, radeon, and amdgpu
create 1 connector (not sure about other drivers) for a single
physical DP++ socket. Since we supply the list of valid values at the
time of creating the connector, we can't know at that point whether in
the future a HDMI or DP will be plugged into it.

  -ilia
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Mun, Gwan-gyeong]

On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > 
> > > > -----Original Message-----
> > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org
> > > > >; Shankar, Uma
> > > > <uma.shankar@intel.com>; dri-devel <
> > > > dri-devel@lists.freedesktop.org>
> > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > property
> > > > 
> > > > So how would this work with a DP++ connector? Should it list
> > > > the HDMI or DP
> > > > properties? Or do we need a custom property checker which is
> > > > aware of what is
> > > > currently plugged in to validate the values?
> > > 
> > > AFAIU For DP++ cases, we detect what kind of sink its driving DP
> > > or HDMI (with a passive dongle).
> > > Based on the type of sink detected, we should expose DP or HDMI
> > > colorspaces to userspace.
> > 
> > For i915 DP connector always drives DP mode, HDMI connector always
> > drives
> > HDMI mode, even when the physical connector is DP++.
> 
> Right, i915 creates 2 connectors, while nouveau, radeon, and amdgpu
> create 1 connector (not sure about other drivers) for a single
> physical DP++ socket. Since we supply the list of valid values at the
> time of creating the connector, we can't know at that point whether
> in
> the future a HDMI or DP will be plugged into it.
> 
>   -ilia
Ilia, does it mean that the drm_connector type is
DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?

And Ville and Uma,  when we are useing dp active dongle (DP to HDMI
dongle and DP branch device is HDMI) should we expose HDMI colorspace?

-G.G.
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ilia Mirkin]

On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
<gwan-gyeong.mun@intel.com> wrote:
>
> On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > <ville.syrjala@linux.intel.com> wrote:
> > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > >
> > > > > -----Original Message-----
> > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org
> > > > > >; Shankar, Uma
> > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > dri-devel@lists.freedesktop.org>
> > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > property
> > > > >
> > > > > So how would this work with a DP++ connector? Should it list
> > > > > the HDMI or DP
> > > > > properties? Or do we need a custom property checker which is
> > > > > aware of what is
> > > > > currently plugged in to validate the values?
> > > >
> > > > AFAIU For DP++ cases, we detect what kind of sink its driving DP
> > > > or HDMI (with a passive dongle).
> > > > Based on the type of sink detected, we should expose DP or HDMI
> > > > colorspaces to userspace.
> > >
> > > For i915 DP connector always drives DP mode, HDMI connector always
> > > drives
> > > HDMI mode, even when the physical connector is DP++.
> >
> > Right, i915 creates 2 connectors, while nouveau, radeon, and amdgpu
> > create 1 connector (not sure about other drivers) for a single
> > physical DP++ socket. Since we supply the list of valid values at the
> > time of creating the connector, we can't know at that point whether
> > in
> > the future a HDMI or DP will be plugged into it.
> >
> >   -ilia
> Ilia, does it mean that the drm_connector type is
> DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?

That is correct. The connector type is "DisplayPort" in such a case.

Cheers,

  -ilia
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Mun, Gwan-gyeong]

On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> <gwan-gyeong.mun@intel.com> wrote:
> > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > <ville.syrjala@linux.intel.com> wrote:
> > > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > > > -----Original Message-----
> > > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > > Cc: Intel Graphics Development <
> > > > > > intel-gfx@lists.freedesktop.org
> > > > > > > ; Shankar, Uma
> > > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > > dri-devel@lists.freedesktop.org>
> > > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > > property
> > > > > > 
> > > > > > So how would this work with a DP++ connector? Should it
> > > > > > list
> > > > > > the HDMI or DP
> > > > > > properties? Or do we need a custom property checker which
> > > > > > is
> > > > > > aware of what is
> > > > > > currently plugged in to validate the values?
> > > > > 
> > > > > AFAIU For DP++ cases, we detect what kind of sink its driving
> > > > > DP
> > > > > or HDMI (with a passive dongle).
> > > > > Based on the type of sink detected, we should expose DP or
> > > > > HDMI
> > > > > colorspaces to userspace.
> > > > 
> > > > For i915 DP connector always drives DP mode, HDMI connector
> > > > always
> > > > drives
> > > > HDMI mode, even when the physical connector is DP++.
> > > 
> > > Right, i915 creates 2 connectors, while nouveau, radeon, and
> > > amdgpu
> > > create 1 connector (not sure about other drivers) for a single
> > > physical DP++ socket. Since we supply the list of valid values at
> > > the
> > > time of creating the connector, we can't know at that point
> > > whether
> > > in
> > > the future a HDMI or DP will be plugged into it.
> > > 
> > >   -ilia
> > Ilia, does it mean that the drm_connector type is
> > DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> 
> That is correct. The connector type is "DisplayPort" in such a case.
> 
> Cheers,
> 
>   -ilia

For now drm_mode_create_colorspace_property() is only used for i915.
IMHO, when other drivers ( nouveau, radeon, and amdgpu ) are ready for
using of drm_mode_create_colorspace_property(),
what about do we add a variable which can identify DP++ and DP to
drm_connector?
And when the drivers (nouveau, radeon, and amdgpu) detect the current
protocol, the drivers will set the variable.

Br,
- G.G.
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ville Syrjälä]

On Tue, Sep 10, 2019 at 07:34:31AM +0000, Mun, Gwan-gyeong wrote:
> On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > <gwan-gyeong.mun@intel.com> wrote:
> > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > > <ville.syrjala@linux.intel.com> wrote:
> > > > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > > > > -----Original Message-----
> > > > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > > > Cc: Intel Graphics Development <
> > > > > > > intel-gfx@lists.freedesktop.org
> > > > > > > > ; Shankar, Uma
> > > > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > > > dri-devel@lists.freedesktop.org>
> > > > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > > > property
> > > > > > > 
> > > > > > > So how would this work with a DP++ connector? Should it
> > > > > > > list
> > > > > > > the HDMI or DP
> > > > > > > properties? Or do we need a custom property checker which
> > > > > > > is
> > > > > > > aware of what is
> > > > > > > currently plugged in to validate the values?
> > > > > > 
> > > > > > AFAIU For DP++ cases, we detect what kind of sink its driving
> > > > > > DP
> > > > > > or HDMI (with a passive dongle).
> > > > > > Based on the type of sink detected, we should expose DP or
> > > > > > HDMI
> > > > > > colorspaces to userspace.
> > > > > 
> > > > > For i915 DP connector always drives DP mode, HDMI connector
> > > > > always
> > > > > drives
> > > > > HDMI mode, even when the physical connector is DP++.
> > > > 
> > > > Right, i915 creates 2 connectors, while nouveau, radeon, and
> > > > amdgpu
> > > > create 1 connector (not sure about other drivers) for a single
> > > > physical DP++ socket. Since we supply the list of valid values at
> > > > the
> > > > time of creating the connector, we can't know at that point
> > > > whether
> > > > in
> > > > the future a HDMI or DP will be plugged into it.
> > > > 
> > > >   -ilia
> > > Ilia, does it mean that the drm_connector type is
> > > DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> > 
> > That is correct. The connector type is "DisplayPort" in such a case.
> > 
> > Cheers,
> > 
> >   -ilia
> 
> For now drm_mode_create_colorspace_property() is only used for i915.
> IMHO, when other drivers ( nouveau, radeon, and amdgpu ) are ready for
> using of drm_mode_create_colorspace_property(),
> what about do we add a variable which can identify DP++ and DP to
> drm_connector?
> And when the drivers (nouveau, radeon, and amdgpu) detect the current
> protocol, the drivers will set the variable.

IMO better to just have two functions in that case: one for DP, another
for HDMI.

-- 
Ville Syrjälä
Intel
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ilia Mirkin]

On Tue, Sep 10, 2019 at 3:34 AM Mun, Gwan-gyeong
<gwan-gyeong.mun@intel.com> wrote:
>
> On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > <gwan-gyeong.mun@intel.com> wrote:
> > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > > <ville.syrjala@linux.intel.com> wrote:
> > > > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > > > > -----Original Message-----
> > > > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > > > Cc: Intel Graphics Development <
> > > > > > > intel-gfx@lists.freedesktop.org
> > > > > > > > ; Shankar, Uma
> > > > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > > > dri-devel@lists.freedesktop.org>
> > > > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > > > property
> > > > > > >
> > > > > > > So how would this work with a DP++ connector? Should it
> > > > > > > list
> > > > > > > the HDMI or DP
> > > > > > > properties? Or do we need a custom property checker which
> > > > > > > is
> > > > > > > aware of what is
> > > > > > > currently plugged in to validate the values?
> > > > > >
> > > > > > AFAIU For DP++ cases, we detect what kind of sink its driving
> > > > > > DP
> > > > > > or HDMI (with a passive dongle).
> > > > > > Based on the type of sink detected, we should expose DP or
> > > > > > HDMI
> > > > > > colorspaces to userspace.
> > > > >
> > > > > For i915 DP connector always drives DP mode, HDMI connector
> > > > > always
> > > > > drives
> > > > > HDMI mode, even when the physical connector is DP++.
> > > >
> > > > Right, i915 creates 2 connectors, while nouveau, radeon, and
> > > > amdgpu
> > > > create 1 connector (not sure about other drivers) for a single
> > > > physical DP++ socket. Since we supply the list of valid values at
> > > > the
> > > > time of creating the connector, we can't know at that point
> > > > whether
> > > > in
> > > > the future a HDMI or DP will be plugged into it.
> > > >
> > > >   -ilia
> > > Ilia, does it mean that the drm_connector type is
> > > DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> >
> > That is correct. The connector type is "DisplayPort" in such a case.
> >
> > Cheers,
> >
> >   -ilia
>
> For now drm_mode_create_colorspace_property() is only used for i915.
> IMHO, when other drivers ( nouveau, radeon, and amdgpu ) are ready for
> using of drm_mode_create_colorspace_property(),
> what about do we add a variable which can identify DP++ and DP to
> drm_connector?
> And when the drivers (nouveau, radeon, and amdgpu) detect the current
> protocol, the drivers will set the variable.

I've been working on adding this to nouveau.

Can/should such properties be added/removed at "runtime", rather than
at connector creation time? Either way, the function
drm_mode_create_colorspace_property as proposed would not be reusable,
since it looks at the connector type, which will always be
"DisplayPort" in such cases.

  -ilia
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ilia Mirkin]

On Tue, Sep 10, 2019 at 9:21 AM Ilia Mirkin <imirkin@alum.mit.edu> wrote:
>
> On Tue, Sep 10, 2019 at 3:34 AM Mun, Gwan-gyeong
> <gwan-gyeong.mun@intel.com> wrote:
> >
> > On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > > <gwan-gyeong.mun@intel.com> wrote:
> > > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > > > <ville.syrjala@linux.intel.com> wrote:
> > > > > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > > > > > -----Original Message-----
> > > > > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > > > > Cc: Intel Graphics Development <
> > > > > > > > intel-gfx@lists.freedesktop.org
> > > > > > > > > ; Shankar, Uma
> > > > > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > > > > dri-devel@lists.freedesktop.org>
> > > > > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > > > > property
> > > > > > > >
> > > > > > > > So how would this work with a DP++ connector? Should it
> > > > > > > > list
> > > > > > > > the HDMI or DP
> > > > > > > > properties? Or do we need a custom property checker which
> > > > > > > > is
> > > > > > > > aware of what is
> > > > > > > > currently plugged in to validate the values?
> > > > > > >
> > > > > > > AFAIU For DP++ cases, we detect what kind of sink its driving
> > > > > > > DP
> > > > > > > or HDMI (with a passive dongle).
> > > > > > > Based on the type of sink detected, we should expose DP or
> > > > > > > HDMI
> > > > > > > colorspaces to userspace.
> > > > > >
> > > > > > For i915 DP connector always drives DP mode, HDMI connector
> > > > > > always
> > > > > > drives
> > > > > > HDMI mode, even when the physical connector is DP++.
> > > > >
> > > > > Right, i915 creates 2 connectors, while nouveau, radeon, and
> > > > > amdgpu
> > > > > create 1 connector (not sure about other drivers) for a single
> > > > > physical DP++ socket. Since we supply the list of valid values at
> > > > > the
> > > > > time of creating the connector, we can't know at that point
> > > > > whether
> > > > > in
> > > > > the future a HDMI or DP will be plugged into it.
> > > > >
> > > > >   -ilia
> > > > Ilia, does it mean that the drm_connector type is
> > > > DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> > >
> > > That is correct. The connector type is "DisplayPort" in such a case.
> > >
> > > Cheers,
> > >
> > >   -ilia
> >
> > For now drm_mode_create_colorspace_property() is only used for i915.
> > IMHO, when other drivers ( nouveau, radeon, and amdgpu ) are ready for
> > using of drm_mode_create_colorspace_property(),
> > what about do we add a variable which can identify DP++ and DP to
> > drm_connector?
> > And when the drivers (nouveau, radeon, and amdgpu) detect the current
> > protocol, the drivers will set the variable.
>
> I've been working on adding this to nouveau.
>
> Can/should such properties be added/removed at "runtime", rather than
> at connector creation time? Either way, the function
> drm_mode_create_colorspace_property as proposed would not be reusable,
> since it looks at the connector type, which will always be
> "DisplayPort" in such cases.

Summary of conversation Ville and I had on IRC:

 - DP++ connectors to provide a single combined list of options for colorspace
 - set_property hook will check against currently plugged in thing,
and reject incorrect values
 - in the case where someone sets e.g. an HDMI value for an
HDMI-plugged-in thing, and then unplugs, and then plugs in a DP
screen, the modeset should continue to succeed but use a default
colorspace value.

I think there was a bit of contention on that last point. Open to
opinions, but we should try to avoid putting undue burden on esp
non-atomic userspace.

Cheers,

  -ilia
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Ville Syrjälä]

On Sat, Sep 07, 2019 at 11:19:55PM +0000, Mun, Gwan-gyeong wrote:
> On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > <ville.syrjala@linux.intel.com> wrote:
> > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > 
> > > > > -----Original Message-----
> > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org
> > > > > >; Shankar, Uma
> > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > dri-devel@lists.freedesktop.org>
> > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > property
> > > > > 
> > > > > So how would this work with a DP++ connector? Should it list
> > > > > the HDMI or DP
> > > > > properties? Or do we need a custom property checker which is
> > > > > aware of what is
> > > > > currently plugged in to validate the values?
> > > > 
> > > > AFAIU For DP++ cases, we detect what kind of sink its driving DP
> > > > or HDMI (with a passive dongle).
> > > > Based on the type of sink detected, we should expose DP or HDMI
> > > > colorspaces to userspace.
> > > 
> > > For i915 DP connector always drives DP mode, HDMI connector always
> > > drives
> > > HDMI mode, even when the physical connector is DP++.
> > 
> > Right, i915 creates 2 connectors, while nouveau, radeon, and amdgpu
> > create 1 connector (not sure about other drivers) for a single
> > physical DP++ socket. Since we supply the list of valid values at the
> > time of creating the connector, we can't know at that point whether
> > in
> > the future a HDMI or DP will be plugged into it.
> > 
> >   -ilia
> Ilia, does it mean that the drm_connector type is
> DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> 
> And Ville and Uma,  when we are useing dp active dongle (DP to HDMI
> dongle and DP branch device is HDMI) should we expose HDMI colorspace?

We still set it up via DP MSA/VSC no? In that case it should follow the
DP spec I think. LSPCON is probably different because we manually generate
the AVI infoframe for it. But I'm not sure how we're going to reconcile
that with the DP stuff we also set up for it.

-- 
Ville Syrjälä
Intel
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Mun, Gwan-gyeong]

On Mon, 2019-09-09 at 13:25 +0300, Ville Syrjälä wrote:
> On Sat, Sep 07, 2019 at 11:19:55PM +0000, Mun, Gwan-gyeong wrote:
> > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > > <ville.syrjala@linux.intel.com> wrote:
> > > > On Fri, Sep 06, 2019 at 11:31:55AM +0000, Shankar, Uma wrote:
> > > > > > -----Original Message-----
> > > > > > From: Ilia Mirkin <imirkin@alum.mit.edu>
> > > > > > Sent: Tuesday, September 3, 2019 6:12 PM
> > > > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
> > > > > > Cc: Intel Graphics Development <
> > > > > > intel-gfx@lists.freedesktop.org
> > > > > > > ; Shankar, Uma
> > > > > > <uma.shankar@intel.com>; dri-devel <
> > > > > > dri-devel@lists.freedesktop.org>
> > > > > > Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace
> > > > > > property
> > > > > > 
> > > > > > So how would this work with a DP++ connector? Should it
> > > > > > list
> > > > > > the HDMI or DP
> > > > > > properties? Or do we need a custom property checker which
> > > > > > is
> > > > > > aware of what is
> > > > > > currently plugged in to validate the values?
> > > > > 
> > > > > AFAIU For DP++ cases, we detect what kind of sink its driving
> > > > > DP
> > > > > or HDMI (with a passive dongle).
> > > > > Based on the type of sink detected, we should expose DP or
> > > > > HDMI
> > > > > colorspaces to userspace.
> > > > 
> > > > For i915 DP connector always drives DP mode, HDMI connector
> > > > always
> > > > drives
> > > > HDMI mode, even when the physical connector is DP++.
> > > 
> > > Right, i915 creates 2 connectors, while nouveau, radeon, and
> > > amdgpu
> > > create 1 connector (not sure about other drivers) for a single
> > > physical DP++ socket. Since we supply the list of valid values at
> > > the
> > > time of creating the connector, we can't know at that point
> > > whether
> > > in
> > > the future a HDMI or DP will be plugged into it.
> > > 
> > >   -ilia
> > Ilia, does it mean that the drm_connector type is
> > DRM_MODE_CONNECTOR_DisplayPort and protocol is DP++ mode?
> > 
> > And Ville and Uma,  when we are useing dp active dongle (DP to HDMI
> > dongle and DP branch device is HDMI) should we expose HDMI
> > colorspace?
> 
> We still set it up via DP MSA/VSC no? In that case it should follow
> the
> DP spec I think. LSPCON is probably different because we manually 
Yes, I agree too. 

- G.G.
> generate
> the AVI infoframe for it. But I'm not sure how we're going to
> reconcile
> that with the DP stuff we also set up for it.
> 
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Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property

[Shankar, Uma]

>-----Original Message-----
>From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
>gyeong Mun
>Sent: Tuesday, September 3, 2019 2:43 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; dri-devel@lists.freedesktop.org
>Subject: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
>
>In order to use colorspace property to Display Port connectors, it extends
>DRM_MODE_CONNECTOR_DisplayPort connector_type on
>drm_mode_create_colorspace_property function.
>
>v3: Addressed review comments from Ville
>    - Add new colorimetry options for DP 1.4a spec.
>    - Separate set of colorimetry enum values for DP.

Thanks Ville for spotting this and Gwan-gyeong Mun for fixing it.
Somehow missed this in my first scan.

>v4: Add additional comments to struct drm_prop_enum_list.
>    Polishing an enum string of struct drm_prop_enum_list
>Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>---
> drivers/gpu/drm/drm_connector.c | 46 +++++++++++++++++++++++++++++++++
> include/drm/drm_connector.h     |  8 ++++++
> 2 files changed, 54 insertions(+)
>
>diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
>index 4c766624b20d..5834e6d330a0 100644
>--- a/drivers/gpu/drm/drm_connector.c
>+++ b/drivers/gpu/drm/drm_connector.c
>@@ -882,6 +882,44 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
>= {
> 	{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-
>P3_RGB_Theater" },  };
>
>+/*
>+ * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
>+Encoding/Colorimetry
>+ * Format Table 2-120
>+ */
>+static const struct drm_prop_enum_list dp_colorspaces[] = {
>+	/* For Default case, driver will set the colorspace */
>+	{ DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
>+	/* Colorimetry based on IEC 61966-2-1 */
>+	{ DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
>+	{ DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB,
>"wide_gamut_fixed_point_RGB" },
>+	/* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB */
>+	{ DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
>+	{ DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
>+	/* Colorimetry based on SMPTE RP 431-2 */
>+	{ DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
>+	/* Colorimetry based on ITU-R BT.2020 */
>+	{ DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
>+	{ DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
>+	{ DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
>+	/* Standard Definition Colorimetry based on IEC 61966-2-4 */
>+	{ DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
>+	/* High Definition Colorimetry based on IEC 61966-2-4 */
>+	{ DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
>+	/* Colorimetry based on IEC 61966-2-1/Amendment 1 */
>+	{ DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
>+	/* Colorimetry based on IEC 61966-2-5 [33] */
>+	{ DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
>+	/* Colorimetry based on ITU-R BT.2020 */
>+	{ DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
>+	/* Colorimetry based on ITU-R BT.2020 */
>+	{ DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
>+	/*
>+	 * Colorumetry based on Digital Imaging and Communications in Medicine

Typo here.

>+	 * (DICOM) Part 14: Grayscale Standard Display Function
>+	 */
>+	{ DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE,
>+"DICOM_Part_14_Grayscale" }, };
>+
> /**
>  * DOC: standard connector properties
>  *
>@@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct
>drm_connector *connector)
> 						ARRAY_SIZE(hdmi_colorspaces));
> 		if (!prop)
> 			return -ENOMEM;
>+	} else if (connector->connector_type ==
>DRM_MODE_CONNECTOR_DisplayPort ||
>+		   connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>+		prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
>+						"Colorspace",
>+						dp_colorspaces,
>+						ARRAY_SIZE(dp_colorspaces));
>+		if (!prop)
>+			return -ENOMEM;
> 	} else {
> 		DRM_DEBUG_KMS("Colorspace property not supported\n");
> 		return 0;
>diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
>681cb590f952..8848e5d6b0c4 100644
>--- a/include/drm/drm_connector.h
>+++ b/include/drm/drm_connector.h
>@@ -281,6 +281,14 @@ enum drm_panel_orientation {
> /* Additional Colorimetry extension added as part of CTA 861.G */
> #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65		11
> #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER		12
>+/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
>+#define DRM_MODE_COLORIMETRY_SRGB			13
>+#define DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB	14
>+#define DRM_MODE_COLORIMETRY_SCRGB			15
>+#define DRM_MODE_COLORIMETRY_ADOBE_RGB			16

I feel we can re-use the OPRGB version of HDMI to define the ADOBE_RGB.  My
understanding is they should be the same. Someone please correct me if that’s not
the case.

>+#define DRM_MODE_COLORIMETRY_DCP_P3_RGB			17

Same for DCI_P3 we can re-use the DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65.

>+#define DRM_MODE_COLORIMETRY_BT601_YCC			18
>+#define DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE	19
>
> /**
>  * enum drm_bus_flags - bus_flags info for &drm_display_info
>--
>2.23.0
>
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[PATCH v4 4/7] drm/i915/dp: Attach colorspace property

[Gwan-gyeong Mun]

It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.

Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT2020 on a
sink device.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6b7587c71e49..9fa107d720ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6445,6 +6445,8 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 	else if (INTEL_GEN(dev_priv) >= 5)
 		drm_connector_attach_max_bpc_property(connector, 6, 12);
 
+	intel_attach_colorspace_property(connector);
+
 	if (intel_dp_is_edp(intel_dp)) {
 		u32 allowed_scalers;
 
-- 
2.23.0

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[PATCH v4 5/7] drm/i915: Add new GMP register size for GEN11

[Gwan-gyeong Mun]

According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Uma's review comments.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++--
 drivers/gpu/drm/i915/i915_reg.h           |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c500fc9154c8..287999b31217 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -189,13 +189,19 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
-static int hsw_dip_data_size(unsigned int type)
+static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
+			     unsigned int type)
 {
 	switch (type) {
 	case DP_SDP_VSC:
 		return VIDEO_DIP_VSC_DATA_SIZE;
 	case DP_SDP_PPS:
 		return VIDEO_DIP_PPS_DATA_SIZE;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		if (INTEL_GEN(dev_priv) >= 11)
+			return VIDEO_DIP_GMP_DATA_SIZE;
+		else
+			return VIDEO_DIP_DATA_SIZE;
 	default:
 		return VIDEO_DIP_DATA_SIZE;
 	}
@@ -514,7 +520,7 @@ static void hsw_write_infoframe(struct intel_encoder *encoder,
 	int i;
 	u32 val = I915_READ(ctl_reg);
 
-	data_size = hsw_dip_data_size(type);
+	data_size = hsw_dip_data_size(dev_priv, type);
 
 	val &= ~hsw_infoframe_enable(type);
 	I915_WRITE(ctl_reg, val);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c43b8c583bb..8b31ad7426d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4667,6 +4667,7 @@ enum {
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE	32
+#define   VIDEO_DIP_GMP_DATA_SIZE	36
 #define   VIDEO_DIP_VSC_DATA_SIZE	36
 #define   VIDEO_DIP_PPS_DATA_SIZE	132
 #define VIDEO_DIP_CTL		_MMIO(0x61170)
-- 
2.23.0

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RE: [PATCH v4 5/7] drm/i915: Add new GMP register size for GEN11

[Shankar, Uma]

>-----Original Message-----
>From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-
>gyeong Mun
>Sent: Tuesday, September 3, 2019 2:43 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; dri-devel@lists.freedesktop.org
>Subject: [PATCH v4 5/7] drm/i915: Add new GMP register size for GEN11
>
>According to Bspec, GEN11 and prior GEN11 have different register size for HDR
>Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
>GEN11. And it makes handle different register size for
>HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
>platforms. It addresses Uma's review comments.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++--
> drivers/gpu/drm/i915/i915_reg.h           |  1 +
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
>b/drivers/gpu/drm/i915/display/intel_hdmi.c
>index c500fc9154c8..287999b31217 100644
>--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>@@ -189,13 +189,19 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> 	}
> }
>
>-static int hsw_dip_data_size(unsigned int type)
>+static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
>+			     unsigned int type)
> {
> 	switch (type) {
> 	case DP_SDP_VSC:
> 		return VIDEO_DIP_VSC_DATA_SIZE;
> 	case DP_SDP_PPS:
> 		return VIDEO_DIP_PPS_DATA_SIZE;
>+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			return VIDEO_DIP_GMP_DATA_SIZE;
>+		else
>+			return VIDEO_DIP_DATA_SIZE;
> 	default:
> 		return VIDEO_DIP_DATA_SIZE;
> 	}
>@@ -514,7 +520,7 @@ static void hsw_write_infoframe(struct intel_encoder
>*encoder,
> 	int i;
> 	u32 val = I915_READ(ctl_reg);
>
>-	data_size = hsw_dip_data_size(type);
>+	data_size = hsw_dip_data_size(dev_priv, type);
>
> 	val &= ~hsw_infoframe_enable(type);
> 	I915_WRITE(ctl_reg, val);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>6c43b8c583bb..8b31ad7426d6 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4667,6 +4667,7 @@ enum {
>  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
>  * of the infoframe structure specified by CEA-861. */
> #define   VIDEO_DIP_DATA_SIZE	32
>+#define   VIDEO_DIP_GMP_DATA_SIZE	36
> #define   VIDEO_DIP_VSC_DATA_SIZE	36
> #define   VIDEO_DIP_PPS_DATA_SIZE	132
> #define VIDEO_DIP_CTL		_MMIO(0x61170)
>--
>2.23.0
>
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[PATCH v4 6/7] drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata

[Gwan-gyeong Mun]

Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
static HDR metadata. The HDR Metadata will be provided by userspace
compositors, based on blending policies and passed to the driver through
a blob property.

Because each of GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet, it adds and uses different register
size.

Setup Infoframe SDP header and data block in function
intel_dp_setup_hdr_metadata_infoframe_sdp for HDR Static Metadata as per
dp 1.4 spec and CTA-861-F spec.
As per DP 1.4 spec, 2.2.2.5 SDP Formats. It enables Dynamic Range and
Mastering Infoframe for HDR content, which is defined in CTA-861-F spec.
According to DP 1.4 spec and CEA-861-F spec Table 5, in order to transmit
static HDR metadata, we have to use Non-audio INFOFRAME SDP v1.3.

+--------------------------------+-------------------------------+
|      [ Packet Type Value ]     |       [ Packet Type ]         |
+--------------------------------+-------------------------------+
| 80h + Non-audio INFOFRAME Type | CEA-861-F Non-audio INFOFRAME |
+--------------------------------+-------------------------------+
|      [Transmission Timing]                                     |
+----------------------------------------------------------------+
| As per CEA-861-F for INFOFRAME, including CEA-861.3 within     |
| which Dynamic Range and Mastering INFOFRAME are defined        |
+----------------------------------------------------------------+

v2: Add a missed blank line after function declaration.
v3: Remove not handled return values from
    intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c  | 89 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h  |  3 +
 3 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 87dc5a19cb7b..111a5c95be85 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3612,6 +3612,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
 	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9fa107d720ee..7fcc9f28d2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4596,6 +4596,83 @@ intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
 }
 
+static void
+intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state,
+					  const struct drm_connector_state *conn_state)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
+	struct dp_sdp infoframe_sdp = {};
+	struct hdmi_drm_infoframe drm_infoframe = {};
+	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
+	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+	ssize_t len;
+	int ret;
+
+	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
+	if (ret) {
+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+		return;
+	}
+
+	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
+	if (len < 0) {
+		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
+		return;
+	}
+
+	if (len != infoframe_size) {
+		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+		return;
+	}
+
+	/*
+	 * Set up the infoframe sdp packet for HDR static metadata.
+	 * Prepare VSC Header for SU as per DP 1.4a spec,
+	 * Table 2-100 and Table 2-101
+	 */
+
+	/* Packet ID, 00h for non-Audio INFOFRAME */
+	infoframe_sdp.sdp_header.HB0 = 0;
+	/*
+	 * Packet Type 80h + Non-audio INFOFRAME Type value
+	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
+	 */
+	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
+	/*
+	 * Least Significant Eight Bits of (Data Byte Count – 1)
+	 * infoframe_size - 1,
+	 */
+	infoframe_sdp.sdp_header.HB2 = 0x1D;
+	/* INFOFRAME SDP Version Number */
+	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+	infoframe_sdp.db[0] = drm_infoframe.version;
+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+	infoframe_sdp.db[1] = drm_infoframe.length;
+	/*
+	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
+	 * HDMI_INFOFRAME_HEADER_SIZE
+	 */
+	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
+	       HDMI_DRM_INFOFRAME_SIZE);
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		intel_dig_port->write_infoframe(&intel_dig_port->base,
+						crtc_state,
+						HDMI_PACKET_TYPE_GAMUT_METADATA,
+						&infoframe_sdp,
+						VIDEO_DIP_GMP_DATA_SIZE);
+	else
+		/* Prior to GEN11, Header size: 4 bytes, Data size: 28 bytes */
+		intel_dig_port->write_infoframe(&intel_dig_port->base,
+						crtc_state,
+						HDMI_PACKET_TYPE_GAMUT_METADATA,
+						&infoframe_sdp,
+						VIDEO_DIP_DATA_SIZE);
+}
+
 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state)
@@ -4606,6 +4683,18 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
 }
 
+void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state)
+{
+	if (!conn_state->hdr_output_metadata)
+		return;
+
+	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
+						  crtc_state,
+						  conn_state);
+}
+
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 87883d0d5977..5613073d1dd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -116,6 +116,9 @@ bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state);
 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state);
+void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct drm_connector_state *conn_state);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
-- 
2.23.0

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RE: [PATCH v4 6/7] drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata

[Shankar, Uma]

>-----Original Message-----
>From: Mun, Gwan-gyeong
>Sent: Tuesday, September 3, 2019 2:43 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>Sharma, Shashank <shashank.sharma@intel.com>; ville.syrjala@linux.intel.com
>Subject: [PATCH v4 6/7] drm/i915/dp: Program an Infoframe SDP Header and DB for
>HDR Static Metadata
>
>Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
>header and data block setup for HDR Static Metadata. It enables writing of HDR
>metadata infoframe SDP to panel. Support for HDR video was introduced in
>DisplayPort 1.4. It implements the CTA-861-G standard for transport of static HDR
>metadata. The HDR Metadata will be provided by userspace compositors, based on
>blending policies and passed to the driver through a blob property.
>
>Because each of GEN11 and prior GEN11 have different register size for HDR
>Metadata Infoframe SDP packet, it adds and uses different register size.
>
>Setup Infoframe SDP header and data block in function
>intel_dp_setup_hdr_metadata_infoframe_sdp for HDR Static Metadata as per dp 1.4
>spec and CTA-861-F spec.
>As per DP 1.4 spec, 2.2.2.5 SDP Formats. It enables Dynamic Range and Mastering
>Infoframe for HDR content, which is defined in CTA-861-F spec.
>According to DP 1.4 spec and CEA-861-F spec Table 5, in order to transmit static HDR
>metadata, we have to use Non-audio INFOFRAME SDP v1.3.
>
>+--------------------------------+-------------------------------+
>|      [ Packet Type Value ]     |       [ Packet Type ]         |
>+--------------------------------+-------------------------------+
>| 80h + Non-audio INFOFRAME Type | CEA-861-F Non-audio INFOFRAME |
>+--------------------------------+-------------------------------+
>|      [Transmission Timing]                                     |
>+----------------------------------------------------------------+
>| As per CEA-861-F for INFOFRAME, including CEA-861.3 within     |
>| which Dynamic Range and Mastering INFOFRAME are defined        |
>+----------------------------------------------------------------+
>
>v2: Add a missed blank line after function declaration.
>v3: Remove not handled return values from
>    intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c |  1 +
>drivers/gpu/drm/i915/display/intel_dp.c  | 89 ++++++++++++++++++++++++
>drivers/gpu/drm/i915/display/intel_dp.h  |  3 +
> 3 files changed, 93 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 87dc5a19cb7b..111a5c95be85 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3612,6 +3612,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
>*encoder,
> 	intel_edp_backlight_on(crtc_state, conn_state);
> 	intel_psr_enable(intel_dp, crtc_state);
> 	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
>+	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> 	intel_edp_drrs_enable(intel_dp, crtc_state);
>
> 	if (crtc_state->has_audio)
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>b/drivers/gpu/drm/i915/display/intel_dp.c
>index 9fa107d720ee..7fcc9f28d2e7 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.c
>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>@@ -4596,6 +4596,83 @@ intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> 			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));  }
>
>+static void
>+intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
>+					  const struct intel_crtc_state *crtc_state,
>+					  const struct drm_connector_state
>*conn_state) {
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
>+	struct dp_sdp infoframe_sdp = {};
>+	struct hdmi_drm_infoframe drm_infoframe = {};
>+	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
>HDMI_DRM_INFOFRAME_SIZE;
>+	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
>HDMI_DRM_INFOFRAME_SIZE];
>+	ssize_t len;
>+	int ret;
>+
>+	ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
>+	if (ret) {
>+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
>+		return;
>+	}
>+
>+	len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
>+	if (len < 0) {
>+		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
>infoframe\n");
>+		return;
>+	}
>+
>+	if (len != infoframe_size) {
>+		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
>+		return;
>+	}
>+
>+	/*
>+	 * Set up the infoframe sdp packet for HDR static metadata.
>+	 * Prepare VSC Header for SU as per DP 1.4a spec,
>+	 * Table 2-100 and Table 2-101
>+	 */
>+
>+	/* Packet ID, 00h for non-Audio INFOFRAME */
>+	infoframe_sdp.sdp_header.HB0 = 0;
>+	/*
>+	 * Packet Type 80h + Non-audio INFOFRAME Type value
>+	 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
>+	 */
>+	infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
>+	/*
>+	 * Least Significant Eight Bits of (Data Byte Count – 1)
>+	 * infoframe_size - 1,
>+	 */
>+	infoframe_sdp.sdp_header.HB2 = 0x1D;
>+	/* INFOFRAME SDP Version Number */
>+	infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
>+	/* CTA Header Byte 2 (INFOFRAME Version Number) */
>+	infoframe_sdp.db[0] = drm_infoframe.version;
>+	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE
>*/
>+	infoframe_sdp.db[1] = drm_infoframe.length;
>+	/*
>+	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
>+	 * HDMI_INFOFRAME_HEADER_SIZE
>+	 */
>+	memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
>+	       HDMI_DRM_INFOFRAME_SIZE);
>+
>+	if (INTEL_GEN(dev_priv) >= 11)
>+		intel_dig_port->write_infoframe(&intel_dig_port->base,
>+						crtc_state,
>+
>	HDMI_PACKET_TYPE_GAMUT_METADATA,
>+						&infoframe_sdp,
>+						VIDEO_DIP_GMP_DATA_SIZE);
>+	else
>+		/* Prior to GEN11, Header size: 4 bytes, Data size: 28 bytes */
>+		intel_dig_port->write_infoframe(&intel_dig_port->base,
>+						crtc_state,
>+
>	HDMI_PACKET_TYPE_GAMUT_METADATA,
>+						&infoframe_sdp,
>+						VIDEO_DIP_DATA_SIZE);
>+}
>+
> void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> 			 const struct intel_crtc_state *crtc_state,
> 			 const struct drm_connector_state *conn_state) @@ -
>4606,6 +4683,18 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> 	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);  }
>
>+void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
>+				  const struct intel_crtc_state *crtc_state,
>+				  const struct drm_connector_state *conn_state) {
>+	if (!conn_state->hdr_output_metadata)
>+		return;
>+
>+	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
>+						  crtc_state,
>+						  conn_state);
>+}
>+
> static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
> 	int status = 0;
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>b/drivers/gpu/drm/i915/display/intel_dp.h
>index 87883d0d5977..5613073d1dd5 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.h
>+++ b/drivers/gpu/drm/i915/display/intel_dp.h
>@@ -116,6 +116,9 @@ bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state
>*crtc_state);  void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> 			 const struct intel_crtc_state *crtc_state,
> 			 const struct drm_connector_state *conn_state);
>+void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
>+				  const struct intel_crtc_state *crtc_state,
>+				  const struct drm_connector_state *conn_state);
> bool intel_digital_port_connected(struct intel_encoder *encoder);
>
> static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>--
>2.23.0

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[PATCH v4 7/7] drm/i915/dp: Attach HDR metadata property to DP connector

[Gwan-gyeong Mun]

It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.

v2: Minor style fix

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7fcc9f28d2e7..2466d7aff670 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6536,6 +6536,11 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 	intel_attach_colorspace_property(connector);
 
+	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
+		drm_object_attach_property(&connector->base,
+					   connector->dev->mode_config.hdr_output_metadata_property,
+					   0);
+
 	if (intel_dp_is_edp(intel_dp)) {
 		u32 allowed_scalers;
 
-- 
2.23.0

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✓ Fi.CI.BAT: success for drm/i915/dp: Support for DP HDR outputs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Support for DP HDR outputs (rev4)
URL   : https://patchwork.freedesktop.org/series/65656/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6825 -> Patchwork_14264
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/

Known issues
------------

  Here are the changes found in Patchwork_14264 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-cml-u2:          [PASS][1] -> [FAIL][2] ([fdo#110627])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_requests:
    - {fi-icl-guc}:       [INCOMPLETE][3] ([fdo#107713] / [fdo#109644] / [fdo#110464]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/fi-icl-guc/igt@i915_selftest@live_requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/fi-icl-guc/igt@i915_selftest@live_requests.html

  * igt@kms_frontbuffer_tracking@basic:
    - {fi-icl-guc}:       [FAIL][5] ([fdo#103167]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111096]) -> [FAIL][8] ([fdo#111407])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
  [fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
  [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (53 -> 44)
------------------------------

  Missing    (9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6825 -> Patchwork_14264

  CI-20190529: 20190529
  CI_DRM_6825: f58d764f8e206f346e591fb18622a2a55fa85930 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5163: 9bd37d5e307748a5b43e92a5b0ea9be8fc60b339 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14264: 8325007c06eca44b129ead4c906e9cd8bb312d0c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8325007c06ec drm/i915/dp: Attach HDR metadata property to DP connector
426625e70e7e drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata
19ad12535690 drm/i915: Add new GMP register size for GEN11
b45058506b13 drm/i915/dp: Attach colorspace property
c638aca1ca0e drm: Add DisplayPort colorspace property
348de46e4abe drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA
f74d9edb0dc3 drm/i915/dp: Extend program of VSC Header and DB for Colorimetry Format

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/
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✗ Fi.CI.IGT: failure for drm/i915/dp: Support for DP HDR outputs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Support for DP HDR outputs (rev4)
URL   : https://patchwork.freedesktop.org/series/65656/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6825_full -> Patchwork_14264_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14264_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14264_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14264_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-iclb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb4/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb4/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  
Known issues
------------

  Here are the changes found in Patchwork_14264_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-kbl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#103665])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-kbl2/igt@gem_ctx_isolation@vcs1-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-kbl4/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#111325]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +21 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb5/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_pipe_control_store_loop@fresh-buffer:
    - shard-apl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl4/igt@gem_pipe_control_store_loop@fresh-buffer.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl8/igt@gem_pipe_control_store_loop@fresh-buffer.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108686])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl3/igt@gem_tiled_swapping@non-threaded.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl3/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#102670])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#105363])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#108303])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb3/igt@kms_flip_tiling@flip-x-tiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb3/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#103167]) +6 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145] / [fdo#110403]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103166])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl5/igt@gem_ctx_isolation@vecs0-s3.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl4/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][33] ([fdo#110841]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_eio@reset-stress:
    - shard-kbl:          [FAIL][35] ([fdo#109661]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-kbl6/igt@gem_eio@reset-stress.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-kbl2/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [SKIP][37] ([fdo#109276]) -> [PASS][38] +10 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][39] ([fdo#111325]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-kbl:          [INCOMPLETE][41] ([fdo#103665] / [fdo#107807]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-kbl2/igt@i915_pm_rpm@system-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-kbl2/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-skl:          [INCOMPLETE][43] ([fdo#104108]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl6/igt@kms_fbcon_fbt@fbc-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl3/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-apl:          [FAIL][45] ([fdo#105363]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl2/igt@kms_flip@flip-vs-expired-vblank.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [FAIL][47] ([fdo#100368]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-iclb:         [FAIL][49] ([fdo#103167]) -> [PASS][50] +5 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_plane@pixel-format-pipe-a-planes:
    - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-apl1/igt@kms_plane@pixel-format-pipe-a-planes.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-apl7/igt@kms_plane@pixel-format-pipe-a-planes.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb4/igt@kms_psr2_su@page_flip.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb7/igt@kms_psr@psr2_suspend.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb2/igt@kms_psr@psr2_suspend.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][57] ([fdo#110728]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-skl2/igt@perf@polling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-skl4/igt@perf@polling.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111329])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][61] ([fdo#109276]) -> [FAIL][62] ([fdo#111330])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb3/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][63] ([fdo#111330]) -> [SKIP][64] ([fdo#109276])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][65] ([fdo#107724]) -> [SKIP][66] ([fdo#109349])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6825/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6825 -> Patchwork_14264

  CI-20190529: 20190529
  CI_DRM_6825: f58d764f8e206f346e591fb18622a2a55fa85930 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5163: 9bd37d5e307748a5b43e92a5b0ea9be8fc60b339 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14264: 8325007c06eca44b129ead4c906e9cd8bb312d0c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14264/
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