* [PATCH v16 01/13] drm/i915: introduce a mechanism to extend execbuf2
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 02/13] drm/i915: add syncobj timeline support Lionel Landwerlin
` (14 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 39 ++++++++++++++++++-
include/uapi/drm/i915_drm.h | 26 +++++++++++--
2 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 27dbcb508055..4f5fd946ab28 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -25,6 +25,7 @@
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
enum {
FORCE_CPU_RELOC = 1,
@@ -272,6 +273,10 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct {
+ u64 flags; /** Available extensions parameters */
+ } extensions;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1940,7 +1945,8 @@ static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
+ I915_EXEC_USE_EXTENSIONS))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2442,6 +2448,33 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
+ struct i915_execbuffer *eb)
+{
+ eb->extensions.flags = 0;
+
+ if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
+ return 0;
+
+ /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
+ * have another flag also using it at the same time.
+ */
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return -EINVAL;
+
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2488,6 +2521,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
+ err = parse_execbuf2_extensions(args, &eb);
+ if (err)
+ return err;
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..0a99c26730e1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1007,6 +1007,10 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
+enum drm_i915_gem_execbuffer_ext {
+ DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
@@ -1023,8 +1027,15 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
- * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
- * struct drm_i915_gem_exec_fence *fences.
+ * & I915_EXEC_USE_EXTENSIONS are not set.
+ *
+ * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+ * of struct drm_i915_gem_exec_fence and num_cliprects is the length
+ * of the array.
+ *
+ * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
+ * single struct drm_i915_gem_base_execbuffer_ext and num_cliprects is
+ * 0.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (0x3f)
@@ -1142,7 +1153,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_USE_EXTENSIONS implies that
+ * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
+ * list of i915_user_extension. Each i915_user_extension node is the base of a
+ * larger structure. The list of supported structures are listed in the
+ * drm_i915_gem_execbuffer_ext enum.
+ */
+#define I915_EXEC_USE_EXTENSIONS (1 << 21)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 02/13] drm/i915: add syncobj timeline support
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 01/13] drm/i915: introduce a mechanism to extend execbuf2 Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 21:06 ` Chris Wilson
2019-09-09 9:31 ` [PATCH v16 03/13] drm/i915/perf: drop list of streams Lionel Landwerlin
` (13 subsequent siblings)
15 siblings, 1 reply; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
v7: Report ENOENT with invalid syncobj handle (Lionel)
v8: Check for out of order timeline point insertion (Chris)
v9: After explanations on
https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
drop the ordering check from v8 (Lionel)
v10: Set first extension enum item to 1 (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 307 ++++++++++++++----
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_getparam.c | 1 +
include/uapi/drm/i915_drm.h | 39 +++
4 files changed, 293 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 4f5fd946ab28..e488f22f53a4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -214,6 +214,13 @@ enum {
* the batchbuffer in trusted mode, otherwise the ioctl is rejected.
*/
+struct i915_eb_fences {
+ struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
+ struct dma_fence *dma_fence;
+ u64 value;
+ struct dma_fence_chain *chain_fence;
+};
+
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -276,6 +283,7 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
+ struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
} extensions;
};
@@ -2320,67 +2328,217 @@ eb_pin_engine(struct i915_execbuffer *eb,
}
static void
-__free_fence_array(struct drm_syncobj **fences, unsigned int n)
+__free_fence_array(struct i915_eb_fences *fences, unsigned int n)
{
- while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ while (n--) {
+ drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
+ dma_fence_put(fences[n].dma_fence);
+ kfree(fences[n].chain_fence);
+ }
kvfree(fences);
}
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_eb_fences *
+get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences =
+ &eb->extensions.timeline_fences;
+ struct drm_i915_gem_exec_fence __user *user_fences;
+ struct i915_eb_fences *fences;
+ u64 __user *user_values;
+ u64 num_fences, num_user_fences = timeline_fences->fence_count;
+ unsigned long n;
+ int err;
+
+ /* Check multiplication overflow for access_ok() and kvmalloc_array() */
+ BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
+ if (num_user_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user_fences),
+ SIZE_MAX / sizeof(*fences)))
+ return ERR_PTR(-EINVAL);
+
+ user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
+ if (!access_ok(user_fences, num_user_fences * sizeof(*user_fences)))
+ return ERR_PTR(-EFAULT);
+
+ user_values = u64_to_user_ptr(timeline_fences->values_ptr);
+ if (!access_ok(user_values, num_user_fences * sizeof(*user_values)))
+ return ERR_PTR(-EFAULT);
+
+ fences = kvmalloc_array(num_user_fences, sizeof(*fences),
+ __GFP_NOWARN | GFP_KERNEL);
+ if (!fences)
+ return ERR_PTR(-ENOMEM);
+
+ BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+ ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+
+ for (n = 0, num_fences = 0; n < timeline_fences->fence_count; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
+ struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
+ u64 point;
+
+ if (__copy_from_user(&user_fence, user_fences++, sizeof(user_fence))) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (__get_user(point, user_values++)) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!syncobj) {
+ DRM_DEBUG("Invalid syncobj handle provided\n");
+ err = -ENOENT;
+ goto err;
+ }
+
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+
+ err = dma_fence_chain_find_seqno(&fence, point);
+ if (err) {
+ DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
+ drm_syncobj_put(syncobj);
+ goto err;
+ }
+
+ /* A point might have been signaled already and
+ * garbage collected from the timeline. In this case
+ * just ignore the point and carry on.
+ */
+ if (!fence) {
+ drm_syncobj_put(syncobj);
+ continue;
+ }
+ }
+
+ /*
+ * For timeline syncobjs we need to preallocate chains for
+ * later signaling.
+ */
+ if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
+ /*
+ * Waiting and signaling the same point (when point !=
+ * 0) would break the timeline.
+ */
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ DRM_DEBUG("Tring to wait & signal the same timeline point.\n");
+ err = -EINVAL;
+ drm_syncobj_put(syncobj);
+ goto err;
+ }
+
+ fences[num_fences].chain_fence =
+ kmalloc(sizeof(*fences[num_fences].chain_fence),
+ GFP_KERNEL);
+ if (!fences[num_fences].chain_fence) {
+ drm_syncobj_put(syncobj);
+ err = -ENOMEM;
+ DRM_DEBUG("Unable to alloc chain_fence\n");
+ goto err;
+ }
+ } else {
+ fences[num_fences].chain_fence = NULL;
+ }
+
+ fences[num_fences].syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
+ fences[num_fences].dma_fence = fence;
+ fences[num_fences].value = point;
+ num_fences++;
+ }
+
+ *out_n_fences = num_fences;
+
+ return fences;
+
+err:
+ __free_fence_array(fences, num_fences);
+ return ERR_PTR(err);
+}
+
+static struct i915_eb_fences *
+get_legacy_fence_array(struct i915_execbuffer *eb,
+ int *out_n_fences)
{
- const unsigned long nfences = args->num_cliprects;
+ struct drm_i915_gem_execbuffer2 *args = eb->args;
struct drm_i915_gem_exec_fence __user *user;
- struct drm_syncobj **fences;
+ struct i915_eb_fences *fences;
+ const u32 num_fences = args->num_cliprects;
unsigned long n;
int err;
- if (!(args->flags & I915_EXEC_FENCE_ARRAY))
- return NULL;
+ *out_n_fences = num_fences;
/* Check multiplication overflow for access_ok() and kvmalloc_array() */
BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
- if (nfences > min_t(unsigned long,
- ULONG_MAX / sizeof(*user),
- SIZE_MAX / sizeof(*fences)))
+ if (*out_n_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user),
+ SIZE_MAX / sizeof(*fences)))
return ERR_PTR(-EINVAL);
user = u64_to_user_ptr(args->cliprects_ptr);
- if (!access_ok(user, nfences * sizeof(*user)))
+ if (!access_ok(user, *out_n_fences * sizeof(*user)))
return ERR_PTR(-EFAULT);
- fences = kvmalloc_array(nfences, sizeof(*fences),
+ fences = kvmalloc_array(*out_n_fences, sizeof(*fences),
__GFP_NOWARN | GFP_KERNEL);
if (!fences)
return ERR_PTR(-ENOMEM);
- for (n = 0; n < nfences; n++) {
- struct drm_i915_gem_exec_fence fence;
+ for (n = 0; n < *out_n_fences; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
- if (__copy_from_user(&fence, user++, sizeof(fence))) {
+ if (__copy_from_user(&user_fence, user++, sizeof(user_fence))) {
err = -EFAULT;
goto err;
}
- if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
err = -EINVAL;
goto err;
}
- syncobj = drm_syncobj_find(file, fence.handle);
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
if (!syncobj) {
DRM_DEBUG("Invalid syncobj handle provided\n");
err = -ENOENT;
goto err;
}
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+ }
+
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
- fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+ fences[n].syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
+ fences[n].dma_fence = fence;
+ fences[n].value = 0;
+ fences[n].chain_fence = NULL;
}
return fences;
@@ -2390,37 +2548,44 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
return ERR_PTR(err);
}
+static struct i915_eb_fences *
+get_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return get_legacy_fence_array(eb, out_n_fences);
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES))
+ return get_timeline_fence_array(eb, out_n_fences);
+
+ *out_n_fences = 0;
+ return NULL;
+}
+
static void
-put_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_syncobj **fences)
+put_fence_array(struct i915_eb_fences *fences, int nfences)
{
if (fences)
- __free_fence_array(fences, args->num_cliprects);
+ __free_fence_array(fences, nfences);
}
static int
await_fence_array(struct i915_execbuffer *eb,
- struct drm_syncobj **fences)
+ struct i915_eb_fences *fences,
+ int nfences)
{
- const unsigned int nfences = eb->args->num_cliprects;
unsigned int n;
int err;
for (n = 0; n < nfences; n++) {
struct drm_syncobj *syncobj;
- struct dma_fence *fence;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n].syncobj, &flags, 2);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
- fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
-
- err = i915_request_await_dma_fence(eb->request, fence);
- dma_fence_put(fence);
+ err = i915_request_await_dma_fence(eb->request,
+ fences[n].dma_fence);
if (err < 0)
return err;
}
@@ -2430,9 +2595,9 @@ await_fence_array(struct i915_execbuffer *eb,
static void
signal_fence_array(struct i915_execbuffer *eb,
- struct drm_syncobj **fences)
+ struct i915_eb_fences *fences,
+ int nfences)
{
- const unsigned int nfences = eb->args->num_cliprects;
struct dma_fence * const fence = &eb->request->fence;
unsigned int n;
@@ -2440,15 +2605,46 @@ signal_fence_array(struct i915_execbuffer *eb,
struct drm_syncobj *syncobj;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n].syncobj, &flags, 2);
if (!(flags & I915_EXEC_FENCE_SIGNAL))
continue;
- drm_syncobj_replace_fence(syncobj, fence);
+ if (fences[n].chain_fence) {
+ drm_syncobj_add_point(syncobj, fences[n].chain_fence,
+ fence, fences[n].value);
+ /*
+ * The chain's ownership is transferred to the
+ * timeline.
+ */
+ fences[n].chain_fence = NULL;
+ } else {
+ drm_syncobj_replace_fence(syncobj, fence);
+ }
}
}
+static int parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
+{
+ struct i915_execbuffer *eb = data;
+
+ /* Timeline fences are incompatible with the fence array flag. */
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return -EINVAL;
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES))
+ return -EINVAL;
+
+ if (copy_from_user(&eb->extensions.timeline_fences, ext,
+ sizeof(eb->extensions.timeline_fences)))
+ return -EFAULT;
+
+ eb->extensions.flags |= BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES);
+
+ return 0;
+}
+
static const i915_user_extension_fn execbuf_extensions[] = {
+ [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
};
static int
@@ -2479,14 +2675,15 @@ static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
struct drm_i915_gem_execbuffer2 *args,
- struct drm_i915_gem_exec_object2 *exec,
- struct drm_syncobj **fences)
+ struct drm_i915_gem_exec_object2 *exec)
{
struct i915_execbuffer eb;
struct dma_fence *in_fence = NULL;
struct dma_fence *exec_fence = NULL;
struct sync_file *out_fence = NULL;
+ struct i915_eb_fences *fences = NULL;
int out_fence_fd = -1;
+ int nfences = 0;
int err;
BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
@@ -2525,10 +2722,16 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (err)
return err;
+ fences = get_fence_array(&eb, &nfences);
+ if (IS_ERR(fences))
+ return PTR_ERR(fences);
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
- if (!in_fence)
- return -EINVAL;
+ if (!in_fence) {
+ err = -EINVAL;
+ goto err_fences;
+ }
}
if (args->flags & I915_EXEC_FENCE_SUBMIT) {
@@ -2673,7 +2876,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
if (fences) {
- err = await_fence_array(&eb, fences);
+ err = await_fence_array(&eb, fences, nfences);
if (err)
goto err_request;
}
@@ -2704,7 +2907,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
i915_request_add(eb.request);
if (fences)
- signal_fence_array(&eb, fences);
+ signal_fence_array(&eb, fences, nfences);
if (out_fence) {
if (err == 0) {
@@ -2739,6 +2942,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
dma_fence_put(exec_fence);
err_in_fence:
dma_fence_put(in_fence);
+err_fences:
+ put_fence_array(fences, nfences);
return err;
}
@@ -2832,7 +3037,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
exec2_list[i].flags = 0;
}
- err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
+ err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
if (exec2.flags & __EXEC_HAS_RELOC) {
struct drm_i915_gem_exec_object __user *user_exec_list =
u64_to_user_ptr(args->buffers_ptr);
@@ -2863,7 +3068,6 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
{
struct drm_i915_gem_execbuffer2 *args = data;
struct drm_i915_gem_exec_object2 *exec2_list;
- struct drm_syncobj **fences = NULL;
const size_t count = args->buffer_count;
int err;
@@ -2891,15 +3095,7 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
return -EFAULT;
}
- if (args->flags & I915_EXEC_FENCE_ARRAY) {
- fences = get_fence_array(args, file);
- if (IS_ERR(fences)) {
- kvfree(exec2_list);
- return PTR_ERR(fences);
- }
- }
-
- err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
+ err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
/*
* Now that we have begun execution of the batchbuffer, we ignore
@@ -2939,7 +3135,6 @@ end:;
}
args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
- put_fence_array(args, fences);
kvfree(exec2_list);
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7b2c81a8bbaa..7ad507e30a43 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2807,7 +2807,8 @@ static struct drm_driver driver = {
*/
.driver_features =
DRIVER_GEM |
- DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
+ DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
+ DRIVER_SYNCOBJ_TIMELINE,
.release = i915_driver_release,
.open = i915_driver_open,
.lastclose = i915_driver_lastclose,
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 5d9101376a3d..da6faa84e5b8 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -130,6 +130,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
+ case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0a99c26730e1..3d031e81648b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
+ * timeline syncobj through drm_i915_gem_execbuf_ext_timeline_fences. See
+ * I915_EXEC_USE_EXTENSIONS.
+ */
+#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1008,9 +1015,41 @@ struct drm_i915_gem_exec_fence {
};
enum drm_i915_gem_execbuffer_ext {
+ /**
+ * See drm_i915_gem_execbuf_ext_timeline_fences.
+ */
+ DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 1,
+
DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
};
+/**
+ * This structure describes an array of drm_syncobj and associated points for
+ * timeline variants of drm_syncobj. It is invalid to append this structure to
+ * the execbuf if I915_EXEC_FENCE_ARRAY is set.
+ */
+struct drm_i915_gem_execbuffer_ext_timeline_fences {
+ struct i915_user_extension base;
+
+ /**
+ * Number of element in the handles_ptr & value_ptr arrays.
+ */
+ __u64 fence_count;
+
+ /**
+ * Pointer to an array of struct drm_i915_gem_exec_fence of length
+ * fence_count.
+ */
+ __u64 handles_ptr;
+
+ /**
+ * Pointer to an array of u64 values of length fence_count. Values
+ * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
+ * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
+ */
+ __u64 values_ptr;
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
--
2.23.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 03/13] drm/i915/perf: drop list of streams
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 01/13] drm/i915: introduce a mechanism to extend execbuf2 Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 02/13] drm/i915: add syncobj timeline support Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-10 17:06 ` Umesh Nerlige Ramappa
2019-09-09 9:31 ` [PATCH v16 04/13] drm/i915/perf: store the associated engine of a stream Lionel Landwerlin
` (12 subsequent siblings)
15 siblings, 1 reply; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ------
drivers/gpu/drm/i915/i915_perf.c | 16 +---------------
2 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db7480831e52..75607450ba00 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1082,11 +1082,6 @@ struct i915_perf_stream {
*/
struct drm_i915_private *dev_priv;
- /**
- * @link: Links the stream into ``&drm_i915_private->streams``
- */
- struct list_head link;
-
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
@@ -1671,7 +1666,6 @@ struct drm_i915_private {
* except exclusive_stream.
*/
struct mutex lock;
- struct list_head streams;
/*
* The stream currently using the OA unit. If accessed
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c1b764233761..d18cd332afb7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1435,9 +1435,6 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /* Maybe make ->pollin per-stream state if we support multiple
- * concurrent streams in the future.
- */
stream->pollin = false;
}
@@ -1494,10 +1491,6 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /*
- * Maybe make ->pollin per-stream state if we support multiple
- * concurrent streams in the future.
- */
stream->pollin = false;
}
@@ -2633,8 +2626,6 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
if (stream->ops->destroy)
stream->ops->destroy(stream);
- list_del(&stream->link);
-
if (stream->ctx)
i915_gem_context_put(stream->ctx);
@@ -2783,8 +2774,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
goto err_flags;
}
- list_add(&stream->link, &dev_priv->perf.streams);
-
if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
f_flags |= O_CLOEXEC;
if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
@@ -2793,7 +2782,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
if (stream_fd < 0) {
ret = stream_fd;
- goto err_open;
+ goto err_flags;
}
if (!(param->flags & I915_PERF_FLAG_DISABLED))
@@ -2806,8 +2795,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
return stream_fd;
-err_open:
- list_del(&stream->link);
err_flags:
if (stream->ops->destroy)
stream->ops->destroy(stream);
@@ -3643,7 +3630,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
}
if (dev_priv->perf.ops.enable_metric_set) {
- INIT_LIST_HEAD(&dev_priv->perf.streams);
mutex_init(&dev_priv->perf.lock);
oa_sample_rate_hard_limit = 1000 *
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v16 03/13] drm/i915/perf: drop list of streams
2019-09-09 9:31 ` [PATCH v16 03/13] drm/i915/perf: drop list of streams Lionel Landwerlin
@ 2019-09-10 17:06 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 22+ messages in thread
From: Umesh Nerlige Ramappa @ 2019-09-10 17:06 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
Minor comment below. With or without it,
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:06PM +0300, Lionel Landwerlin wrote:
>At some point in time there was the idea that we could have multiple
>stream from the same piece of HW but that never materialized and given
>the hard time we already have making everything work with the
>submission side, there is no real point having this list of 1 element
>around.
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 6 ------
> drivers/gpu/drm/i915/i915_perf.c | 16 +---------------
> 2 files changed, 1 insertion(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index db7480831e52..75607450ba00 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1082,11 +1082,6 @@ struct i915_perf_stream {
> */
> struct drm_i915_private *dev_priv;
>
>- /**
>- * @link: Links the stream into ``&drm_i915_private->streams``
>- */
>- struct list_head link;
>-
> /**
> * @wakeref: As we keep the device awake while the perf stream is
> * active, we track our runtime pm reference for later release.
>@@ -1671,7 +1666,6 @@ struct drm_i915_private {
> * except exclusive_stream.
> */
> struct mutex lock;
>- struct list_head streams;
>
> /*
> * The stream currently using the OA unit. If accessed
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index c1b764233761..d18cd332afb7 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -1435,9 +1435,6 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
> */
> memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
>
>- /* Maybe make ->pollin per-stream state if we support multiple
>- * concurrent streams in the future.
>- */
> stream->pollin = false;
> }
>
>@@ -1494,10 +1491,6 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> */
> memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
>
>- /*
>- * Maybe make ->pollin per-stream state if we support multiple
>- * concurrent streams in the future.
>- */
one more instance of the above comment remains in i915_perf_read.
> stream->pollin = false;
> }
>
>@@ -2633,8 +2626,6 @@ static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
> if (stream->ops->destroy)
> stream->ops->destroy(stream);
>
>- list_del(&stream->link);
>-
> if (stream->ctx)
> i915_gem_context_put(stream->ctx);
>
>@@ -2783,8 +2774,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
> goto err_flags;
> }
>
>- list_add(&stream->link, &dev_priv->perf.streams);
>-
> if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
> f_flags |= O_CLOEXEC;
> if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
>@@ -2793,7 +2782,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
> stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
> if (stream_fd < 0) {
> ret = stream_fd;
>- goto err_open;
>+ goto err_flags;
> }
>
> if (!(param->flags & I915_PERF_FLAG_DISABLED))
>@@ -2806,8 +2795,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
>
> return stream_fd;
>
>-err_open:
>- list_del(&stream->link);
> err_flags:
> if (stream->ops->destroy)
> stream->ops->destroy(stream);
>@@ -3643,7 +3630,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> }
>
> if (dev_priv->perf.ops.enable_metric_set) {
>- INIT_LIST_HEAD(&dev_priv->perf.streams);
> mutex_init(&dev_priv->perf.lock);
>
> oa_sample_rate_hard_limit = 1000 *
>--
>2.23.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v16 04/13] drm/i915/perf: store the associated engine of a stream
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (2 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 03/13] drm/i915/perf: drop list of streams Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-10 0:21 ` Umesh Nerlige Ramappa
2019-09-09 9:31 ` [PATCH v16 05/13] drm/i915/perf: introduce a versioning of the i915-perf uapi Lionel Landwerlin
` (11 subsequent siblings)
15 siblings, 1 reply; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++++
drivers/gpu/drm/i915/i915_perf.c | 7 +++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 75607450ba00..274a1193d4f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1088,6 +1088,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+ * @engine: Engine associated with this performance stream.
+ */
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d18cd332afb7..9d5a3522aa35 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -363,6 +363,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -2201,6 +2203,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
format_size = dev_priv->perf.oa_formats[props->oa_format].size;
+ stream->engine = props->engine;
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2843,6 +2847,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = dev_priv->engine[RCS0];
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v16 04/13] drm/i915/perf: store the associated engine of a stream
2019-09-09 9:31 ` [PATCH v16 04/13] drm/i915/perf: store the associated engine of a stream Lionel Landwerlin
@ 2019-09-10 0:21 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 22+ messages in thread
From: Umesh Nerlige Ramappa @ 2019-09-10 0:21 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:07PM +0300, Lionel Landwerlin wrote:
>We'll use this information later to verify that a client trying to
>reconfigure the stream does so on the right engine.
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++++
> drivers/gpu/drm/i915/i915_perf.c | 7 +++++++
> 2 files changed, 12 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 75607450ba00..274a1193d4f0 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1088,6 +1088,11 @@ struct i915_perf_stream {
> */
> intel_wakeref_t wakeref;
>
>+ /**
>+ * @engine: Engine associated with this performance stream.
>+ */
>+ struct intel_engine_cs *engine;
>+
> /**
> * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
> * properties given when opening a stream, representing the contents
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index d18cd332afb7..9d5a3522aa35 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -363,6 +363,8 @@ struct perf_open_properties {
> int oa_format;
> bool oa_periodic;
> int oa_period_exponent;
>+
>+ struct intel_engine_cs *engine;
> };
>
> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
>@@ -2201,6 +2203,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
>
> format_size = dev_priv->perf.oa_formats[props->oa_format].size;
>
>+ stream->engine = props->engine;
>+
> stream->sample_flags |= SAMPLE_OA_REPORT;
> stream->sample_size += format_size;
>
>@@ -2843,6 +2847,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> return -EINVAL;
> }
>
>+ /* At the moment we only support using i915-perf on the RCS. */
>+ props->engine = dev_priv->engine[RCS0];
>+
> /* Considering that ID = 0 is reserved and assuming that we don't
> * (currently) expect any configurations to ever specify duplicate
> * values for a particular property ID then the last _PROP_MAX value is
>--
>2.23.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v16 05/13] drm/i915/perf: introduce a versioning of the i915-perf uapi
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (3 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 04/13] drm/i915/perf: store the associated engine of a stream Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 06/13] drm/i915/perf: move perf types to their own header Lionel Landwerlin
` (10 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_getparam.c | 4 ++++
drivers/gpu/drm/i915/i915_perf.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_perf.h | 1 +
include/uapi/drm/i915_drm.h | 20 ++++++++++++++++++++
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index da6faa84e5b8..bd41cc5ce906 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -5,6 +5,7 @@
#include "gt/intel_engine_user.h"
#include "i915_drv.h"
+#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
@@ -157,6 +158,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9d5a3522aa35..40a1ec2bc96b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3697,3 +3697,13 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
dev_priv->perf.initialized = false;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index a412b16d9ffc..95549de65212 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -18,6 +18,7 @@ void i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
+int i915_perf_ioctl_version(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3d031e81648b..e98c9a7baa91 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -618,6 +618,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 54
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 55
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1903,23 +1909,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1929,6 +1943,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1960,6 +1976,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1967,6 +1985,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 06/13] drm/i915/perf: move perf types to their own header
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (4 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 05/13] drm/i915/perf: introduce a versioning of the i915-perf uapi Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-10 17:35 ` Umesh Nerlige Ramappa
2019-09-09 9:31 ` [PATCH v16 07/13] drm/i915/perf: allow for CS OA configs to be created lazily Lionel Landwerlin
` (9 subsequent siblings)
15 siblings, 1 reply; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
Following a pattern used throughout the driver.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 300 +----------------------
drivers/gpu/drm/i915/i915_perf.h | 2 +
drivers/gpu/drm/i915/i915_perf_types.h | 327 +++++++++++++++++++++++++
3 files changed, 330 insertions(+), 299 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_perf_types.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 274a1193d4f0..f4145ae6ab6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -92,6 +92,7 @@
#include "i915_gem_fence_reg.h"
#include "i915_gem_gtt.h"
#include "i915_gpu_error.h"
+#include "i915_perf_types.h"
#include "i915_request.h"
#include "i915_scheduler.h"
#include "gt/intel_timeline.h"
@@ -979,305 +980,6 @@ struct intel_wm_config {
bool sprites_scaled;
};
-struct i915_oa_format {
- u32 format;
- int size;
-};
-
-struct i915_oa_reg {
- i915_reg_t addr;
- u32 value;
-};
-
-struct i915_oa_config {
- char uuid[UUID_STRING_LEN + 1];
- int id;
-
- const struct i915_oa_reg *mux_regs;
- u32 mux_regs_len;
- const struct i915_oa_reg *b_counter_regs;
- u32 b_counter_regs_len;
- const struct i915_oa_reg *flex_regs;
- u32 flex_regs_len;
-
- struct attribute_group sysfs_metric;
- struct attribute *attrs[2];
- struct device_attribute sysfs_metric_id;
-
- atomic_t ref_count;
-};
-
-struct i915_perf_stream;
-
-/**
- * struct i915_perf_stream_ops - the OPs to support a specific stream type
- */
-struct i915_perf_stream_ops {
- /**
- * @enable: Enables the collection of HW samples, either in response to
- * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
- * without `I915_PERF_FLAG_DISABLED`.
- */
- void (*enable)(struct i915_perf_stream *stream);
-
- /**
- * @disable: Disables the collection of HW samples, either in response
- * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
- * the stream.
- */
- void (*disable)(struct i915_perf_stream *stream);
-
- /**
- * @poll_wait: Call poll_wait, passing a wait queue that will be woken
- * once there is something ready to read() for the stream
- */
- void (*poll_wait)(struct i915_perf_stream *stream,
- struct file *file,
- poll_table *wait);
-
- /**
- * @wait_unlocked: For handling a blocking read, wait until there is
- * something to ready to read() for the stream. E.g. wait on the same
- * wait queue that would be passed to poll_wait().
- */
- int (*wait_unlocked)(struct i915_perf_stream *stream);
-
- /**
- * @read: Copy buffered metrics as records to userspace
- * **buf**: the userspace, destination buffer
- * **count**: the number of bytes to copy, requested by userspace
- * **offset**: zero at the start of the read, updated as the read
- * proceeds, it represents how many bytes have been copied so far and
- * the buffer offset for copying the next record.
- *
- * Copy as many buffered i915 perf samples and records for this stream
- * to userspace as will fit in the given buffer.
- *
- * Only write complete records; returning -%ENOSPC if there isn't room
- * for a complete record.
- *
- * Return any error condition that results in a short read such as
- * -%ENOSPC or -%EFAULT, even though these may be squashed before
- * returning to userspace.
- */
- int (*read)(struct i915_perf_stream *stream,
- char __user *buf,
- size_t count,
- size_t *offset);
-
- /**
- * @destroy: Cleanup any stream specific resources.
- *
- * The stream will always be disabled before this is called.
- */
- void (*destroy)(struct i915_perf_stream *stream);
-};
-
-/**
- * struct i915_perf_stream - state for a single open stream FD
- */
-struct i915_perf_stream {
- /**
- * @dev_priv: i915 drm device
- */
- struct drm_i915_private *dev_priv;
-
- /**
- * @wakeref: As we keep the device awake while the perf stream is
- * active, we track our runtime pm reference for later release.
- */
- intel_wakeref_t wakeref;
-
- /**
- * @engine: Engine associated with this performance stream.
- */
- struct intel_engine_cs *engine;
-
- /**
- * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
- * properties given when opening a stream, representing the contents
- * of a single sample as read() by userspace.
- */
- u32 sample_flags;
-
- /**
- * @sample_size: Considering the configured contents of a sample
- * combined with the required header size, this is the total size
- * of a single sample record.
- */
- int sample_size;
-
- /**
- * @ctx: %NULL if measuring system-wide across all contexts or a
- * specific context that is being monitored.
- */
- struct i915_gem_context *ctx;
-
- /**
- * @enabled: Whether the stream is currently enabled, considering
- * whether the stream was opened in a disabled state and based
- * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
- */
- bool enabled;
-
- /**
- * @ops: The callbacks providing the implementation of this specific
- * type of configured stream.
- */
- const struct i915_perf_stream_ops *ops;
-
- /**
- * @oa_config: The OA configuration used by the stream.
- */
- struct i915_oa_config *oa_config;
-
- /**
- * The OA context specific information.
- */
- struct intel_context *pinned_ctx;
- u32 specific_ctx_id;
- u32 specific_ctx_id_mask;
-
- struct hrtimer poll_check_timer;
- wait_queue_head_t poll_wq;
- bool pollin;
-
- bool periodic;
- int period_exponent;
-
- /**
- * State of the OA buffer.
- */
- struct {
- struct i915_vma *vma;
- u8 *vaddr;
- u32 last_ctx_id;
- int format;
- int format_size;
- int size_exponent;
-
- /**
- * Locks reads and writes to all head/tail state
- *
- * Consider: the head and tail pointer state needs to be read
- * consistently from a hrtimer callback (atomic context) and
- * read() fop (user context) with tail pointer updates happening
- * in atomic context and head updates in user context and the
- * (unlikely) possibility of read() errors needing to reset all
- * head/tail state.
- *
- * Note: Contention/performance aren't currently a significant
- * concern here considering the relatively low frequency of
- * hrtimer callbacks (5ms period) and that reads typically only
- * happen in response to a hrtimer event and likely complete
- * before the next callback.
- *
- * Note: This lock is not held *while* reading and copying data
- * to userspace so the value of head observed in htrimer
- * callbacks won't represent any partial consumption of data.
- */
- spinlock_t ptr_lock;
-
- /**
- * One 'aging' tail pointer and one 'aged' tail pointer ready to
- * used for reading.
- *
- * Initial values of 0xffffffff are invalid and imply that an
- * update is required (and should be ignored by an attempted
- * read)
- */
- struct {
- u32 offset;
- } tails[2];
-
- /**
- * Index for the aged tail ready to read() data up to.
- */
- unsigned int aged_tail_idx;
-
- /**
- * A monotonic timestamp for when the current aging tail pointer
- * was read; used to determine when it is old enough to trust.
- */
- u64 aging_timestamp;
-
- /**
- * Although we can always read back the head pointer register,
- * we prefer to avoid trusting the HW state, just to avoid any
- * risk that some hardware condition could * somehow bump the
- * head pointer unpredictably and cause us to forward the wrong
- * OA buffer data to userspace.
- */
- u32 head;
- } oa_buffer;
-};
-
-/**
- * struct i915_oa_ops - Gen specific implementation of an OA unit stream
- */
-struct i915_oa_ops {
- /**
- * @is_valid_b_counter_reg: Validates register's address for
- * programming boolean counters for a particular platform.
- */
- bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
- u32 addr);
-
- /**
- * @is_valid_mux_reg: Validates register's address for programming mux
- * for a particular platform.
- */
- bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
-
- /**
- * @is_valid_flex_reg: Validates register's address for programming
- * flex EU filtering for a particular platform.
- */
- bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
-
- /**
- * @enable_metric_set: Selects and applies any MUX configuration to set
- * up the Boolean and Custom (B/C) counters that are part of the
- * counter reports being sampled. May apply system constraints such as
- * disabling EU clock gating as required.
- */
- int (*enable_metric_set)(struct i915_perf_stream *stream);
-
- /**
- * @disable_metric_set: Remove system constraints associated with using
- * the OA unit.
- */
- void (*disable_metric_set)(struct i915_perf_stream *stream);
-
- /**
- * @oa_enable: Enable periodic sampling
- */
- void (*oa_enable)(struct i915_perf_stream *stream);
-
- /**
- * @oa_disable: Disable periodic sampling
- */
- void (*oa_disable)(struct i915_perf_stream *stream);
-
- /**
- * @read: Copy data from the circular OA buffer into a given userspace
- * buffer.
- */
- int (*read)(struct i915_perf_stream *stream,
- char __user *buf,
- size_t count,
- size_t *offset);
-
- /**
- * @oa_hw_tail_read: read the OA tail pointer register
- *
- * In particular this enables us to share all the fiddly code for
- * handling the OA unit tail pointer race that affects multiple
- * generations.
- */
- u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
-};
-
struct intel_cdclk_state {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 95549de65212..270193526b56 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -8,6 +8,8 @@
#include <linux/types.h>
+#include "i915_perf_types.h"
+
struct drm_device;
struct drm_file;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
new file mode 100644
index 000000000000..c6673b67d694
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _I915_PERF_TYPES_H_
+#define _I915_PERF_TYPES_H_
+
+#include <linux/atomic.h>
+#include <linux/device.h>
+#include <linux/hrtimer.h>
+#include <linux/list.h>
+#include <linux/poll.h>
+#include <linux/sysfs.h>
+#include <linux/uuid.h>
+#include <linux/wait.h>
+
+#include "i915_reg.h"
+#include "intel_wakeref.h"
+
+struct drm_i915_private;
+struct file;
+struct i915_gem_context;
+struct i915_vma;
+struct intel_context;
+struct intel_engine_cs;
+
+struct i915_oa_format {
+ u32 format;
+ int size;
+};
+
+struct i915_oa_reg {
+ i915_reg_t addr;
+ u32 value;
+};
+
+struct i915_oa_config {
+ char uuid[UUID_STRING_LEN + 1];
+ int id;
+
+ const struct i915_oa_reg *mux_regs;
+ u32 mux_regs_len;
+ const struct i915_oa_reg *b_counter_regs;
+ u32 b_counter_regs_len;
+ const struct i915_oa_reg *flex_regs;
+ u32 flex_regs_len;
+
+ struct attribute_group sysfs_metric;
+ struct attribute *attrs[2];
+ struct device_attribute sysfs_metric_id;
+
+ atomic_t ref_count;
+};
+
+struct i915_perf_stream;
+
+/**
+ * struct i915_perf_stream_ops - the OPs to support a specific stream type
+ */
+struct i915_perf_stream_ops {
+ /**
+ * @enable: Enables the collection of HW samples, either in response to
+ * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
+ * without `I915_PERF_FLAG_DISABLED`.
+ */
+ void (*enable)(struct i915_perf_stream *stream);
+
+ /**
+ * @disable: Disables the collection of HW samples, either in response
+ * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
+ * the stream.
+ */
+ void (*disable)(struct i915_perf_stream *stream);
+
+ /**
+ * @poll_wait: Call poll_wait, passing a wait queue that will be woken
+ * once there is something ready to read() for the stream
+ */
+ void (*poll_wait)(struct i915_perf_stream *stream,
+ struct file *file,
+ poll_table *wait);
+
+ /**
+ * @wait_unlocked: For handling a blocking read, wait until there is
+ * something to ready to read() for the stream. E.g. wait on the same
+ * wait queue that would be passed to poll_wait().
+ */
+ int (*wait_unlocked)(struct i915_perf_stream *stream);
+
+ /**
+ * @read: Copy buffered metrics as records to userspace
+ * **buf**: the userspace, destination buffer
+ * **count**: the number of bytes to copy, requested by userspace
+ * **offset**: zero at the start of the read, updated as the read
+ * proceeds, it represents how many bytes have been copied so far and
+ * the buffer offset for copying the next record.
+ *
+ * Copy as many buffered i915 perf samples and records for this stream
+ * to userspace as will fit in the given buffer.
+ *
+ * Only write complete records; returning -%ENOSPC if there isn't room
+ * for a complete record.
+ *
+ * Return any error condition that results in a short read such as
+ * -%ENOSPC or -%EFAULT, even though these may be squashed before
+ * returning to userspace.
+ */
+ int (*read)(struct i915_perf_stream *stream,
+ char __user *buf,
+ size_t count,
+ size_t *offset);
+
+ /**
+ * @destroy: Cleanup any stream specific resources.
+ *
+ * The stream will always be disabled before this is called.
+ */
+ void (*destroy)(struct i915_perf_stream *stream);
+};
+
+/**
+ * struct i915_perf_stream - state for a single open stream FD
+ */
+struct i915_perf_stream {
+ /**
+ * @dev_priv: i915 drm device
+ */
+ struct drm_i915_private *dev_priv;
+
+ /**
+ * @wakeref: As we keep the device awake while the perf stream is
+ * active, we track our runtime pm reference for later release.
+ */
+ intel_wakeref_t wakeref;
+
+ /**
+ * @engine: Engine associated with this performance stream.
+ */
+ struct intel_engine_cs *engine;
+
+ /**
+ * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
+ * properties given when opening a stream, representing the contents
+ * of a single sample as read() by userspace.
+ */
+ u32 sample_flags;
+
+ /**
+ * @sample_size: Considering the configured contents of a sample
+ * combined with the required header size, this is the total size
+ * of a single sample record.
+ */
+ int sample_size;
+
+ /**
+ * @ctx: %NULL if measuring system-wide across all contexts or a
+ * specific context that is being monitored.
+ */
+ struct i915_gem_context *ctx;
+
+ /**
+ * @enabled: Whether the stream is currently enabled, considering
+ * whether the stream was opened in a disabled state and based
+ * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
+ */
+ bool enabled;
+
+ /**
+ * @ops: The callbacks providing the implementation of this specific
+ * type of configured stream.
+ */
+ const struct i915_perf_stream_ops *ops;
+
+ /**
+ * @oa_config: The OA configuration used by the stream.
+ */
+ struct i915_oa_config *oa_config;
+
+ /**
+ * The OA context specific information.
+ */
+ struct intel_context *pinned_ctx;
+ u32 specific_ctx_id;
+ u32 specific_ctx_id_mask;
+
+ struct hrtimer poll_check_timer;
+ wait_queue_head_t poll_wq;
+ bool pollin;
+
+ bool periodic;
+ int period_exponent;
+
+ /**
+ * State of the OA buffer.
+ */
+ struct {
+ struct i915_vma *vma;
+ u8 *vaddr;
+ u32 last_ctx_id;
+ int format;
+ int format_size;
+ int size_exponent;
+
+ /**
+ * Locks reads and writes to all head/tail state
+ *
+ * Consider: the head and tail pointer state needs to be read
+ * consistently from a hrtimer callback (atomic context) and
+ * read() fop (user context) with tail pointer updates happening
+ * in atomic context and head updates in user context and the
+ * (unlikely) possibility of read() errors needing to reset all
+ * head/tail state.
+ *
+ * Note: Contention/performance aren't currently a significant
+ * concern here considering the relatively low frequency of
+ * hrtimer callbacks (5ms period) and that reads typically only
+ * happen in response to a hrtimer event and likely complete
+ * before the next callback.
+ *
+ * Note: This lock is not held *while* reading and copying data
+ * to userspace so the value of head observed in htrimer
+ * callbacks won't represent any partial consumption of data.
+ */
+ spinlock_t ptr_lock;
+
+ /**
+ * One 'aging' tail pointer and one 'aged' tail pointer ready to
+ * used for reading.
+ *
+ * Initial values of 0xffffffff are invalid and imply that an
+ * update is required (and should be ignored by an attempted
+ * read)
+ */
+ struct {
+ u32 offset;
+ } tails[2];
+
+ /**
+ * Index for the aged tail ready to read() data up to.
+ */
+ unsigned int aged_tail_idx;
+
+ /**
+ * A monotonic timestamp for when the current aging tail pointer
+ * was read; used to determine when it is old enough to trust.
+ */
+ u64 aging_timestamp;
+
+ /**
+ * Although we can always read back the head pointer register,
+ * we prefer to avoid trusting the HW state, just to avoid any
+ * risk that some hardware condition could * somehow bump the
+ * head pointer unpredictably and cause us to forward the wrong
+ * OA buffer data to userspace.
+ */
+ u32 head;
+ } oa_buffer;
+};
+
+/**
+ * struct i915_oa_ops - Gen specific implementation of an OA unit stream
+ */
+struct i915_oa_ops {
+ /**
+ * @is_valid_b_counter_reg: Validates register's address for
+ * programming boolean counters for a particular platform.
+ */
+ bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
+ u32 addr);
+
+ /**
+ * @is_valid_mux_reg: Validates register's address for programming mux
+ * for a particular platform.
+ */
+ bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
+
+ /**
+ * @is_valid_flex_reg: Validates register's address for programming
+ * flex EU filtering for a particular platform.
+ */
+ bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
+
+ /**
+ * @enable_metric_set: Selects and applies any MUX configuration to set
+ * up the Boolean and Custom (B/C) counters that are part of the
+ * counter reports being sampled. May apply system constraints such as
+ * disabling EU clock gating as required.
+ */
+ int (*enable_metric_set)(struct i915_perf_stream *stream);
+
+ /**
+ * @disable_metric_set: Remove system constraints associated with using
+ * the OA unit.
+ */
+ void (*disable_metric_set)(struct i915_perf_stream *stream);
+
+ /**
+ * @oa_enable: Enable periodic sampling
+ */
+ void (*oa_enable)(struct i915_perf_stream *stream);
+
+ /**
+ * @oa_disable: Disable periodic sampling
+ */
+ void (*oa_disable)(struct i915_perf_stream *stream);
+
+ /**
+ * @read: Copy data from the circular OA buffer into a given userspace
+ * buffer.
+ */
+ int (*read)(struct i915_perf_stream *stream,
+ char __user *buf,
+ size_t count,
+ size_t *offset);
+
+ /**
+ * @oa_hw_tail_read: read the OA tail pointer register
+ *
+ * In particular this enables us to share all the fiddly code for
+ * handling the OA unit tail pointer race that affects multiple
+ * generations.
+ */
+ u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
+};
+
+#endif /* _I915_PERF_TYPES_H_ */
--
2.23.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v16 06/13] drm/i915/perf: move perf types to their own header
2019-09-09 9:31 ` [PATCH v16 06/13] drm/i915/perf: move perf types to their own header Lionel Landwerlin
@ 2019-09-10 17:35 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 22+ messages in thread
From: Umesh Nerlige Ramappa @ 2019-09-10 17:35 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
Looks good. The struct perf inside drm_i915_private could also move to
i915_perf_types.h. Irrespective of that,
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Regards,
Umesh
On Mon, Sep 09, 2019 at 12:31:09PM +0300, Lionel Landwerlin wrote:
>Following a pattern used throughout the driver.
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 300 +----------------------
> drivers/gpu/drm/i915/i915_perf.h | 2 +
> drivers/gpu/drm/i915/i915_perf_types.h | 327 +++++++++++++++++++++++++
> 3 files changed, 330 insertions(+), 299 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/i915_perf_types.h
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 274a1193d4f0..f4145ae6ab6e 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -92,6 +92,7 @@
> #include "i915_gem_fence_reg.h"
> #include "i915_gem_gtt.h"
> #include "i915_gpu_error.h"
>+#include "i915_perf_types.h"
> #include "i915_request.h"
> #include "i915_scheduler.h"
> #include "gt/intel_timeline.h"
>@@ -979,305 +980,6 @@ struct intel_wm_config {
> bool sprites_scaled;
> };
>
>-struct i915_oa_format {
>- u32 format;
>- int size;
>-};
>-
>-struct i915_oa_reg {
>- i915_reg_t addr;
>- u32 value;
>-};
>-
>-struct i915_oa_config {
>- char uuid[UUID_STRING_LEN + 1];
>- int id;
>-
>- const struct i915_oa_reg *mux_regs;
>- u32 mux_regs_len;
>- const struct i915_oa_reg *b_counter_regs;
>- u32 b_counter_regs_len;
>- const struct i915_oa_reg *flex_regs;
>- u32 flex_regs_len;
>-
>- struct attribute_group sysfs_metric;
>- struct attribute *attrs[2];
>- struct device_attribute sysfs_metric_id;
>-
>- atomic_t ref_count;
>-};
>-
>-struct i915_perf_stream;
>-
>-/**
>- * struct i915_perf_stream_ops - the OPs to support a specific stream type
>- */
>-struct i915_perf_stream_ops {
>- /**
>- * @enable: Enables the collection of HW samples, either in response to
>- * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
>- * without `I915_PERF_FLAG_DISABLED`.
>- */
>- void (*enable)(struct i915_perf_stream *stream);
>-
>- /**
>- * @disable: Disables the collection of HW samples, either in response
>- * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
>- * the stream.
>- */
>- void (*disable)(struct i915_perf_stream *stream);
>-
>- /**
>- * @poll_wait: Call poll_wait, passing a wait queue that will be woken
>- * once there is something ready to read() for the stream
>- */
>- void (*poll_wait)(struct i915_perf_stream *stream,
>- struct file *file,
>- poll_table *wait);
>-
>- /**
>- * @wait_unlocked: For handling a blocking read, wait until there is
>- * something to ready to read() for the stream. E.g. wait on the same
>- * wait queue that would be passed to poll_wait().
>- */
>- int (*wait_unlocked)(struct i915_perf_stream *stream);
>-
>- /**
>- * @read: Copy buffered metrics as records to userspace
>- * **buf**: the userspace, destination buffer
>- * **count**: the number of bytes to copy, requested by userspace
>- * **offset**: zero at the start of the read, updated as the read
>- * proceeds, it represents how many bytes have been copied so far and
>- * the buffer offset for copying the next record.
>- *
>- * Copy as many buffered i915 perf samples and records for this stream
>- * to userspace as will fit in the given buffer.
>- *
>- * Only write complete records; returning -%ENOSPC if there isn't room
>- * for a complete record.
>- *
>- * Return any error condition that results in a short read such as
>- * -%ENOSPC or -%EFAULT, even though these may be squashed before
>- * returning to userspace.
>- */
>- int (*read)(struct i915_perf_stream *stream,
>- char __user *buf,
>- size_t count,
>- size_t *offset);
>-
>- /**
>- * @destroy: Cleanup any stream specific resources.
>- *
>- * The stream will always be disabled before this is called.
>- */
>- void (*destroy)(struct i915_perf_stream *stream);
>-};
>-
>-/**
>- * struct i915_perf_stream - state for a single open stream FD
>- */
>-struct i915_perf_stream {
>- /**
>- * @dev_priv: i915 drm device
>- */
>- struct drm_i915_private *dev_priv;
>-
>- /**
>- * @wakeref: As we keep the device awake while the perf stream is
>- * active, we track our runtime pm reference for later release.
>- */
>- intel_wakeref_t wakeref;
>-
>- /**
>- * @engine: Engine associated with this performance stream.
>- */
>- struct intel_engine_cs *engine;
>-
>- /**
>- * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
>- * properties given when opening a stream, representing the contents
>- * of a single sample as read() by userspace.
>- */
>- u32 sample_flags;
>-
>- /**
>- * @sample_size: Considering the configured contents of a sample
>- * combined with the required header size, this is the total size
>- * of a single sample record.
>- */
>- int sample_size;
>-
>- /**
>- * @ctx: %NULL if measuring system-wide across all contexts or a
>- * specific context that is being monitored.
>- */
>- struct i915_gem_context *ctx;
>-
>- /**
>- * @enabled: Whether the stream is currently enabled, considering
>- * whether the stream was opened in a disabled state and based
>- * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
>- */
>- bool enabled;
>-
>- /**
>- * @ops: The callbacks providing the implementation of this specific
>- * type of configured stream.
>- */
>- const struct i915_perf_stream_ops *ops;
>-
>- /**
>- * @oa_config: The OA configuration used by the stream.
>- */
>- struct i915_oa_config *oa_config;
>-
>- /**
>- * The OA context specific information.
>- */
>- struct intel_context *pinned_ctx;
>- u32 specific_ctx_id;
>- u32 specific_ctx_id_mask;
>-
>- struct hrtimer poll_check_timer;
>- wait_queue_head_t poll_wq;
>- bool pollin;
>-
>- bool periodic;
>- int period_exponent;
>-
>- /**
>- * State of the OA buffer.
>- */
>- struct {
>- struct i915_vma *vma;
>- u8 *vaddr;
>- u32 last_ctx_id;
>- int format;
>- int format_size;
>- int size_exponent;
>-
>- /**
>- * Locks reads and writes to all head/tail state
>- *
>- * Consider: the head and tail pointer state needs to be read
>- * consistently from a hrtimer callback (atomic context) and
>- * read() fop (user context) with tail pointer updates happening
>- * in atomic context and head updates in user context and the
>- * (unlikely) possibility of read() errors needing to reset all
>- * head/tail state.
>- *
>- * Note: Contention/performance aren't currently a significant
>- * concern here considering the relatively low frequency of
>- * hrtimer callbacks (5ms period) and that reads typically only
>- * happen in response to a hrtimer event and likely complete
>- * before the next callback.
>- *
>- * Note: This lock is not held *while* reading and copying data
>- * to userspace so the value of head observed in htrimer
>- * callbacks won't represent any partial consumption of data.
>- */
>- spinlock_t ptr_lock;
>-
>- /**
>- * One 'aging' tail pointer and one 'aged' tail pointer ready to
>- * used for reading.
>- *
>- * Initial values of 0xffffffff are invalid and imply that an
>- * update is required (and should be ignored by an attempted
>- * read)
>- */
>- struct {
>- u32 offset;
>- } tails[2];
>-
>- /**
>- * Index for the aged tail ready to read() data up to.
>- */
>- unsigned int aged_tail_idx;
>-
>- /**
>- * A monotonic timestamp for when the current aging tail pointer
>- * was read; used to determine when it is old enough to trust.
>- */
>- u64 aging_timestamp;
>-
>- /**
>- * Although we can always read back the head pointer register,
>- * we prefer to avoid trusting the HW state, just to avoid any
>- * risk that some hardware condition could * somehow bump the
>- * head pointer unpredictably and cause us to forward the wrong
>- * OA buffer data to userspace.
>- */
>- u32 head;
>- } oa_buffer;
>-};
>-
>-/**
>- * struct i915_oa_ops - Gen specific implementation of an OA unit stream
>- */
>-struct i915_oa_ops {
>- /**
>- * @is_valid_b_counter_reg: Validates register's address for
>- * programming boolean counters for a particular platform.
>- */
>- bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
>- u32 addr);
>-
>- /**
>- * @is_valid_mux_reg: Validates register's address for programming mux
>- * for a particular platform.
>- */
>- bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
>-
>- /**
>- * @is_valid_flex_reg: Validates register's address for programming
>- * flex EU filtering for a particular platform.
>- */
>- bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
>-
>- /**
>- * @enable_metric_set: Selects and applies any MUX configuration to set
>- * up the Boolean and Custom (B/C) counters that are part of the
>- * counter reports being sampled. May apply system constraints such as
>- * disabling EU clock gating as required.
>- */
>- int (*enable_metric_set)(struct i915_perf_stream *stream);
>-
>- /**
>- * @disable_metric_set: Remove system constraints associated with using
>- * the OA unit.
>- */
>- void (*disable_metric_set)(struct i915_perf_stream *stream);
>-
>- /**
>- * @oa_enable: Enable periodic sampling
>- */
>- void (*oa_enable)(struct i915_perf_stream *stream);
>-
>- /**
>- * @oa_disable: Disable periodic sampling
>- */
>- void (*oa_disable)(struct i915_perf_stream *stream);
>-
>- /**
>- * @read: Copy data from the circular OA buffer into a given userspace
>- * buffer.
>- */
>- int (*read)(struct i915_perf_stream *stream,
>- char __user *buf,
>- size_t count,
>- size_t *offset);
>-
>- /**
>- * @oa_hw_tail_read: read the OA tail pointer register
>- *
>- * In particular this enables us to share all the fiddly code for
>- * handling the OA unit tail pointer race that affects multiple
>- * generations.
>- */
>- u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
>-};
>-
> struct intel_cdclk_state {
> unsigned int cdclk, vco, ref, bypass;
> u8 voltage_level;
>diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
>index 95549de65212..270193526b56 100644
>--- a/drivers/gpu/drm/i915/i915_perf.h
>+++ b/drivers/gpu/drm/i915/i915_perf.h
>@@ -8,6 +8,8 @@
>
> #include <linux/types.h>
>
>+#include "i915_perf_types.h"
>+
> struct drm_device;
> struct drm_file;
> struct drm_i915_private;
>diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
>new file mode 100644
>index 000000000000..c6673b67d694
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/i915_perf_types.h
>@@ -0,0 +1,327 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2019 Intel Corporation
>+ */
>+
>+#ifndef _I915_PERF_TYPES_H_
>+#define _I915_PERF_TYPES_H_
>+
>+#include <linux/atomic.h>
>+#include <linux/device.h>
>+#include <linux/hrtimer.h>
>+#include <linux/list.h>
>+#include <linux/poll.h>
>+#include <linux/sysfs.h>
>+#include <linux/uuid.h>
>+#include <linux/wait.h>
>+
>+#include "i915_reg.h"
>+#include "intel_wakeref.h"
>+
>+struct drm_i915_private;
>+struct file;
>+struct i915_gem_context;
>+struct i915_vma;
>+struct intel_context;
>+struct intel_engine_cs;
>+
>+struct i915_oa_format {
>+ u32 format;
>+ int size;
>+};
>+
>+struct i915_oa_reg {
>+ i915_reg_t addr;
>+ u32 value;
>+};
>+
>+struct i915_oa_config {
>+ char uuid[UUID_STRING_LEN + 1];
>+ int id;
>+
>+ const struct i915_oa_reg *mux_regs;
>+ u32 mux_regs_len;
>+ const struct i915_oa_reg *b_counter_regs;
>+ u32 b_counter_regs_len;
>+ const struct i915_oa_reg *flex_regs;
>+ u32 flex_regs_len;
>+
>+ struct attribute_group sysfs_metric;
>+ struct attribute *attrs[2];
>+ struct device_attribute sysfs_metric_id;
>+
>+ atomic_t ref_count;
>+};
>+
>+struct i915_perf_stream;
>+
>+/**
>+ * struct i915_perf_stream_ops - the OPs to support a specific stream type
>+ */
>+struct i915_perf_stream_ops {
>+ /**
>+ * @enable: Enables the collection of HW samples, either in response to
>+ * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
>+ * without `I915_PERF_FLAG_DISABLED`.
>+ */
>+ void (*enable)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @disable: Disables the collection of HW samples, either in response
>+ * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
>+ * the stream.
>+ */
>+ void (*disable)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @poll_wait: Call poll_wait, passing a wait queue that will be woken
>+ * once there is something ready to read() for the stream
>+ */
>+ void (*poll_wait)(struct i915_perf_stream *stream,
>+ struct file *file,
>+ poll_table *wait);
>+
>+ /**
>+ * @wait_unlocked: For handling a blocking read, wait until there is
>+ * something to ready to read() for the stream. E.g. wait on the same
>+ * wait queue that would be passed to poll_wait().
>+ */
>+ int (*wait_unlocked)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @read: Copy buffered metrics as records to userspace
>+ * **buf**: the userspace, destination buffer
>+ * **count**: the number of bytes to copy, requested by userspace
>+ * **offset**: zero at the start of the read, updated as the read
>+ * proceeds, it represents how many bytes have been copied so far and
>+ * the buffer offset for copying the next record.
>+ *
>+ * Copy as many buffered i915 perf samples and records for this stream
>+ * to userspace as will fit in the given buffer.
>+ *
>+ * Only write complete records; returning -%ENOSPC if there isn't room
>+ * for a complete record.
>+ *
>+ * Return any error condition that results in a short read such as
>+ * -%ENOSPC or -%EFAULT, even though these may be squashed before
>+ * returning to userspace.
>+ */
>+ int (*read)(struct i915_perf_stream *stream,
>+ char __user *buf,
>+ size_t count,
>+ size_t *offset);
>+
>+ /**
>+ * @destroy: Cleanup any stream specific resources.
>+ *
>+ * The stream will always be disabled before this is called.
>+ */
>+ void (*destroy)(struct i915_perf_stream *stream);
>+};
>+
>+/**
>+ * struct i915_perf_stream - state for a single open stream FD
>+ */
>+struct i915_perf_stream {
>+ /**
>+ * @dev_priv: i915 drm device
>+ */
>+ struct drm_i915_private *dev_priv;
>+
>+ /**
>+ * @wakeref: As we keep the device awake while the perf stream is
>+ * active, we track our runtime pm reference for later release.
>+ */
>+ intel_wakeref_t wakeref;
>+
>+ /**
>+ * @engine: Engine associated with this performance stream.
>+ */
>+ struct intel_engine_cs *engine;
>+
>+ /**
>+ * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
>+ * properties given when opening a stream, representing the contents
>+ * of a single sample as read() by userspace.
>+ */
>+ u32 sample_flags;
>+
>+ /**
>+ * @sample_size: Considering the configured contents of a sample
>+ * combined with the required header size, this is the total size
>+ * of a single sample record.
>+ */
>+ int sample_size;
>+
>+ /**
>+ * @ctx: %NULL if measuring system-wide across all contexts or a
>+ * specific context that is being monitored.
>+ */
>+ struct i915_gem_context *ctx;
>+
>+ /**
>+ * @enabled: Whether the stream is currently enabled, considering
>+ * whether the stream was opened in a disabled state and based
>+ * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
>+ */
>+ bool enabled;
>+
>+ /**
>+ * @ops: The callbacks providing the implementation of this specific
>+ * type of configured stream.
>+ */
>+ const struct i915_perf_stream_ops *ops;
>+
>+ /**
>+ * @oa_config: The OA configuration used by the stream.
>+ */
>+ struct i915_oa_config *oa_config;
>+
>+ /**
>+ * The OA context specific information.
>+ */
>+ struct intel_context *pinned_ctx;
>+ u32 specific_ctx_id;
>+ u32 specific_ctx_id_mask;
>+
>+ struct hrtimer poll_check_timer;
>+ wait_queue_head_t poll_wq;
>+ bool pollin;
>+
>+ bool periodic;
>+ int period_exponent;
>+
>+ /**
>+ * State of the OA buffer.
>+ */
>+ struct {
>+ struct i915_vma *vma;
>+ u8 *vaddr;
>+ u32 last_ctx_id;
>+ int format;
>+ int format_size;
>+ int size_exponent;
>+
>+ /**
>+ * Locks reads and writes to all head/tail state
>+ *
>+ * Consider: the head and tail pointer state needs to be read
>+ * consistently from a hrtimer callback (atomic context) and
>+ * read() fop (user context) with tail pointer updates happening
>+ * in atomic context and head updates in user context and the
>+ * (unlikely) possibility of read() errors needing to reset all
>+ * head/tail state.
>+ *
>+ * Note: Contention/performance aren't currently a significant
>+ * concern here considering the relatively low frequency of
>+ * hrtimer callbacks (5ms period) and that reads typically only
>+ * happen in response to a hrtimer event and likely complete
>+ * before the next callback.
>+ *
>+ * Note: This lock is not held *while* reading and copying data
>+ * to userspace so the value of head observed in htrimer
>+ * callbacks won't represent any partial consumption of data.
>+ */
>+ spinlock_t ptr_lock;
>+
>+ /**
>+ * One 'aging' tail pointer and one 'aged' tail pointer ready to
>+ * used for reading.
>+ *
>+ * Initial values of 0xffffffff are invalid and imply that an
>+ * update is required (and should be ignored by an attempted
>+ * read)
>+ */
>+ struct {
>+ u32 offset;
>+ } tails[2];
>+
>+ /**
>+ * Index for the aged tail ready to read() data up to.
>+ */
>+ unsigned int aged_tail_idx;
>+
>+ /**
>+ * A monotonic timestamp for when the current aging tail pointer
>+ * was read; used to determine when it is old enough to trust.
>+ */
>+ u64 aging_timestamp;
>+
>+ /**
>+ * Although we can always read back the head pointer register,
>+ * we prefer to avoid trusting the HW state, just to avoid any
>+ * risk that some hardware condition could * somehow bump the
>+ * head pointer unpredictably and cause us to forward the wrong
>+ * OA buffer data to userspace.
>+ */
>+ u32 head;
>+ } oa_buffer;
>+};
>+
>+/**
>+ * struct i915_oa_ops - Gen specific implementation of an OA unit stream
>+ */
>+struct i915_oa_ops {
>+ /**
>+ * @is_valid_b_counter_reg: Validates register's address for
>+ * programming boolean counters for a particular platform.
>+ */
>+ bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
>+ u32 addr);
>+
>+ /**
>+ * @is_valid_mux_reg: Validates register's address for programming mux
>+ * for a particular platform.
>+ */
>+ bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
>+
>+ /**
>+ * @is_valid_flex_reg: Validates register's address for programming
>+ * flex EU filtering for a particular platform.
>+ */
>+ bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
>+
>+ /**
>+ * @enable_metric_set: Selects and applies any MUX configuration to set
>+ * up the Boolean and Custom (B/C) counters that are part of the
>+ * counter reports being sampled. May apply system constraints such as
>+ * disabling EU clock gating as required.
>+ */
>+ int (*enable_metric_set)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @disable_metric_set: Remove system constraints associated with using
>+ * the OA unit.
>+ */
>+ void (*disable_metric_set)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @oa_enable: Enable periodic sampling
>+ */
>+ void (*oa_enable)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @oa_disable: Disable periodic sampling
>+ */
>+ void (*oa_disable)(struct i915_perf_stream *stream);
>+
>+ /**
>+ * @read: Copy data from the circular OA buffer into a given userspace
>+ * buffer.
>+ */
>+ int (*read)(struct i915_perf_stream *stream,
>+ char __user *buf,
>+ size_t count,
>+ size_t *offset);
>+
>+ /**
>+ * @oa_hw_tail_read: read the OA tail pointer register
>+ *
>+ * In particular this enables us to share all the fiddly code for
>+ * handling the OA unit tail pointer race that affects multiple
>+ * generations.
>+ */
>+ u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
>+};
>+
>+#endif /* _I915_PERF_TYPES_H_ */
>--
>2.23.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v16 07/13] drm/i915/perf: allow for CS OA configs to be created lazily
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (5 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 06/13] drm/i915/perf: move perf types to their own header Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 08/13] drm/i915/perf: implement active wait for noa configurations Lionel Landwerlin
` (8 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
v4: Fix oa config unref/put when not found (Lionel)
v5: Allocate BOs for configurations on the stream instead of globally
(Lionel)
v6: Fix 64bit division (Chris)
v7: Store allocated config BOs into the stream (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 270 ++++++++++++++++---
drivers/gpu/drm/i915/i915_perf.h | 26 ++
drivers/gpu/drm/i915/i915_perf_types.h | 15 +-
5 files changed, 273 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index fbad403ab7ac..b6373fbc927d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -135,6 +135,7 @@
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4145ae6ab6e..7eb31923cde9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1363,8 +1363,8 @@ struct drm_i915_private {
struct mutex metrics_lock;
/*
- * List of dynamic configurations, you need to hold
- * dev_priv->perf.metrics_lock to access it.
+ * List of dynamic configurations (struct i915_oa_config), you
+ * need to hold dev_priv->perf.metrics_lock to access it.
*/
struct idr metrics_idr;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 40a1ec2bc96b..93a424c4a577 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -367,11 +367,19 @@ struct perf_open_properties {
struct intel_engine_cs *engine;
};
+struct i915_oa_config_bo {
+ struct list_head link;
+
+ struct i915_oa_config *oa_config;
+ struct drm_i915_gem_object *bo;
+};
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
-static void free_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
+ struct i915_oa_config *oa_config = container_of(ref, typeof(*oa_config), ref);
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
@@ -381,40 +389,194 @@ static void free_oa_config(struct drm_i915_private *dev_priv,
kfree(oa_config);
}
-static void put_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32 n_regs)
{
- if (!atomic_dec_and_test(&oa_config->ref_count))
- return;
+ u32 i;
+
+ for (i = 0; i < n_regs; i++) {
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min(n_regs - i,
+ (u32)MI_LOAD_REGISTER_IMM_MAX_REGS);
- free_oa_config(dev_priv, oa_config);
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
+ }
+
+ return cs;
}
-static int get_oa_config(struct drm_i915_private *dev_priv,
- int metrics_set,
- struct i915_oa_config **out_config)
+static struct i915_oa_config_bo *alloc_oa_config_buffer(struct drm_i915_private *i915,
+ struct i915_oa_config *oa_config)
{
- int ret;
+ struct i915_oa_config_bo *oa_bo;
+ size_t config_length = 0;
+ u32 *cs;
+ int err;
+
+ oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
+ if (!oa_bo)
+ return ERR_PTR(-ENOMEM);
+
+ oa_bo->oa_config = i915_oa_config_get(oa_config);
+
+ if (oa_config->mux_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->mux_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->mux_regs_len * 8;
+ }
+ if (oa_config->b_counter_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->b_counter_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->b_counter_regs_len * 8;
+ }
+ if (oa_config->flex_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->flex_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->flex_regs_len * 8;
+ }
+ config_length += 4; /* MI_BATCH_BUFFER_END */
+ config_length = ALIGN(config_length, I915_GTT_PAGE_SIZE);
+
+ oa_bo->bo = i915_gem_object_create_shmem(i915, config_length);
+ if (IS_ERR(oa_bo->bo)) {
+ err = PTR_ERR(oa_bo->bo);
+ goto err_oa_config;
+ }
+
+ cs = i915_gem_object_pin_map(oa_bo->bo, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_oa_bo;
+ }
+
+ cs = write_cs_mi_lri(cs, oa_config->mux_regs, oa_config->mux_regs_len);
+ cs = write_cs_mi_lri(cs, oa_config->b_counter_regs, oa_config->b_counter_regs_len);
+ cs = write_cs_mi_lri(cs, oa_config->flex_regs, oa_config->flex_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(oa_bo->bo);
+ i915_gem_object_unpin_map(oa_bo->bo);
+
+ return oa_bo;
+
+err_oa_bo:
+ i915_gem_object_put(oa_bo->bo);
+err_oa_config:
+ i915_oa_config_put(oa_bo->oa_config);
+ kfree(oa_bo);
+
+ return ERR_PTR(err);
+}
+
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config)
+{
+ struct i915_oa_config *oa_config;
+ int err;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ err = mutex_lock_interruptible(&i915->perf.metrics_lock);
+ if (err)
+ return err;
if (metrics_set == 1) {
- *out_config = &dev_priv->perf.test_config;
- atomic_inc(&dev_priv->perf.test_config.ref_count);
- return 0;
+ oa_config = &i915->perf.test_config;
+ } else {
+ oa_config = idr_find(&i915->perf.metrics_idr, metrics_set);
+ if (!oa_config)
+ err = -EINVAL;
}
- ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
- if (ret)
- return ret;
+ if (!err)
+ *out_config = i915_oa_config_get(oa_config);
- *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
- else
- atomic_inc(&(*out_config)->ref_count);
+ mutex_unlock(&i915->perf.metrics_lock);
- mutex_unlock(&dev_priv->perf.metrics_lock);
+ return err;
+}
- return ret;
+static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
+{
+ i915_oa_config_put(oa_bo->oa_config);
+ i915_gem_object_put(oa_bo->bo);
+ kfree(oa_bo);
+}
+
+int i915_perf_get_oa_config_and_bo(struct i915_perf_stream *stream,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj)
+{
+ struct drm_i915_private *i915 = stream->dev_priv;
+ struct i915_oa_config *oa_config;
+ int err = 0;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ err = i915_perf_get_oa_config(i915, metrics_set, &oa_config);
+ if (err)
+ return err;
+
+ if (out_config)
+ *out_config = oa_config;
+
+ if (out_obj) {
+ struct i915_oa_config_bo *oa_bo = NULL, *oa_bo_iter;
+
+ /* Look for the buffer in the already allocated BOs attached
+ * to the stream.
+ */
+ err = mutex_lock_interruptible(&stream->config_mutex);
+ if (err)
+ goto err;
+
+ list_for_each_entry(oa_bo_iter, &stream->oa_config_bos, link) {
+ if (oa_bo_iter->oa_config == oa_config &&
+ memcmp(oa_bo_iter->oa_config->uuid,
+ oa_config->uuid,
+ sizeof(oa_config->uuid)) == 0) {
+ oa_bo = oa_bo_iter;
+ break;
+ }
+ }
+
+ mutex_unlock(&stream->config_mutex);
+
+ if (!oa_bo) {
+ oa_bo = alloc_oa_config_buffer(i915, oa_config);
+ if (IS_ERR(oa_bo)) {
+ err = PTR_ERR(oa_bo);
+ goto err;
+ }
+
+ err = mutex_lock_interruptible(&stream->config_mutex);
+ if (err) {
+ free_oa_config_bo(oa_bo);
+ goto err;
+ }
+
+ list_add(&oa_bo->link, &stream->oa_config_bos);
+
+ mutex_unlock(&stream->config_mutex);
+ }
+
+ *out_obj = i915_gem_object_get(oa_bo->bo);
+ }
+
+err:
+ if (err) {
+ i915_oa_config_put(oa_config);
+ *out_config = NULL;
+ }
+
+ return err;
}
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
@@ -1362,6 +1524,18 @@ free_oa_buffer(struct i915_perf_stream *stream)
stream->oa_buffer.vaddr = NULL;
}
+static void
+free_oa_configs(struct i915_perf_stream *stream)
+{
+ struct i915_oa_config_bo *oa_bo, *tmp;
+
+ i915_oa_config_put(stream->oa_config);
+ list_for_each_entry_safe(oa_bo, tmp, &stream->oa_config_bos, link) {
+ list_del(&oa_bo->link);
+ free_oa_config_bo(oa_bo);
+ }
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
@@ -1385,7 +1559,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
if (stream->ctx)
oa_put_render_ctx_id(stream);
- put_oa_config(dev_priv, stream->oa_config);
+ free_oa_configs(stream);
if (dev_priv->perf.spurious_report_rs.missed) {
DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
@@ -2199,6 +2373,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return -EINVAL;
}
+ mutex_init(&stream->config_mutex);
+
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
format_size = dev_priv->perf.oa_formats[props->oa_format].size;
@@ -2227,7 +2403,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
}
- ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config);
+ ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
+ &stream->oa_config);
if (ret) {
DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
goto err_config;
@@ -2265,6 +2442,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_enable;
}
+ DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
+
mutex_unlock(&dev_priv->drm.struct_mutex);
hrtimer_init(&stream->poll_check_timer,
@@ -2284,11 +2463,11 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_buffer(stream);
err_oa_buf_alloc:
- put_oa_config(dev_priv, stream->oa_config);
-
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
+ free_oa_configs(stream);
+
err_config:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2309,8 +2488,12 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine,
return;
stream = engine->i915->perf.exclusive_stream;
- if (stream)
+
+ if (stream) {
+ mutex_lock(&stream->config_mutex);
gen8_update_reg_state_unlocked(stream, ce, regs, stream->oa_config);
+ mutex_unlock(&stream->config_mutex);
+ }
}
/**
@@ -2653,7 +2836,9 @@ static int i915_perf_release(struct inode *inode, struct file *file)
struct drm_i915_private *dev_priv = stream->dev_priv;
mutex_lock(&dev_priv->perf.lock);
+
i915_perf_destroy_locked(stream);
+
mutex_unlock(&dev_priv->perf.lock);
/* Release the reference the perf stream kept on the driver. */
@@ -2762,6 +2947,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
goto err_ctx;
}
+ INIT_LIST_HEAD(&stream->oa_config_bos);
stream->dev_priv = dev_priv;
stream->ctx = specific_ctx;
@@ -3088,7 +3274,8 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (ret)
goto sysfs_error;
- atomic_set(&dev_priv->perf.test_config.ref_count, 1);
+ dev_priv->perf.test_config.i915 = dev_priv;
+ kref_init(&dev_priv->perf.test_config.ref);
goto exit;
@@ -3344,7 +3531,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
return -ENOMEM;
}
- atomic_set(&oa_config->ref_count, 1);
+ oa_config->i915 = dev_priv;
+ kref_init(&oa_config->ref);
if (!uuid_is_valid(args->uuid)) {
DRM_DEBUG("Invalid uuid format for OA config\n");
@@ -3443,7 +3631,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
sysfs_err:
mutex_unlock(&dev_priv->perf.metrics_lock);
reg_err:
- put_oa_config(dev_priv, oa_config);
+ i915_oa_config_put(oa_config);
DRM_DEBUG("Failed to add new OA config\n");
return err;
}
@@ -3479,13 +3667,13 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
if (ret)
- goto lock_err;
+ return ret;
oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg);
if (!oa_config) {
DRM_DEBUG("Failed to remove unknown OA config\n");
ret = -ENOENT;
- goto config_err;
+ goto err_unlock;
}
GEM_BUG_ON(*arg != oa_config->id);
@@ -3495,13 +3683,16 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
idr_remove(&dev_priv->perf.metrics_idr, *arg);
+ mutex_unlock(&dev_priv->perf.metrics_lock);
+
DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
- put_oa_config(dev_priv, oa_config);
+ i915_oa_config_put(oa_config);
+
+ return 0;
-config_err:
+err_unlock:
mutex_unlock(&dev_priv->perf.metrics_lock);
-lock_err:
return ret;
}
@@ -3671,10 +3862,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
static int destroy_config(int id, void *p, void *data)
{
- struct drm_i915_private *dev_priv = data;
struct i915_oa_config *oa_config = p;
- put_oa_config(dev_priv, oa_config);
+ i915_oa_config_put(oa_config);
return 0;
}
@@ -3688,7 +3878,7 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.initialized)
return;
- idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv);
+ idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, NULL);
idr_destroy(&dev_priv->perf.metrics_idr);
unregister_sysctl_table(dev_priv->perf.sysctl_header);
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 270193526b56..1c85487876a4 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -7,12 +7,16 @@
#define __I915_PERF_H__
#include <linux/types.h>
+#include <linux/kref.h>
#include "i915_perf_types.h"
struct drm_device;
struct drm_file;
+struct drm_i915_gem_object;
struct drm_i915_private;
+struct i915_oa_config;
+struct i915_perf_stream;
struct intel_context;
struct intel_engine_cs;
@@ -31,5 +35,27 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct intel_context *ce,
u32 *reg_state);
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config);
+int i915_perf_get_oa_config_and_bo(struct i915_perf_stream *stream,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj);
+void i915_oa_config_release(struct kref *ref);
+
+static inline struct i915_oa_config *i915_oa_config_get(struct i915_oa_config *oa_config)
+{
+ kref_get(&oa_config->ref);
+ return oa_config;
+}
+
+static inline void i915_oa_config_put(struct i915_oa_config *oa_config)
+{
+ if (!oa_config)
+ return;
+
+ kref_put(&oa_config->ref, i915_oa_config_release);
+}
#endif /* __I915_PERF_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index c6673b67d694..6cde38b6277b 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -36,6 +36,8 @@ struct i915_oa_reg {
};
struct i915_oa_config {
+ struct drm_i915_private *i915;
+
char uuid[UUID_STRING_LEN + 1];
int id;
@@ -50,7 +52,7 @@ struct i915_oa_config {
struct attribute *attrs[2];
struct device_attribute sysfs_metric_id;
- atomic_t ref_count;
+ struct kref ref;
};
struct i915_perf_stream;
@@ -172,11 +174,22 @@ struct i915_perf_stream {
*/
const struct i915_perf_stream_ops *ops;
+ /**
+ * @active_config_mutex: Protects access to @oa_config & @oa_config_bos.
+ */
+ struct mutex config_mutex;
+
/**
* @oa_config: The OA configuration used by the stream.
*/
struct i915_oa_config *oa_config;
+ /**
+ * @oa_config_bos: A list of struct i915_oa_config_bo allocated lazily
+ * each time @oa_config changes.
+ */
+ struct list_head oa_config_bos;
+
/**
* The OA context specific information.
*/
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 08/13] drm/i915/perf: implement active wait for noa configurations
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (6 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 07/13] drm/i915/perf: allow for CS OA configs to be created lazily Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 09/13] drm/i915: add wait flags to i915_active_request_retire Lionel Landwerlin
` (7 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 30 +++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 233 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_perf_types.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
7 files changed, 300 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b6373fbc927d..fab318c71d24 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -160,6 +160,7 @@
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -238,6 +239,29 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_ALU_OP(op, src1, src2) (((op) << 20) | ((src1) << 10) | (src2))
+/* operands */
+#define MI_ALU_OP_NOOP 0
+#define MI_ALU_OP_LOAD 128
+#define MI_ALU_OP_LOADINV 1152
+#define MI_ALU_OP_LOAD0 129
+#define MI_ALU_OP_LOAD1 1153
+#define MI_ALU_OP_ADD 256
+#define MI_ALU_OP_SUB 257
+#define MI_ALU_OP_AND 258
+#define MI_ALU_OP_OR 259
+#define MI_ALU_OP_XOR 260
+#define MI_ALU_OP_STORE 384
+#define MI_ALU_OP_STOREINV 1408
+/* sources */
+#define MI_ALU_SRC_REG(x) (x) /* 0 -> 15 */
+#define MI_ALU_SRC_SRCA 32
+#define MI_ALU_SRC_SRCB 33
+#define MI_ALU_SRC_ACCU 49
+#define MI_ALU_SRC_ZF 50
+#define MI_ALU_SRC_CF 51
+
/*
* Commands used only by the command parser
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dc295c196d11..f752b6cf9ea1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -97,6 +97,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 708855e051b5..b00b1a6f8d68 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3578,6 +3578,35 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+
+ /* This would lead to infinite waits as we're doing timestamp
+ * difference on the CS with only 32bits.
+ */
+ if (val > mul_u32_u32(U32_MAX, RUNTIME_INFO(i915)->cs_timestamp_frequency_khz))
+ return -EINVAL;
+
+ atomic64_set(&i915->perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(&i915->perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIRE BIT(2)
@@ -4354,6 +4383,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
{"i915_wedged", &i915_wedged_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7eb31923cde9..2c6f37219dff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1403,6 +1403,8 @@ struct drm_i915_private {
struct i915_oa_ops ops;
const struct i915_oa_format *oa_formats;
+
+ atomic64_t noa_programming_delay;
} perf;
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 93a424c4a577..d01494180465 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -408,6 +409,7 @@ static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32 n_r
}
static struct i915_oa_config_bo *alloc_oa_config_buffer(struct drm_i915_private *i915,
+ struct i915_vma *noa_wait,
struct i915_oa_config *oa_config)
{
struct i915_oa_config_bo *oa_bo;
@@ -436,7 +438,7 @@ static struct i915_oa_config_bo *alloc_oa_config_buffer(struct drm_i915_private
MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
config_length += oa_config->flex_regs_len * 8;
}
- config_length += 4; /* MI_BATCH_BUFFER_END */
+ config_length += 12; /* MI_BATCH_BUFFER_START into noa_wait loop */
config_length = ALIGN(config_length, I915_GTT_PAGE_SIZE);
oa_bo->bo = i915_gem_object_create_shmem(i915, config_length);
@@ -455,7 +457,11 @@ static struct i915_oa_config_bo *alloc_oa_config_buffer(struct drm_i915_private
cs = write_cs_mi_lri(cs, oa_config->b_counter_regs, oa_config->b_counter_regs_len);
cs = write_cs_mi_lri(cs, oa_config->flex_regs, oa_config->flex_regs_len);
- *cs++ = MI_BATCH_BUFFER_END;
+ /* Jump into the NOA wait busy loop. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8);
+ *cs++ = i915_ggtt_offset(noa_wait);
+ *cs++ = 0;
i915_gem_object_flush_map(oa_bo->bo);
i915_gem_object_unpin_map(oa_bo->bo);
@@ -550,7 +556,9 @@ int i915_perf_get_oa_config_and_bo(struct i915_perf_stream *stream,
mutex_unlock(&stream->config_mutex);
if (!oa_bo) {
- oa_bo = alloc_oa_config_buffer(i915, oa_config);
+ oa_bo = alloc_oa_config_buffer(i915,
+ stream->noa_wait,
+ oa_config);
if (IS_ERR(oa_bo)) {
err = PTR_ERR(oa_bo);
goto err;
@@ -1524,6 +1532,16 @@ free_oa_buffer(struct i915_perf_stream *stream)
stream->oa_buffer.vaddr = NULL;
}
+static void
+free_noa_wait(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *i915 = stream->dev_priv;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_vma_unpin_and_release(&stream->noa_wait, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
+}
+
static void
free_oa_configs(struct i915_perf_stream *stream)
{
@@ -1552,6 +1570,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
mutex_unlock(&dev_priv->drm.struct_mutex);
free_oa_buffer(stream);
+ free_noa_wait(stream);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
@@ -1731,6 +1750,202 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
return ret;
}
+static u32 *save_restore_register(struct drm_i915_private *i915, u32 *cs,
+ bool save, i915_reg_t reg, u32 offset,
+ u32 dword_count)
+{
+ u32 d;
+
+ for (d = 0; d < dword_count; d++) {
+ if (save) {
+ *cs++ = INTEL_GEN(i915) >= 8 ?
+ MI_STORE_REGISTER_MEM_GEN8 :
+ MI_STORE_REGISTER_MEM;
+ } else {
+ *cs++ = INTEL_GEN(i915) >= 8 ?
+ MI_LOAD_REGISTER_MEM_GEN8 :
+ MI_LOAD_REGISTER_MEM;
+ }
+ *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
+ *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
+ *cs++ = 0;
+ }
+
+ return cs;
+}
+
+static int alloc_noa_wait(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *i915 = stream->dev_priv;
+ struct drm_i915_gem_object *bo;
+ struct i915_vma *vma;
+ const u64 delay_ticks = 0xffffffffffffffff -
+ DIV64_U64_ROUND_UP(
+ atomic64_read(&i915->perf.noa_programming_delay) *
+ RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
+ 1000000ull);
+ u32 *batch, *ts0, *cs, *jump;
+ int ret, i;
+ enum { START_TS, NOW_TS, DELTA_TS, JUMP_PREDICATE, DELTA_TARGET, N_CS_GPR };
+
+ bo = i915_gem_object_create_internal(i915, 4096);
+ if (IS_ERR(bo)) {
+ DRM_ERROR("Failed to allocate NOA wait batchbuffer\n");
+ return PTR_ERR(bo);
+ }
+
+ /*
+ * We pin in GGTT because we jump into this buffer now because
+ * multiple OA config BOs will have a jump to this address and it
+ * needs to be fixed during the lifetime of the i915/perf stream.
+ */
+ vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unref;
+ }
+
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
+ if (IS_ERR(batch)) {
+ ret = PTR_ERR(batch);
+ goto err_unpin;
+ }
+
+ /* Save registers. */
+ for (i = 0; i < N_CS_GPR; i++) {
+ cs = save_restore_register(
+ i915, cs, true /* save */, HSW_CS_GPR(i),
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ }
+ cs = save_restore_register(
+ i915, cs, true /* save */, MI_PREDICATE_RESULT_1,
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+
+ /* First timestamp snapshot location. */
+ ts0 = cs;
+
+ /*
+ * Initial snapshot of the timestamp register to implement the wait.
+ * We work with 32b values, so clear out the top 32b bits of the
+ * register because the ALU works 64bits.
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS)) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS));
+
+ /*
+ * This is the location we're going to jump back into until the
+ * required amount of time has passed.
+ */
+ jump = cs;
+
+ /*
+ * Take another snapshot of the timestamp register. Take care to clear
+ * up the top 32bits of CS_GPR(1) as we're using it for other
+ * operations below.
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS)) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS));
+
+ /*
+ * Do a diff between the 2 timestamps and store the result back into
+ * CS_GPR(1).
+ */
+ *cs++ = MI_MATH(5);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(NOW_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(START_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_SUB, 0, 0);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(DELTA_TS), MI_ALU_SRC_ACCU);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
+
+ /*
+ * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
+ * timestamp have rolled over the 32bits) into the predicate register
+ * to be used for the predicated jump.
+ */
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
+
+ /* Restart from the beginning if we had timestamps roll over. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
+ MI_BATCH_PREDICATE;
+ *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
+ *cs++ = 0;
+
+ /*
+ * Now add the diff between to previous timestamps and add it to :
+ * (((1 * << 64) - 1) - delay_ns)
+ *
+ * When the Carry Flag contains 1 this means the elapsed time is
+ * longer than the expected delay, and we can exit the wait loop.
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET));
+ *cs++ = lower_32_bits(delay_ticks);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET)) + 4;
+ *cs++ = upper_32_bits(delay_ticks);
+
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(DELTA_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(DELTA_TARGET));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_ADD, 0, 0);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STOREINV, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
+
+ /*
+ * Transfer the result into the predicate register to be used for the
+ * predicated jump.
+ */
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
+
+ /* Predicate the jump. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
+ MI_BATCH_PREDICATE;
+ *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
+ *cs++ = 0;
+
+ /* Restore registers. */
+ for (i = 0; i < N_CS_GPR; i++) {
+ cs = save_restore_register(
+ i915, cs, false /* save */, HSW_CS_GPR(i),
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ }
+ cs = save_restore_register(
+ i915, cs, false /* save */, MI_PREDICATE_RESULT_1,
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+
+ /* And return to the ring. */
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ GEM_BUG_ON((cs - batch) > (PAGE_SIZE / sizeof(*batch)));
+
+ i915_gem_object_flush_map(bo);
+ i915_gem_object_unpin_map(bo);
+
+ stream->noa_wait = vma;
+
+ return 0;
+
+err_unpin:
+ __i915_vma_unpin(vma);
+
+err_unref:
+ i915_gem_object_put(bo);
+
+ return ret;
+}
+
static void config_oa_regs(struct drm_i915_private *dev_priv,
const struct i915_oa_reg *regs,
u32 n_regs)
@@ -2403,6 +2618,12 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
}
+ ret = alloc_noa_wait(stream);
+ if (ret) {
+ DRM_DEBUG("Unable to allocate NOA wait batch buffer\n");
+ goto err_noa_wait_alloc;
+ }
+
ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
&stream->oa_config);
if (ret) {
@@ -2469,6 +2690,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_configs(stream);
err_config:
+ free_noa_wait(stream);
+
+err_noa_wait_alloc:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -3856,6 +4080,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
ratelimit_set_flags(&dev_priv->perf.spurious_report_rs,
RATELIMIT_MSG_ON_RELEASE);
+ atomic64_set(&dev_priv->perf.noa_programming_delay,
+ 500 * 1000 /* 500us */);
+
dev_priv->perf.initialized = true;
}
}
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 6cde38b6277b..15ee0d33e44f 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -269,6 +269,12 @@ struct i915_perf_stream {
*/
u32 head;
} oa_buffer;
+
+ /**
+ * A batch buffer doing a wait on the GPU for the NOA logic to be
+ * reprogrammed.
+ */
+ struct i915_vma *noa_wait;
};
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..8fea97b02365 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -545,7 +545,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
-
+#define MI_PREDICATE_DATA _MMIO(0x2410)
+#define MI_PREDICATE_RESULT _MMIO(0x2418)
+#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
#define LOWER_SLICE_DISABLED (0 << 0)
--
2.23.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 09/13] drm/i915: add wait flags to i915_active_request_retire
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (7 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 08/13] drm/i915/perf: implement active wait for noa configurations Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 10/13] drm/i915/perf: execute OA configuration from command stream Lionel Landwerlin
` (6 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
An upcoming change needs not to be interrupted.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_active.c | 4 +++-
drivers/gpu/drm/i915/i915_active.h | 5 ++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index 6a447f1d0110..c808c28c9464 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -425,7 +425,9 @@ int i915_active_wait(struct i915_active *ref)
break;
}
- err = i915_active_request_retire(&it->base, BKL(ref));
+ err = i915_active_request_retire(&it->base,
+ I915_WAIT_INTERRUPTIBLE,
+ BKL(ref));
if (err)
break;
}
diff --git a/drivers/gpu/drm/i915/i915_active.h b/drivers/gpu/drm/i915/i915_active.h
index f95058f99057..35a6089b44fd 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -309,6 +309,7 @@ i915_active_request_isset(const struct i915_active_request *active)
*/
static inline int __must_check
i915_active_request_retire(struct i915_active_request *active,
+ unsigned int flags,
struct mutex *mutex)
{
struct i915_request *request;
@@ -318,9 +319,7 @@ i915_active_request_retire(struct i915_active_request *active,
if (!request)
return 0;
- ret = i915_request_wait(request,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT);
+ ret = i915_request_wait(request, flags, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
--
2.23.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 10/13] drm/i915/perf: execute OA configuration from command stream
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (8 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 09/13] drm/i915: add wait flags to i915_active_request_retire Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 11/13] drm/i915: add a new perf configuration execbuf parameter Lionel Landwerlin
` (5 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke things from the CPU.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
v4: Create i915 request in emit_oa_config() to avoid deadlocks (Lionel)
v5: Move locking to the stream (Lionel)
v6: Move active reconfiguration request into i915_perf_stream (Lionel)
v7: Pin VMA outside request creation (Chris)
Lock VMA before move to active (Chris)
v8: Fix double free on stream->initial_oa_config_bo (Lionel)
Don't allow interruption when waiting on active config request
(Lionel)
v9: Don't ignore return value from i915_active_request_retire (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 174 ++++++++++++++++---------
drivers/gpu/drm/i915/i915_perf_types.h | 15 ++-
2 files changed, 128 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d01494180465..929ab54ee371 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1557,18 +1557,23 @@ free_oa_configs(struct i915_perf_stream *stream)
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
+ int err;
BUG_ON(stream != dev_priv->perf.exclusive_stream);
- /*
- * Unset exclusive_stream first, it will be checked while disabling
- * the metric set on gen8+.
- */
mutex_lock(&dev_priv->drm.struct_mutex);
- dev_priv->perf.exclusive_stream = NULL;
+ mutex_lock(&stream->config_mutex);
dev_priv->perf.ops.disable_metric_set(stream);
+ err = i915_active_request_retire(&stream->active_config_rq, 0,
+ &stream->config_mutex);
+ mutex_unlock(&stream->config_mutex);
+ dev_priv->perf.exclusive_stream = NULL;
mutex_unlock(&dev_priv->drm.struct_mutex);
+ if (err)
+ DRM_ERROR("Failed to disable perf stream\n");
+
+
free_oa_buffer(stream);
free_noa_wait(stream);
@@ -1794,6 +1799,10 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
return PTR_ERR(bo);
}
+ ret = i915_mutex_lock_interruptible(&i915->drm);
+ if (ret)
+ goto err_unref;
+
/*
* We pin in GGTT because we jump into this buffer now because
* multiple OA config BOs will have a jump to this address and it
@@ -1801,10 +1810,13 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*/
vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
if (IS_ERR(vma)) {
+ mutex_unlock(&i915->drm.struct_mutex);
ret = PTR_ERR(vma);
goto err_unref;
}
+ mutex_unlock(&i915->drm.struct_mutex);
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
@@ -1938,7 +1950,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_vma_unpin_and_release(&vma, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
err_unref:
i915_gem_object_put(bo);
@@ -1946,50 +1960,73 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
return ret;
}
-static void config_oa_regs(struct drm_i915_private *dev_priv,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
- for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ lockdep_assert_held(&stream->config_mutex);
+
+ vma = i915_vma_instance(stream->initial_oa_config_bo,
+ &stream->engine->gt->ggtt->vm, NULL);
+ if (unlikely(IS_ERR(vma)))
+ return PTR_ERR(vma);
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_vma_unpin;
- I915_WRITE(reg->addr, reg->value);
+ rq = i915_request_create(stream->engine->kernel_context);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_add_request;
}
-}
-static void delay_after_mux(void)
-{
- /*
- * It apparently takes a fairly long time for a new MUX
- * configuration to be be applied after these register writes.
- * This delay duration was derived empirically based on the
- * render_basic config but hopefully it covers the maximum
- * configuration latency.
- *
- * As a fallback, the checks in _append_oa_reports() to skip
- * invalid OA reports do also seem to work to discard reports
- * generated before this config has completed - albeit not
- * silently.
- *
- * Unfortunately this is essentially a magic number, since we
- * don't currently know of a reliable mechanism for predicting
- * how long the MUX config will take to apply and besides
- * seeing invalid reports we don't know of a reliable way to
- * explicitly check that the MUX config has landed.
- *
- * It's even possible we've miss characterized the underlying
- * problem - it just seems like the simplest explanation why
- * a delay at this location would mitigate any invalid reports.
- */
- usleep_range(15000, 20000);
+ err = i915_active_request_set(&stream->active_config_rq,
+ rq);
+ if (err)
+ goto err_add_request;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, 0);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, 0);
+ i915_vma_unlock(vma);
+ if (err)
+ goto err_add_request;
+
+ cs = intel_ring_begin(rq, INTEL_GEN(i915) >= 8 ? 4 : 2);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_add_request;
+ }
+
+ if (INTEL_GEN(i915) > 8) {
+ *cs++ = MI_BATCH_BUFFER_START_GEN8;
+ *cs++ = lower_32_bits(vma->node.start);
+ *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = MI_NOOP;
+ } else {
+ *cs++ = MI_BATCH_BUFFER_START;
+ *cs++ = vma->node.start;
+ }
+
+ intel_ring_advance(rq, cs);
+
+err_add_request:
+ i915_request_add(rq);
+err_vma_unpin:
+ i915_vma_unpin(vma);
+
+ return err;
}
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
- const struct i915_oa_config *oa_config = stream->oa_config;
/*
* PRM:
@@ -2006,13 +2043,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream *stream)
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
GEN6_CSUNIT_CLOCK_GATE_DISABLE));
- config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
- delay_after_mux();
-
- config_oa_regs(dev_priv, oa_config->b_counter_regs,
- oa_config->b_counter_regs_len);
-
- return 0;
+ return emit_oa_config(dev_priv, stream);
}
static void hsw_disable_metric_set(struct i915_perf_stream *stream)
@@ -2371,13 +2402,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
if (ret)
return ret;
- config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
- delay_after_mux();
-
- config_oa_regs(dev_priv, oa_config->b_counter_regs,
- oa_config->b_counter_regs_len);
-
- return 0;
+ return emit_oa_config(dev_priv, stream);
}
static void gen8_disable_metric_set(struct i915_perf_stream *stream)
@@ -2596,6 +2621,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->engine = props->engine;
+ INIT_ACTIVE_REQUEST(&stream->active_config_rq,
+ &stream->config_mutex);
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2624,8 +2652,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_noa_wait_alloc;
}
- ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
- &stream->oa_config);
+ ret = i915_perf_get_oa_config_and_bo(stream, props->metrics_set,
+ &stream->oa_config,
+ &stream->initial_oa_config_bo);
if (ret) {
DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
goto err_config;
@@ -2657,16 +2686,35 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->ops = &i915_oa_stream_ops;
dev_priv->perf.exclusive_stream = stream;
+ mutex_lock(&stream->config_mutex);
ret = dev_priv->perf.ops.enable_metric_set(stream);
if (ret) {
+ int err;
+
DRM_DEBUG("Unable to enable metric set\n");
- goto err_enable;
+ /*
+ * Ignore the return value since we already have an error from
+ * the enable vfunc.
+ */
+ err = i915_active_request_retire(&stream->active_config_rq, 0,
+ &stream->config_mutex);
+ if (err)
+ DRM_ERROR("Wait on OA configuration request failed.\n");
+ } else {
+ ret = i915_active_request_retire(&stream->active_config_rq, 0,
+ &stream->config_mutex);
}
- DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
-
+ mutex_unlock(&stream->config_mutex);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ i915_gem_object_put(stream->initial_oa_config_bo);
+ stream->initial_oa_config_bo = NULL;
+ if (ret)
+ goto err_enable;
+
+ DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
+
hrtimer_init(&stream->poll_check_timer,
CLOCK_MONOTONIC, HRTIMER_MODE_REL);
stream->poll_check_timer.function = oa_poll_check_timer_cb;
@@ -2676,8 +2724,11 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return 0;
err_enable:
- dev_priv->perf.exclusive_stream = NULL;
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ mutex_lock(&stream->config_mutex);
dev_priv->perf.ops.disable_metric_set(stream);
+ mutex_unlock(&stream->config_mutex);
+ dev_priv->perf.exclusive_stream = NULL;
mutex_unlock(&dev_priv->drm.struct_mutex);
err_lock:
@@ -2689,6 +2740,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_configs(stream);
+ if (stream->initial_oa_config_bo)
+ i915_gem_object_put(stream->initial_oa_config_bo);
+
err_config:
free_noa_wait(stream);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 15ee0d33e44f..26cdb68197f9 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -15,9 +15,11 @@
#include <linux/uuid.h>
#include <linux/wait.h>
+#include "i915_active_types.h"
#include "i915_reg.h"
#include "intel_wakeref.h"
+struct drm_i915_gem_object;
struct drm_i915_private;
struct file;
struct i915_gem_context;
@@ -175,7 +177,8 @@ struct i915_perf_stream {
const struct i915_perf_stream_ops *ops;
/**
- * @active_config_mutex: Protects access to @oa_config & @oa_config_bos.
+ * @active_config_mutex: Protects access to @active_config_rq,
+ * @oa_config & @oa_config_bos.
*/
struct mutex config_mutex;
@@ -190,6 +193,16 @@ struct i915_perf_stream {
*/
struct list_head oa_config_bos;
+ /**
+ * @active_config_rq: Last request reconfiguring the HW.
+ */
+ struct i915_active_request active_config_rq;
+
+ /**
+ * @initial_oa_config_bo: First OA configuration BO to be run.
+ */
+ struct drm_i915_gem_object *initial_oa_config_bo;
+
/**
* The OA context specific information.
*/
--
2.23.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 11/13] drm/i915: add a new perf configuration execbuf parameter
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (9 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 10/13] drm/i915/perf: execute OA configuration from command stream Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 12/13] drm/i915/perf: allow holding preemption on filtered ctx Lionel Landwerlin
` (4 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process making the execbuf with this flag to
also own the perf fd at the time of execbuf.
v2: Add a emit_oa_config() vfunc in the intel_engine_cs (Chris)
Move oa_config vma to active (Chris)
v3: Don't drop the lock for engine lookup (Chris)
Move OA config vma to active before writing the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
v6: Use BIT_ULL (Chris)
v7: Hold drm.struct_mutex when serializing the request with OA config (Chris)
v8: Remove active request from engine (Lionel)
v9: Move fetching OA configuration pass engine pinning (Lionel)
Lock VMA before moving to active (Chris)
v10: Fix leak on perf_fd (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 147 +++++++++++++++++-
drivers/gpu/drm/i915/i915_getparam.c | 4 +
include/uapi/drm/i915_drm.h | 39 +++++
3 files changed, 188 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e488f22f53a4..ccb5ab542427 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -24,6 +24,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
+#include "i915_perf.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -284,7 +285,12 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
+ struct drm_i915_gem_execbuffer_ext_perf perf_config;
} extensions;
+
+ struct file *perf_file;
+ struct i915_oa_config *oa_config; /** HW configuration for OA, NULL is not needed. */
+ struct i915_vma *oa_vma;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1152,6 +1158,58 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
return err;
}
+
+static int
+eb_get_oa_config(struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_object *oa_bo;
+ int err = 0;
+
+ eb->perf_file = NULL;
+ eb->oa_config = NULL;
+ eb->oa_vma = NULL;
+
+ if ((eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF)) == 0)
+ return 0;
+
+ eb->perf_file = fget(eb->extensions.perf_config.perf_fd);
+ if (!eb->perf_file)
+ return -EINVAL;
+
+ err = i915_mutex_lock_interruptible(&eb->i915->drm);
+ if (err)
+ return err;
+
+ if (eb->perf_file->private_data != eb->i915->perf.exclusive_stream)
+ err = -EINVAL;
+
+ mutex_unlock(&eb->i915->drm.struct_mutex);
+
+ if (err)
+ return err;
+
+ if (eb->i915->perf.exclusive_stream->engine != eb->engine)
+ return -EINVAL;
+
+ err = i915_perf_get_oa_config_and_bo(
+ eb->i915->perf.exclusive_stream,
+ eb->extensions.perf_config.oa_config,
+ &eb->oa_config, &oa_bo);
+ if (err)
+ return err;
+
+ eb->oa_vma = i915_vma_instance(oa_bo,
+ &eb->engine->gt->ggtt->vm, NULL);
+ i915_gem_object_put(oa_bo);
+ if (IS_ERR(eb->oa_vma)) {
+ err = PTR_ERR(eb->oa_vma);
+ eb->oa_vma = NULL;
+ return err;
+ }
+
+ return 0;
+}
+
static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
struct i915_vma *vma,
unsigned int len)
@@ -2051,6 +2109,54 @@ add_to_client(struct i915_request *rq, struct drm_file *file)
spin_unlock(&file_priv->mm.lock);
}
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ struct i915_perf_stream *perf_stream;
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ perf_stream = eb->perf_file->private_data;
+
+ err = mutex_lock_interruptible(&perf_stream->config_mutex);
+ if (err)
+ return err;
+
+ err = i915_active_request_set(&perf_stream->active_config_rq,
+ eb->request);
+ if (err)
+ goto out;
+
+ /*
+ * If the config hasn't changed, skip reconfiguring the HW (this is
+ * subject to a delay we want to avoid has much as possible).
+ */
+ if (eb->oa_config == perf_stream->oa_config)
+ goto out;
+
+ i915_vma_lock(eb->oa_vma);
+ err = i915_request_await_object(eb->request, eb->oa_vma->obj, false); /* await_resv already! */
+ if (!err)
+ err = i915_vma_move_to_active(eb->oa_vma, eb->request, 0);
+ i915_vma_unlock(eb->oa_vma);
+ if (err)
+ goto out;
+
+ err = eb->engine->emit_bb_start(eb->request,
+ eb->oa_vma->node.start,
+ 0, I915_DISPATCH_SECURE);
+ if (err)
+ goto out;
+
+ swap(eb->oa_config, perf_stream->oa_config);
+
+out:
+ mutex_unlock(&perf_stream->config_mutex);
+
+ return err;
+}
+
static int eb_submit(struct i915_execbuffer *eb)
{
int err;
@@ -2077,6 +2183,10 @@ static int eb_submit(struct i915_execbuffer *eb)
return err;
}
+ err = eb_oa_config(eb);
+ if (err)
+ return err;
+
err = eb->engine->emit_bb_start(eb->request,
eb->batch->node.start +
eb->batch_start_offset,
@@ -2643,8 +2753,25 @@ static int parse_timeline_fences(struct i915_user_extension __user *ext, void *d
return 0;
}
+static int parse_perf_config(struct i915_user_extension __user *ext, void *data)
+{
+ struct i915_execbuffer *eb = data;
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF))
+ return -EINVAL;
+
+ if (copy_from_user(&eb->extensions.perf_config, ext,
+ sizeof(eb->extensions.perf_config)))
+ return -EFAULT;
+
+ eb->extensions.flags |= BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF);
+
+ return 0;
+}
+
static const i915_user_extension_fn execbuf_extensions[] = {
[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
+ [DRM_I915_GEM_EXECBUFFER_EXT_PERF] = parse_perf_config,
};
static int
@@ -2769,9 +2896,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_context;
+ err = eb_get_oa_config(&eb);
+ if (err)
+ goto err_oa_config;
+
err = i915_mutex_lock_interruptible(dev);
if (err)
- goto err_engine;
+ goto err_oa_config;
err = eb_relocate(&eb);
if (err) {
@@ -2889,6 +3020,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
}
+ if (eb.oa_vma) {
+ err = i915_vma_pin(eb.oa_vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_request;
+ }
+
/*
* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
@@ -2929,7 +3066,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (eb.exec)
eb_release_vmas(&eb);
mutex_unlock(&dev->struct_mutex);
-err_engine:
+err_oa_config:
+ if (eb.perf_file)
+ fput(eb.perf_file);
+ if (eb.oa_config)
+ i915_oa_config_put(eb.oa_config);
+ if (eb.oa_vma)
+ i915_vma_unpin(eb.oa_vma);
eb_unpin_engine(&eb);
err_context:
i915_gem_context_put(eb.gem_context);
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index bd41cc5ce906..39d4c2c2e0f4 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -161,6 +161,10 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+ case I915_PARAM_HAS_EXEC_PERF_CONFIG:
+ /* Obviously requires perf support. */
+ value = i915->perf.initialized;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e98c9a7baa91..3166c9ca85f3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -624,6 +624,16 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_PERF_REVISION 55
+/*
+ * Request an i915/perf performance configuration change before running the
+ * commands given in an execbuf.
+ *
+ * Performance configuration ID and the file descriptor of the i915 perf
+ * stream are given through drm_i915_gem_execbuffer_ext_perf. See
+ * I915_EXEC_EXT.
+ */
+#define I915_PARAM_HAS_EXEC_PERF_CONFIG 56
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1026,6 +1036,12 @@ enum drm_i915_gem_execbuffer_ext {
*/
DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 1,
+ /**
+ * This identifier is associated with
+ * drm_i915_gem_execbuffer_perf_ext.
+ */
+ DRM_I915_GEM_EXECBUFFER_EXT_PERF,
+
DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
};
@@ -1056,6 +1072,29 @@ struct drm_i915_gem_execbuffer_ext_timeline_fences {
__u64 values_ptr;
};
+struct drm_i915_gem_execbuffer_ext_perf {
+ struct i915_user_extension base;
+
+ /**
+ * Performance file descriptor returned by DRM_IOCTL_I915_PERF_OPEN.
+ * This is used to identify that the application requesting a HW
+ * performance configuration change actually has a right to do so
+ * because it also has access the i915-perf stream.
+ */
+ __s32 perf_fd;
+
+ /**
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 pad;
+
+ /**
+ * OA configuration ID to switch to before executing the commands
+ * associated to the execbuf.
+ */
+ __u64 oa_config;
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
--
2.23.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 12/13] drm/i915/perf: allow holding preemption on filtered ctx
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (10 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 11/13] drm/i915: add a new perf configuration execbuf parameter Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 9:31 ` [PATCH v16 13/13] drm/i915: add support for perf configuration queries Lionel Landwerlin
` (3 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++
drivers/gpu/drm/i915/i915_perf.c | 30 +++++++++++++++++--
drivers/gpu/drm/i915/i915_perf_types.h | 8 +++++
include/uapi/drm/i915_drm.h | 11 +++++++
4 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ccb5ab542427..230af0f0761a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2128,6 +2128,14 @@ static int eb_oa_config(struct i915_execbuffer *eb)
if (err)
goto out;
+ /*
+ * If the perf stream was opened with hold preemption, flag the
+ * request properly so that the priority of the request is bumped once
+ * it reaches the execlist ports.
+ */
+ if (eb->i915->perf.exclusive_stream->hold_preemption)
+ eb->request->flags |= I915_REQUEST_NOPREEMPT;
+
/*
* If the config hasn't changed, skip reconfiguring the HW (this is
* subject to a delay we want to avoid has much as possible).
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 929ab54ee371..0ffcb8d16154 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -343,6 +343,8 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -357,6 +359,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2631,6 +2634,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
if (WARN_ON(stream->oa_buffer.format_size == 0))
return -EINVAL;
+ stream->hold_preemption = props->hold_preemption;
+
stream->oa_buffer.format =
dev_priv->perf.oa_formats[props->oa_format].format;
@@ -3190,6 +3195,15 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
}
}
+ if (props->hold_preemption) {
+ if (!props->single_context) {
+ DRM_DEBUG("preemption disable with no context\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ privileged_op = true;
+ }
+
/*
* On Haswell the OA unit supports clock gating off for a specific
* context and in this mode there's no visibility of metrics for the
@@ -3204,7 +3218,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
*/
- if (IS_HASWELL(dev_priv) && specific_ctx)
+ if (IS_HASWELL(dev_priv) && specific_ctx && !props->hold_preemption)
privileged_op = false;
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
@@ -3214,7 +3228,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
*/
if (privileged_op &&
i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
- DRM_DEBUG("Insufficient privileges to open system-wide i915 perf stream\n");
+ DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
ret = -EACCES;
goto err_ctx;
}
@@ -3411,6 +3425,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
props->oa_periodic = true;
props->oa_period_exponent = value;
break;
+ case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
+ props->hold_preemption = !!value;
+ break;
case DRM_I915_PERF_PROP_MAX:
MISSING_CASE(id);
return -EINVAL;
@@ -4176,5 +4193,12 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
*/
int i915_perf_ioctl_version(void)
{
- return 1;
+ /* 1: initial version
+ *
+ * 2: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
+ * preemption on a particular context so that performance data is
+ * accessible from a delta of MI_RPC reports without looking at the
+ * OA buffer.
+ */
+ return 2;
}
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 26cdb68197f9..b5fc1e596ba3 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -170,6 +170,14 @@ struct i915_perf_stream {
*/
bool enabled;
+ /**
+ * @hold_preemption: Whether preemption is put on hold for command
+ * submissions done on the @ctx. This is useful for some drivers that
+ * cannot easily post process the OA buffer context to subtract delta
+ * of performance counters not associated with @ctx.
+ */
+ bool hold_preemption;
+
/**
* @ops: The callbacks providing the implementation of this specific
* type of configured stream.
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3166c9ca85f3..5850d68327ec 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1987,6 +1987,17 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
+ /**
+ * Specifying this property is only valid when specify a context to
+ * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
+ * will hold preemption of the particular context we want to gather
+ * performance data about. The execbuf2 submissions must include a
+ * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
+ *
+ * This property is available in perf revision 2.
+ */
+ DRM_I915_PERF_PROP_HOLD_PREEMPTION,
+
DRM_I915_PERF_PROP_MAX /* non-ABI */
};
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v16 13/13] drm/i915: add support for perf configuration queries
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (11 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 12/13] drm/i915/perf: allow holding preemption on filtered ctx Lionel Landwerlin
@ 2019-09-09 9:31 ` Lionel Landwerlin
2019-09-09 13:46 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Vulkan performance query support (rev17) Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 22+ messages in thread
From: Lionel Landwerlin @ 2019-09-09 9:31 UTC (permalink / raw)
To: intel-gfx
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
v5: Drop lock when copying config content to userspace (Chris)
v6: Drop lock when copying config list to userspace (Chris)
Fix deadlock when calling i915_perf_get_oa_config() under
perf.metrics_lock (Lionel)
Add i915_oa_config_get() (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 3 +
drivers/gpu/drm/i915/i915_query.c | 282 ++++++++++++++++++++++++++++++
include/uapi/drm/i915_drm.h | 65 ++++++-
4 files changed, 353 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c6f37219dff..eab42269fc5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1368,6 +1368,12 @@ struct drm_i915_private {
*/
struct idr metrics_idr;
+ /*
+ * Number of dynamic configurations, you need to hold
+ * dev_priv->perf.metrics_lock to access it.
+ */
+ u32 n_metrics;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0ffcb8d16154..cf392e4d6870 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3917,6 +3917,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
goto sysfs_err;
}
+ dev_priv->perf.n_metrics++;
+
mutex_unlock(&dev_priv->perf.metrics_lock);
DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
@@ -3977,6 +3979,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
&oa_config->sysfs_metric);
idr_remove(&dev_priv->perf.metrics_idr, *arg);
+ dev_priv->perf.n_metrics--;
mutex_unlock(&dev_priv->perf.metrics_lock);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index abac5042da2b..e1f0c184a209 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -7,6 +7,7 @@
#include <linux/nospec.h>
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_query.h"
#include <uapi/drm/i915_drm.h>
@@ -140,10 +141,291 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+ * We'll just put the number of registers, and won't copy the
+ * register.
+ */
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg *kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+ user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_oa_config *oa_config = NULL;
+ char uuid[UUID_STRING_LEN + 1];
+ u64 config_id;
+ u32 flags, total_size;
+ int ret;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ total_size = sizeof(struct drm_i915_query_perf_config) +
+ sizeof(struct drm_i915_perf_oa_config);
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+ DRM_DEBUG("Invalid query config data item size=%u expected=%u\n",
+ query_item->length, total_size);
+ return -EINVAL;
+ }
+
+ if (!access_ok(user_query_config_ptr, total_size))
+ return -EFAULT;
+
+ if (__get_user(flags, &user_query_config_ptr->flags))
+ return -EFAULT;
+
+ if (flags != 0)
+ return -EINVAL;
+
+ if (use_uuid) {
+ BUILD_BUG_ON(sizeof(user_query_config_ptr->uuid) >= sizeof(uuid));
+
+ memset(&uuid, 0, sizeof(uuid));
+ if (__copy_from_user(uuid, user_query_config_ptr->uuid,
+ sizeof(user_query_config_ptr->uuid)))
+ return -EFAULT;
+ } else {
+ if (__get_user(config_id, &user_query_config_ptr->config))
+ return -EFAULT;
+ }
+
+ if (use_uuid) {
+ struct i915_oa_config *tmp;
+ int id;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
+ if (ret)
+ return ret;
+
+ idr_for_each_entry(&i915->perf.metrics_idr, tmp, id) {
+ if (!strcmp(tmp->uuid, uuid)) {
+ oa_config = i915_oa_config_get(tmp);
+ break;
+ }
+ }
+
+ mutex_unlock(&i915->perf.metrics_lock);
+ } else {
+ ret = i915_perf_get_oa_config(i915, config_id, &oa_config);
+ }
+
+ if (ret || !oa_config)
+ return -ENOENT;
+
+ if (__copy_from_user(&user_config, user_config_ptr,
+ sizeof(user_config))) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_boolean_regs,
+ user_config.boolean_regs_ptr,
+ oa_config->b_counter_regs_len);
+ if (ret)
+ goto out;
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_flex_regs,
+ user_config.flex_regs_ptr,
+ oa_config->flex_regs_len);
+ if (ret)
+ goto out;
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_mux_regs,
+ user_config.mux_regs_ptr,
+ oa_config->mux_regs_len);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->b_counter_regs,
+ oa_config->b_counter_regs_len,
+ user_config.boolean_regs_ptr,
+ &user_config.n_boolean_regs);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->flex_regs,
+ oa_config->flex_regs_len,
+ user_config.flex_regs_ptr,
+ &user_config.n_flex_regs);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->mux_regs,
+ oa_config->mux_regs_len,
+ user_config.mux_regs_ptr,
+ &user_config.n_mux_regs);
+ if (ret)
+ goto out;
+
+ memcpy(user_config.uuid, oa_config->uuid, sizeof(user_config.uuid));
+
+ if (__copy_to_user(user_config_ptr, &user_config,
+ sizeof(user_config))) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ ret = total_size;
+
+out:
+ i915_oa_config_put(oa_config);
+
+ return ret;
+}
+
+static int query_perf_config_list(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct i915_oa_config *oa_config;
+ u32 flags, total_size;
+ u64 i, n_configs, *oa_config_ids;
+ int ret, id;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ /* Count the default test configuration */
+ n_configs = i915->perf.n_metrics + 1;
+ total_size = sizeof(struct drm_i915_query_perf_config) +
+ sizeof(u64) * n_configs;
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+ DRM_DEBUG("Invalid query config list item size=%u expected=%u\n",
+ query_item->length, total_size);
+ return -EINVAL;
+ }
+
+ if (!access_ok(user_query_config_ptr, total_size))
+ return -EFAULT;
+
+ if (__get_user(flags, &user_query_config_ptr->flags))
+ return -EFAULT;
+
+ if (flags != 0)
+ return -EINVAL;
+
+ if (__put_user(n_configs, &user_query_config_ptr->config))
+ return -EFAULT;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
+ if (ret)
+ return ret;
+
+ /* Count the configs. */
+ n_configs = 1;
+ idr_for_each_entry(&i915->perf.metrics_idr, oa_config, id)
+ n_configs++;
+
+ oa_config_ids =
+ kmalloc_array(n_configs, sizeof(*oa_config_ids), GFP_KERNEL);
+ if (!oa_config_ids) {
+ mutex_unlock(&i915->perf.metrics_lock);
+ return -ENOMEM;
+ }
+
+ i = 0;
+ oa_config_ids[i++] = 1ull;
+ idr_for_each_entry(&i915->perf.metrics_idr, oa_config, id)
+ oa_config_ids[i++] = id;
+
+ mutex_unlock(&i915->perf.metrics_lock);
+
+ ret = copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config)),
+ oa_config_ids,
+ n_configs * sizeof(*oa_config_ids));
+ kfree(oa_config_ids);
+ if (ret)
+ return ret;
+
+ return total_size;
+}
+
+static int query_perf_config(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ switch (query_item->flags) {
+ case DRM_I915_QUERY_PERF_CONFIG_LIST:
+ return query_perf_config_list(i915, query_item);
+ case DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID:
+ return query_perf_config_data(i915, query_item, true);
+ case DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID:
+ return query_perf_config_data(i915, query_item, false);
+ default:
+ return -EINVAL;
+ }
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) = {
query_topology_info,
query_engine_info,
+ query_perf_config,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5850d68327ec..2e7215989df2 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1037,8 +1037,7 @@ enum drm_i915_gem_execbuffer_ext {
DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 1,
/**
- * This identifier is associated with
- * drm_i915_gem_execbuffer_perf_ext.
+ * See drm_i915_gem_execbuffer_perf_ext.
*/
DRM_I915_GEM_EXECBUFFER_EXT_PERF,
@@ -2113,6 +2112,7 @@ struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
/* Must be kept compact -- no holes and well documented */
/*
@@ -2124,9 +2124,18 @@ struct drm_i915_query_item {
__s32 length;
/*
- * Unused for now. Must be cleared to zero.
+ * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+ *
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+ * following :
+ * - DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
+#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
/*
* Data will be written at the location pointed by data_ptr when the
@@ -2252,6 +2261,56 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+ */
+struct drm_i915_query_perf_config {
+ union {
+ /*
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
+ * this fields to the number of configurations available.
+ */
+ __u64 n_configs;
+
+ /*
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
+ * i915 will use the value in this field as configuration
+ * identifier to decide what data to write into config_ptr.
+ */
+ __u64 config;
+
+ /*
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
+ * i915 will use the value in this field as configuration
+ * identifier to decide what data to write into config_ptr.
+ *
+ * String formatted like "%08x-%04x-%04x-%04x-%012x"
+ */
+ char uuid[36];
+ };
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 flags;
+
+ /*
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
+ * write an array of __u64 of configuration identifiers.
+ *
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
+ * write a struct drm_i915_perf_oa_config. If the following fields of
+ * drm_i915_perf_oa_config are set not set to 0, i915 will write into
+ * the associated pointers the values of submitted when the
+ * configuration was created :
+ *
+ * - n_mux_regs
+ * - n_boolean_regs
+ * - n_flex_regs
+ */
+ __u8 data[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Vulkan performance query support (rev17)
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (12 preceding siblings ...)
2019-09-09 9:31 ` [PATCH v16 13/13] drm/i915: add support for perf configuration queries Lionel Landwerlin
@ 2019-09-09 13:46 ` Patchwork
2019-09-09 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-09-09 14:11 ` ✗ Fi.CI.BAT: failure " Patchwork
15 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-09-09 13:46 UTC (permalink / raw)
To: Zhou, David(ChunMing); +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f668eec43e67 drm/i915: introduce a mechanism to extend execbuf2
-:141: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#141: FILE: include/uapi/drm/i915_drm.h:1165:
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS<<1))
^
total: 0 errors, 0 warnings, 1 checks, 113 lines checked
01e462c1ffb7 drm/i915: add syncobj timeline support
-:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#25:
https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
total: 0 errors, 1 warnings, 0 checks, 541 lines checked
4585dca189a7 drm/i915/perf: drop list of streams
b57c0c8e871e drm/i915/perf: store the associated engine of a stream
6ca796aee82c drm/i915/perf: introduce a versioning of the i915-perf uapi
907b2948cada drm/i915/perf: move perf types to their own header
-:342: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#342:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 647 lines checked
cac9acbbf105 drm/i915/perf: allow for CS OA configs to be created lazily
9151840280e8 drm/i915/perf: implement active wait for noa configurations
-:258: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#258: FILE: drivers/gpu/drm/i915/i915_perf.c:1783:
+ DIV64_U64_ROUND_UP(
-:283: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#283: FILE: drivers/gpu/drm/i915/i915_perf.c:1808:
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
-:291: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#291: FILE: drivers/gpu/drm/i915/i915_perf.c:1816:
+ cs = save_restore_register(
-:295: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#295: FILE: drivers/gpu/drm/i915/i915_perf.c:1820:
+ cs = save_restore_register(
-:395: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#395: FILE: drivers/gpu/drm/i915/i915_perf.c:1920:
+ cs = save_restore_register(
-:399: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#399: FILE: drivers/gpu/drm/i915/i915_perf.c:1924:
+ cs = save_restore_register(
total: 0 errors, 0 warnings, 6 checks, 418 lines checked
cbc959b97634 drm/i915: add wait flags to i915_active_request_retire
83208e81f732 drm/i915/perf: execute OA configuration from command stream
-:68: CHECK:LINE_SPACING: Please don't use multiple blank lines
#68: FILE: drivers/gpu/drm/i915/i915_perf.c:1576:
+
+
total: 0 errors, 0 warnings, 1 checks, 311 lines checked
2efaf8d89c09 drm/i915: add a new perf configuration execbuf parameter
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#27:
v7: Hold drm.struct_mutex when serializing the request with OA config (Chris)
-:67: CHECK:LINE_SPACING: Please don't use multiple blank lines
#67: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1161:
+
-:100: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#100: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1194:
+ err = i915_perf_get_oa_config_and_bo(
-:153: WARNING:LONG_LINE_COMMENT: line over 100 characters
#153: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2139:
+ err = i915_request_await_object(eb->request, eb->oa_vma->obj, false); /* await_resv already! */
total: 0 errors, 2 warnings, 2 checks, 273 lines checked
3aea377b5819 drm/i915/perf: allow holding preemption on filtered ctx
a30df8fa37a2 drm/i915: add support for perf configuration queries
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: Vulkan performance query support (rev17)
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (13 preceding siblings ...)
2019-09-09 13:46 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Vulkan performance query support (rev17) Patchwork
@ 2019-09-09 13:53 ` Patchwork
2019-09-09 14:11 ` ✗ Fi.CI.BAT: failure " Patchwork
15 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-09-09 13:53 UTC (permalink / raw)
To: Zhou, David(ChunMing); +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: introduce a mechanism to extend execbuf2
Okay!
Commit: drm/i915: add syncobj timeline support
Okay!
Commit: drm/i915/perf: drop list of streams
+drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1492:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216
Commit: drm/i915/perf: store the associated engine of a stream
Okay!
Commit: drm/i915/perf: introduce a versioning of the i915-perf uapi
Okay!
Commit: drm/i915/perf: move perf types to their own header
Okay!
Commit: drm/i915/perf: allow for CS OA configs to be created lazily
Okay!
Commit: drm/i915/perf: implement active wait for noa configurations
Okay!
Commit: drm/i915: add wait flags to i915_active_request_retire
Okay!
Commit: drm/i915/perf: execute OA configuration from command stream
Okay!
Commit: drm/i915: add a new perf configuration execbuf parameter
Okay!
Commit: drm/i915/perf: allow holding preemption on filtered ctx
Okay!
Commit: drm/i915: add support for perf configuration queries
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: Vulkan performance query support (rev17)
2019-09-09 9:31 [PATCH v16 00/13] drm/i915: Vulkan performance query support Lionel Landwerlin
` (14 preceding siblings ...)
2019-09-09 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-09-09 14:11 ` Patchwork
15 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-09-09 14:11 UTC (permalink / raw)
To: Zhou, David(ChunMing); +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev17)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6853 -> Patchwork_14324
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14324 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14324, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14324:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][3] ([fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111096]) -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-hpd-fast:
- fi-kbl-7500u: [SKIP][7] ([fdo#109271]) -> [FAIL][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium@common-hpd-after-suspend:
- {fi-icl-u4}: [FAIL][9] ([fdo#111049]) -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-icl-u4/igt@kms_chamelium@common-hpd-after-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-icl-u4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}: [FAIL][11] ([fdo#111045]) -> [FAIL][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-hpd-fast:
- {fi-icl-u4}: [SKIP][13] ([fdo#109309]) -> [FAIL][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-icl-u4/igt@kms_chamelium@vga-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-icl-u4/igt@kms_chamelium@vga-hpd-fast.html
Known issues
------------
Here are the changes found in Patchwork_14324 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][15] -> [SKIP][16] ([fdo#109271] / [fdo#109278]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_busy@basic-flip-c.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][17] -> [FAIL][18] ([fdo#109635 ]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2: [PASS][19] -> [FAIL][20] ([fdo#108767]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][21] -> [DMESG-WARN][22] ([fdo#102614])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
- fi-icl-u2: [PASS][23] -> [FAIL][24] ([fdo#103167])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [PASS][25] -> [SKIP][26] ([fdo#109271]) +23 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-kbl-7500u/igt@prime_vgem@basic-fence-flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-kbl-7500u/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-write-read:
- fi-icl-u3: [DMESG-WARN][27] ([fdo#107724]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-icl-u3/igt@gem_mmap_gtt@basic-write-read.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-icl-u3/igt@gem_mmap_gtt@basic-write-read.html
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-cml-u2: [DMESG-WARN][29] ([fdo#102505]) -> [FAIL][30] ([fdo#108767] / [fdo#109380])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2: [SKIP][31] ([fdo#110753]) -> [FAIL][32] ([fdo#108767]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-cml-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-cml-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-hpd-fast:
- fi-cml-u2: [SKIP][33] ([fdo#109309]) -> [FAIL][34] ([fdo#108767]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6853/fi-cml-u2/igt@kms_chamelium@vga-hpd-fast.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/fi-cml-u2/igt@kms_chamelium@vga-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110753]: https://bugs.freedesktop.org/show_bug.cgi?id=110753
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (53 -> 46)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6853 -> Patchwork_14324
CI-20190529: 20190529
CI_DRM_6853: ad1a8a60aba111d2c186d19391d5a17bd09ab48b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5176: 0102dcf4e2e8b357b59173fe1ff78069148080c6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14324: a30df8fa37a295af79a98255e53ff1ce2a22dae3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a30df8fa37a2 drm/i915: add support for perf configuration queries
3aea377b5819 drm/i915/perf: allow holding preemption on filtered ctx
2efaf8d89c09 drm/i915: add a new perf configuration execbuf parameter
83208e81f732 drm/i915/perf: execute OA configuration from command stream
cbc959b97634 drm/i915: add wait flags to i915_active_request_retire
9151840280e8 drm/i915/perf: implement active wait for noa configurations
cac9acbbf105 drm/i915/perf: allow for CS OA configs to be created lazily
907b2948cada drm/i915/perf: move perf types to their own header
6ca796aee82c drm/i915/perf: introduce a versioning of the i915-perf uapi
b57c0c8e871e drm/i915/perf: store the associated engine of a stream
4585dca189a7 drm/i915/perf: drop list of streams
01e462c1ffb7 drm/i915: add syncobj timeline support
f668eec43e67 drm/i915: introduce a mechanism to extend execbuf2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14324/
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