[PATCH v4 0/8] cdclk consolidation and rework for BXT-TGL

[PATCH v4 0/8] cdclk consolidation and rework for BXT-TGL

[Matt Roper]

Previous version of the series was here:
    https://lists.freedesktop.org/archives/intel-gfx/2019-September/211853.html

This version incorporates Ville's comments, most of which are on the
second patch where we introduce the cdclk tables.  The structure and
parsing of the tables is now done in a cleaner and more future-proof
manner.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Matt Roper (8):
  drm/i915: Consolidate bxt/cnl/icl cdclk readout
  drm/i915: Use literal representation of cdclk tables
  drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
  drm/i915: Kill cnl_sanitize_cdclk()
  drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk
  drm/i915: Add calc_voltage_level display vfunc
  drm/i915: Enhance cdclk sanitization
  drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk

 drivers/gpu/drm/i915/display/intel_cdclk.c | 965 +++++++--------------
 drivers/gpu/drm/i915/display/intel_cdclk.h |   7 +
 drivers/gpu/drm/i915/i915_drv.h            |   4 +
 3 files changed, 345 insertions(+), 631 deletions(-)

-- 
2.20.1

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[PATCH v4 1/8] drm/i915: Consolidate bxt/cnl/icl cdclk readout

[Matt Roper]

Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp.  Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.

Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me think we should be writing to hardware rather than
reading from it.

v2:
 - Fix icl_calc_voltage_level() limits.  (Ville)
 - Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on
   gen10+ to avoid confusion.  (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +++++++++------------
 1 file changed, 138 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d3e56628af70..01ed3262d91e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1190,6 +1190,36 @@ static u8 bxt_calc_voltage_level(int cdclk)
 	return DIV_ROUND_UP(cdclk, 25000);
 }
 
+static u8 cnl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 336000)
+		return 2;
+	else if (cdclk > 168000)
+		return 1;
+	else
+		return 0;
+}
+
+static u8 icl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 556800)
+		return 2;
+	else if (cdclk > 312000)
+		return 1;
+	else
+		return 0;
+}
+
+static u8 ehl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 326400)
+		return 2;
+	else if (cdclk > 180000)
+		return 1;
+	else
+		return 0;
+}
+
 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
 	int ratio;
@@ -1236,23 +1266,69 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 	return dev_priv->cdclk.hw.ref * ratio;
 }
 
-static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
-			      struct intel_cdclk_state *cdclk_state)
+static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
 {
-	u32 val;
+	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
+		cdclk_state->ref = 24000;
+	else
+		cdclk_state->ref = 19200;
+}
 
-	cdclk_state->ref = 19200;
-	cdclk_state->vco = 0;
+static void icl_readout_refclk(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
+{
+	u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
+
+	switch (dssm) {
+	default:
+		MISSING_CASE(dssm);
+		/* fall through */
+	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+		cdclk_state->ref = 24000;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+		cdclk_state->ref = 19200;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+		cdclk_state->ref = 38400;
+		break;
+	}
+}
+
+static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
+{
+	u32 val, ratio;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_readout_refclk(dev_priv, cdclk_state);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_readout_refclk(dev_priv, cdclk_state);
+	else
+		cdclk_state->ref = 19200;
 
 	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+	    (val & BXT_DE_PLL_LOCK) == 0) {
+		/*
+		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+		 * setting it to zero is a way to signal that.
+		 */
+		cdclk_state->vco = 0;
 		return;
+	}
 
-	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
-		return;
+	/*
+	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
+	 * it in a separate PLL control register.
+	 */
+	if (INTEL_GEN(dev_priv) >= 10)
+		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
+	else
+		ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
 
-	val = I915_READ(BXT_DE_PLL_CTL);
-	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+	cdclk_state->vco = ratio * cdclk_state->ref;
 }
 
 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1261,12 +1337,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	u32 divider;
 	int div;
 
-	bxt_de_pll_update(dev_priv, cdclk_state);
-
-	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
+	if (INTEL_GEN(dev_priv) >= 12)
+		cdclk_state->bypass = cdclk_state->ref / 2;
+	else if (INTEL_GEN(dev_priv) >= 11)
+		cdclk_state->bypass = 50000;
+	else
+		cdclk_state->bypass = cdclk_state->ref;
 
-	if (cdclk_state->vco == 0)
+	bxt_de_pll_readout(dev_priv, cdclk_state);
+	if (cdclk_state->vco == 0) {
+		cdclk_state->cdclk = cdclk_state->bypass;
 		goto out;
+	}
 
 	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
 
@@ -1275,13 +1357,15 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 		div = 2;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
-		WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
+		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+		     "Unsupported divider\n");
 		div = 3;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_2:
 		div = 4;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_4:
+		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
 		div = 8;
 		break;
 	default:
@@ -1296,8 +1380,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	 * Can't read this out :( Let's assume it's
 	 * at least what the CDCLK frequency requires.
 	 */
-	cdclk_state->voltage_level =
-		bxt_calc_voltage_level(cdclk_state->cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		cdclk_state->voltage_level =
+			ehl_calc_voltage_level(cdclk_state->cdclk);
+	else if (INTEL_GEN(dev_priv) >= 11)
+		cdclk_state->voltage_level =
+			icl_calc_voltage_level(cdclk_state->cdclk);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		cdclk_state->voltage_level =
+			cnl_calc_voltage_level(cdclk_state->cdclk);
+	else
+		cdclk_state->voltage_level =
+			bxt_calc_voltage_level(cdclk_state->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1515,76 +1609,6 @@ static int cnl_calc_cdclk(int min_cdclk)
 		return 168000;
 }
 
-static u8 cnl_calc_voltage_level(int cdclk)
-{
-	if (cdclk > 336000)
-		return 2;
-	else if (cdclk > 168000)
-		return 1;
-	else
-		return 0;
-}
-
-static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
-				 struct intel_cdclk_state *cdclk_state)
-{
-	u32 val;
-
-	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
-		cdclk_state->ref = 24000;
-	else
-		cdclk_state->ref = 19200;
-
-	cdclk_state->vco = 0;
-
-	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
-		return;
-
-	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
-		return;
-
-	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
-}
-
-static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
-			 struct intel_cdclk_state *cdclk_state)
-{
-	u32 divider;
-	int div;
-
-	cnl_cdclk_pll_update(dev_priv, cdclk_state);
-
-	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
-
-	if (cdclk_state->vco == 0)
-		goto out;
-
-	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
-
-	switch (divider) {
-	case BXT_CDCLK_CD2X_DIV_SEL_1:
-		div = 2;
-		break;
-	case BXT_CDCLK_CD2X_DIV_SEL_2:
-		div = 4;
-		break;
-	default:
-		MISSING_CASE(divider);
-		return;
-	}
-
-	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
-
- out:
-	/*
-	 * Can't read this out :( Let's assume it's
-	 * at least what the CDCLK frequency requires.
-	 */
-	cdclk_state->voltage_level =
-		cnl_calc_voltage_level(cdclk_state->cdclk);
-}
-
 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -1830,91 +1854,6 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 	return dev_priv->cdclk.hw.ref * ratio;
 }
 
-static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
-{
-	if (IS_ELKHARTLAKE(dev_priv)) {
-		if (cdclk > 312000)
-			return 2;
-		else if (cdclk > 180000)
-			return 1;
-		else
-			return 0;
-	} else {
-		if (cdclk > 556800)
-			return 2;
-		else if (cdclk > 312000)
-			return 1;
-		else
-			return 0;
-	}
-}
-
-static void icl_get_cdclk(struct drm_i915_private *dev_priv,
-			  struct intel_cdclk_state *cdclk_state)
-{
-	u32 val;
-	int div;
-
-	val = I915_READ(SKL_DSSM);
-	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
-	default:
-		MISSING_CASE(val);
-		/* fall through */
-	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
-		cdclk_state->ref = 24000;
-		break;
-	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
-		cdclk_state->ref = 19200;
-		break;
-	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
-		cdclk_state->ref = 38400;
-		break;
-	}
-
-	if (INTEL_GEN(dev_priv) >= 12)
-		cdclk_state->bypass = cdclk_state->ref / 2;
-	else
-		cdclk_state->bypass = 50000;
-
-	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
-	    (val & BXT_DE_PLL_LOCK) == 0) {
-		/*
-		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
-		 * setting it to zero is a way to signal that.
-		 */
-		cdclk_state->vco = 0;
-		cdclk_state->cdclk = cdclk_state->bypass;
-		goto out;
-	}
-
-	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
-
-	val = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
-	switch (val) {
-	case BXT_CDCLK_CD2X_DIV_SEL_1:
-		div = 2;
-		break;
-	case BXT_CDCLK_CD2X_DIV_SEL_2:
-		div = 4;
-		break;
-	default:
-		MISSING_CASE(val);
-		div = 2;
-		break;
-	}
-
-	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
-
-out:
-	/*
-	 * Can't read this out :( Let's assume it's
-	 * at least what the CDCLK frequency requires.
-	 */
-	cdclk_state->voltage_level =
-		icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
-}
-
 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state sanitized_state;
@@ -1946,9 +1885,12 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
 	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
 						     sanitized_state.cdclk);
-	sanitized_state.voltage_level =
-				icl_calc_voltage_level(dev_priv,
-						       sanitized_state.cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		sanitized_state.voltage_level =
+			ehl_calc_voltage_level(sanitized_state.cdclk);
+	else
+		sanitized_state.voltage_level =
+			icl_calc_voltage_level(sanitized_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
@@ -1959,8 +1901,12 @@ static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
-	cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
-							   cdclk_state.cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		cdclk_state.voltage_level =
+			ehl_calc_voltage_level(cdclk_state.cdclk);
+	else
+		cdclk_state.voltage_level =
+			icl_calc_voltage_level(cdclk_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -2561,9 +2507,14 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		max(icl_calc_voltage_level(dev_priv, cdclk),
-		    cnl_compute_min_voltage_level(state));
+	if (IS_ELKHARTLAKE(dev_priv))
+		state->cdclk.logical.voltage_level =
+			max(ehl_calc_voltage_level(cdclk),
+			    cnl_compute_min_voltage_level(state));
+	else
+		state->cdclk.logical.voltage_level =
+			max(icl_calc_voltage_level(cdclk),
+			    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
 		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
@@ -2571,8 +2522,12 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			icl_calc_voltage_level(dev_priv, cdclk);
+		if (IS_ELKHARTLAKE(dev_priv))
+			state->cdclk.actual.voltage_level =
+				ehl_calc_voltage_level(cdclk);
+		else
+			state->cdclk.actual.voltage_level =
+				icl_calc_voltage_level(cdclk);
 	} else {
 		state->cdclk.actual = state->cdclk.logical;
 	}
@@ -2819,11 +2774,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		dev_priv->display.get_cdclk = icl_get_cdclk;
-	else if (IS_CANNONLAKE(dev_priv))
-		dev_priv->display.get_cdclk = cnl_get_cdclk;
-	else if (IS_GEN9_LP(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
 		dev_priv->display.get_cdclk = bxt_get_cdclk;
 	else if (IS_GEN9_BC(dev_priv))
 		dev_priv->display.get_cdclk = skl_get_cdclk;
-- 
2.20.1

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Re: [PATCH v4 1/8] drm/i915: Consolidate bxt/cnl/icl cdclk readout

[Ville Syrjälä]

On Tue, Sep 10, 2019 at 08:42:45AM -0700, Matt Roper wrote:
> Aside from a few minor register changes and some different clock values,
> cdclk design hasn't changed much since gen9lp.  Let's consolidate the
> handlers for bxt, cnl, and icl to keep the codeflow consistent.
> 
> Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
> "update" makes me think we should be writing to hardware rather than
> reading from it.
> 
> v2:
>  - Fix icl_calc_voltage_level() limits.  (Ville)
>  - Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on
>    gen10+ to avoid confusion.  (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +++++++++------------
>  1 file changed, 138 insertions(+), 187 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d3e56628af70..01ed3262d91e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1190,6 +1190,36 @@ static u8 bxt_calc_voltage_level(int cdclk)
>  	return DIV_ROUND_UP(cdclk, 25000);
>  }
>  
> +static u8 cnl_calc_voltage_level(int cdclk)
> +{
> +	if (cdclk > 336000)
> +		return 2;
> +	else if (cdclk > 168000)
> +		return 1;
> +	else
> +		return 0;
> +}
> +
> +static u8 icl_calc_voltage_level(int cdclk)
> +{
> +	if (cdclk > 556800)
> +		return 2;
> +	else if (cdclk > 312000)
> +		return 1;
> +	else
> +		return 0;
> +}
> +
> +static u8 ehl_calc_voltage_level(int cdclk)
> +{
> +	if (cdclk > 326400)

This still looks off.

> +		return 2;
> +	else if (cdclk > 180000)
> +		return 1;
> +	else
> +		return 0;
> +}
> +
>  static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  {
>  	int ratio;
> @@ -1236,23 +1266,69 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  	return dev_priv->cdclk.hw.ref * ratio;
>  }
>  
> -static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
> -			      struct intel_cdclk_state *cdclk_state)
> +static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
> +			       struct intel_cdclk_state *cdclk_state)
>  {
> -	u32 val;
> +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> +		cdclk_state->ref = 24000;
> +	else
> +		cdclk_state->ref = 19200;
> +}
>  
> -	cdclk_state->ref = 19200;
> -	cdclk_state->vco = 0;
> +static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> +			       struct intel_cdclk_state *cdclk_state)
> +{
> +	u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
> +
> +	switch (dssm) {
> +	default:
> +		MISSING_CASE(dssm);
> +		/* fall through */
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> +		cdclk_state->ref = 24000;
> +		break;
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> +		cdclk_state->ref = 19200;
> +		break;
> +	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> +		cdclk_state->ref = 38400;
> +		break;
> +	}
> +}
> +
> +static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> +			       struct intel_cdclk_state *cdclk_state)
> +{
> +	u32 val, ratio;
> +
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		icl_readout_refclk(dev_priv, cdclk_state);
> +	else if (IS_CANNONLAKE(dev_priv))
> +		cnl_readout_refclk(dev_priv, cdclk_state);
> +	else
> +		cdclk_state->ref = 19200;
>  
>  	val = I915_READ(BXT_DE_PLL_ENABLE);
> -	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> +	    (val & BXT_DE_PLL_LOCK) == 0) {
> +		/*
> +		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> +		 * setting it to zero is a way to signal that.
> +		 */
> +		cdclk_state->vco = 0;
>  		return;
> +	}
>  
> -	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> -		return;
> +	/*
> +	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
> +	 * it in a separate PLL control register.
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 10)
> +		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
> +	else
> +		ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
>  
> -	val = I915_READ(BXT_DE_PLL_CTL);
> -	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +	cdclk_state->vco = ratio * cdclk_state->ref;
>  }
>  
>  static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> @@ -1261,12 +1337,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	u32 divider;
>  	int div;
>  
> -	bxt_de_pll_update(dev_priv, cdclk_state);
> -
> -	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		cdclk_state->bypass = cdclk_state->ref / 2;
> +	else if (INTEL_GEN(dev_priv) >= 11)
> +		cdclk_state->bypass = 50000;
> +	else
> +		cdclk_state->bypass = cdclk_state->ref;
>  
> -	if (cdclk_state->vco == 0)
> +	bxt_de_pll_readout(dev_priv, cdclk_state);
> +	if (cdclk_state->vco == 0) {
> +		cdclk_state->cdclk = cdclk_state->bypass;
>  		goto out;
> +	}
>  
>  	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
>  
> @@ -1275,13 +1357,15 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  		div = 2;
>  		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> -		WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
> +		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
> +		     "Unsupported divider\n");
>  		div = 3;
>  		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_2:
>  		div = 4;
>  		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_4:
> +		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
>  		div = 8;
>  		break;
>  	default:
> @@ -1296,8 +1380,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	 * Can't read this out :( Let's assume it's
>  	 * at least what the CDCLK frequency requires.
>  	 */
> -	cdclk_state->voltage_level =
> -		bxt_calc_voltage_level(cdclk_state->cdclk);
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		cdclk_state->voltage_level =
> +			ehl_calc_voltage_level(cdclk_state->cdclk);
> +	else if (INTEL_GEN(dev_priv) >= 11)
> +		cdclk_state->voltage_level =
> +			icl_calc_voltage_level(cdclk_state->cdclk);
> +	else if (INTEL_GEN(dev_priv) >= 10)
> +		cdclk_state->voltage_level =
> +			cnl_calc_voltage_level(cdclk_state->cdclk);
> +	else
> +		cdclk_state->voltage_level =
> +			bxt_calc_voltage_level(cdclk_state->cdclk);
>  }
>  
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1515,76 +1609,6 @@ static int cnl_calc_cdclk(int min_cdclk)
>  		return 168000;
>  }
>  
> -static u8 cnl_calc_voltage_level(int cdclk)
> -{
> -	if (cdclk > 336000)
> -		return 2;
> -	else if (cdclk > 168000)
> -		return 1;
> -	else
> -		return 0;
> -}
> -
> -static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> -				 struct intel_cdclk_state *cdclk_state)
> -{
> -	u32 val;
> -
> -	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> -		cdclk_state->ref = 24000;
> -	else
> -		cdclk_state->ref = 19200;
> -
> -	cdclk_state->vco = 0;
> -
> -	val = I915_READ(BXT_DE_PLL_ENABLE);
> -	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> -		return;
> -
> -	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> -		return;
> -
> -	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> -}
> -
> -static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> -			 struct intel_cdclk_state *cdclk_state)
> -{
> -	u32 divider;
> -	int div;
> -
> -	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> -
> -	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
> -
> -	if (cdclk_state->vco == 0)
> -		goto out;
> -
> -	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> -
> -	switch (divider) {
> -	case BXT_CDCLK_CD2X_DIV_SEL_1:
> -		div = 2;
> -		break;
> -	case BXT_CDCLK_CD2X_DIV_SEL_2:
> -		div = 4;
> -		break;
> -	default:
> -		MISSING_CASE(divider);
> -		return;
> -	}
> -
> -	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> -
> - out:
> -	/*
> -	 * Can't read this out :( Let's assume it's
> -	 * at least what the CDCLK frequency requires.
> -	 */
> -	cdclk_state->voltage_level =
> -		cnl_calc_voltage_level(cdclk_state->cdclk);
> -}
> -
>  static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>  {
>  	u32 val;
> @@ -1830,91 +1854,6 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  	return dev_priv->cdclk.hw.ref * ratio;
>  }
>  
> -static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
> -{
> -	if (IS_ELKHARTLAKE(dev_priv)) {
> -		if (cdclk > 312000)
> -			return 2;
> -		else if (cdclk > 180000)
> -			return 1;
> -		else
> -			return 0;
> -	} else {
> -		if (cdclk > 556800)
> -			return 2;
> -		else if (cdclk > 312000)
> -			return 1;
> -		else
> -			return 0;
> -	}
> -}
> -
> -static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> -			  struct intel_cdclk_state *cdclk_state)
> -{
> -	u32 val;
> -	int div;
> -
> -	val = I915_READ(SKL_DSSM);
> -	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> -	default:
> -		MISSING_CASE(val);
> -		/* fall through */
> -	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> -		cdclk_state->ref = 24000;
> -		break;
> -	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> -		cdclk_state->ref = 19200;
> -		break;
> -	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> -		cdclk_state->ref = 38400;
> -		break;
> -	}
> -
> -	if (INTEL_GEN(dev_priv) >= 12)
> -		cdclk_state->bypass = cdclk_state->ref / 2;
> -	else
> -		cdclk_state->bypass = 50000;
> -
> -	val = I915_READ(BXT_DE_PLL_ENABLE);
> -	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> -	    (val & BXT_DE_PLL_LOCK) == 0) {
> -		/*
> -		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> -		 * setting it to zero is a way to signal that.
> -		 */
> -		cdclk_state->vco = 0;
> -		cdclk_state->cdclk = cdclk_state->bypass;
> -		goto out;
> -	}
> -
> -	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> -
> -	val = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> -	switch (val) {
> -	case BXT_CDCLK_CD2X_DIV_SEL_1:
> -		div = 2;
> -		break;
> -	case BXT_CDCLK_CD2X_DIV_SEL_2:
> -		div = 4;
> -		break;
> -	default:
> -		MISSING_CASE(val);
> -		div = 2;
> -		break;
> -	}
> -
> -	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> -
> -out:
> -	/*
> -	 * Can't read this out :( Let's assume it's
> -	 * at least what the CDCLK frequency requires.
> -	 */
> -	cdclk_state->voltage_level =
> -		icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
> -}
> -
>  static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state sanitized_state;
> @@ -1946,9 +1885,12 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>  	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
>  	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
>  						     sanitized_state.cdclk);
> -	sanitized_state.voltage_level =
> -				icl_calc_voltage_level(dev_priv,
> -						       sanitized_state.cdclk);
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		sanitized_state.voltage_level =
> +			ehl_calc_voltage_level(sanitized_state.cdclk);
> +	else
> +		sanitized_state.voltage_level =
> +			icl_calc_voltage_level(sanitized_state.cdclk);
>  
>  	cnl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
>  }
> @@ -1959,8 +1901,12 @@ static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  	cdclk_state.cdclk = cdclk_state.bypass;
>  	cdclk_state.vco = 0;
> -	cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
> -							   cdclk_state.cdclk);
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		cdclk_state.voltage_level =
> +			ehl_calc_voltage_level(cdclk_state.cdclk);
> +	else
> +		cdclk_state.voltage_level =
> +			icl_calc_voltage_level(cdclk_state.cdclk);
>  
>  	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
>  }
> @@ -2561,9 +2507,14 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
> -	state->cdclk.logical.voltage_level =
> -		max(icl_calc_voltage_level(dev_priv, cdclk),
> -		    cnl_compute_min_voltage_level(state));
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		state->cdclk.logical.voltage_level =
> +			max(ehl_calc_voltage_level(cdclk),
> +			    cnl_compute_min_voltage_level(state));
> +	else
> +		state->cdclk.logical.voltage_level =
> +			max(icl_calc_voltage_level(cdclk),
> +			    cnl_compute_min_voltage_level(state));
>  
>  	if (!state->active_pipes) {
>  		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
> @@ -2571,8 +2522,12 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  
>  		state->cdclk.actual.vco = vco;
>  		state->cdclk.actual.cdclk = cdclk;
> -		state->cdclk.actual.voltage_level =
> -			icl_calc_voltage_level(dev_priv, cdclk);
> +		if (IS_ELKHARTLAKE(dev_priv))
> +			state->cdclk.actual.voltage_level =
> +				ehl_calc_voltage_level(cdclk);
> +		else
> +			state->cdclk.actual.voltage_level =
> +				icl_calc_voltage_level(cdclk);
>  	} else {
>  		state->cdclk.actual = state->cdclk.logical;
>  	}
> @@ -2819,11 +2774,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		dev_priv->display.get_cdclk = icl_get_cdclk;
> -	else if (IS_CANNONLAKE(dev_priv))
> -		dev_priv->display.get_cdclk = cnl_get_cdclk;
> -	else if (IS_GEN9_LP(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
>  		dev_priv->display.get_cdclk = bxt_get_cdclk;
>  	else if (IS_GEN9_BC(dev_priv))
>  		dev_priv->display.get_cdclk = skl_get_cdclk;
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 1/8] drm/i915: Consolidate bxt/cnl/icl cdclk readout

[Matt Roper]

Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp.  Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.

Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me think we should be writing to hardware rather than
reading from it.

v2:
 - Fix icl_calc_voltage_level() limits.  (Ville)
 - Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on
   gen10+ to avoid confusion.  (Ville)

v3:
 - Also fix ehl_calc_voltage_level() limits.  (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +++++++++------------
 1 file changed, 138 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d3e56628af70..dfcb1cc58951 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1190,6 +1190,36 @@ static u8 bxt_calc_voltage_level(int cdclk)
 	return DIV_ROUND_UP(cdclk, 25000);
 }
 
+static u8 cnl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 336000)
+		return 2;
+	else if (cdclk > 168000)
+		return 1;
+	else
+		return 0;
+}
+
+static u8 icl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 556800)
+		return 2;
+	else if (cdclk > 312000)
+		return 1;
+	else
+		return 0;
+}
+
+static u8 ehl_calc_voltage_level(int cdclk)
+{
+	if (cdclk > 312000)
+		return 2;
+	else if (cdclk > 180000)
+		return 1;
+	else
+		return 0;
+}
+
 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
 	int ratio;
@@ -1236,23 +1266,69 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 	return dev_priv->cdclk.hw.ref * ratio;
 }
 
-static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
-			      struct intel_cdclk_state *cdclk_state)
+static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
 {
-	u32 val;
+	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
+		cdclk_state->ref = 24000;
+	else
+		cdclk_state->ref = 19200;
+}
 
-	cdclk_state->ref = 19200;
-	cdclk_state->vco = 0;
+static void icl_readout_refclk(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
+{
+	u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
+
+	switch (dssm) {
+	default:
+		MISSING_CASE(dssm);
+		/* fall through */
+	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+		cdclk_state->ref = 24000;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+		cdclk_state->ref = 19200;
+		break;
+	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+		cdclk_state->ref = 38400;
+		break;
+	}
+}
+
+static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
+			       struct intel_cdclk_state *cdclk_state)
+{
+	u32 val, ratio;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_readout_refclk(dev_priv, cdclk_state);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_readout_refclk(dev_priv, cdclk_state);
+	else
+		cdclk_state->ref = 19200;
 
 	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+	    (val & BXT_DE_PLL_LOCK) == 0) {
+		/*
+		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+		 * setting it to zero is a way to signal that.
+		 */
+		cdclk_state->vco = 0;
 		return;
+	}
 
-	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
-		return;
+	/*
+	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
+	 * it in a separate PLL control register.
+	 */
+	if (INTEL_GEN(dev_priv) >= 10)
+		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
+	else
+		ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
 
-	val = I915_READ(BXT_DE_PLL_CTL);
-	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+	cdclk_state->vco = ratio * cdclk_state->ref;
 }
 
 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1261,12 +1337,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	u32 divider;
 	int div;
 
-	bxt_de_pll_update(dev_priv, cdclk_state);
-
-	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
+	if (INTEL_GEN(dev_priv) >= 12)
+		cdclk_state->bypass = cdclk_state->ref / 2;
+	else if (INTEL_GEN(dev_priv) >= 11)
+		cdclk_state->bypass = 50000;
+	else
+		cdclk_state->bypass = cdclk_state->ref;
 
-	if (cdclk_state->vco == 0)
+	bxt_de_pll_readout(dev_priv, cdclk_state);
+	if (cdclk_state->vco == 0) {
+		cdclk_state->cdclk = cdclk_state->bypass;
 		goto out;
+	}
 
 	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
 
@@ -1275,13 +1357,15 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 		div = 2;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
-		WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
+		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+		     "Unsupported divider\n");
 		div = 3;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_2:
 		div = 4;
 		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_4:
+		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
 		div = 8;
 		break;
 	default:
@@ -1296,8 +1380,18 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	 * Can't read this out :( Let's assume it's
 	 * at least what the CDCLK frequency requires.
 	 */
-	cdclk_state->voltage_level =
-		bxt_calc_voltage_level(cdclk_state->cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		cdclk_state->voltage_level =
+			ehl_calc_voltage_level(cdclk_state->cdclk);
+	else if (INTEL_GEN(dev_priv) >= 11)
+		cdclk_state->voltage_level =
+			icl_calc_voltage_level(cdclk_state->cdclk);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		cdclk_state->voltage_level =
+			cnl_calc_voltage_level(cdclk_state->cdclk);
+	else
+		cdclk_state->voltage_level =
+			bxt_calc_voltage_level(cdclk_state->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1515,76 +1609,6 @@ static int cnl_calc_cdclk(int min_cdclk)
 		return 168000;
 }
 
-static u8 cnl_calc_voltage_level(int cdclk)
-{
-	if (cdclk > 336000)
-		return 2;
-	else if (cdclk > 168000)
-		return 1;
-	else
-		return 0;
-}
-
-static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
-				 struct intel_cdclk_state *cdclk_state)
-{
-	u32 val;
-
-	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
-		cdclk_state->ref = 24000;
-	else
-		cdclk_state->ref = 19200;
-
-	cdclk_state->vco = 0;
-
-	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
-		return;
-
-	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
-		return;
-
-	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
-}
-
-static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
-			 struct intel_cdclk_state *cdclk_state)
-{
-	u32 divider;
-	int div;
-
-	cnl_cdclk_pll_update(dev_priv, cdclk_state);
-
-	cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
-
-	if (cdclk_state->vco == 0)
-		goto out;
-
-	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
-
-	switch (divider) {
-	case BXT_CDCLK_CD2X_DIV_SEL_1:
-		div = 2;
-		break;
-	case BXT_CDCLK_CD2X_DIV_SEL_2:
-		div = 4;
-		break;
-	default:
-		MISSING_CASE(divider);
-		return;
-	}
-
-	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
-
- out:
-	/*
-	 * Can't read this out :( Let's assume it's
-	 * at least what the CDCLK frequency requires.
-	 */
-	cdclk_state->voltage_level =
-		cnl_calc_voltage_level(cdclk_state->cdclk);
-}
-
 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -1830,91 +1854,6 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 	return dev_priv->cdclk.hw.ref * ratio;
 }
 
-static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
-{
-	if (IS_ELKHARTLAKE(dev_priv)) {
-		if (cdclk > 312000)
-			return 2;
-		else if (cdclk > 180000)
-			return 1;
-		else
-			return 0;
-	} else {
-		if (cdclk > 556800)
-			return 2;
-		else if (cdclk > 312000)
-			return 1;
-		else
-			return 0;
-	}
-}
-
-static void icl_get_cdclk(struct drm_i915_private *dev_priv,
-			  struct intel_cdclk_state *cdclk_state)
-{
-	u32 val;
-	int div;
-
-	val = I915_READ(SKL_DSSM);
-	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
-	default:
-		MISSING_CASE(val);
-		/* fall through */
-	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
-		cdclk_state->ref = 24000;
-		break;
-	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
-		cdclk_state->ref = 19200;
-		break;
-	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
-		cdclk_state->ref = 38400;
-		break;
-	}
-
-	if (INTEL_GEN(dev_priv) >= 12)
-		cdclk_state->bypass = cdclk_state->ref / 2;
-	else
-		cdclk_state->bypass = 50000;
-
-	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
-	    (val & BXT_DE_PLL_LOCK) == 0) {
-		/*
-		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
-		 * setting it to zero is a way to signal that.
-		 */
-		cdclk_state->vco = 0;
-		cdclk_state->cdclk = cdclk_state->bypass;
-		goto out;
-	}
-
-	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
-
-	val = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
-	switch (val) {
-	case BXT_CDCLK_CD2X_DIV_SEL_1:
-		div = 2;
-		break;
-	case BXT_CDCLK_CD2X_DIV_SEL_2:
-		div = 4;
-		break;
-	default:
-		MISSING_CASE(val);
-		div = 2;
-		break;
-	}
-
-	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
-
-out:
-	/*
-	 * Can't read this out :( Let's assume it's
-	 * at least what the CDCLK frequency requires.
-	 */
-	cdclk_state->voltage_level =
-		icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
-}
-
 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state sanitized_state;
@@ -1946,9 +1885,12 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
 	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
 						     sanitized_state.cdclk);
-	sanitized_state.voltage_level =
-				icl_calc_voltage_level(dev_priv,
-						       sanitized_state.cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		sanitized_state.voltage_level =
+			ehl_calc_voltage_level(sanitized_state.cdclk);
+	else
+		sanitized_state.voltage_level =
+			icl_calc_voltage_level(sanitized_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
@@ -1959,8 +1901,12 @@ static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
-	cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
-							   cdclk_state.cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		cdclk_state.voltage_level =
+			ehl_calc_voltage_level(cdclk_state.cdclk);
+	else
+		cdclk_state.voltage_level =
+			icl_calc_voltage_level(cdclk_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -2561,9 +2507,14 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		max(icl_calc_voltage_level(dev_priv, cdclk),
-		    cnl_compute_min_voltage_level(state));
+	if (IS_ELKHARTLAKE(dev_priv))
+		state->cdclk.logical.voltage_level =
+			max(ehl_calc_voltage_level(cdclk),
+			    cnl_compute_min_voltage_level(state));
+	else
+		state->cdclk.logical.voltage_level =
+			max(icl_calc_voltage_level(cdclk),
+			    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
 		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
@@ -2571,8 +2522,12 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			icl_calc_voltage_level(dev_priv, cdclk);
+		if (IS_ELKHARTLAKE(dev_priv))
+			state->cdclk.actual.voltage_level =
+				ehl_calc_voltage_level(cdclk);
+		else
+			state->cdclk.actual.voltage_level =
+				icl_calc_voltage_level(cdclk);
 	} else {
 		state->cdclk.actual = state->cdclk.logical;
 	}
@@ -2819,11 +2774,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		dev_priv->display.get_cdclk = icl_get_cdclk;
-	else if (IS_CANNONLAKE(dev_priv))
-		dev_priv->display.get_cdclk = cnl_get_cdclk;
-	else if (IS_GEN9_LP(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
 		dev_priv->display.get_cdclk = bxt_get_cdclk;
 	else if (IS_GEN9_BC(dev_priv))
 		dev_priv->display.get_cdclk = skl_get_cdclk;
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v4 2/8] drm/i915: Use literal representation of cdclk tables

[Matt Roper]

The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms.  We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabling new platforms.  Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.

v2: Fix comparison when finding best cdclk.

v3: Another logic fix for calc_cdclk.

v4:
 - Use named initializers for cdclk tables. (Ville)
 - Include refclk as a field in the table instead of adding all three
   ratios for each entry. (Ville)
 - Terminate tables with an empty entry to avoid needing to store the
   table size. (Ville)
 - Don't try so hard to return reasonable values from our lookup
   functions if we get impossible inputs; just WARN and return 0.
   (Ville)
 - Keep a bxt_ prefix on the lookup functions since they're still only
   used on bxt+ for now.  We can rename them later if we extend this
   table-based approach back to older platforms.  (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 303 +++++++--------------
 drivers/gpu/drm/i915/display/intel_cdclk.h |   7 +
 drivers/gpu/drm/i915/i915_drv.h            |   3 +
 3 files changed, 110 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 01ed3262d91e..c8cf288b8e8e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1161,28 +1161,88 @@ static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static int bxt_calc_cdclk(int min_cdclk)
-{
-	if (min_cdclk > 576000)
-		return 624000;
-	else if (min_cdclk > 384000)
-		return 576000;
-	else if (min_cdclk > 288000)
-		return 384000;
-	else if (min_cdclk > 144000)
-		return 288000;
-	else
-		return 144000;
+static const struct intel_cdclk_vals bxt_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
+	{}
+};
+
+static const struct intel_cdclk_vals glk_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk =  79200, .divider = 8, .ratio = 33 },
+	{ .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
+	{ .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
+	{}
+};
+
+static const struct intel_cdclk_vals cnl_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 168000, 4, 35 },
+	{ .refclk = 19200, .cdclk = 336000, 2, 35 },
+	{ .refclk = 19200, .cdclk = 528000, 2, 55 },
+
+	{ .refclk = 24000, .cdclk = 168000, 4, 35 },
+	{ .refclk = 24000, .cdclk = 336000, 2, 35 },
+	{ .refclk = 24000, .cdclk = 528000, 2, 55 },
+	{}
+};
+
+static const struct intel_cdclk_vals icl_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
+	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+	{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
+	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+	{ .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
+	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+	{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
+	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+	{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
+	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+	{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
+	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+	{}
+};
+
+static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
+{
+	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+	int i;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+		    table[i].cdclk >= min_cdclk)
+			return table[i].cdclk;
+
+	WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
+	     min_cdclk, dev_priv->cdclk.hw.ref);
+	return 0;
 }
 
-static int glk_calc_cdclk(int min_cdclk)
+static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
-	if (min_cdclk > 158400)
-		return 316800;
-	else if (min_cdclk > 79200)
-		return 158400;
-	else
-		return 79200;
+	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+	int i;
+
+	if (cdclk == dev_priv->cdclk.hw.bypass)
+		return 0;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+		    table[i].cdclk == cdclk)
+			return dev_priv->cdclk.hw.ref * table[i].ratio;
+
+	WARN(1, "cdclk %d not valid for refclk %u\n",
+	     cdclk, dev_priv->cdclk.hw.ref);
+	return 0;
 }
 
 static u8 bxt_calc_voltage_level(int cdclk)
@@ -1220,52 +1280,6 @@ static u8 ehl_calc_voltage_level(int cdclk)
 		return 0;
 }
 
-static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 144000:
-	case 288000:
-	case 384000:
-	case 576000:
-		ratio = 60;
-		break;
-	case 624000:
-		ratio = 65;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
-static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case  79200:
-	case 158400:
-	case 316800:
-		ratio = 33;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
 			       struct intel_cdclk_state *cdclk_state)
 {
@@ -1576,13 +1590,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 	 * - The initial CDCLK needs to be read from VBT.
 	 *   Need to make this change after VBT has changes for BXT.
 	 */
-	if (IS_GEMINILAKE(dev_priv)) {
-		cdclk_state.cdclk = glk_calc_cdclk(0);
-		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
-	} else {
-		cdclk_state.cdclk = bxt_calc_cdclk(0);
-		cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
-	}
+	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
@@ -1599,16 +1608,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static int cnl_calc_cdclk(int min_cdclk)
-{
-	if (min_cdclk > 336000)
-		return 528000;
-	else if (min_cdclk > 168000)
-		return 336000;
-	else
-		return 168000;
-}
-
 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -1718,29 +1717,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
 }
 
-static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 168000:
-	case 336000:
-		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
-		break;
-	case 528000:
-		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	u32 cdctl, expected;
@@ -1783,77 +1759,6 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
-static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
-{
-	static const int ranges_24[] = { 180000, 192000, 312000, 324000,
-					 552000, 648000 };
-	static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
-					    556800, 652800 };
-	const int *ranges;
-	int len, i;
-
-	switch (ref) {
-	default:
-		MISSING_CASE(ref);
-		/* fall through */
-	case 24000:
-		ranges = ranges_24;
-		len = ARRAY_SIZE(ranges_24);
-		break;
-	case 19200:
-	case 38400:
-		ranges = ranges_19_38;
-		len = ARRAY_SIZE(ranges_19_38);
-		break;
-	}
-
-	for (i = 0; i < len; i++) {
-		if (min_cdclk <= ranges[i])
-			return ranges[i];
-	}
-
-	WARN_ON(min_cdclk > ranges[len - 1]);
-	return ranges[len - 1];
-}
-
-static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 172800:
-	case 307200:
-	case 326400:
-	case 556800:
-	case 652800:
-		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
-			dev_priv->cdclk.hw.ref != 38400);
-		break;
-	case 180000:
-	case 312000:
-	case 324000:
-	case 552000:
-	case 648000:
-		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
-		break;
-	case 192000:
-		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
-			dev_priv->cdclk.hw.ref != 38400 &&
-			dev_priv->cdclk.hw.ref != 24000);
-		break;
-	}
-
-	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state sanitized_state;
@@ -1882,8 +1787,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
 
 	sanitized_state.ref = dev_priv->cdclk.hw.ref;
-	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
-	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
+	sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
 						     sanitized_state.cdclk);
 	if (IS_ELKHARTLAKE(dev_priv))
 		sanitized_state.voltage_level =
@@ -1923,8 +1828,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = cnl_calc_cdclk(0);
-	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
@@ -2426,13 +2331,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	if (IS_GEMINILAKE(dev_priv)) {
-		cdclk = glk_calc_cdclk(min_cdclk);
-		vco = glk_de_pll_vco(dev_priv, cdclk);
-	} else {
-		cdclk = bxt_calc_cdclk(min_cdclk);
-		vco = bxt_de_pll_vco(dev_priv, cdclk);
-	}
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2440,13 +2340,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 		bxt_calc_voltage_level(cdclk);
 
 	if (!state->active_pipes) {
-		if (IS_GEMINILAKE(dev_priv)) {
-			cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
-			vco = glk_de_pll_vco(dev_priv, cdclk);
-		} else {
-			cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
-			vco = bxt_de_pll_vco(dev_priv, cdclk);
-		}
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2468,8 +2363,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	cdclk = cnl_calc_cdclk(min_cdclk);
-	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2478,8 +2373,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 		    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
-		cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
-		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2495,15 +2390,14 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	unsigned int ref = state->cdclk.logical.ref;
 	int min_cdclk, cdclk, vco;
 
 	min_cdclk = intel_compute_min_cdclk(state);
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	cdclk = icl_calc_cdclk(min_cdclk, ref);
-	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2517,8 +2411,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 			    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
-		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
-		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2754,12 +2648,15 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk.table = bxt_cdclk_table;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		dev_priv->display.set_cdclk = skl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 4d6f7f5f8930..ca6d651946b9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,13 @@ struct intel_atomic_state;
 struct intel_cdclk_state;
 struct intel_crtc_state;
 
+struct intel_cdclk_vals {
+	u32 refclk;
+	u32 cdclk;
+	u8 divider;	/* CD2X divider * 2 */
+	u8 ratio;
+};
+
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
 void intel_cdclk_init(struct drm_i915_private *i915);
 void intel_cdclk_uninit(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e289b4ffd34b..ff6aff2a4866 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1420,6 +1420,9 @@ struct drm_i915_private {
 		/* The current hardware cdclk state */
 		struct intel_cdclk_state hw;
 
+		/* cdclk, divider, and ratio table from bspec */
+		const struct intel_cdclk_vals *table;
+
 		int force_min_cdclk;
 	} cdclk;
 
-- 
2.20.1

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v4 2/8] drm/i915: Use literal representation of cdclk tables

[Ville Syrjälä]

On Tue, Sep 10, 2019 at 08:42:46AM -0700, Matt Roper wrote:
> The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
> dividers in an easy-to-read table for most recent platforms.  We've been
> translating the data from that table into platform-specific code logic,
> but it's easy to overlook an area we need to update when adding new
> cdclk values or enabling new platforms.  Let's just add a form of the
> bspec table to the code and then adjust our functions to pull what they
> need directly out of the table.
> 
> v2: Fix comparison when finding best cdclk.
> 
> v3: Another logic fix for calc_cdclk.
> 
> v4:
>  - Use named initializers for cdclk tables. (Ville)
>  - Include refclk as a field in the table instead of adding all three
>    ratios for each entry. (Ville)
>  - Terminate tables with an empty entry to avoid needing to store the
>    table size. (Ville)
>  - Don't try so hard to return reasonable values from our lookup
>    functions if we get impossible inputs; just WARN and return 0.
>    (Ville)
>  - Keep a bxt_ prefix on the lookup functions since they're still only
>    used on bxt+ for now.  We can rename them later if we extend this
>    table-based approach back to older platforms.  (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 303 +++++++--------------
>  drivers/gpu/drm/i915/display/intel_cdclk.h |   7 +
>  drivers/gpu/drm/i915/i915_drv.h            |   3 +
>  3 files changed, 110 insertions(+), 203 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 01ed3262d91e..c8cf288b8e8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1161,28 +1161,88 @@ static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
>  }
>  
> -static int bxt_calc_cdclk(int min_cdclk)
> -{
> -	if (min_cdclk > 576000)
> -		return 624000;
> -	else if (min_cdclk > 384000)
> -		return 576000;
> -	else if (min_cdclk > 288000)
> -		return 384000;
> -	else if (min_cdclk > 144000)
> -		return 288000;
> -	else
> -		return 144000;
> +static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> +	{ .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> +	{ .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> +	{ .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> +	{ .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> +	{ .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> +	{}
> +};

If only we had constexpr so we could do
BUILD_BUG_ON(ref*ratio == cdclk*div) without having to hand roll
it for every table entry. Oh well.

> +
> +static const struct intel_cdclk_vals glk_cdclk_table[] = {
> +	{ .refclk = 19200, .cdclk =  79200, .divider = 8, .ratio = 33 },
> +	{ .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> +	{ .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> +	{}
> +};
> +
> +static const struct intel_cdclk_vals cnl_cdclk_table[] = {
> +	{ .refclk = 19200, .cdclk = 168000, 4, 35 },
> +	{ .refclk = 19200, .cdclk = 336000, 2, 35 },
> +	{ .refclk = 19200, .cdclk = 528000, 2, 55 },
> +
> +	{ .refclk = 24000, .cdclk = 168000, 4, 35 },
> +	{ .refclk = 24000, .cdclk = 336000, 2, 35 },
> +	{ .refclk = 24000, .cdclk = 528000, 2, 55 },

The ratios looks wrong here. Also missing .divider= and .ratio=.

> +	{}
> +};
> +
> +static const struct intel_cdclk_vals icl_cdclk_table[] = {
> +	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> +	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> +	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> +	{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> +	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> +	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> +	{ .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> +	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> +	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> +	{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> +	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> +	{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> +	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
> +	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> +	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> +	{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> +	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> +	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> +	{}
> +};

Everything else seems to check out.

With the cnl tables fixed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
> +static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> +{
> +	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
> +	int i;
> +
> +	for (i = 0; table[i].refclk; i++)
> +		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
> +		    table[i].cdclk >= min_cdclk)
> +			return table[i].cdclk;
> +
> +	WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
> +	     min_cdclk, dev_priv->cdclk.hw.ref);
> +	return 0;
>  }
>  
> -static int glk_calc_cdclk(int min_cdclk)
> +static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>  {
> -	if (min_cdclk > 158400)
> -		return 316800;
> -	else if (min_cdclk > 79200)
> -		return 158400;
> -	else
> -		return 79200;
> +	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
> +	int i;
> +
> +	if (cdclk == dev_priv->cdclk.hw.bypass)
> +		return 0;
> +
> +	for (i = 0; table[i].refclk; i++)
> +		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
> +		    table[i].cdclk == cdclk)
> +			return dev_priv->cdclk.hw.ref * table[i].ratio;
> +
> +	WARN(1, "cdclk %d not valid for refclk %u\n",
> +	     cdclk, dev_priv->cdclk.hw.ref);
> +	return 0;
>  }
>  
>  static u8 bxt_calc_voltage_level(int cdclk)
> @@ -1220,52 +1280,6 @@ static u8 ehl_calc_voltage_level(int cdclk)
>  		return 0;
>  }
>  
> -static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> -{
> -	int ratio;
> -
> -	if (cdclk == dev_priv->cdclk.hw.bypass)
> -		return 0;
> -
> -	switch (cdclk) {
> -	default:
> -		MISSING_CASE(cdclk);
> -		/* fall through */
> -	case 144000:
> -	case 288000:
> -	case 384000:
> -	case 576000:
> -		ratio = 60;
> -		break;
> -	case 624000:
> -		ratio = 65;
> -		break;
> -	}
> -
> -	return dev_priv->cdclk.hw.ref * ratio;
> -}
> -
> -static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> -{
> -	int ratio;
> -
> -	if (cdclk == dev_priv->cdclk.hw.bypass)
> -		return 0;
> -
> -	switch (cdclk) {
> -	default:
> -		MISSING_CASE(cdclk);
> -		/* fall through */
> -	case  79200:
> -	case 158400:
> -	case 316800:
> -		ratio = 33;
> -		break;
> -	}
> -
> -	return dev_priv->cdclk.hw.ref * ratio;
> -}
> -
>  static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
>  			       struct intel_cdclk_state *cdclk_state)
>  {
> @@ -1576,13 +1590,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
>  	 * - The initial CDCLK needs to be read from VBT.
>  	 *   Need to make this change after VBT has changes for BXT.
>  	 */
> -	if (IS_GEMINILAKE(dev_priv)) {
> -		cdclk_state.cdclk = glk_calc_cdclk(0);
> -		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
> -	} else {
> -		cdclk_state.cdclk = bxt_calc_cdclk(0);
> -		cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
> -	}
> +	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
> +	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>  	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> @@ -1599,16 +1608,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
>  }
>  
> -static int cnl_calc_cdclk(int min_cdclk)
> -{
> -	if (min_cdclk > 336000)
> -		return 528000;
> -	else if (min_cdclk > 168000)
> -		return 336000;
> -	else
> -		return 168000;
> -}
> -
>  static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>  {
>  	u32 val;
> @@ -1718,29 +1717,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>  	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
>  }
>  
> -static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> -{
> -	int ratio;
> -
> -	if (cdclk == dev_priv->cdclk.hw.bypass)
> -		return 0;
> -
> -	switch (cdclk) {
> -	default:
> -		MISSING_CASE(cdclk);
> -		/* fall through */
> -	case 168000:
> -	case 336000:
> -		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
> -		break;
> -	case 528000:
> -		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
> -		break;
> -	}
> -
> -	return dev_priv->cdclk.hw.ref * ratio;
> -}
> -
>  static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 cdctl, expected;
> @@ -1783,77 +1759,6 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk.hw.vco = -1;
>  }
>  
> -static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> -{
> -	static const int ranges_24[] = { 180000, 192000, 312000, 324000,
> -					 552000, 648000 };
> -	static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
> -					    556800, 652800 };
> -	const int *ranges;
> -	int len, i;
> -
> -	switch (ref) {
> -	default:
> -		MISSING_CASE(ref);
> -		/* fall through */
> -	case 24000:
> -		ranges = ranges_24;
> -		len = ARRAY_SIZE(ranges_24);
> -		break;
> -	case 19200:
> -	case 38400:
> -		ranges = ranges_19_38;
> -		len = ARRAY_SIZE(ranges_19_38);
> -		break;
> -	}
> -
> -	for (i = 0; i < len; i++) {
> -		if (min_cdclk <= ranges[i])
> -			return ranges[i];
> -	}
> -
> -	WARN_ON(min_cdclk > ranges[len - 1]);
> -	return ranges[len - 1];
> -}
> -
> -static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> -{
> -	int ratio;
> -
> -	if (cdclk == dev_priv->cdclk.hw.bypass)
> -		return 0;
> -
> -	switch (cdclk) {
> -	default:
> -		MISSING_CASE(cdclk);
> -		/* fall through */
> -	case 172800:
> -	case 307200:
> -	case 326400:
> -	case 556800:
> -	case 652800:
> -		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> -			dev_priv->cdclk.hw.ref != 38400);
> -		break;
> -	case 180000:
> -	case 312000:
> -	case 324000:
> -	case 552000:
> -	case 648000:
> -		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> -		break;
> -	case 192000:
> -		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> -			dev_priv->cdclk.hw.ref != 38400 &&
> -			dev_priv->cdclk.hw.ref != 24000);
> -		break;
> -	}
> -
> -	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> -
> -	return dev_priv->cdclk.hw.ref * ratio;
> -}
> -
>  static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state sanitized_state;
> @@ -1882,8 +1787,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>  	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
>  
>  	sanitized_state.ref = dev_priv->cdclk.hw.ref;
> -	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> -	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> +	sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
> +	sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
>  						     sanitized_state.cdclk);
>  	if (IS_ELKHARTLAKE(dev_priv))
>  		sanitized_state.voltage_level =
> @@ -1923,8 +1828,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>  
>  	cdclk_state = dev_priv->cdclk.hw;
>  
> -	cdclk_state.cdclk = cnl_calc_cdclk(0);
> -	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> +	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
> +	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>  	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
>  
>  	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> @@ -2426,13 +2331,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	if (min_cdclk < 0)
>  		return min_cdclk;
>  
> -	if (IS_GEMINILAKE(dev_priv)) {
> -		cdclk = glk_calc_cdclk(min_cdclk);
> -		vco = glk_de_pll_vco(dev_priv, cdclk);
> -	} else {
> -		cdclk = bxt_calc_cdclk(min_cdclk);
> -		vco = bxt_de_pll_vco(dev_priv, cdclk);
> -	}
> +	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> +	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
> @@ -2440,13 +2340,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
>  		bxt_calc_voltage_level(cdclk);
>  
>  	if (!state->active_pipes) {
> -		if (IS_GEMINILAKE(dev_priv)) {
> -			cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
> -			vco = glk_de_pll_vco(dev_priv, cdclk);
> -		} else {
> -			cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
> -			vco = bxt_de_pll_vco(dev_priv, cdclk);
> -		}
> +		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> +		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  		state->cdclk.actual.vco = vco;
>  		state->cdclk.actual.cdclk = cdclk;
> @@ -2468,8 +2363,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	if (min_cdclk < 0)
>  		return min_cdclk;
>  
> -	cdclk = cnl_calc_cdclk(min_cdclk);
> -	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> +	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> +	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
> @@ -2478,8 +2373,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  		    cnl_compute_min_voltage_level(state));
>  
>  	if (!state->active_pipes) {
> -		cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
> -		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> +		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> +		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  		state->cdclk.actual.vco = vco;
>  		state->cdclk.actual.cdclk = cdclk;
> @@ -2495,15 +2390,14 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	unsigned int ref = state->cdclk.logical.ref;
>  	int min_cdclk, cdclk, vco;
>  
>  	min_cdclk = intel_compute_min_cdclk(state);
>  	if (min_cdclk < 0)
>  		return min_cdclk;
>  
> -	cdclk = icl_calc_cdclk(min_cdclk, ref);
> -	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> +	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  	state->cdclk.logical.vco = vco;
>  	state->cdclk.logical.cdclk = cdclk;
> @@ -2517,8 +2411,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>  			    cnl_compute_min_voltage_level(state));
>  
>  	if (!state->active_pipes) {
> -		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
> -		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> +		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>  
>  		state->cdclk.actual.vco = vco;
>  		state->cdclk.actual.cdclk = cdclk;
> @@ -2754,12 +2648,15 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) >= 11) {
>  		dev_priv->display.set_cdclk = cnl_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> +		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->display.set_cdclk = cnl_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> +		dev_priv->cdclk.table = cnl_cdclk_table;
>  	} else if (IS_GEN9_LP(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk.table = bxt_cdclk_table;
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		dev_priv->display.set_cdclk = skl_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 4d6f7f5f8930..ca6d651946b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -15,6 +15,13 @@ struct intel_atomic_state;
>  struct intel_cdclk_state;
>  struct intel_crtc_state;
>  
> +struct intel_cdclk_vals {
> +	u32 refclk;
> +	u32 cdclk;
> +	u8 divider;	/* CD2X divider * 2 */
> +	u8 ratio;
> +};
> +
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
>  void intel_cdclk_init(struct drm_i915_private *i915);
>  void intel_cdclk_uninit(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e289b4ffd34b..ff6aff2a4866 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1420,6 +1420,9 @@ struct drm_i915_private {
>  		/* The current hardware cdclk state */
>  		struct intel_cdclk_state hw;
>  
> +		/* cdclk, divider, and ratio table from bspec */
> +		const struct intel_cdclk_vals *table;
> +
>  		int force_min_cdclk;
>  	} cdclk;
>  
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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Re: [PATCH v4 2/8] drm/i915: Use literal representation of cdclk tables

[Ville Syrjälä]

On Tue, Sep 10, 2019 at 08:42:46AM -0700, Matt Roper wrote:
... 
> +struct intel_cdclk_vals {
> +	u32 refclk;

Oh, I think (at least currently) refclk would fit into u16,
so we could pack this a bit tighter still.

> +	u32 cdclk;
> +	u8 divider;	/* CD2X divider * 2 */
> +	u8 ratio;
> +};
> +
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
>  void intel_cdclk_init(struct drm_i915_private *i915);
>  void intel_cdclk_uninit(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e289b4ffd34b..ff6aff2a4866 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1420,6 +1420,9 @@ struct drm_i915_private {
>  		/* The current hardware cdclk state */
>  		struct intel_cdclk_state hw;
>  
> +		/* cdclk, divider, and ratio table from bspec */
> +		const struct intel_cdclk_vals *table;
> +
>  		int force_min_cdclk;
>  	} cdclk;
>  
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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[PATCH v5 2/8] drm/i915: Use literal representation of cdclk tables

[Matt Roper]

The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms.  We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabling new platforms.  Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.

v2: Fix comparison when finding best cdclk.

v3: Another logic fix for calc_cdclk.

v4:
 - Use named initializers for cdclk tables. (Ville)
 - Include refclk as a field in the table instead of adding all three
   ratios for each entry. (Ville)
 - Terminate tables with an empty entry to avoid needing to store the
   table size. (Ville)
 - Don't try so hard to return reasonable values from our lookup
   functions if we get impossible inputs; just WARN and return 0.
   (Ville)
 - Keep a bxt_ prefix on the lookup functions since they're still only
   used on bxt+ for now.  We can rename them later if we extend this
   table-based approach back to older platforms.  (Ville)

v5:
 - Fix cnl table's ratios for 24mhz refclk. (Ville)
 - Don't miss the named initializers on the cnl table. (Ville)
 - Represent refclk in table as u16 rather than u32. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 303 +++++++--------------
 drivers/gpu/drm/i915/display/intel_cdclk.h |   7 +
 drivers/gpu/drm/i915/i915_drv.h            |   3 +
 3 files changed, 110 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dfcb1cc58951..f3431b530966 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1161,28 +1161,88 @@ static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static int bxt_calc_cdclk(int min_cdclk)
-{
-	if (min_cdclk > 576000)
-		return 624000;
-	else if (min_cdclk > 384000)
-		return 576000;
-	else if (min_cdclk > 288000)
-		return 384000;
-	else if (min_cdclk > 144000)
-		return 288000;
-	else
-		return 144000;
+static const struct intel_cdclk_vals bxt_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
+	{ .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
+	{}
+};
+
+static const struct intel_cdclk_vals glk_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk =  79200, .divider = 8, .ratio = 33 },
+	{ .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
+	{ .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
+	{}
+};
+
+static const struct intel_cdclk_vals cnl_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
+	{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
+	{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
+
+	{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
+	{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
+	{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
+	{}
+};
+
+static const struct intel_cdclk_vals icl_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
+	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+	{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
+	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+	{ .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
+	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+	{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
+	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+	{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
+	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+	{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
+	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+	{}
+};
+
+static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
+{
+	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+	int i;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+		    table[i].cdclk >= min_cdclk)
+			return table[i].cdclk;
+
+	WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
+	     min_cdclk, dev_priv->cdclk.hw.ref);
+	return 0;
 }
 
-static int glk_calc_cdclk(int min_cdclk)
+static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 {
-	if (min_cdclk > 158400)
-		return 316800;
-	else if (min_cdclk > 79200)
-		return 158400;
-	else
-		return 79200;
+	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+	int i;
+
+	if (cdclk == dev_priv->cdclk.hw.bypass)
+		return 0;
+
+	for (i = 0; table[i].refclk; i++)
+		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+		    table[i].cdclk == cdclk)
+			return dev_priv->cdclk.hw.ref * table[i].ratio;
+
+	WARN(1, "cdclk %d not valid for refclk %u\n",
+	     cdclk, dev_priv->cdclk.hw.ref);
+	return 0;
 }
 
 static u8 bxt_calc_voltage_level(int cdclk)
@@ -1220,52 +1280,6 @@ static u8 ehl_calc_voltage_level(int cdclk)
 		return 0;
 }
 
-static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 144000:
-	case 288000:
-	case 384000:
-	case 576000:
-		ratio = 60;
-		break;
-	case 624000:
-		ratio = 65;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
-static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case  79200:
-	case 158400:
-	case 316800:
-		ratio = 33;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
 			       struct intel_cdclk_state *cdclk_state)
 {
@@ -1576,13 +1590,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 	 * - The initial CDCLK needs to be read from VBT.
 	 *   Need to make this change after VBT has changes for BXT.
 	 */
-	if (IS_GEMINILAKE(dev_priv)) {
-		cdclk_state.cdclk = glk_calc_cdclk(0);
-		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
-	} else {
-		cdclk_state.cdclk = bxt_calc_cdclk(0);
-		cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
-	}
+	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
@@ -1599,16 +1608,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static int cnl_calc_cdclk(int min_cdclk)
-{
-	if (min_cdclk > 336000)
-		return 528000;
-	else if (min_cdclk > 168000)
-		return 336000;
-	else
-		return 168000;
-}
-
 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -1718,29 +1717,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
 }
 
-static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 168000:
-	case 336000:
-		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
-		break;
-	case 528000:
-		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
-		break;
-	}
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	u32 cdctl, expected;
@@ -1783,77 +1759,6 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = -1;
 }
 
-static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
-{
-	static const int ranges_24[] = { 180000, 192000, 312000, 324000,
-					 552000, 648000 };
-	static const int ranges_19_38[] = { 172800, 192000, 307200, 326400,
-					    556800, 652800 };
-	const int *ranges;
-	int len, i;
-
-	switch (ref) {
-	default:
-		MISSING_CASE(ref);
-		/* fall through */
-	case 24000:
-		ranges = ranges_24;
-		len = ARRAY_SIZE(ranges_24);
-		break;
-	case 19200:
-	case 38400:
-		ranges = ranges_19_38;
-		len = ARRAY_SIZE(ranges_19_38);
-		break;
-	}
-
-	for (i = 0; i < len; i++) {
-		if (min_cdclk <= ranges[i])
-			return ranges[i];
-	}
-
-	WARN_ON(min_cdclk > ranges[len - 1]);
-	return ranges[len - 1];
-}
-
-static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
-	int ratio;
-
-	if (cdclk == dev_priv->cdclk.hw.bypass)
-		return 0;
-
-	switch (cdclk) {
-	default:
-		MISSING_CASE(cdclk);
-		/* fall through */
-	case 172800:
-	case 307200:
-	case 326400:
-	case 556800:
-	case 652800:
-		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
-			dev_priv->cdclk.hw.ref != 38400);
-		break;
-	case 180000:
-	case 312000:
-	case 324000:
-	case 552000:
-	case 648000:
-		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
-		break;
-	case 192000:
-		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
-			dev_priv->cdclk.hw.ref != 38400 &&
-			dev_priv->cdclk.hw.ref != 24000);
-		break;
-	}
-
-	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
-
-	return dev_priv->cdclk.hw.ref * ratio;
-}
-
 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state sanitized_state;
@@ -1882,8 +1787,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
 
 	sanitized_state.ref = dev_priv->cdclk.hw.ref;
-	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
-	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
+	sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
 						     sanitized_state.cdclk);
 	if (IS_ELKHARTLAKE(dev_priv))
 		sanitized_state.voltage_level =
@@ -1923,8 +1828,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = cnl_calc_cdclk(0);
-	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
+	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
@@ -2426,13 +2331,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	if (IS_GEMINILAKE(dev_priv)) {
-		cdclk = glk_calc_cdclk(min_cdclk);
-		vco = glk_de_pll_vco(dev_priv, cdclk);
-	} else {
-		cdclk = bxt_calc_cdclk(min_cdclk);
-		vco = bxt_de_pll_vco(dev_priv, cdclk);
-	}
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2440,13 +2340,8 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 		bxt_calc_voltage_level(cdclk);
 
 	if (!state->active_pipes) {
-		if (IS_GEMINILAKE(dev_priv)) {
-			cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
-			vco = glk_de_pll_vco(dev_priv, cdclk);
-		} else {
-			cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
-			vco = bxt_de_pll_vco(dev_priv, cdclk);
-		}
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2468,8 +2363,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	cdclk = cnl_calc_cdclk(min_cdclk);
-	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2478,8 +2373,8 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 		    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
-		cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
-		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2495,15 +2390,14 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
 static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	unsigned int ref = state->cdclk.logical.ref;
 	int min_cdclk, cdclk, vco;
 
 	min_cdclk = intel_compute_min_cdclk(state);
 	if (min_cdclk < 0)
 		return min_cdclk;
 
-	cdclk = icl_calc_cdclk(min_cdclk, ref);
-	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
@@ -2517,8 +2411,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 			    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
-		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
-		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
+		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
@@ -2754,12 +2648,15 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = cnl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk.table = bxt_cdclk_table;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		dev_priv->display.set_cdclk = skl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 4d6f7f5f8930..1afa84ab6018 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,13 @@ struct intel_atomic_state;
 struct intel_cdclk_state;
 struct intel_crtc_state;
 
+struct intel_cdclk_vals {
+	u16 refclk;
+	u32 cdclk;
+	u8 divider;	/* CD2X divider * 2 */
+	u8 ratio;
+};
+
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
 void intel_cdclk_init(struct drm_i915_private *i915);
 void intel_cdclk_uninit(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e289b4ffd34b..ff6aff2a4866 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1420,6 +1420,9 @@ struct drm_i915_private {
 		/* The current hardware cdclk state */
 		struct intel_cdclk_state hw;
 
+		/* cdclk, divider, and ratio table from bspec */
+		const struct intel_cdclk_vals *table;
+
 		int force_min_cdclk;
 	} cdclk;
 
-- 
2.20.1

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Re: [PATCH v5 2/8] drm/i915: Use literal representation of cdclk tables

[Ville Syrjälä]

On Tue, Sep 10, 2019 at 09:15:06AM -0700, Matt Roper wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 4d6f7f5f8930..1afa84ab6018 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -15,6 +15,13 @@ struct intel_atomic_state;
>  struct intel_cdclk_state;
>  struct intel_crtc_state;
>  
> +struct intel_cdclk_vals {
> +	u16 refclk;
> +	u32 cdclk;

Those two should be swapped around, otherwise the compiler will pad
things out needlessly.

> +	u8 divider;	/* CD2X divider * 2 */
> +	u8 ratio;
> +};
> +
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
>  void intel_cdclk_init(struct drm_i915_private *i915);
>  void intel_cdclk_uninit(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e289b4ffd34b..ff6aff2a4866 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1420,6 +1420,9 @@ struct drm_i915_private {
>  		/* The current hardware cdclk state */
>  		struct intel_cdclk_state hw;
>  
> +		/* cdclk, divider, and ratio table from bspec */
> +		const struct intel_cdclk_vals *table;
> +
>  		int force_min_cdclk;
>  	} cdclk;
>  
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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[PATCH v4 3/8] drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk

[Matt Roper]

We'd previously combined ICL/TGL logic into the cnl_set_cdclk function,
but BXT is pretty similar as well.  Roll the cnl/icl/tgl logic back into
the bxt function; the only things we really need to handle separately
are punit notification and calling different functions to enable/disable
the cdclk PLL.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 267 +++++++++------------
 1 file changed, 119 insertions(+), 148 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c8cf288b8e8e..14229c68d4be 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1440,6 +1440,39 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
 	dev_priv->cdclk.hw.vco = vco;
 }
 
+static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	val &= ~BXT_DE_PLL_PLL_ENABLE;
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
+		DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
+
+	dev_priv->cdclk.hw.vco = 0;
+}
+
+static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+{
+	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+	u32 val;
+
+	val = CNL_CDCLK_PLL_RATIO(ratio);
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	val |= BXT_DE_PLL_PLL_ENABLE;
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
+		DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
+
+	dev_priv->cdclk.hw.vco = vco;
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_state *cdclk_state,
 			  enum pipe pipe)
@@ -1449,6 +1482,27 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	u32 val, divider;
 	int ret;
 
+	/* Inform power controller of upcoming frequency change. */
+	if (INTEL_GEN(dev_priv) >= 10)
+		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+					SKL_CDCLK_PREPARE_FOR_CHANGE,
+					SKL_CDCLK_READY_FOR_CHANGE,
+					SKL_CDCLK_READY_FOR_CHANGE, 3);
+	else
+		/*
+		 * BSpec requires us to wait up to 150usec, but that leads to
+		 * timeouts; the 2ms used here is based on experiment.
+		 */
+		ret = sandybridge_pcode_write_timeout(dev_priv,
+						      HSW_PCODE_DE_WRITE_FREQ_REQ,
+						      0x80000000, 150, 2);
+
+	if (ret) {
+		DRM_ERROR("Failed to inform PCU about cdclk change (err %d, freq %d)\n",
+			  ret, cdclk);
+		return;
+	}
+
 	/* cdclk = vco / 2 / div{1,1.5,2,4} */
 	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
 	default:
@@ -1459,63 +1513,82 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
 		break;
 	case 3:
-		WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
+		WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+		     "Unsupported divider\n");
 		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
 		break;
 	case 4:
 		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
 		break;
 	case 8:
+		WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
 		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
 		break;
 	}
 
-	/*
-	 * Inform power controller of upcoming frequency change. BSpec
-	 * requires us to wait up to 150usec, but that leads to timeouts;
-	 * the 2ms used here is based on experiment.
-	 */
-	ret = sandybridge_pcode_write_timeout(dev_priv,
-					      HSW_PCODE_DE_WRITE_FREQ_REQ,
-					      0x80000000, 150, 2);
-	if (ret) {
-		DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
-			  ret, cdclk);
-		return;
-	}
+	if (INTEL_GEN(dev_priv) >= 10) {
+		if (dev_priv->cdclk.hw.vco != 0 &&
+		    dev_priv->cdclk.hw.vco != vco)
+			cnl_cdclk_pll_disable(dev_priv);
 
-	if (dev_priv->cdclk.hw.vco != 0 &&
-	    dev_priv->cdclk.hw.vco != vco)
-		bxt_de_pll_disable(dev_priv);
+		if (dev_priv->cdclk.hw.vco != vco)
+			cnl_cdclk_pll_enable(dev_priv, vco);
 
-	if (dev_priv->cdclk.hw.vco != vco)
-		bxt_de_pll_enable(dev_priv, vco);
+	} else {
+		if (dev_priv->cdclk.hw.vco != 0 &&
+		    dev_priv->cdclk.hw.vco != vco)
+			bxt_de_pll_disable(dev_priv);
+
+		if (dev_priv->cdclk.hw.vco != vco)
+			bxt_de_pll_enable(dev_priv, vco);
+	}
 
 	val = divider | skl_cdclk_decimal(cdclk);
-	if (pipe == INVALID_PIPE)
-		val |= BXT_CDCLK_CD2X_PIPE_NONE;
-	else
-		val |= BXT_CDCLK_CD2X_PIPE(pipe);
+
+	if (INTEL_GEN(dev_priv) >= 12) {
+		if (pipe == INVALID_PIPE)
+			val |= TGL_CDCLK_CD2X_PIPE_NONE;
+		else
+			val |= TGL_CDCLK_CD2X_PIPE(pipe);
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		if (pipe == INVALID_PIPE)
+			val |= ICL_CDCLK_CD2X_PIPE_NONE;
+		else
+			val |= ICL_CDCLK_CD2X_PIPE(pipe);
+	} else {
+		if (pipe == INVALID_PIPE)
+			val |= BXT_CDCLK_CD2X_PIPE_NONE;
+		else
+			val |= BXT_CDCLK_CD2X_PIPE(pipe);
+	}
+
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
 	 * enable otherwise.
 	 */
-	if (cdclk >= 500000)
+	if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
 	I915_WRITE(CDCLK_CTL, val);
 
 	if (pipe != INVALID_PIPE)
 		intel_wait_for_vblank(dev_priv, pipe);
 
-	/*
-	 * The timeout isn't specified, the 2ms used here is based on
-	 * experiment.
-	 * FIXME: Waiting for the request completion could be delayed until
-	 * the next PCODE request based on BSpec.
-	 */
-	ret = sandybridge_pcode_write_timeout(dev_priv,
-					      HSW_PCODE_DE_WRITE_FREQ_REQ,
-					      cdclk_state->voltage_level, 150, 2);
+	if (INTEL_GEN(dev_priv) >= 10) {
+		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+					      cdclk_state->voltage_level);
+	} else {
+		/*
+		 * The timeout isn't specified, the 2ms used here is based on
+		 * experiment.
+		 * FIXME: Waiting for the request completion could be delayed
+		 * until the next PCODE request based on BSpec.
+		 */
+		ret = sandybridge_pcode_write_timeout(dev_priv,
+						      HSW_PCODE_DE_WRITE_FREQ_REQ,
+						      cdclk_state->voltage_level,
+						      150, 2);
+	}
+
 	if (ret) {
 		DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
 			  ret, cdclk);
@@ -1523,6 +1596,13 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	}
 
 	intel_update_cdclk(dev_priv);
+
+	if (INTEL_GEN(dev_priv) >= 10)
+		/*
+		 * Can't read out the voltage level :(
+		 * Let's just assume everything is as expected.
+		 */
+		dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
 }
 
 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1608,115 +1688,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	val = I915_READ(BXT_DE_PLL_ENABLE);
-	val &= ~BXT_DE_PLL_PLL_ENABLE;
-	I915_WRITE(BXT_DE_PLL_ENABLE, val);
-
-	/* Timeout 200us */
-	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
-		DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
-
-	dev_priv->cdclk.hw.vco = 0;
-}
-
-static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
-{
-	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
-	u32 val;
-
-	val = CNL_CDCLK_PLL_RATIO(ratio);
-	I915_WRITE(BXT_DE_PLL_ENABLE, val);
-
-	val |= BXT_DE_PLL_PLL_ENABLE;
-	I915_WRITE(BXT_DE_PLL_ENABLE, val);
-
-	/* Timeout 200us */
-	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
-		DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
-
-	dev_priv->cdclk.hw.vco = vco;
-}
-
-static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state,
-			  enum pipe pipe)
-{
-	int cdclk = cdclk_state->cdclk;
-	int vco = cdclk_state->vco;
-	u32 val, divider;
-	int ret;
-
-	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-				SKL_CDCLK_PREPARE_FOR_CHANGE,
-				SKL_CDCLK_READY_FOR_CHANGE,
-				SKL_CDCLK_READY_FOR_CHANGE, 3);
-	if (ret) {
-		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
-			  ret);
-		return;
-	}
-
-	/* cdclk = vco / 2 / div{1,2} */
-	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
-	default:
-		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
-		WARN_ON(vco != 0);
-		/* fall through */
-	case 2:
-		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
-		break;
-	case 4:
-		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
-		break;
-	}
-
-	if (dev_priv->cdclk.hw.vco != 0 &&
-	    dev_priv->cdclk.hw.vco != vco)
-		cnl_cdclk_pll_disable(dev_priv);
-
-	if (dev_priv->cdclk.hw.vco != vco)
-		cnl_cdclk_pll_enable(dev_priv, vco);
-
-	val = divider | skl_cdclk_decimal(cdclk);
-
-	if (INTEL_GEN(dev_priv) >= 12) {
-		if (pipe == INVALID_PIPE)
-			val |= TGL_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= TGL_CDCLK_CD2X_PIPE(pipe);
-	} else if (INTEL_GEN(dev_priv) >= 11) {
-		if (pipe == INVALID_PIPE)
-			val |= ICL_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= ICL_CDCLK_CD2X_PIPE(pipe);
-	} else {
-		if (pipe == INVALID_PIPE)
-			val |= BXT_CDCLK_CD2X_PIPE_NONE;
-		else
-			val |= BXT_CDCLK_CD2X_PIPE(pipe);
-	}
-	I915_WRITE(CDCLK_CTL, val);
-
-	if (pipe != INVALID_PIPE)
-		intel_wait_for_vblank(dev_priv, pipe);
-
-	/* inform PCU of the change */
-	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
-				cdclk_state->voltage_level);
-
-	intel_update_cdclk(dev_priv);
-
-	/*
-	 * Can't read out the voltage level :(
-	 * Let's just assume everything is as expected.
-	 */
-	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
-}
-
 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	u32 cdctl, expected;
@@ -1797,7 +1768,7 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 		sanitized_state.voltage_level =
 			icl_calc_voltage_level(sanitized_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
+	bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
 
 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -1813,7 +1784,7 @@ static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
 		cdclk_state.voltage_level =
 			icl_calc_voltage_level(cdclk_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
@@ -1832,7 +1803,7 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -1843,7 +1814,7 @@ static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
+	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -2646,11 +2617,11 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) >= 11) {
-		dev_priv->display.set_cdclk = cnl_set_cdclk;
+		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		dev_priv->display.set_cdclk = cnl_set_cdclk;
+		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
 		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
-- 
2.20.1

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[PATCH v4 4/8] drm/i915: Kill cnl_sanitize_cdclk()

[Matt Roper]

The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +---------------------
 1 file changed, 2 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 14229c68d4be..3c763c70ebea 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1636,7 +1636,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
 	 * enable otherwise.
 	 */
-	if (dev_priv->cdclk.hw.cdclk >= 500000)
+	if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
 		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
 
 	if (cdctl == expected)
@@ -1688,48 +1688,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
-{
-	u32 cdctl, expected;
-
-	intel_update_cdclk(dev_priv);
-	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
-
-	if (dev_priv->cdclk.hw.vco == 0 ||
-	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
-		goto sanitize;
-
-	/* DPLL okay; verify the cdclock
-	 *
-	 * Some BIOS versions leave an incorrect decimal frequency value and
-	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
-	 * so sanitize this register.
-	 */
-	cdctl = I915_READ(CDCLK_CTL);
-	/*
-	 * Let's ignore the pipe field, since BIOS could have configured the
-	 * dividers both synching to an active pipe, or asynchronously
-	 * (PIPE_NONE).
-	 */
-	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
-
-	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
-		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
-
-	if (cdctl == expected)
-		/* All well; nothing to sanitize */
-		return;
-
-sanitize:
-	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
-
-	/* force cdclk programming */
-	dev_priv->cdclk.hw.cdclk = 0;
-
-	/* force full PLL disable + enable */
-	dev_priv->cdclk.hw.vco = -1;
-}
-
 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state sanitized_state;
@@ -1791,7 +1749,7 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state cdclk_state;
 
-	cnl_sanitize_cdclk(dev_priv);
+	bxt_sanitize_cdclk(dev_priv);
 
 	if (dev_priv->cdclk.hw.cdclk != 0 &&
 	    dev_priv->cdclk.hw.vco != 0)
-- 
2.20.1

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[PATCH v4 5/8] drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk

[Matt Roper]

The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.

v2: Reverse platform conditional order for consistency.  (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++++++---------------
 1 file changed, 14 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3c763c70ebea..518cc95456d3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1683,7 +1683,18 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
-	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+	if (IS_ELKHARTLAKE(dev_priv))
+		cdclk_state.voltage_level =
+			ehl_calc_voltage_level(cdclk_state.cdclk);
+	else if (INTEL_GEN(dev_priv) >= 11)
+		cdclk_state.voltage_level =
+			icl_calc_voltage_level(cdclk_state.cdclk);
+	else if (INTEL_GEN(dev_priv) >= 10)
+		cdclk_state.voltage_level =
+			cnl_calc_voltage_level(cdclk_state.cdclk);
+	else
+		cdclk_state.voltage_level =
+			bxt_calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -1729,22 +1740,6 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
 
-static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
-	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
-	cdclk_state.cdclk = cdclk_state.bypass;
-	cdclk_state.vco = 0;
-	if (IS_ELKHARTLAKE(dev_priv))
-		cdclk_state.voltage_level =
-			ehl_calc_voltage_level(cdclk_state.cdclk);
-	else
-		cdclk_state.voltage_level =
-			icl_calc_voltage_level(cdclk_state.cdclk);
-
-	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
-}
-
 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state cdclk_state;
@@ -1764,17 +1759,6 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
-	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
-	cdclk_state.cdclk = cdclk_state.bypass;
-	cdclk_state.vco = 0;
-	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
-
-	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
-}
-
 /**
  * intel_cdclk_init - Initialize CDCLK
  * @i915: i915 device
@@ -1805,14 +1789,10 @@ void intel_cdclk_init(struct drm_i915_private *i915)
  */
 void intel_cdclk_uninit(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) >= 11)
-		icl_uninit_cdclk(i915);
-	else if (IS_CANNONLAKE(i915))
-		cnl_uninit_cdclk(i915);
+	if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
+		bxt_uninit_cdclk(i915);
 	else if (IS_GEN9_BC(i915))
 		skl_uninit_cdclk(i915);
-	else if (IS_GEN9_LP(i915))
-		bxt_uninit_cdclk(i915);
 }
 
 /**
-- 
2.20.1

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[PATCH v4 6/8] drm/i915: Add calc_voltage_level display vfunc

[Matt Roper]

With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 75 ++++++++--------------
 drivers/gpu/drm/i915/i915_drv.h            |  1 +
 2 files changed, 27 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 518cc95456d3..cb2fc68c9335 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1394,18 +1394,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	 * Can't read this out :( Let's assume it's
 	 * at least what the CDCLK frequency requires.
 	 */
-	if (IS_ELKHARTLAKE(dev_priv))
-		cdclk_state->voltage_level =
-			ehl_calc_voltage_level(cdclk_state->cdclk);
-	else if (INTEL_GEN(dev_priv) >= 11)
-		cdclk_state->voltage_level =
-			icl_calc_voltage_level(cdclk_state->cdclk);
-	else if (INTEL_GEN(dev_priv) >= 10)
-		cdclk_state->voltage_level =
-			cnl_calc_voltage_level(cdclk_state->cdclk);
-	else
-		cdclk_state->voltage_level =
-			bxt_calc_voltage_level(cdclk_state->cdclk);
+	cdclk_state->voltage_level =
+		dev_priv->display.calc_voltage_level(cdclk_state->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1672,7 +1662,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 	 */
 	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
 	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
-	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+	cdclk_state.voltage_level =
+		dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -1683,18 +1674,8 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state.cdclk = cdclk_state.bypass;
 	cdclk_state.vco = 0;
-	if (IS_ELKHARTLAKE(dev_priv))
-		cdclk_state.voltage_level =
-			ehl_calc_voltage_level(cdclk_state.cdclk);
-	else if (INTEL_GEN(dev_priv) >= 11)
-		cdclk_state.voltage_level =
-			icl_calc_voltage_level(cdclk_state.cdclk);
-	else if (INTEL_GEN(dev_priv) >= 10)
-		cdclk_state.voltage_level =
-			cnl_calc_voltage_level(cdclk_state.cdclk);
-	else
-		cdclk_state.voltage_level =
-			bxt_calc_voltage_level(cdclk_state.cdclk);
+	cdclk_state.voltage_level =
+		dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -1730,12 +1711,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
 	sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
 						     sanitized_state.cdclk);
-	if (IS_ELKHARTLAKE(dev_priv))
-		sanitized_state.voltage_level =
-			ehl_calc_voltage_level(sanitized_state.cdclk);
-	else
-		sanitized_state.voltage_level =
-			icl_calc_voltage_level(sanitized_state.cdclk);
+	sanitized_state.voltage_level =
+		dev_priv->display.calc_voltage_level(sanitized_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
@@ -1754,7 +1731,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
 	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
-	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
+	cdclk_state.voltage_level =
+		dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
@@ -2246,7 +2224,7 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
 	state->cdclk.logical.voltage_level =
-		bxt_calc_voltage_level(cdclk);
+		dev_priv->display.calc_voltage_level(cdclk);
 
 	if (!state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2255,7 +2233,7 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
 		state->cdclk.actual.voltage_level =
-			bxt_calc_voltage_level(cdclk);
+			dev_priv->display.calc_voltage_level(cdclk);
 	} else {
 		state->cdclk.actual = state->cdclk.logical;
 	}
@@ -2310,14 +2288,9 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
-	if (IS_ELKHARTLAKE(dev_priv))
-		state->cdclk.logical.voltage_level =
-			max(ehl_calc_voltage_level(cdclk),
-			    cnl_compute_min_voltage_level(state));
-	else
-		state->cdclk.logical.voltage_level =
-			max(icl_calc_voltage_level(cdclk),
-			    cnl_compute_min_voltage_level(state));
+	state->cdclk.logical.voltage_level =
+		max(dev_priv->display.calc_voltage_level(cdclk),
+		    cnl_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2325,12 +2298,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 		state->cdclk.actual.vco = vco;
 		state->cdclk.actual.cdclk = cdclk;
-		if (IS_ELKHARTLAKE(dev_priv))
-			state->cdclk.actual.voltage_level =
-				ehl_calc_voltage_level(cdclk);
-		else
-			state->cdclk.actual.voltage_level =
-				icl_calc_voltage_level(cdclk);
+		state->cdclk.actual.voltage_level =
+			dev_priv->display.calc_voltage_level(cdclk);
 	} else {
 		state->cdclk.actual = state->cdclk.logical;
 	}
@@ -2554,17 +2523,25 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (IS_ELKHARTLAKE(dev_priv)) {
+		dev_priv->display.set_cdclk = bxt_set_cdclk;
+		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
+		dev_priv->cdclk.table = icl_cdclk_table;
+	} else if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
 		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
 		dev_priv->cdclk.table = bxt_cdclk_table;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		dev_priv->display.set_cdclk = skl_set_cdclk;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff6aff2a4866..dc4d40b44d74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -276,6 +276,7 @@ struct drm_i915_display_funcs {
 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
 	void (*update_wm)(struct intel_crtc *crtc);
 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
+	u8 (*calc_voltage_level)(int cdclk);
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
 	bool (*get_pipe_config)(struct intel_crtc *,
-- 
2.20.1

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[PATCH v4 7/8] drm/i915: Enhance cdclk sanitization

[Matt Roper]

When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 34 ++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb2fc68c9335..686c1e6100f0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1598,6 +1598,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	u32 cdctl, expected;
+	int cdclk, vco;
 
 	intel_update_cdclk(dev_priv);
 	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
@@ -1620,8 +1621,37 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	 */
 	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
 
-	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
-		skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+	/* Make sure this is a legal cdclk value for the platform */
+	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
+	if (cdclk != dev_priv->cdclk.hw.cdclk)
+		goto sanitize;
+
+	/* Make sure the VCO is correct for the cdclk */
+	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
+	if (vco != dev_priv->cdclk.hw.vco)
+		goto sanitize;
+
+	expected = skl_cdclk_decimal(cdclk);
+
+	/* Figure out what CD2X divider we should be using for this cdclk */
+	switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
+				  dev_priv->cdclk.hw.cdclk)) {
+	case 2:
+		expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
+		break;
+	case 3:
+		expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
+		break;
+	case 4:
+		expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
+		break;
+	case 8:
+		expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
+		break;
+	default:
+		goto sanitize;
+	}
+
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
 	 * enable otherwise.
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v4 8/8] drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk

[Matt Roper]

The BXT and CNL functions were already basically identical, whereas
ICL's function tried to do its own sanitization rather than calling
bxt_sanitize_cdclk.

This should actually fix a bug in our ICL initialization where it would
consider the /2 CD2X divider invalid and force an unnecessary
sanitization (we now have valid clock frequencies that use this
divider).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +---------------------
 1 file changed, 2 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 686c1e6100f0..3b2966a16ec7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1710,63 +1710,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
-static void icl_init_cdclk(struct drm_i915_private *dev_priv)
-{
-	struct intel_cdclk_state sanitized_state;
-	u32 val;
-
-	/* This sets dev_priv->cdclk.hw. */
-	intel_update_cdclk(dev_priv);
-	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
-
-	/* This means CDCLK disabled. */
-	if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
-		goto sanitize;
-
-	val = I915_READ(CDCLK_CTL);
-
-	if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
-		goto sanitize;
-
-	if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
-	    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
-		goto sanitize;
-
-	return;
-
-sanitize:
-	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
-
-	sanitized_state.ref = dev_priv->cdclk.hw.ref;
-	sanitized_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
-	sanitized_state.vco = bxt_calc_cdclk_pll_vco(dev_priv,
-						     sanitized_state.cdclk);
-	sanitized_state.voltage_level =
-		dev_priv->display.calc_voltage_level(sanitized_state.cdclk);
-
-	bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
-}
-
-static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
-{
-	struct intel_cdclk_state cdclk_state;
-
-	bxt_sanitize_cdclk(dev_priv);
-
-	if (dev_priv->cdclk.hw.cdclk != 0 &&
-	    dev_priv->cdclk.hw.vco != 0)
-		return;
-
-	cdclk_state = dev_priv->cdclk.hw;
-
-	cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
-	cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
-	cdclk_state.voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
-
-	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
-}
-
 /**
  * intel_cdclk_init - Initialize CDCLK
  * @i915: i915 device
@@ -1778,14 +1721,10 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
  */
 void intel_cdclk_init(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) >= 11)
-		icl_init_cdclk(i915);
-	else if (IS_CANNONLAKE(i915))
-		cnl_init_cdclk(i915);
+	if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
+		bxt_init_cdclk(i915);
 	else if (IS_GEN9_BC(i915))
 		skl_init_cdclk(i915);
-	else if (IS_GEN9_LP(i915))
-		bxt_init_cdclk(i915);
 }
 
 /**
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for cdclk consolidation and rework for BXT-TGL (rev5)

[Patchwork]

== Series Details ==

Series: cdclk consolidation and rework for BXT-TGL (rev5)
URL   : https://patchwork.freedesktop.org/series/66365/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c7ffbe99a9da drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:81: CHECK:CAMELCASE: Avoid CamelCase: <CNL_DSSM_CDCLK_PLL_REFCLK_24MHz>
#81: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1272:
+	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)

total: 0 errors, 0 warnings, 1 checks, 412 lines checked
0b12faaf504b drm/i915: Use literal representation of cdclk tables
ade79d916b5c drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
4d1593ea66fc drm/i915: Kill cnl_sanitize_cdclk()
3b06fc2eac50 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
05d3115ff981 drm/i915: Add calc_voltage_level display vfunc
202e21f4a86f drm/i915: Enhance cdclk sanitization
1dfdfc7ecb8a drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for cdclk consolidation and rework for BXT-TGL (rev6)

[Patchwork]

== Series Details ==

Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL   : https://patchwork.freedesktop.org/series/66365/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c43a4d52b847 drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:81: CHECK:CAMELCASE: Avoid CamelCase: <CNL_DSSM_CDCLK_PLL_REFCLK_24MHz>
#81: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1272:
+	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)

total: 0 errors, 0 warnings, 1 checks, 412 lines checked
37ddadb11c01 drm/i915: Use literal representation of cdclk tables
ab429f360abd drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
9cb44aa8a751 drm/i915: Kill cnl_sanitize_cdclk()
780de9619be6 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
3609840b0ce8 drm/i915: Add calc_voltage_level display vfunc
5c0e43cdb759 drm/i915: Enhance cdclk sanitization
a21088c79279 drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for cdclk consolidation and rework for BXT-TGL (rev5)

[Patchwork]

== Series Details ==

Series: cdclk consolidation and rework for BXT-TGL (rev5)
URL   : https://patchwork.freedesktop.org/series/66365/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14344
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/

Known issues
------------

  Here are the changes found in Patchwork_14344 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-copy:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-icl-u2:          [INCOMPLETE][3] ([fdo#107713] / [fdo#111381]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_render_tiled_blits@basic:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u3/igt@gem_render_tiled_blits@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/fi-icl-u3/igt@gem_render_tiled_blits@basic.html

  * igt@kms_chamelium@dp-edid-read:
    - {fi-icl-u4}:        [FAIL][7] ([fdo#111045]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][9] ([fdo#111096]) -> [FAIL][10] ([fdo#111407])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 45)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6861 -> Patchwork_14344

  CI-20190529: 20190529
  CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14344: 1dfdfc7ecb8a401d3dd6dfcb2ddfc2b237cb1bff @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1dfdfc7ecb8a drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk
202e21f4a86f drm/i915: Enhance cdclk sanitization
05d3115ff981 drm/i915: Add calc_voltage_level display vfunc
3b06fc2eac50 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
4d1593ea66fc drm/i915: Kill cnl_sanitize_cdclk()
ade79d916b5c drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
0b12faaf504b drm/i915: Use literal representation of cdclk tables
c7ffbe99a9da drm/i915: Consolidate bxt/cnl/icl cdclk readout

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14344/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for cdclk consolidation and rework for BXT-TGL (rev6)

[Patchwork]

== Series Details ==

Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL   : https://patchwork.freedesktop.org/series/66365/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14345
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/

Known issues
------------

  Here are the changes found in Patchwork_14345 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u3/igt@gem_mmap_gtt@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-icl-u3/igt@gem_mmap_gtt@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - {fi-icl-guc}:       [INCOMPLETE][3] ([fdo#107713] / [fdo#111381]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html
    - fi-icl-u2:          [INCOMPLETE][5] ([fdo#107713] / [fdo#111381]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_render_tiled_blits@basic:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-icl-u3/igt@gem_render_tiled_blits@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-icl-u3/igt@gem_render_tiled_blits@basic.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][9] ([fdo#111108]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111096]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381


Participating hosts (54 -> 47)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6861 -> Patchwork_14345

  CI-20190529: 20190529
  CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14345: a21088c79279e1d0a78c197d2d5d1029e60f9546 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a21088c79279 drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk
5c0e43cdb759 drm/i915: Enhance cdclk sanitization
3609840b0ce8 drm/i915: Add calc_voltage_level display vfunc
780de9619be6 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
9cb44aa8a751 drm/i915: Kill cnl_sanitize_cdclk()
ab429f360abd drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
37ddadb11c01 drm/i915: Use literal representation of cdclk tables
c43a4d52b847 drm/i915: Consolidate bxt/cnl/icl cdclk readout

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for cdclk consolidation and rework for BXT-TGL (rev6)

[Patchwork]

== Series Details ==

Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL   : https://patchwork.freedesktop.org/series/66365/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_6861_full and Patchwork_14345_full:

### New Piglit tests (7) ###

  * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_14345_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@basic-hang-rcs0:
    - shard-glk:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk6/igt@gem_busy@basic-hang-rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk3/igt@gem_busy@basic-hang-rcs0.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preempt-hang-vebox:
    - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb1/igt@gem_exec_schedule@preempt-hang-vebox.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/igt@gem_exec_schedule@preempt-hang-vebox.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#111325]) +9 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@i915_pm_rpm@modeset-stress-extra-wait:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#108840])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb7/igt@i915_pm_rpm@modeset-stress-extra-wait.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/igt@i915_pm_rpm@modeset-stress-extra-wait.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
    - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#111609])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk1/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/igt@kms_flip@dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl1/igt@kms_setmode@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/igt@kms_setmode@basic.html

  * igt@perf@polling:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl1/igt@perf@polling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl8/igt@perf@polling.html

  * igt@testdisplay:
    - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([fdo#105763] / [fdo#106538])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk7/igt@testdisplay.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/igt@testdisplay.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][31] ([fdo#111325]) -> [PASS][32] +4 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-skl:          [FAIL][39] ([fdo#100368]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-skl:          [INCOMPLETE][43] ([fdo#104108] / [fdo#106978]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl5/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +3 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@perf@blocking:
    - shard-skl:          [FAIL][49] ([fdo#110728]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl9/igt@perf@blocking.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/igt@perf@blocking.html

  * igt@perf@polling:
    - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl7/igt@perf@polling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl8/igt@perf@polling.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][53] ([fdo#109276]) -> [PASS][54] +21 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6861 -> Patchwork_14345

  CI-20190529: 20190529
  CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14345: a21088c79279e1d0a78c197d2d5d1029e60f9546 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✓ Fi.CI.IGT: success for cdclk consolidation and rework for BXT-TGL (rev6)

[Matt Roper]

On Tue, Sep 10, 2019 at 11:55:40PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: cdclk consolidation and rework for BXT-TGL (rev6)
> URL   : https://patchwork.freedesktop.org/series/66365/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 

Applied to dinq.  Thanks Ville for the reviews.


Matt

>   
> 
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_6861_full and Patchwork_14345_full:
> 
> ### New Piglit tests (7) ###
> 
>   * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d:
>     - Statuses : 1 incomplete(s)
>     - Exec time: [0.0] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_14345_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_busy@basic-hang-rcs0:
>     - shard-glk:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk6/igt@gem_busy@basic-hang-rcs0.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk3/igt@gem_busy@basic-hang-rcs0.html
> 
>   * igt@gem_ctx_isolation@rcs0-s3:
>     - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
> 
>   * igt@gem_exec_schedule@preempt-contexts-bsd2:
>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/igt@gem_exec_schedule@preempt-contexts-bsd2.html
> 
>   * igt@gem_exec_schedule@preempt-hang-vebox:
>     - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb1/igt@gem_exec_schedule@preempt-hang-vebox.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/igt@gem_exec_schedule@preempt-hang-vebox.html
> 
>   * igt@gem_exec_schedule@reorder-wide-bsd:
>     - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#111325]) +9 similar issues
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
> 
>   * igt@i915_pm_rpm@modeset-stress-extra-wait:
>     - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#108840])
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb7/igt@i915_pm_rpm@modeset-stress-extra-wait.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/igt@i915_pm_rpm@modeset-stress-extra-wait.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
>     - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
> 
>   * igt@kms_flip@dpms-vs-vblank-race-interruptible:
>     - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#111609])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk1/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible:
>     - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) +1 similar issue
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
>     - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>   * igt@kms_psr@psr2_sprite_mmap_gtt:
>     - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
> 
>   * igt@kms_setmode@basic:
>     - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl1/igt@kms_setmode@basic.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/igt@kms_setmode@basic.html
> 
>   * igt@perf@polling:
>     - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl1/igt@perf@polling.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl8/igt@perf@polling.html
> 
>   * igt@testdisplay:
>     - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([fdo#105763] / [fdo#106538])
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk7/igt@testdisplay.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/igt@testdisplay.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_schedule@preempt-other-chain-bsd:
>     - shard-iclb:         [SKIP][31] ([fdo#111325]) -> [PASS][32] +4 similar issues
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-apl:          [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +1 similar issue
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_flip@2x-flip-vs-expired-vblank:
>     - shard-glk:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_flip@plain-flip-fb-recreate-interruptible:
>     - shard-skl:          [FAIL][39] ([fdo#100368]) -> [PASS][40]
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
>     - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
> 
>   * igt@kms_frontbuffer_tracking@psr-suspend:
>     - shard-skl:          [INCOMPLETE][43] ([fdo#104108] / [fdo#106978]) -> [PASS][44]
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl5/igt@kms_frontbuffer_tracking@psr-suspend.html
> 
>   * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>     - shard-skl:          [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> 
>   * igt@kms_psr@psr2_sprite_plane_move:
>     - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +3 similar issues
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
> 
>   * igt@perf@blocking:
>     - shard-skl:          [FAIL][49] ([fdo#110728]) -> [PASS][50]
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-skl9/igt@perf@blocking.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/igt@perf@blocking.html
> 
>   * igt@perf@polling:
>     - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-apl7/igt@perf@polling.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl8/igt@perf@polling.html
> 
>   * igt@prime_vgem@fence-wait-bsd2:
>     - shard-iclb:         [SKIP][53] ([fdo#109276]) -> [PASS][54] +21 similar issues
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_ctx_isolation@vcs1-nonpriv:
>     - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
> 
>   * igt@gem_mocs_settings@mocs-isolation-bsd2:
>     - shard-iclb:         [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> 
>   * igt@gem_mocs_settings@mocs-settings-bsd2:
>     - shard-iclb:         [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
> 
>   
>   [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
>   [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
>   [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
>   [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
>   [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
>   [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
>   [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
>   [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
>   [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
>   [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
>   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>   [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_6861 -> Patchwork_14345
> 
>   CI-20190529: 20190529
>   CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_14345: a21088c79279e1d0a78c197d2d5d1029e60f9546 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✓ Fi.CI.IGT: success for cdclk consolidation and rework for BXT-TGL (rev6)

[Saarinen, Jani]

Hi, 


> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Matt
> Roper
> Sent: keskiviikko 11. syyskuuta 2019 6.43
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for cdclk consolidation and rework for
> BXT-TGL (rev6)
> 
> On Tue, Sep 10, 2019 at 11:55:40PM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: cdclk consolidation and rework for BXT-TGL (rev6)
> > URL   : https://patchwork.freedesktop.org/series/66365/
> > State : success
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
> > ====================================================
> >
> > Summary
> > -------
> >
> >   **SUCCESS**
> >
> >   No regressions found.
> >
> 
> Applied to dinq.  Thanks Ville for the reviews.
Matt, this seems to break TGL now. 
See: 
http://gfx-ci.fi.intel.com/tree/drm-tip/CI_DRM_6864/fi-tgl-u/boot0.txt
WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)
<4>[   11.971515] WARNING: CPU: 6 PID: 331 at drivers/gpu/drm/i915/display/intel_display.c:14556 skl_max_scale+0xa4/0xb0 [i915]

And
http://gfx-ci.fi.intel.com/tree/drm-tip/CI_DRM_6864/git-log-oneline.txt
Martin, is there bug already? 


> 
> Matt
> 
> >
> >
> > New tests
> > ---------
> >
> >   New tests have been introduced between CI_DRM_6861_full and
> Patchwork_14345_full:
> >
> > ### New Piglit tests (7) ###
> >
> >   * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d:
> >     - Statuses : 1 incomplete(s)
> >     - Exec time: [0.0] s
> >
> >
> >
> > Known issues
> > ------------
> >
> >   Here are the changes found in Patchwork_14345_full that come from known
> issues:
> >
> > ### IGT changes ###
> >
> > #### Issues hit ####
> >
> >   * igt@gem_busy@basic-hang-rcs0:
> >     - shard-glk:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
> >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> glk6/igt@gem_busy@basic-hang-rcs0.html
> >    [2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk3/ig
> > t@gem_busy@basic-hang-rcs0.html
> >
> >   * igt@gem_ctx_isolation@rcs0-s3:
> >     - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues
> >    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> apl4/igt@gem_ctx_isolation@rcs0-s3.html
> >    [4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl7/ig
> > t@gem_ctx_isolation@rcs0-s3.html
> >
> >   * igt@gem_exec_schedule@preempt-contexts-bsd2:
> >     - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues
> >    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
> >    [6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/i
> > gt@gem_exec_schedule@preempt-contexts-bsd2.html
> >
> >   * igt@gem_exec_schedule@preempt-hang-vebox:
> >     - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
> >    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb1/igt@gem_exec_schedule@preempt-hang-vebox.html
> >    [8]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/i
> > gt@gem_exec_schedule@preempt-hang-vebox.html
> >
> >   * igt@gem_exec_schedule@reorder-wide-bsd:
> >     - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#111325]) +9 similar issues
> >    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
> >    [10]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
> > gt@gem_exec_schedule@reorder-wide-bsd.html
> >
> >   * igt@i915_pm_rpm@modeset-stress-extra-wait:
> >     - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] /
> [fdo#108840])
> >    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb7/igt@i915_pm_rpm@modeset-stress-extra-wait.html
> >    [12]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/i
> > gt@i915_pm_rpm@modeset-stress-extra-wait.html
> >
> >   * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
> >     - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
> >    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> apl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
> >    [14]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl3/ig
> > t@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
> >
> >   * igt@kms_flip@dpms-vs-vblank-race-interruptible:
> >     - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#111609])
> >    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> glk1/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
> >    [16]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/ig
> > t@kms_flip@dpms-vs-vblank-race-interruptible.html
> >
> >   * igt@kms_flip@flip-vs-suspend-interruptible:
> >     - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) +1 similar
> issue
> >    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
> >    [18]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-hsw1/ig
> > t@kms_flip@flip-vs-suspend-interruptible.html
> >
> >   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
> >     - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues
> >    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
> >    [20]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb3/i
> > gt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
> >
> >   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> >     - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
> >    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> >    [22]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl7/ig
> > t@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> >
> >   * igt@kms_psr@psr2_sprite_mmap_gtt:
> >     - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
> >    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> >    [24]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
> > gt@kms_psr@psr2_sprite_mmap_gtt.html
> >
> >   * igt@kms_setmode@basic:
> >     - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
> >    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> apl1/igt@kms_setmode@basic.html
> >    [26]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/ig
> > t@kms_setmode@basic.html
> >
> >   * igt@perf@polling:
> >     - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
> >    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl1/igt@perf@polling.html
> >    [28]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl8/ig
> > t@perf@polling.html
> >
> >   * igt@testdisplay:
> >     - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([fdo#105763] /
> [fdo#106538])
> >    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> glk7/igt@testdisplay.html
> >    [30]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/ig
> > t@testdisplay.html
> >
> >
> > #### Possible fixes ####
> >
> >   * igt@gem_exec_schedule@preempt-other-chain-bsd:
> >     - shard-iclb:         [SKIP][31] ([fdo#111325]) -> [PASS][32] +4 similar issues
> >    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> >    [32]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb8/i
> > gt@gem_exec_schedule@preempt-other-chain-bsd.html
> >
> >   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> >     - shard-apl:          [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +1 similar
> issue
> >    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> >    [34]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/ig
> > t@kms_cursor_crc@pipe-c-cursor-suspend.html
> >
> >   * igt@kms_flip@2x-flip-vs-expired-vblank:
> >     - shard-glk:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
> >    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
> >    [36]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk1/ig
> > t@kms_flip@2x-flip-vs-expired-vblank.html
> >
> >   * igt@kms_flip@flip-vs-expired-vblank:
> >     - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
> >    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl10/igt@kms_flip@flip-vs-expired-vblank.html
> >    [38]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl9/ig
> > t@kms_flip@flip-vs-expired-vblank.html
> >
> >   * igt@kms_flip@plain-flip-fb-recreate-interruptible:
> >     - shard-skl:          [FAIL][39] ([fdo#100368]) -> [PASS][40]
> >    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
> >    [40]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/i
> > gt@kms_flip@plain-flip-fb-recreate-interruptible.html
> >
> >   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
> >     - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
> >    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
> >    [42]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/i
> > gt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
> >
> >   * igt@kms_frontbuffer_tracking@psr-suspend:
> >     - shard-skl:          [INCOMPLETE][43] ([fdo#104108] / [fdo#106978]) -> [PASS][44]
> >    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
> >    [44]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl5/ig
> > t@kms_frontbuffer_tracking@psr-suspend.html
> >
> >   * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> >     - shard-skl:          [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
> >    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> >    [46]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl4/ig
> > t@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> >
> >   * igt@kms_psr@psr2_sprite_plane_move:
> >     - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +3 similar issues
> >    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb7/igt@kms_psr@psr2_sprite_plane_move.html
> >    [48]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/i
> > gt@kms_psr@psr2_sprite_plane_move.html
> >
> >   * igt@perf@blocking:
> >     - shard-skl:          [FAIL][49] ([fdo#110728]) -> [PASS][50]
> >    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> skl9/igt@perf@blocking.html
> >    [50]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/i
> > gt@perf@blocking.html
> >
> >   * igt@perf@polling:
> >     - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar
> issue
> >    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> apl7/igt@perf@polling.html
> >    [52]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl8/ig
> > t@perf@polling.html
> >
> >   * igt@prime_vgem@fence-wait-bsd2:
> >     - shard-iclb:         [SKIP][53] ([fdo#109276]) -> [PASS][54] +21 similar issues
> >    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb3/igt@prime_vgem@fence-wait-bsd2.html
> >    [54]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
> > gt@prime_vgem@fence-wait-bsd2.html
> >
> >
> > #### Warnings ####
> >
> >   * igt@gem_ctx_isolation@vcs1-nonpriv:
> >     - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
> >    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
> >    [56]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
> > gt@gem_ctx_isolation@vcs1-nonpriv.html
> >
> >   * igt@gem_mocs_settings@mocs-isolation-bsd2:
> >     - shard-iclb:         [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
> >    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> >    [58]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/i
> > gt@gem_mocs_settings@mocs-isolation-bsd2.html
> >
> >   * igt@gem_mocs_settings@mocs-settings-bsd2:
> >     - shard-iclb:         [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
> >    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
> iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
> >    [60]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
> > gt@gem_mocs_settings@mocs-settings-bsd2.html
> >
> >
> >   [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
> >   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> >   [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
> >   [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
> >   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> >   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> >   [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> >   [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
> >   [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
> >   [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
> >   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> >   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> >   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> >   [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
> >   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> >   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> >   [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
> >   [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
> >   [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> >   [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
> >   [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> >   [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
> >   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
> >   [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
> >
> >
> > Participating hosts (10 -> 10)
> > ------------------------------
> >
> >   No changes in participating hosts
> >
> >
> > Build changes
> > -------------
> >
> >   * CI: CI-20190529 -> None
> >   * Linux: CI_DRM_6861 -> Patchwork_14345
> >
> >   CI-20190529: 20190529
> >   CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @
> git://anongit.freedesktop.org/gfx-ci/linux
> >   IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >   Patchwork_14345: a21088c79279e1d0a78c197d2d5d1029e60f9546 @
> git://anongit.freedesktop.org/gfx-ci/linux
> >   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> > git://anongit.freedesktop.org/piglit
> >
> > == Logs ==
> >
> > For more details see:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: ✓ Fi.CI.IGT: success for cdclk consolidation and rework for BXT-TGL (rev6)

[Peres, Martin]

On 11/09/2019 09:16, Saarinen, Jani wrote:
> Hi, 
> 
> 
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Matt
>> Roper
>> Sent: keskiviikko 11. syyskuuta 2019 6.43
>> To: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for cdclk consolidation and rework for
>> BXT-TGL (rev6)
>>
>> On Tue, Sep 10, 2019 at 11:55:40PM +0000, Patchwork wrote:
>>> == Series Details ==
>>>
>>> Series: cdclk consolidation and rework for BXT-TGL (rev6)
>>> URL   : https://patchwork.freedesktop.org/series/66365/
>>> State : success
>>>
>>> == Summary ==
>>>
>>> CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
>>> ====================================================
>>>
>>> Summary
>>> -------
>>>
>>>   **SUCCESS**
>>>
>>>   No regressions found.
>>>
>>
>> Applied to dinq.  Thanks Ville for the reviews.
> Matt, this seems to break TGL now. 
> See: 
> http://gfx-ci.fi.intel.com/tree/drm-tip/CI_DRM_6864/fi-tgl-u/boot0.txt
> WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)
> <4>[   11.971515] WARNING: CPU: 6 PID: 331 at drivers/gpu/drm/i915/display/intel_display.c:14556 skl_max_scale+0xa4/0xb0 [i915]
> 
> And
> http://gfx-ci.fi.intel.com/tree/drm-tip/CI_DRM_6864/git-log-oneline.txt
> Martin, is there bug already? 

https://bugs.freedesktop.org/show_bug.cgi?id=111641

Martin

> 
> 
>>
>> Matt
>>
>>>
>>>
>>> New tests
>>> ---------
>>>
>>>   New tests have been introduced between CI_DRM_6861_full and
>> Patchwork_14345_full:
>>>
>>> ### New Piglit tests (7) ###
>>>
>>>   * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>   * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d:
>>>     - Statuses : 1 incomplete(s)
>>>     - Exec time: [0.0] s
>>>
>>>
>>>
>>> Known issues
>>> ------------
>>>
>>>   Here are the changes found in Patchwork_14345_full that come from known
>> issues:
>>>
>>> ### IGT changes ###
>>>
>>> #### Issues hit ####
>>>
>>>   * igt@gem_busy@basic-hang-rcs0:
>>>     - shard-glk:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
>>>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> glk6/igt@gem_busy@basic-hang-rcs0.html
>>>    [2]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk3/ig
>>> t@gem_busy@basic-hang-rcs0.html
>>>
>>>   * igt@gem_ctx_isolation@rcs0-s3:
>>>     - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues
>>>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> apl4/igt@gem_ctx_isolation@rcs0-s3.html
>>>    [4]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl7/ig
>>> t@gem_ctx_isolation@rcs0-s3.html
>>>
>>>   * igt@gem_exec_schedule@preempt-contexts-bsd2:
>>>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues
>>>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
>>>    [6]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/i
>>> gt@gem_exec_schedule@preempt-contexts-bsd2.html
>>>
>>>   * igt@gem_exec_schedule@preempt-hang-vebox:
>>>     - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
>>>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb1/igt@gem_exec_schedule@preempt-hang-vebox.html
>>>    [8]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/i
>>> gt@gem_exec_schedule@preempt-hang-vebox.html
>>>
>>>   * igt@gem_exec_schedule@reorder-wide-bsd:
>>>     - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#111325]) +9 similar issues
>>>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
>>>    [10]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
>>> gt@gem_exec_schedule@reorder-wide-bsd.html
>>>
>>>   * igt@i915_pm_rpm@modeset-stress-extra-wait:
>>>     - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] /
>> [fdo#108840])
>>>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb7/igt@i915_pm_rpm@modeset-stress-extra-wait.html
>>>    [12]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/i
>>> gt@i915_pm_rpm@modeset-stress-extra-wait.html
>>>
>>>   * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
>>>     - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
>>>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> apl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
>>>    [14]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl3/ig
>>> t@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
>>>
>>>   * igt@kms_flip@dpms-vs-vblank-race-interruptible:
>>>     - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#111609])
>>>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> glk1/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
>>>    [16]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/ig
>>> t@kms_flip@dpms-vs-vblank-race-interruptible.html
>>>
>>>   * igt@kms_flip@flip-vs-suspend-interruptible:
>>>     - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) +1 similar
>> issue
>>>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> hsw7/igt@kms_flip@flip-vs-suspend-interruptible.html
>>>    [18]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-hsw1/ig
>>> t@kms_flip@flip-vs-suspend-interruptible.html
>>>
>>>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
>>>     - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues
>>>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
>>>    [20]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb3/i
>>> gt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
>>>
>>>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>>>     - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
>>>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>>>    [22]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl7/ig
>>> t@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>>>
>>>   * igt@kms_psr@psr2_sprite_mmap_gtt:
>>>     - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
>>>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
>>>    [24]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
>>> gt@kms_psr@psr2_sprite_mmap_gtt.html
>>>
>>>   * igt@kms_setmode@basic:
>>>     - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
>>>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> apl1/igt@kms_setmode@basic.html
>>>    [26]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/ig
>>> t@kms_setmode@basic.html
>>>
>>>   * igt@perf@polling:
>>>     - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
>>>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl1/igt@perf@polling.html
>>>    [28]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl8/ig
>>> t@perf@polling.html
>>>
>>>   * igt@testdisplay:
>>>     - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([fdo#105763] /
>> [fdo#106538])
>>>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> glk7/igt@testdisplay.html
>>>    [30]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk5/ig
>>> t@testdisplay.html
>>>
>>>
>>> #### Possible fixes ####
>>>
>>>   * igt@gem_exec_schedule@preempt-other-chain-bsd:
>>>     - shard-iclb:         [SKIP][31] ([fdo#111325]) -> [PASS][32] +4 similar issues
>>>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>>>    [32]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb8/i
>>> gt@gem_exec_schedule@preempt-other-chain-bsd.html
>>>
>>>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>>>     - shard-apl:          [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +1 similar
>> issue
>>>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>>>    [34]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl5/ig
>>> t@kms_cursor_crc@pipe-c-cursor-suspend.html
>>>
>>>   * igt@kms_flip@2x-flip-vs-expired-vblank:
>>>     - shard-glk:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
>>>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
>>>    [36]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-glk1/ig
>>> t@kms_flip@2x-flip-vs-expired-vblank.html
>>>
>>>   * igt@kms_flip@flip-vs-expired-vblank:
>>>     - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
>>>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl10/igt@kms_flip@flip-vs-expired-vblank.html
>>>    [38]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl9/ig
>>> t@kms_flip@flip-vs-expired-vblank.html
>>>
>>>   * igt@kms_flip@plain-flip-fb-recreate-interruptible:
>>>     - shard-skl:          [FAIL][39] ([fdo#100368]) -> [PASS][40]
>>>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
>>>    [40]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/i
>>> gt@kms_flip@plain-flip-fb-recreate-interruptible.html
>>>
>>>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
>>>     - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
>>>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
>>>    [42]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb6/i
>>> gt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
>>>
>>>   * igt@kms_frontbuffer_tracking@psr-suspend:
>>>     - shard-skl:          [INCOMPLETE][43] ([fdo#104108] / [fdo#106978]) -> [PASS][44]
>>>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
>>>    [44]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl5/ig
>>> t@kms_frontbuffer_tracking@psr-suspend.html
>>>
>>>   * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>>>     - shard-skl:          [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
>>>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>>>    [46]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl4/ig
>>> t@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>>>
>>>   * igt@kms_psr@psr2_sprite_plane_move:
>>>     - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +3 similar issues
>>>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb7/igt@kms_psr@psr2_sprite_plane_move.html
>>>    [48]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb2/i
>>> gt@kms_psr@psr2_sprite_plane_move.html
>>>
>>>   * igt@perf@blocking:
>>>     - shard-skl:          [FAIL][49] ([fdo#110728]) -> [PASS][50]
>>>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> skl9/igt@perf@blocking.html
>>>    [50]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-skl10/i
>>> gt@perf@blocking.html
>>>
>>>   * igt@perf@polling:
>>>     - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar
>> issue
>>>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> apl7/igt@perf@polling.html
>>>    [52]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-apl8/ig
>>> t@perf@polling.html
>>>
>>>   * igt@prime_vgem@fence-wait-bsd2:
>>>     - shard-iclb:         [SKIP][53] ([fdo#109276]) -> [PASS][54] +21 similar issues
>>>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb3/igt@prime_vgem@fence-wait-bsd2.html
>>>    [54]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
>>> gt@prime_vgem@fence-wait-bsd2.html
>>>
>>>
>>> #### Warnings ####
>>>
>>>   * igt@gem_ctx_isolation@vcs1-nonpriv:
>>>     - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
>>>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
>>>    [56]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
>>> gt@gem_ctx_isolation@vcs1-nonpriv.html
>>>
>>>   * igt@gem_mocs_settings@mocs-isolation-bsd2:
>>>     - shard-iclb:         [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
>>>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>>>    [58]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb7/i
>>> gt@gem_mocs_settings@mocs-isolation-bsd2.html
>>>
>>>   * igt@gem_mocs_settings@mocs-settings-bsd2:
>>>     - shard-iclb:         [SKIP][59] ([fdo#109276]) -> [FAIL][60] ([fdo#111330])
>>>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6861/shard-
>> iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
>>>    [60]:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/shard-iclb4/i
>>> gt@gem_mocs_settings@mocs-settings-bsd2.html
>>>
>>>
>>>   [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
>>>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>>>   [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
>>>   [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
>>>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>>>   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>>>   [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
>>>   [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
>>>   [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
>>>   [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
>>>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>>>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>>>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>>>   [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
>>>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>>>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>>>   [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
>>>   [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
>>>   [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
>>>   [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
>>>   [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
>>>   [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
>>>   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>>>   [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
>>>
>>>
>>> Participating hosts (10 -> 10)
>>> ------------------------------
>>>
>>>   No changes in participating hosts
>>>
>>>
>>> Build changes
>>> -------------
>>>
>>>   * CI: CI-20190529 -> None
>>>   * Linux: CI_DRM_6861 -> Patchwork_14345
>>>
>>>   CI-20190529: 20190529
>>>   CI_DRM_6861: 32c81a3173640f165510de65b8e4137aa049b33f @
>> git://anongit.freedesktop.org/gfx-ci/linux
>>>   IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
>> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>>>   Patchwork_14345: a21088c79279e1d0a78c197d2d5d1029e60f9546 @
>> git://anongit.freedesktop.org/gfx-ci/linux
>>>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
>>> git://anongit.freedesktop.org/piglit
>>>
>>> == Logs ==
>>>
>>> For more details see:
>>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/
>>
>> --
>> Matt Roper
>> Graphics Software Engineer
>> VTT-OSGC Platform Enablement
>> Intel Corporation
>> (916) 356-2795
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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