[PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions

[PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions

[jianzh-5C7GfCeVMHo]

From: Jiange Zhao <Jiange.Zhao@amd.com>

Mailbox functions and interrupts are only for Navi12 VF.

Register functions and irqs during initialization.

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a61f43c0c9df..4c24672be12a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -53,6 +53,7 @@
 #include "vcn_v2_0.h"
 #include "dce_virtual.h"
 #include "mes_v10_1.h"
+#include "mxgpu_nv.h"
 
 static const struct amd_ip_funcs nv_common_ip_funcs;
 
@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 
 	adev->nbio.funcs->detect_hw_virt(adev);
 
+	if (amdgpu_sriov_vf(adev))
+		adev->virt.ops = &xgpu_nv_virt_ops;
+
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle)
 		return -EINVAL;
 	}
 
+	if (amdgpu_sriov_vf(adev)) {
+		amdgpu_virt_init_setting(adev);
+		xgpu_nv_mailbox_set_irq_funcs(adev);
+	}
+
 	return 0;
 }
 
 static int nv_common_late_init(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	if (amdgpu_sriov_vf(adev))
+		xgpu_nv_mailbox_get_irq(adev);
+
 	return 0;
 }
 
 static int nv_common_sw_init(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	if (amdgpu_sriov_vf(adev))
+		xgpu_nv_mailbox_add_irq_id(adev);
+
 	return 0;
 }
 
-- 
2.20.1

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RE: [PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions

[Deng, Emily]

Reviewed-by: Emily Deng <Emily.Deng@amd.com>

>-----Original Message-----
>From: Zhao, Jiange <Jiange.Zhao@amd.com>
>Sent: Wednesday, September 11, 2019 6:25 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Nieto, David M <David.Nieto@amd.com>; Deng, Emily
><Emily.Deng@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>;
>Zhao, Jiange <Jiange.Zhao@amd.com>
>Subject: [PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox
>functions
>
>From: Jiange Zhao <Jiange.Zhao@amd.com>
>
>Mailbox functions and interrupts are only for Navi12 VF.
>
>Register functions and irqs during initialization.
>
>Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>b/drivers/gpu/drm/amd/amdgpu/nv.c index a61f43c0c9df..4c24672be12a
>100644
>--- a/drivers/gpu/drm/amd/amdgpu/nv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>@@ -53,6 +53,7 @@
> #include "vcn_v2_0.h"
> #include "dce_virtual.h"
> #include "mes_v10_1.h"
>+#include "mxgpu_nv.h"
>
> static const struct amd_ip_funcs nv_common_ip_funcs;
>
>@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>
> 	adev->nbio.funcs->detect_hw_virt(adev);
>
>+	if (amdgpu_sriov_vf(adev))
>+		adev->virt.ops = &xgpu_nv_virt_ops;
>+
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
> 	case CHIP_NAVI14:
>@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle)
> 		return -EINVAL;
> 	}
>
>+	if (amdgpu_sriov_vf(adev)) {
>+		amdgpu_virt_init_setting(adev);
>+		xgpu_nv_mailbox_set_irq_funcs(adev);
>+	}
>+
> 	return 0;
> }
>
> static int nv_common_late_init(void *handle)  {
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	if (amdgpu_sriov_vf(adev))
>+		xgpu_nv_mailbox_get_irq(adev);
>+
> 	return 0;
> }
>
> static int nv_common_sw_init(void *handle)  {
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	if (amdgpu_sriov_vf(adev))
>+		xgpu_nv_mailbox_add_irq_id(adev);
>+
> 	return 0;
> }
>
>--
>2.20.1

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