* [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
@ 2019-09-13 7:51 Chris Wilson
2019-09-13 7:51 ` [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Chris Wilson @ 2019-09-13 7:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE on read size (Mika)
BSpec: 18331.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++++++++++++++++++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..18e8314641a8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -910,6 +910,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
@@ -935,6 +938,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -957,6 +974,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1010,6 +1028,15 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1080,6 +1107,46 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
+ GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
+ GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
+ GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
+ GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
+ GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
+};
+
static void
ilk_dummy_write(struct intel_uncore *uncore)
{
@@ -1228,6 +1295,7 @@ __gen_read(func, 16) \
__gen_read(func, 32) \
__gen_read(func, 64)
+__gen_reg_read_funcs(gen12_fwtable);
__gen_reg_read_funcs(gen11_fwtable);
__gen_reg_read_funcs(fwtable);
__gen_reg_read_funcs(gen6);
@@ -1319,6 +1387,7 @@ __gen_write(func, 8) \
__gen_write(func, 16) \
__gen_write(func, 32)
+__gen_reg_write_funcs(gen12_fwtable);
__gen_reg_write_funcs(gen11_fwtable);
__gen_reg_write_funcs(fwtable);
__gen_reg_write_funcs(gen8);
@@ -1690,10 +1759,14 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
- } else {
+ } else if (IS_GEN(i915, 11)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+ } else {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
}
uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 86815c6072a1..0ffb141eb988 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -67,6 +67,7 @@ static int intel_shadow_table_check(void)
} reg_lists[] = {
{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
+ { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
};
const i915_reg_t *reg;
unsigned int i, j;
@@ -101,6 +102,7 @@ int intel_uncore_mock_selftests(void)
{ __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
+ { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
};
int err, i;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support
2019-09-13 7:51 [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Chris Wilson
@ 2019-09-13 7:51 ` Chris Wilson
2019-09-21 0:39 ` Lucas De Marchi
2019-09-13 10:09 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-09-13 7:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo, Michel Thierry
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
v2: GEM_BUG_ON on mask size (Lionel)
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
CC: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com> #v1
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Sudeep Dutt <sudeep.dutt@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 83 ++++++++++++++++++------
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 72 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS (10) /* HSW upper bound */
+#define GEN_MAX_EUS (16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
- * store eus enabled using bits, no need to multiply by eus per
- * subslice.
- */
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 43db50095257..b5b449a88cf1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3823,7 +3823,8 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 50b05a5de53b..b91a960b037f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ u8 s_en;
+ u32 dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
+ * Instead of splitting these, provide userspace with an array
+ * of DSS to more closely represent the hardware resource.
+ */
+ intel_sseu_set_info(sseu, 1, 6, 16);
+
+ s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
+
+ dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
+
+ /* one bit per pair of EUs */
+ eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
+
+ /* TGL only supports slice-level power gating */
+ sseu->has_slice_pg = 1;
+}
+
static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u8 s_en;
- u32 ss_en, ss_en_mask;
+ u32 ss_en;
u8 eu_en;
- int s;
if (IS_ELKHARTLAKE(dev_priv))
intel_sseu_set_info(sseu, 1, 4, 8);
@@ -197,26 +253,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
- ss_en_mask = BIT(sseu->max_subslices) - 1;
eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
- for (s = 0; s < sseu->max_slices; s++) {
- if (s_en & BIT(s)) {
- int ss_idx = sseu->max_subslices * s;
- int ss;
-
- sseu->slice_mask |= BIT(s);
-
- intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
- ss_en_mask);
-
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
- }
- sseu->eu_per_subslice = hweight8(eu_en);
- sseu->eu_total = compute_eu_total(sseu);
+ gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -959,8 +998,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
gen9_sseu_info_init(dev_priv);
else if (IS_GEN(dev_priv, 10))
gen10_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (IS_GEN(dev_priv, 11))
gen11_sseu_info_init(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 12)
+ gen12_sseu_info_init(dev_priv);
if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
DRM_INFO("Disabling ppGTT for VT-d support\n");
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..30c542144016 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2033,8 +2033,10 @@ struct drm_i915_query {
* (data[X / 8] >> (X % 8)) & 1
*
* - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. The availability of subslice Y in slice
- * X can be queried with the following formula :
+ * whether a subslice is available. Gen12 has dual-subslices, which are
+ * similar to two gen11 subslices. For gen12, this array represents dual-
+ * subslices. The availability of subslice Y in slice X can be queried
+ * with the following formula :
*
* (data[subslice_offset +
* X * subslice_stride +
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
2019-09-13 7:51 [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Chris Wilson
2019-09-13 7:51 ` [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support Chris Wilson
@ 2019-09-13 10:09 ` Patchwork
2019-09-13 10:28 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-14 5:18 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-09-13 10:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
URL : https://patchwork.freedesktop.org/series/66638/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Introduce gen12 forcewake ranges
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
Commit: drm/i915/tgl: s/ss/eu fuse reading support
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
2019-09-13 7:51 [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Chris Wilson
2019-09-13 7:51 ` [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support Chris Wilson
2019-09-13 10:09 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Patchwork
@ 2019-09-13 10:28 ` Patchwork
2019-09-14 5:18 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-09-13 10:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
URL : https://patchwork.freedesktop.org/series/66638/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6888 -> Patchwork_14396
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14396:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-threads:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-tgl-u/igt@gem_close_race@basic-threads.html
Known issues
------------
Here are the changes found in Patchwork_14396 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_flink_basic@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@gem_flink_basic@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724] / [fdo#111214])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@i915_module_load@reload.html
#### Possible fixes ####
* igt@gem_ctx_create@basic:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-bxt-dsi/igt@gem_ctx_create@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-bxt-dsi/igt@gem_ctx_create@basic.html
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}: [INCOMPLETE][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][15] ([fdo#102614]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6888 -> Patchwork_14396
CI-20190529: 20190529
CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5179: 3374cd0b048f9c277b2815bf80502f9f89680176 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14396: 6d8d64cae887cc8bf87e6a24b1bd88658c7be9fd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6d8d64cae887 drm/i915/tgl: s/ss/eu fuse reading support
bc347bc86f73 drm/i915/tgl: Introduce gen12 forcewake ranges
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
2019-09-13 7:51 [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Chris Wilson
` (2 preceding siblings ...)
2019-09-13 10:28 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-14 5:18 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-09-14 5:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
URL : https://patchwork.freedesktop.org/series/66638/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6888_full -> Patchwork_14396_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14396_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
* igt@i915_suspend@forcewake:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@i915_suspend@forcewake.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb7/igt@i915_suspend@forcewake.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#105767])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-kbl: [PASS][11] -> [FAIL][12] ([fdo#105363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-skl9/igt@kms_flip_tiling@flip-to-x-tiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-skl8/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103166])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109642] / [fdo#111068])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb2/igt@kms_psr2_su@page_flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb4/igt@kms_psr2_su@page_flip.html
* igt@perf@short-reads:
- shard-glk: [PASS][29] -> [FAIL][30] ([fdo#103183])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-glk4/igt@perf@short-reads.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-glk1/igt@perf@short-reads.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +6 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_eio@reset-stress:
- shard-iclb: [FAIL][33] ([fdo#109661]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb8/igt@gem_eio@reset-stress.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb4/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][35] ([fdo#111325]) -> [PASS][36] +10 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_softpin@softpin:
- shard-apl: [INCOMPLETE][37] ([fdo#103927]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-apl5/igt@gem_softpin@softpin.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-apl2/igt@gem_softpin@softpin.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [DMESG-WARN][39] ([fdo#108686]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][41] ([fdo#103355]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-hsw: [INCOMPLETE][43] ([fdo#103540]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-hsw4/igt@kms_flip@2x-flip-vs-fences-interruptible.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-hsw1/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [FAIL][45] ([fdo#100368]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][47] ([fdo#103167]) -> [PASS][48] +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +26 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb5/igt@prime_busy@hang-bsd2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb2/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][53] ([fdo#109276]) -> [FAIL][54] ([fdo#111330]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb8/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][55] ([fdo#111330]) -> [SKIP][56] ([fdo#109276]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/shard-iclb3/igt@gem_mocs_settings@mocs-reset-bsd2.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6888 -> Patchwork_14396
CI-20190529: 20190529
CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5179: 3374cd0b048f9c277b2815bf80502f9f89680176 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14396: 6d8d64cae887cc8bf87e6a24b1bd88658c7be9fd @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support
2019-09-13 7:51 ` [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support Chris Wilson
@ 2019-09-21 0:39 ` Lucas De Marchi
2019-09-22 16:48 ` Lionel Landwerlin
0 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2019-09-21 0:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: Oscar Mateo, Michel Thierry, Intel Graphics
On Fri, Sep 13, 2019 at 12:51 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
> some duplicated resources/paths. Although DSS behave similarly to 2
> subslices, instead of splitting this and presenting userspace with bits
> not directly representative of hardware resources, present userspace
> with a subslice_mask made up of DSS bits instead.
>
> v2: GEM_BUG_ON on mask size (Lionel)
>
> Bspec: 29547
> Bspec: 12247
> Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> CC: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com> #v1
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Sudeep Dutt <sudeep.dutt@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
After this I get the correct values for TGL:
- Available Subslice Total: 2
- Available Slice0 subslices: 2
- Available EU Total: 16
- Available EU Per Subslice: 8
+ Available Subslice Total: 6
+ Available Slice0 subslices: 6
+ Available EU Total: 96
+ Available EU Per Subslice: 16
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.c | 83 ++++++++++++++++++------
> include/uapi/drm/i915_drm.h | 6 +-
> 5 files changed, 72 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 4070f6ff1db6..d1d225204f09 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -18,12 +18,13 @@ struct drm_i915_private;
> #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> -#define GEN_MAX_EUS (10) /* HSW upper bound */
> +#define GEN_MAX_EUS (16) /* TGL upper bound */
> #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
>
> struct sseu_dev_info {
> u8 slice_mask;
> u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> + u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
> u16 eu_total;
> u8 eu_per_subslice;
> u8 min_eu_in_pool;
> @@ -40,12 +41,6 @@ struct sseu_dev_info {
>
> u8 ss_stride;
> u8 eu_stride;
> -
> - /* We don't have more than 8 eus per subslice at the moment and as we
> - * store eus enabled using bits, no need to multiply by eus per
> - * subslice.
> - */
> - u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 43db50095257..b5b449a88cf1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3823,7 +3823,8 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
>
> - if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> + if (info->sseu.has_subslice_pg &&
> + !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ecebc82f..47847135a11f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
>
> +#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
> +
> #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 50b05a5de53b..b91a960b037f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> + u8 s_en, u32 ss_en, u16 eu_en)
> +{
> + int s, ss;
> +
> + /* ss_en represents entire subslice mask across all slices */
> + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> + sizeof(ss_en) * BITS_PER_BYTE);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + if ((s_en & BIT(s)) == 0)
> + continue;
> +
> + sseu->slice_mask |= BIT(s);
> +
> + intel_sseu_set_subslices(sseu, s, ss_en);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, s, ss))
> + sseu_set_eus(sseu, s, ss, eu_en);
> + }
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + u8 s_en;
> + u32 dss_en;
> + u16 eu_en = 0;
> + u8 eu_en_fuse;
> + int eu;
> +
> + /*
> + * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
> + * Instead of splitting these, provide userspace with an array
> + * of DSS to more closely represent the hardware resource.
> + */
> + intel_sseu_set_info(sseu, 1, 6, 16);
> +
> + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> +
> + dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
> +
> + /* one bit per pair of EUs */
> + eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
> + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
> + if (eu_en_fuse & BIT(eu))
> + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> +
> + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
> +
> + /* TGL only supports slice-level power gating */
> + sseu->has_slice_pg = 1;
> +}
> +
> static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> u8 s_en;
> - u32 ss_en, ss_en_mask;
> + u32 ss_en;
> u8 eu_en;
> - int s;
>
> if (IS_ELKHARTLAKE(dev_priv))
> intel_sseu_set_info(sseu, 1, 4, 8);
> @@ -197,26 +253,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>
> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> - ss_en_mask = BIT(sseu->max_subslices) - 1;
> eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
>
> - for (s = 0; s < sseu->max_slices; s++) {
> - if (s_en & BIT(s)) {
> - int ss_idx = sseu->max_subslices * s;
> - int ss;
> -
> - sseu->slice_mask |= BIT(s);
> -
> - intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
> - ss_en_mask);
> -
> - for (ss = 0; ss < sseu->max_subslices; ss++)
> - if (intel_sseu_has_subslice(sseu, s, ss))
> - sseu_set_eus(sseu, s, ss, eu_en);
> - }
> - }
> - sseu->eu_per_subslice = hweight8(eu_en);
> - sseu->eu_total = compute_eu_total(sseu);
> + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -959,8 +998,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> gen9_sseu_info_init(dev_priv);
> else if (IS_GEN(dev_priv, 10))
> gen10_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) >= 11)
> + else if (IS_GEN(dev_priv, 11))
> gen11_sseu_info_init(dev_priv);
> + else if (INTEL_GEN(dev_priv) >= 12)
> + gen12_sseu_info_init(dev_priv);
>
> if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
> DRM_INFO("Disabling ppGTT for VT-d support\n");
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 469dc512cca3..30c542144016 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2033,8 +2033,10 @@ struct drm_i915_query {
> * (data[X / 8] >> (X % 8)) & 1
> *
> * - the subslice mask for each slice with one bit per subslice telling
> - * whether a subslice is available. The availability of subslice Y in slice
> - * X can be queried with the following formula :
> + * whether a subslice is available. Gen12 has dual-subslices, which are
> + * similar to two gen11 subslices. For gen12, this array represents dual-
> + * subslices. The availability of subslice Y in slice X can be queried
> + * with the following formula :
> *
> * (data[subslice_offset +
> * X * subslice_stride +
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support
2019-09-21 0:39 ` Lucas De Marchi
@ 2019-09-22 16:48 ` Lionel Landwerlin
2019-09-23 15:17 ` Summers, Stuart
0 siblings, 1 reply; 8+ messages in thread
From: Lionel Landwerlin @ 2019-09-22 16:48 UTC (permalink / raw)
To: Lucas De Marchi, Chris Wilson; +Cc: Oscar Mateo, Michel Thierry, Intel Graphics
On 21/09/2019 03:39, Lucas De Marchi wrote:
> On Fri, Sep 13, 2019 at 12:51 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>
>> Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
>> some duplicated resources/paths. Although DSS behave similarly to 2
>> subslices, instead of splitting this and presenting userspace with bits
>> not directly representative of hardware resources, present userspace
>> with a subslice_mask made up of DSS bits instead.
>>
>> v2: GEM_BUG_ON on mask size (Lionel)
>>
>> Bspec: 29547
>> Bspec: 12247
>> Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> CC: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com> #v1
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: James Ausmus <james.ausmus@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Sudeep Dutt <sudeep.dutt@intel.com>
>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
> After this I get the correct values for TGL:
> - Available Subslice Total: 2
> - Available Slice0 subslices: 2
> - Available EU Total: 16
> - Available EU Per Subslice: 8
> + Available Subslice Total: 6
> + Available Slice0 subslices: 6
> + Available EU Total: 96
> + Available EU Per Subslice: 16
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Lucas De Marchi
Btw, shouldn't we print "Dualsubslice" rather than "Subslice" for TGL?
-Lionel
>> drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
>> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> drivers/gpu/drm/i915/intel_device_info.c | 83 ++++++++++++++++++------
>> include/uapi/drm/i915_drm.h | 6 +-
>> 5 files changed, 72 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> index 4070f6ff1db6..d1d225204f09 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> @@ -18,12 +18,13 @@ struct drm_i915_private;
>> #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
>> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
>> #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
>> -#define GEN_MAX_EUS (10) /* HSW upper bound */
>> +#define GEN_MAX_EUS (16) /* TGL upper bound */
>> #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
>>
>> struct sseu_dev_info {
>> u8 slice_mask;
>> u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
>> + u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
>> u16 eu_total;
>> u8 eu_per_subslice;
>> u8 min_eu_in_pool;
>> @@ -40,12 +41,6 @@ struct sseu_dev_info {
>>
>> u8 ss_stride;
>> u8 eu_stride;
>> -
>> - /* We don't have more than 8 eus per subslice at the moment and as we
>> - * store eus enabled using bits, no need to multiply by eus per
>> - * subslice.
>> - */
>> - u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
>> };
>>
>> /*
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 43db50095257..b5b449a88cf1 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -3823,7 +3823,8 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
>> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
>> unsigned int eu_cnt;
>>
>> - if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>> + if (info->sseu.has_subslice_pg &&
>> + !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>> /* skip disabled subslice */
>> continue;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index bf37ecebc82f..47847135a11f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>
>> #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
>>
>> +#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
>> +
>> #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
>> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
>> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 50b05a5de53b..b91a960b037f 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
>> return total;
>> }
>>
>> +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
>> + u8 s_en, u32 ss_en, u16 eu_en)
>> +{
>> + int s, ss;
>> +
>> + /* ss_en represents entire subslice mask across all slices */
>> + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
>> + sizeof(ss_en) * BITS_PER_BYTE);
>> +
>> + for (s = 0; s < sseu->max_slices; s++) {
>> + if ((s_en & BIT(s)) == 0)
>> + continue;
>> +
>> + sseu->slice_mask |= BIT(s);
>> +
>> + intel_sseu_set_subslices(sseu, s, ss_en);
>> +
>> + for (ss = 0; ss < sseu->max_subslices; ss++)
>> + if (intel_sseu_has_subslice(sseu, s, ss))
>> + sseu_set_eus(sseu, s, ss, eu_en);
>> + }
>> + sseu->eu_per_subslice = hweight16(eu_en);
>> + sseu->eu_total = compute_eu_total(sseu);
>> +}
>> +
>> +static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
>> +{
>> + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>> + u8 s_en;
>> + u32 dss_en;
>> + u16 eu_en = 0;
>> + u8 eu_en_fuse;
>> + int eu;
>> +
>> + /*
>> + * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
>> + * Instead of splitting these, provide userspace with an array
>> + * of DSS to more closely represent the hardware resource.
>> + */
>> + intel_sseu_set_info(sseu, 1, 6, 16);
>> +
>> + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
>> +
>> + dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
>> +
>> + /* one bit per pair of EUs */
>> + eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
>> + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
>> + if (eu_en_fuse & BIT(eu))
>> + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>> +
>> + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
>> +
>> + /* TGL only supports slice-level power gating */
>> + sseu->has_slice_pg = 1;
>> +}
>> +
>> static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>> {
>> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>> u8 s_en;
>> - u32 ss_en, ss_en_mask;
>> + u32 ss_en;
>> u8 eu_en;
>> - int s;
>>
>> if (IS_ELKHARTLAKE(dev_priv))
>> intel_sseu_set_info(sseu, 1, 4, 8);
>> @@ -197,26 +253,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>>
>> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
>> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
>> - ss_en_mask = BIT(sseu->max_subslices) - 1;
>> eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
>>
>> - for (s = 0; s < sseu->max_slices; s++) {
>> - if (s_en & BIT(s)) {
>> - int ss_idx = sseu->max_subslices * s;
>> - int ss;
>> -
>> - sseu->slice_mask |= BIT(s);
>> -
>> - intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
>> - ss_en_mask);
>> -
>> - for (ss = 0; ss < sseu->max_subslices; ss++)
>> - if (intel_sseu_has_subslice(sseu, s, ss))
>> - sseu_set_eus(sseu, s, ss, eu_en);
>> - }
>> - }
>> - sseu->eu_per_subslice = hweight8(eu_en);
>> - sseu->eu_total = compute_eu_total(sseu);
>> + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
>>
>> /* ICL has no power gating restrictions. */
>> sseu->has_slice_pg = 1;
>> @@ -959,8 +998,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>> gen9_sseu_info_init(dev_priv);
>> else if (IS_GEN(dev_priv, 10))
>> gen10_sseu_info_init(dev_priv);
>> - else if (INTEL_GEN(dev_priv) >= 11)
>> + else if (IS_GEN(dev_priv, 11))
>> gen11_sseu_info_init(dev_priv);
>> + else if (INTEL_GEN(dev_priv) >= 12)
>> + gen12_sseu_info_init(dev_priv);
>>
>> if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
>> DRM_INFO("Disabling ppGTT for VT-d support\n");
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 469dc512cca3..30c542144016 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -2033,8 +2033,10 @@ struct drm_i915_query {
>> * (data[X / 8] >> (X % 8)) & 1
>> *
>> * - the subslice mask for each slice with one bit per subslice telling
>> - * whether a subslice is available. The availability of subslice Y in slice
>> - * X can be queried with the following formula :
>> + * whether a subslice is available. Gen12 has dual-subslices, which are
>> + * similar to two gen11 subslices. For gen12, this array represents dual-
>> + * subslices. The availability of subslice Y in slice X can be queried
>> + * with the following formula :
>> *
>> * (data[subslice_offset +
>> * X * subslice_stride +
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support
2019-09-22 16:48 ` Lionel Landwerlin
@ 2019-09-23 15:17 ` Summers, Stuart
0 siblings, 0 replies; 8+ messages in thread
From: Summers, Stuart @ 2019-09-23 15:17 UTC (permalink / raw)
To: lucas.de.marchi, Landwerlin, Lionel G, chris
Cc: Thierry, Michel, oscar.mateo, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12555 bytes --]
On Sun, 2019-09-22 at 19:48 +0300, Lionel Landwerlin wrote:
> On 21/09/2019 03:39, Lucas De Marchi wrote:
> > On Fri, Sep 13, 2019 at 12:51 AM Chris Wilson <
> > chris@chris-wilson.co.uk> wrote:
> > > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > >
> > > Gen12 has dual-subslices (DSS), which compared to gen11 subslices
> > > have
> > > some duplicated resources/paths. Although DSS behave similarly to
> > > 2
> > > subslices, instead of splitting this and presenting userspace
> > > with bits
> > > not directly representative of hardware resources, present
> > > userspace
> > > with a subslice_mask made up of DSS bits instead.
> > >
> > > v2: GEM_BUG_ON on mask size (Lionel)
> > >
> > > Bspec: 29547
> > > Bspec: 12247
> > > Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > > CC: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > Cc: Michel Thierry <michel.thierry@intel.com> #v1
> > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Daniele Ceraolo Spurio <
> > > daniele.ceraolospurio@intel.com>
> > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > > Signed-off-by: Sudeep Dutt <sudeep.dutt@intel.com>
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > > ---
> >
> > After this I get the correct values for TGL:
> > - Available Subslice Total: 2
> > - Available Slice0 subslices: 2
> > - Available EU Total: 16
> > - Available EU Per Subslice: 8
> > + Available Subslice Total: 6
> > + Available Slice0 subslices: 6
> > + Available EU Total: 96
> > + Available EU Per Subslice: 16
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > Lucas De Marchi
>
>
> Btw, shouldn't we print "Dualsubslice" rather than "Subslice" for
> TGL?
The idea here is that from the userspace perspective, there is still
only one unit which can be utilized in hardware.
Thanks,
Stuart
>
>
> -Lionel
>
>
> > > drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
> > > drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> > > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > > drivers/gpu/drm/i915/intel_device_info.c | 83
> > > ++++++++++++++++++------
> > > include/uapi/drm/i915_drm.h | 6 +-
> > > 5 files changed, 72 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > index 4070f6ff1db6..d1d225204f09 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > @@ -18,12 +18,13 @@ struct drm_i915_private;
> > > #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
> > > #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries,
> > > BITS_PER_BYTE)
> > > #define GEN_MAX_SUBSLICE_STRIDE
> > > GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> > > -#define GEN_MAX_EUS (10) /* HSW upper bound */
> > > +#define GEN_MAX_EUS (16) /* TGL upper bound */
> > > #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
> > >
> > > struct sseu_dev_info {
> > > u8 slice_mask;
> > > u8 subslice_mask[GEN_MAX_SLICES *
> > > GEN_MAX_SUBSLICE_STRIDE];
> > > + u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES *
> > > GEN_MAX_EU_STRIDE];
> > > u16 eu_total;
> > > u8 eu_per_subslice;
> > > u8 min_eu_in_pool;
> > > @@ -40,12 +41,6 @@ struct sseu_dev_info {
> > >
> > > u8 ss_stride;
> > > u8 eu_stride;
> > > -
> > > - /* We don't have more than 8 eus per subslice at the
> > > moment and as we
> > > - * store eus enabled using bits, no need to multiply by
> > > eus per
> > > - * subslice.
> > > - */
> > > - u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
> > > };
> > >
> > > /*
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 43db50095257..b5b449a88cf1 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -3823,7 +3823,8 @@ static void gen10_sseu_device_status(struct
> > > drm_i915_private *dev_priv,
> > > for (ss = 0; ss < info->sseu.max_subslices;
> > > ss++) {
> > > unsigned int eu_cnt;
> > >
> > > - if (!(s_reg[s] &
> > > (GEN9_PGCTL_SS_ACK(ss))))
> > > + if (info->sseu.has_subslice_pg &&
> > > + !(s_reg[s] &
> > > (GEN9_PGCTL_SS_ACK(ss))))
> > > /* skip disabled subslice */
> > > continue;
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index bf37ecebc82f..47847135a11f 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -2956,6 +2956,8 @@ static inline bool
> > > i915_mmio_reg_valid(i915_reg_t reg)
> > >
> > > #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
> > >
> > > +#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
> > > +
> > > #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
> > > #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> > > #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 50b05a5de53b..b91a960b037f 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct
> > > sseu_dev_info *sseu)
> > > return total;
> > > }
> > >
> > > +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> > > + u8 s_en, u32 ss_en, u16
> > > eu_en)
> > > +{
> > > + int s, ss;
> > > +
> > > + /* ss_en represents entire subslice mask across all
> > > slices */
> > > + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> > > + sizeof(ss_en) * BITS_PER_BYTE);
> > > +
> > > + for (s = 0; s < sseu->max_slices; s++) {
> > > + if ((s_en & BIT(s)) == 0)
> > > + continue;
> > > +
> > > + sseu->slice_mask |= BIT(s);
> > > +
> > > + intel_sseu_set_subslices(sseu, s, ss_en);
> > > +
> > > + for (ss = 0; ss < sseu->max_subslices; ss++)
> > > + if (intel_sseu_has_subslice(sseu, s, ss))
> > > + sseu_set_eus(sseu, s, ss, eu_en);
> > > + }
> > > + sseu->eu_per_subslice = hweight16(eu_en);
> > > + sseu->eu_total = compute_eu_total(sseu);
> > > +}
> > > +
> > > +static void gen12_sseu_info_init(struct drm_i915_private
> > > *dev_priv)
> > > +{
> > > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)-
> > > >sseu;
> > > + u8 s_en;
> > > + u32 dss_en;
> > > + u16 eu_en = 0;
> > > + u8 eu_en_fuse;
> > > + int eu;
> > > +
> > > + /*
> > > + * Gen12 has Dual-Subslices, which behave similarly to 2
> > > gen11 SS.
> > > + * Instead of splitting these, provide userspace with an
> > > array
> > > + * of DSS to more closely represent the hardware
> > > resource.
> > > + */
> > > + intel_sseu_set_info(sseu, 1, 6, 16);
> > > +
> > > + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) &
> > > GEN11_GT_S_ENA_MASK;
> > > +
> > > + dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
> > > +
> > > + /* one bit per pair of EUs */
> > > + eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) &
> > > GEN11_EU_DIS_MASK);
> > > + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
> > > + if (eu_en_fuse & BIT(eu))
> > > + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> > > +
> > > + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
> > > +
> > > + /* TGL only supports slice-level power gating */
> > > + sseu->has_slice_pg = 1;
> > > +}
> > > +
> > > static void gen11_sseu_info_init(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)-
> > > >sseu;
> > > u8 s_en;
> > > - u32 ss_en, ss_en_mask;
> > > + u32 ss_en;
> > > u8 eu_en;
> > > - int s;
> > >
> > > if (IS_ELKHARTLAKE(dev_priv))
> > > intel_sseu_set_info(sseu, 1, 4, 8);
> > > @@ -197,26 +253,9 @@ static void gen11_sseu_info_init(struct
> > > drm_i915_private *dev_priv)
> > >
> > > s_en = I915_READ(GEN11_GT_SLICE_ENABLE) &
> > > GEN11_GT_S_ENA_MASK;
> > > ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> > > - ss_en_mask = BIT(sseu->max_subslices) - 1;
> > > eu_en = ~(I915_READ(GEN11_EU_DISABLE) &
> > > GEN11_EU_DIS_MASK);
> > >
> > > - for (s = 0; s < sseu->max_slices; s++) {
> > > - if (s_en & BIT(s)) {
> > > - int ss_idx = sseu->max_subslices * s;
> > > - int ss;
> > > -
> > > - sseu->slice_mask |= BIT(s);
> > > -
> > > - intel_sseu_set_subslices(sseu, s, (ss_en
> > > >> ss_idx) &
> > > - ss_en_m
> > > ask);
> > > -
> > > - for (ss = 0; ss < sseu->max_subslices;
> > > ss++)
> > > - if (intel_sseu_has_subslice(sseu,
> > > s, ss))
> > > - sseu_set_eus(sseu, s, ss,
> > > eu_en);
> > > - }
> > > - }
> > > - sseu->eu_per_subslice = hweight8(eu_en);
> > > - sseu->eu_total = compute_eu_total(sseu);
> > > + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
> > >
> > > /* ICL has no power gating restrictions. */
> > > sseu->has_slice_pg = 1;
> > > @@ -959,8 +998,10 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > > gen9_sseu_info_init(dev_priv);
> > > else if (IS_GEN(dev_priv, 10))
> > > gen10_sseu_info_init(dev_priv);
> > > - else if (INTEL_GEN(dev_priv) >= 11)
> > > + else if (IS_GEN(dev_priv, 11))
> > > gen11_sseu_info_init(dev_priv);
> > > + else if (INTEL_GEN(dev_priv) >= 12)
> > > + gen12_sseu_info_init(dev_priv);
> > >
> > > if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
> > > DRM_INFO("Disabling ppGTT for VT-d support\n");
> > > diff --git a/include/uapi/drm/i915_drm.h
> > > b/include/uapi/drm/i915_drm.h
> > > index 469dc512cca3..30c542144016 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -2033,8 +2033,10 @@ struct drm_i915_query {
> > > * (data[X / 8] >> (X % 8)) & 1
> > > *
> > > * - the subslice mask for each slice with one bit per subslice
> > > telling
> > > - * whether a subslice is available. The availability of
> > > subslice Y in slice
> > > - * X can be queried with the following formula :
> > > + * whether a subslice is available. Gen12 has dual-subslices,
> > > which are
> > > + * similar to two gen11 subslices. For gen12, this array
> > > represents dual-
> > > + * subslices. The availability of subslice Y in slice X can be
> > > queried
> > > + * with the following formula :
> > > *
> > > * (data[subslice_offset +
> > > * X * subslice_stride +
> > > --
> > > 2.23.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-09-23 15:18 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-13 7:51 [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Chris Wilson
2019-09-13 7:51 ` [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support Chris Wilson
2019-09-21 0:39 ` Lucas De Marchi
2019-09-22 16:48 ` Lionel Landwerlin
2019-09-23 15:17 ` Summers, Stuart
2019-09-13 10:09 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges Patchwork
2019-09-13 10:28 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-14 5:18 ` ✓ Fi.CI.IGT: " Patchwork
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