[PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Chris Wilson]

Before we execute a batch, we must first issue any and all TLB
invalidations so that batch picks up the new page table entries.
Tigerlake's preparser is weakening our post-sync CS_STALL inside the
invalidate pipe-control and allowing the loading of the batch buffer
before we have setup its page table (and so it loads the wrong page and
executes indefinitely).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
Suggestions welcome as this does not seem intended behaviour, so I
suspect there is a strong pipecontrol flag we are missing.
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a3f0e4999744..a9e690c303cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2796,11 +2796,14 @@ static int gen11_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
-		cs = intel_ring_begin(request, 6);
+		cs = intel_ring_begin(request, 8);
 		if (IS_ERR(cs))
 			return PTR_ERR(cs);
 
+		*cs++ = MI_ARB_CHECK | 1 << 8 | 1;
 		cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+		*cs++ = MI_ARB_CHECK | 1 << 8;
+
 		intel_ring_advance(request, cs);
 	}
 
-- 
2.23.0

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✓ Fi.CI.BAT: success for drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations
URL   : https://patchwork.freedesktop.org/series/66703/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6894 -> Patchwork_14413
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/

Known issues
------------

  Here are the changes found in Patchwork_14413 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_param@basic:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-icl-u3/igt@gem_ctx_param@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-icl-u3/igt@gem_ctx_param@basic.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - {fi-icl-guc}:       [INCOMPLETE][5] ([fdo#107713] / [fdo#111381]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_exec_fence@basic-await-default:
    - {fi-tgl-u2}:        [FAIL][7] ([fdo#111562] / [fdo#111597]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-tgl-u2/igt@gem_exec_fence@basic-await-default.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-tgl-u2/igt@gem_exec_fence@basic-await-default.html
    - {fi-tgl-u}:         [FAIL][9] ([fdo#111562] / [fdo#111597]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-tgl-u/igt@gem_exec_fence@basic-await-default.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-tgl-u/igt@gem_exec_fence@basic-await-default.html

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-icl-u2:          [FAIL][13] ([fdo#109635 ]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][15] ([fdo#111096]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111144]: https://bugs.freedesktop.org/show_bug.cgi?id=111144
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
  [fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678


Participating hosts (54 -> 44)
------------------------------

  Missing    (10): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-skl-lmem fi-blb-e6850 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6894 -> Patchwork_14413

  CI-20190529: 20190529
  CI_DRM_6894: a323fd657c577491b1660662624bac36bb964222 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5182: f7104497049e3761ac297b66fd5586849b3cfcc8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14413: 4406384c7c9474a3beb67ff0a66127773f5de8a5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4406384c7c94 drm/i915/tgl: Suspend pre-parser across GTT invalidations

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/index.html
_______________________________________________
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✗ Fi.CI.IGT: failure for drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations
URL   : https://patchwork.freedesktop.org/series/66703/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14413_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14413_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14413_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14413_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible.html

  
Known issues
------------

  Here are the changes found in Patchwork_14413_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110854])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb5/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +19 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb5/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#111325]) +7 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-apl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-apl4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#105363])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          [PASS][13] -> [INCOMPLETE][14] ([fdo#105411])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-snb5/igt@kms_flip@flip-vs-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-snb1/igt@kms_flip@flip-vs-suspend.html
    - shard-hsw:          [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-hsw8/igt@kms_flip@flip-vs-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-hsw4/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#108341])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb8/igt@kms_psr@no_drrs.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_universal_plane@universal-plane-pipe-b-sanity:
    - shard-iclb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#107713])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb8/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [PASS][27] -> [INCOMPLETE][28] ([fdo#104108])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-skl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +6 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_eio@reset-stress:
    - shard-iclb:         [FAIL][31] ([fdo#109661]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@gem_eio@reset-stress.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb2/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@preempt-self-bsd:
    - shard-iclb:         [SKIP][33] ([fdo#111325]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@gem_exec_schedule@preempt-self-bsd.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb7/igt@gem_exec_schedule@preempt-self-bsd.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-iclb:         [FAIL][37] ([fdo#103167]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][39] ([fdo#108145]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][41] ([fdo#108145] / [fdo#110403]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][43] ([fdo#109441]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_rotation_crc@cursor-rotation-180:
    - shard-iclb:         [INCOMPLETE][45] ([fdo#107713] / [fdo#110026]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb7/igt@kms_rotation_crc@cursor-rotation-180.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb7/igt@kms_rotation_crc@cursor-rotation-180.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][47] ([fdo#109276]) -> [PASS][48] +10 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][49] ([fdo#111329]) -> [SKIP][50] ([fdo#109276])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][51] ([fdo#111330]) -> [SKIP][52] ([fdo#109276]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6894/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6894 -> Patchwork_14413

  CI-20190529: 20190529
  CI_DRM_6894: a323fd657c577491b1660662624bac36bb964222 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5182: f7104497049e3761ac297b66fd5586849b3cfcc8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14413: 4406384c7c9474a3beb67ff0a66127773f5de8a5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14413/
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Re: [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Daniele Ceraolo Spurio]

On 9/14/19 1:25 AM, Chris Wilson wrote:
> Before we execute a batch, we must first issue any and all TLB
> invalidations so that batch picks up the new page table entries.
> Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> invalidate pipe-control and allowing the loading of the batch buffer
> before we have setup its page table (and so it loads the wrong page and
> executes indefinitely).
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> Suggestions welcome as this does not seem intended behaviour, so I
> suspect there is a strong pipecontrol flag we are missing.

When I discussed the pre-parser with the HW team the feedback I got was 
that the only way to make sure we don't race the memory update is to 
either leave enough CL of space or turn the parser off like you did 
below. That discussion was about actual physical memory access though 
and not TLB.
Anyway, turning off the parser around the pipe control, if it fixes the 
problem, shouldn't be too bad since the main performance advantage of 
the parser is expected inside the user batch. The alternative would 
probably be to stop invalidating the TLBs from within the ring and 
switch to MMIO invalidations when lite-restoring a new request in the 
ring (the CS will implicitly stop the parser and invalidate everything 
on a full ctx switch).

Daniele

> ---
>   drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a3f0e4999744..a9e690c303cc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2796,11 +2796,14 @@ static int gen11_emit_flush_render(struct i915_request *request,
>   		flags |= PIPE_CONTROL_QW_WRITE;
>   		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
>   
> -		cs = intel_ring_begin(request, 6);
> +		cs = intel_ring_begin(request, 8);
>   		if (IS_ERR(cs))
>   			return PTR_ERR(cs);
>   
> +		*cs++ = MI_ARB_CHECK | 1 << 8 | 1;
>   		cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
> +		*cs++ = MI_ARB_CHECK | 1 << 8;
> +
>   		intel_ring_advance(request, cs);
>   	}
>   
> 
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Re: [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2019-09-16 21:37:26)
> 
> 
> On 9/14/19 1:25 AM, Chris Wilson wrote:
> > Before we execute a batch, we must first issue any and all TLB
> > invalidations so that batch picks up the new page table entries.
> > Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> > invalidate pipe-control and allowing the loading of the batch buffer
> > before we have setup its page table (and so it loads the wrong page and
> > executes indefinitely).
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> > Suggestions welcome as this does not seem intended behaviour, so I
> > suspect there is a strong pipecontrol flag we are missing.
> 
> When I discussed the pre-parser with the HW team the feedback I got was 
> that the only way to make sure we don't race the memory update is to 
> either leave enough CL of space or turn the parser off like you did 
> below. That discussion was about actual physical memory access though 
> and not TLB.
> Anyway, turning off the parser around the pipe control, if it fixes the 
> problem, shouldn't be too bad since the main performance advantage of 
> the parser is expected inside the user batch. The alternative would 
> probably be to stop invalidating the TLBs from within the ring and 
> switch to MMIO invalidations when lite-restoring a new request in the 
> ring (the CS will implicitly stop the parser and invalidate everything 
> on a full ctx switch).

I also only observe the effect on rcs0 atm. Does that tie in with the
preparser theory? i.e. that either the MI_FLUSH_DW is a strong barrier
or the preparser is rcs0 only. (Strictly speaking I haven't yet run the
igt_cs_tlb test on tgl/bcs0 so I am basing the above off the igt test
results that pass on bcs0 but consistently failed on rcs0.)
-Chris
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Re: [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Daniele Ceraolo Spurio]

On 9/16/19 1:54 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-09-16 21:37:26)
>>
>>
>> On 9/14/19 1:25 AM, Chris Wilson wrote:
>>> Before we execute a batch, we must first issue any and all TLB
>>> invalidations so that batch picks up the new page table entries.
>>> Tigerlake's preparser is weakening our post-sync CS_STALL inside the
>>> invalidate pipe-control and allowing the loading of the batch buffer
>>> before we have setup its page table (and so it loads the wrong page and
>>> executes indefinitely).
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> ---
>>> Suggestions welcome as this does not seem intended behaviour, so I
>>> suspect there is a strong pipecontrol flag we are missing.
>>
>> When I discussed the pre-parser with the HW team the feedback I got was
>> that the only way to make sure we don't race the memory update is to
>> either leave enough CL of space or turn the parser off like you did
>> below. That discussion was about actual physical memory access though
>> and not TLB.
>> Anyway, turning off the parser around the pipe control, if it fixes the
>> problem, shouldn't be too bad since the main performance advantage of
>> the parser is expected inside the user batch. The alternative would
>> probably be to stop invalidating the TLBs from within the ring and
>> switch to MMIO invalidations when lite-restoring a new request in the
>> ring (the CS will implicitly stop the parser and invalidate everything
>> on a full ctx switch).
> 
> I also only observe the effect on rcs0 atm. Does that tie in with the
> preparser theory? i.e. that either the MI_FLUSH_DW is a strong barrier
> or the preparser is rcs0 only. (Strictly speaking I haven't yet run the
> igt_cs_tlb test on tgl/bcs0 so I am basing the above off the igt test
> results that pass on bcs0 but consistently failed on rcs0.)
> -Chris
> 

AFAIK the pre-parser is part of the core CS logic, which should be the 
same on all engines (although the new behavior was mainly required for 
RCS workloads). The specs also don't mention a different behavior on 
MI_FLUSH. It might just be a timing thing, since I'd expect the MI_FLUSH 
to be faster to execute compared to the pipe control and thus less 
instructions will be accumulated in the pre-fetch FIFO in the meantime, 
also considering that we have 2 calls close to each other (one from the 
breadcrumb fini of the previous request).

Daniele
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