* [PATCH 0/6] Clear Color Support for TGL Render Decompression
@ 2019-09-17 12:11 Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 1/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 4 patches are
currently undergoing review/revision changes. The first 4 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/65290/
Expecting feedback for the last 2 patches. The infrastructure to
test the patch series is WIP.
Dhinakaran Pandiyan (4):
drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
compression
drm/i915/tgl: Gen-12 render decompression
drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
compression
drm/i915/tgl: Gen-12 media compression
Radhakrishna Sripada (2):
drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
drivers/gpu/drm/i915/display/intel_display.c | 121 +++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_sprite.c | 49 +++++--
drivers/gpu/drm/i915/i915_reg.h | 14 ++
include/uapi/drm/drm_fourcc.h | 31 +++++
5 files changed, 200 insertions(+), 18 deletions(-)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 2/6] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan,
Daniel Vetter, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..fb7270bf9670 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,16 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/6] drm/i915/tgl: Gen-12 render decompression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 1/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 3/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, Daniel Vetter,
dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modifier to identify
gen-12 compression. Another notable change is that decompression is
supported on all planes except cursor and on all pipes. This patch adds
decompression support for [A,X]BGR888 pixel formats.
Bspec: 18437
v2: Fix checkpatch warnings (Lucas)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++---
2 files changed, 71 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1cc74844d3ea..69b187c49a70 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return cpp;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2044,6 +2048,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2243,7 +2249,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2430,6 +2437,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2450,7 +2458,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2461,6 +2469,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2481,8 +2507,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+ cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
default:
return NULL;
@@ -2491,7 +2521,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2660,7 +2691,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int main_x, main_y;
int ccs_x, ccs_y;
- intel_tile_dims(fb, i, &tile_width, &tile_height);
+ if (!is_surface_linear(fb->modifier, i)) {
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+ } else {
+ tile_width = 64 / cpp;
+ tile_height = 1;
+ }
+
tile_width *= hsub;
tile_height *= vsub;
@@ -4069,6 +4106,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ /* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
@@ -9844,7 +9883,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+ fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
@@ -15647,6 +15688,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
is_ccs_modifier(fb->modifier))
stride_alignment *= 4;
+ /*
+ * The main surface pitch must be paded to a multiple of four
+ * tile widths.
+ */
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+ i == 0)
+ stride_alignment *= 4;
+
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
i, fb->pitches[i], stride_alignment);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7a7078d0ba23..866d25d38d04 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -535,6 +535,7 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
+ u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
@@ -576,8 +577,10 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ aux_dist |= aux_stride;
+ I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
@@ -1733,7 +1736,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2145,7 +2149,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2307,6 +2312,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
break;
default:
return false;
@@ -2317,6 +2323,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
+ if (is_ccs_modifier(modifier))
+ return true;
+ /* fall through */
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -2525,13 +2534,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: Implement support for gen-12 CCS modifiers */
- plane->has_ccs = false;
- modifiers = gen12_plane_format_modifiers_noccs;
+ modifiers = gen12_plane_format_modifiers_ccs;
plane_funcs = &gen12_plane_funcs;
} else {
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (plane->has_ccs)
modifiers = skl_plane_format_modifiers_ccs;
else
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 1/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 2/6] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 4/6] drm/i915/tgl: " Radhakrishna Sripada
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fb7270bf9670..ec8351922265 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -420,6 +420,16 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/6] drm/i915/tgl: Gen-12 media compression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (2 preceding siblings ...)
2019-09-17 12:11 ` [PATCH 3/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 5/6] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render compressed
buffers. Unlike render decompression, plane 6 and plane 7 do not support
media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
Bspec: 29695
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 69b187c49a70..2da721a6abab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1912,6 +1912,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (color_plane == 1)
return cpp;
/* fall through */
@@ -2049,6 +2050,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2249,8 +2251,15 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2438,6 +2447,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2511,6 +2521,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
ARRAY_SIZE(skl_ccs_formats),
cmd->pixel_format);
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
@@ -2522,6 +2533,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -4109,6 +4121,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9886,6 +9900,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
@@ -15692,7 +15708,8 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
* The main surface pitch must be paded to a multiple of four
* tile widths.
*/
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+ if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
i == 0)
stride_alignment *= 4;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 866d25d38d04..1655984955ca 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1737,7 +1737,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2151,6 +2152,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2308,7 +2310,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (plane->id >= PLANE_SPRITE4)
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2326,14 +2334,18 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
+ /* TODO: Media decompression does support NV12 */
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..096be95ec7f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6688,6 +6688,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/6] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (3 preceding siblings ...)
2019-09-17 12:11 ` [PATCH 4/6] drm/i915/tgl: " Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, dhinakaran.pandiyan, Kalyan Kondapally, ville.syrjala
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.
V2: Description changes as suggested by Rafael.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ec8351922265..f2b79cf749a4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -430,6 +430,17 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
+ * main surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (4 preceding siblings ...)
2019-09-17 12:11 ` [PATCH 5/6] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
@ 2019-09-17 12:11 ` Radhakrishna Sripada
2019-09-17 21:52 ` Matt Roper
2019-09-19 0:53 ` Jordan Justen
2019-09-17 15:05 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support " Patchwork
` (2 subsequent siblings)
8 siblings, 2 replies; 14+ messages in thread
From: Radhakrishna Sripada @ 2019-09-17 12:11 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 47 +++++++++++++++++--
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 10 +++-
drivers/gpu/drm/i915/i915_reg.h | 13 +++++
4 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2da721a6abab..725b9724da49 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
if (color_plane == 1)
return cpp;
/* fall through */
@@ -2051,6 +2052,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2256,6 +2258,7 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return color_plane == 1;
default:
return false;
@@ -2448,6 +2451,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2497,6 +2501,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface. Additional surface is used to pass the Clear Color
+ * structure for the driver to program the DE.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2525,6 +2544,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2534,6 +2557,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -4120,6 +4144,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ ICL_PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
@@ -9897,9 +9924,13 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
- I915_FORMAT_MOD_Y_TILED_CCS;
+ if (INTEL_GEN(dev_priv) >= 12)
+ fb->modifier = val &
+ ICL_PLANE_CTL_CLEAR_COLOR_DISABLE ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
+ else
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
@@ -14322,6 +14353,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
@@ -15709,6 +15749,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
* tile widths.
*/
if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
i == 0)
stride_alignment *= 4;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..a82695a3e0b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -579,6 +579,9 @@ struct intel_plane_state {
u32 slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1655984955ca..3672e8b9c0bc 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2321,6 +2328,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 096be95ec7f9..00c59ed8b114 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6681,6 +6681,7 @@ enum {
#define PLANE_CTL_YUV422_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
+#define ICL_PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13)
#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
#define PLANE_CTL_TILED_MASK (0x7 << 10)
#define PLANE_CTL_TILED_LINEAR (0 << 10)
@@ -6721,6 +6722,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6760,6 +6763,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (5 preceding siblings ...)
2019-09-17 12:11 ` [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
@ 2019-09-17 15:05 ` Patchwork
2019-09-17 15:27 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-18 2:09 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-17 15:05 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b45d10a93b6 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
8c34c16a8118 drm/i915/tgl: Gen-12 render decompression
7c0a2d4fecf3 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
fa6f2cb7eb5e drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2524:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
total: 0 errors, 1 warnings, 0 checks, 134 lines checked
e75d005d2b0a drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7:
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
531124e8273e drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:71: WARNING:LONG_LINE: line over 100 characters
#71: FILE: drivers/gpu/drm/i915/display/intel_display.c:2513:
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
-:72: WARNING:LONG_LINE: line over 100 characters
#72: FILE: drivers/gpu/drm/i915/display/intel_display.c:2514:
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
-:73: WARNING:LONG_LINE: line over 100 characters
#73: FILE: drivers/gpu/drm/i915/display/intel_display.c:2515:
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
-:74: WARNING:LONG_LINE: line over 100 characters
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2516:
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
-:242: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#242: FILE: drivers/gpu/drm/i915/i915_reg.h:6770:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 4 warnings, 1 checks, 193 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for Clear Color Support for TGL Render Decompression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (6 preceding siblings ...)
2019-09-17 15:05 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support " Patchwork
@ 2019-09-17 15:27 ` Patchwork
2019-09-18 2:09 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-17 15:27 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6909 -> Patchwork_14430
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/
Known issues
------------
Here are the changes found in Patchwork_14430 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u3/igt@gem_ctx_exec@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-icl-u3/igt@gem_ctx_exec@basic.html
* igt@i915_module_load@reload:
- fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([fdo#105602]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-apl-guc/igt@i915_module_load@reload.html
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] / [fdo#111214])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u3/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-icl-u3/igt@i915_module_load@reload.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][7] -> [WARN][8] ([fdo#109483])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-apl-guc: [PASS][9] -> [DMESG-WARN][10] ([fdo#103558])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-flip:
- fi-apl-guc: [PASS][11] -> [SKIP][12] ([fdo#109271]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-apl-guc/igt@prime_vgem@basic-fence-flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-apl-guc/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@i915_module_load@reload-no-display:
- {fi-icl-u4}: [DMESG-WARN][13] ([fdo#105602]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u4/igt@i915_module_load@reload-no-display.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-icl-u4/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770: [SKIP][15] ([fdo#109271]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][17] ([fdo#108511]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@vgem_basic@second-client:
- fi-icl-u3: [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/fi-icl-u3/igt@vgem_basic@second-client.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/fi-icl-u3/igt@vgem_basic@second-client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (55 -> 48)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6909 -> Patchwork_14430
CI-20190529: 20190529
CI_DRM_6909: 8a0c508a270fe1d5c5586063096bc14d760b5260 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5189: c78b9959fa4050725b16d55a5e56315884a2753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14430: 531124e8273e02e9bd89159360ccad7195376323 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
531124e8273e drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
e75d005d2b0a drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
fa6f2cb7eb5e drm/i915/tgl: Gen-12 media compression
7c0a2d4fecf3 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
8c34c16a8118 drm/i915/tgl: Gen-12 render decompression
1b45d10a93b6 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-09-17 12:11 ` [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
@ 2019-09-17 21:52 ` Matt Roper
2019-09-19 22:16 ` Sripada, Radhakrishna
2019-09-19 0:53 ` Jordan Justen
1 sibling, 1 reply; 14+ messages in thread
From: Matt Roper @ 2019-09-17 21:52 UTC (permalink / raw)
To: Radhakrishna Sripada
Cc: nanley.g.chery, intel-gfx, dhinakaran.pandiyan, ville.syrjala
On Tue, Sep 17, 2019 at 05:11:55AM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 47 +++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 3 ++
> drivers/gpu/drm/i915/display/intel_sprite.c | 10 +++-
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++
> 4 files changed, 69 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2da721a6abab..725b9724da49 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> if (color_plane == 1)
> return cpp;
> /* fall through */
> @@ -2051,6 +2052,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> return 0;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 4 * 4 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2256,6 +2258,7 @@ static bool is_surface_linear(u64 modifier, int color_plane)
> return true;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return color_plane == 1;
> default:
> return false;
> @@ -2448,6 +2451,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2497,6 +2501,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> + * the main surface. Additional surface is used to pass the Clear Color
> + * structure for the driver to program the DE.
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
I think these last two were supposed to have .has_alpha = true?
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2525,6 +2544,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return lookup_format_info(gen12_ccs_formats,
> + ARRAY_SIZE(gen12_ccs_cc_formats),
> + cmd->pixel_format);
> default:
> return NULL;
> }
> @@ -2534,6 +2557,7 @@ bool is_ccs_modifier(u64 modifier)
> {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
> @@ -4120,6 +4144,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED_CCS:
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> + ICL_PLANE_CTL_CLEAR_COLOR_DISABLE;
I think this needs to be squashed back into the previous patch that
added general gen12 CCS.
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> @@ -9897,9 +9924,13 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> case PLANE_CTL_TILED_Y:
> plane_config->tiling = I915_TILING_Y;
> if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> - I915_FORMAT_MOD_Y_TILED_CCS;
> + if (INTEL_GEN(dev_priv) >= 12)
> + fb->modifier = val &
> + ICL_PLANE_CTL_CLEAR_COLOR_DISABLE ?
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> + else
> + fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> else
> @@ -14322,6 +14353,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>
> plane_state->vma = vma;
>
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> + fb->offsets[2] >> PAGE_SHIFT));
> +
Will this work on framebuffers in stolen memory? Not that it's likely a
regular BIOS would actually setup compressed framebuffers to begin
with...
> + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> + | *(ccaddr + CC_VAL_LOWER_OFFSET);
Is there more data in the clear color page besides the color itself? If
so, maybe we should just use a struct to make the memory layout explicit?
> + kunmap_atomic(ccaddr);
> + }
> +
> return 0;
> }
>
> @@ -15709,6 +15749,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> * tile widths.
> */
> if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
> i == 0)
> stride_alignment *= 4;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..a82695a3e0b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -579,6 +579,9 @@ struct intel_plane_state {
> u32 slave;
>
> struct drm_intel_sprite_colorkey ckey;
> +
> + /* Clear Color Value */
> + u64 ccval;
> };
>
> struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1655984955ca..3672e8b9c0bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> u32 plane_color_ctl = 0;
> unsigned long irqflags;
> u32 keymsk, keymax;
> + u64 ccval = plane_state->ccval;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> + intel_uncore_write64_fw(&dev_priv->uncore,
> + PLANE_CC_VAL(pipe, plane_id), ccval);
> +
> skl_write_plane_wm(plane, crtc_state);
>
> I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> return -EINVAL;
> }
> @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> static const u64 gen12_plane_format_modifiers_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -2321,6 +2328,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> break;
> default:
> return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 096be95ec7f9..00c59ed8b114 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6681,6 +6681,7 @@ enum {
> #define PLANE_CTL_YUV422_VYUY (3 << 16)
> #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> +#define ICL_PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13)
Looks like the whitespace is off here.
Matt
> #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
> #define PLANE_CTL_TILED_MASK (0x7 << 10)
> #define PLANE_CTL_TILED_LINEAR (0 << 10)
> @@ -6721,6 +6722,8 @@ enum {
> #define _PLANE_KEYMAX_1_A 0x701a0
> #define _PLANE_KEYMAX_2_A 0x702a0
> #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> +#define _PLANE_CC_VAL_1_A 0x701b4
> +#define _PLANE_CC_VAL_2_A 0x702b4
> #define _PLANE_AUX_DIST_1_A 0x701c0
> #define _PLANE_AUX_DIST_2_A 0x702c0
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> @@ -6760,6 +6763,16 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> +#define PLANE_CC_VAL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +
> +#define CC_VAL_LOWER_OFFSET 4
> +#define CC_VAL_HIGHER_OFFSET 5
> +
> /* Input CSC Register Definitions */
> #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for Clear Color Support for TGL Render Decompression
2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (7 preceding siblings ...)
2019-09-17 15:27 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-18 2:09 ` Patchwork
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-18 2:09 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6909_full -> Patchwork_14430_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_14430_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14430_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14430_full:
### IGT changes ###
#### Warnings ####
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][1] ([fdo#108566]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
Known issues
------------
Here are the changes found in Patchwork_14430_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +6 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_mmap_gtt@big-copy-xy:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl7/igt@gem_mmap_gtt@big-copy-xy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl2/igt@gem_mmap_gtt@big-copy-xy.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#103558]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103232])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- shard-apl: [PASS][17] -> [SKIP][18] ([fdo#109271] / [fdo#109278]) +19 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl1/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-apl: [PASS][19] -> [SKIP][20] ([fdo#109271]) +177 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl5/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [PASS][21] -> [FAIL][22] ([fdo#105363])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#100368])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +4 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([fdo#106978] / [fdo#107713])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#103313])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [fdo#110403])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#108341])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb8/igt@kms_psr@no_drrs.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#99912])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl4/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl2/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][41] ([fdo#111325]) -> [PASS][42] +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +22 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][45] ([fdo#108566]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl4/igt@gem_softpin@noreloc-s3.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@gem_softpin@noreloc-s3.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-apl: [INCOMPLETE][47] ([fdo#103927]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl3/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl4/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-hsw: [FAIL][49] ([fdo#102887]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-hsw5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-hsw5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
- shard-glk: [FAIL][51] ([fdo#105363]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][53] ([fdo#105363]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [FAIL][55] ([fdo#103167]) -> [PASS][56] +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- shard-iclb: [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb7/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb8/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
* igt@perf@blocking:
- shard-skl: [FAIL][61] ([fdo#110728]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-skl8/igt@perf@blocking.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-skl8/igt@perf@blocking.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][63] ([fdo#109276]) -> [FAIL][64] ([fdo#111330]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@kms_atomic_transition@3x-modeset-transitions-fencing:
- shard-apl: [SKIP][65] ([fdo#109271] / [fdo#109278]) -> [SKIP][66] ([fdo#109271]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl7/igt@kms_atomic_transition@3x-modeset-transitions-fencing.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl1/igt@kms_atomic_transition@3x-modeset-transitions-fencing.html
* igt@kms_busy@extended-modeset-hang-oldfb-render-b:
- shard-apl: [INCOMPLETE][67] ([fdo#103927]) -> [SKIP][68] ([fdo#109271] / [fdo#109278])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl8/igt@kms_busy@extended-modeset-hang-oldfb-render-b.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@kms_busy@extended-modeset-hang-oldfb-render-b.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [SKIP][70] ([fdo#109271]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl1/igt@kms_content_protection@atomic-dpms.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][71] ([fdo#107724]) -> [SKIP][72] ([fdo#109349])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-apl: [DMESG-WARN][73] ([fdo#108566]) -> [DMESG-WARN][74] ([fdo#103558])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][75] ([fdo#108566]) -> [SKIP][76] ([fdo#109271]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-apl: [FAIL][77] ([fdo#108145]) -> [SKIP][78] ([fdo#109271] / [fdo#109278]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6909/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111716]: https://bugs.freedesktop.org/show_bug.cgi?id=111716
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6909 -> Patchwork_14430
CI-20190529: 20190529
CI_DRM_6909: 8a0c508a270fe1d5c5586063096bc14d760b5260 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5189: c78b9959fa4050725b16d55a5e56315884a2753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14430: 531124e8273e02e9bd89159360ccad7195376323 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14430/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-09-17 12:11 ` [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
2019-09-17 21:52 ` Matt Roper
@ 2019-09-19 0:53 ` Jordan Justen
1 sibling, 0 replies; 14+ messages in thread
From: Jordan Justen @ 2019-09-19 0:53 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx
Cc: ville.syrjala, nanley.g.chery, dhinakaran.pandiyan
On 2019-09-17 05:11:55, Radhakrishna Sripada wrote:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> @@ -9897,9 +9924,13 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> case PLANE_CTL_TILED_Y:
> plane_config->tiling = I915_TILING_Y;
> if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
Should {} be added to this `if` since a nested if-else is being added?
> - fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> - I915_FORMAT_MOD_Y_TILED_CCS;
> + if (INTEL_GEN(dev_priv) >= 12)
> + fb->modifier = val &
> + ICL_PLANE_CTL_CLEAR_COLOR_DISABLE ?
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> + else
> + fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> else
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-09-17 21:52 ` Matt Roper
@ 2019-09-19 22:16 ` Sripada, Radhakrishna
2019-09-19 22:38 ` Matt Roper
0 siblings, 1 reply; 14+ messages in thread
From: Sripada, Radhakrishna @ 2019-09-19 22:16 UTC (permalink / raw)
To: Roper, Matthew D
Cc: Chery, Nanley G, intel-gfx, Pandiyan, Dhinakaran, Syrjala, Ville
Hi Matt,
> -----Original Message-----
> From: Roper, Matthew D
> Sent: Tuesday, September 17, 2019 2:53 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Sharma, Shashank <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> Subject: Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL
> Render Decompression
>
> On Tue, Sep 17, 2019 at 05:11:55AM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS
> > is linear and has 4 bits of data for each main surface cache line
> > pair, a ratio of 1:256. Additional Clear Color information is passed
> > from the user-space through an offset in the GEM BO. Add a new
> > modifier to identify and parse new Clear Color information and extend
> > Gen12 render decompression functionality to the newly added modifier.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 47 +++++++++++++++++--
> > .../drm/i915/display/intel_display_types.h | 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 10 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 13 +++++
> > 4 files changed, 69 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2da721a6abab..725b9724da49 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> > /* fall through */
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > if (color_plane == 1)
> > return cpp;
> > /* fall through */
> > @@ -2051,6 +2052,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 4 * 4 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2256,6 +2258,7 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return color_plane == 1;
> > default:
> > return false;
> > @@ -2448,6 +2451,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2497,6 +2501,21 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> > .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line
> > +pair in the
> > + * main surface. And each 64B CCS cache line represents an area of
> > +4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > +dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x
> > +32 pixels in
> > + * the main surface. Additional surface is used to pass the Clear
> > +Color
> > + * structure for the driver to program the DE.
> > + */
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> .cpp
> > += { 4, 1, 0}, .hsub = 2, .vsub = 32, },
>
> I think these last two were supposed to have .has_alpha = true?
Sure will include in the next rev.
>
> > +};
> > +
> > static const struct drm_format_info * lookup_format_info(const
> > struct drm_format_info formats[],
> > int num_formats, u32 format)
> > @@ -2525,6 +2544,10 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
> > return lookup_format_info(gen12_ccs_formats,
> > ARRAY_SIZE(gen12_ccs_formats),
> > cmd->pixel_format);
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return lookup_format_info(gen12_ccs_formats,
> > +
> ARRAY_SIZE(gen12_ccs_cc_formats),
> > + cmd->pixel_format);
> > default:
> > return NULL;
> > }
> > @@ -2534,6 +2557,7 @@ bool is_ccs_modifier(u64 modifier) {
> > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -4120,6
> > +4144,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > /* fall through */
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> > + ICL_PLANE_CTL_CLEAR_COLOR_DISABLE;
>
> I think this needs to be squashed back into the previous patch that added
> general gen12 CCS.
Sure. I will work with DK to get this changes.
>
>
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return PLANE_CTL_TILED_Y |
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> > @@ -9897,9 +9924,13 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
> > case PLANE_CTL_TILED_Y:
> > plane_config->tiling = I915_TILING_Y;
> > if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> > -
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> > - I915_FORMAT_MOD_Y_TILED_CCS;
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + fb->modifier = val &
> > +
> ICL_PLANE_CTL_CLEAR_COLOR_DISABLE ?
> > +
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> > +
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> > + else
> > + fb->modifier =
> I915_FORMAT_MOD_Y_TILED_CCS;
> > else if (val &
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > fb->modifier =
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > else
> > @@ -14322,6 +14353,15 @@ static int intel_plane_pin_fb(struct
> > intel_plane_state *plane_state)
> >
> > plane_state->vma = vma;
> >
> > + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > + u32 *ccaddr =
> kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > + fb-
> >offsets[2] >> PAGE_SHIFT));
> > +
>
> Will this work on framebuffers in stolen memory? Not that it's likely a regular
> BIOS would actually setup compressed framebuffers to begin with...
It is unlikely that BIOS sets up a compressed fb. However FBC could impact as it works with
Stolen memory. I am not sure about the interaction between fbc and render compression
working at the same time. Apart from that I am unable to think of an issue. Will try to figure
out during testing.
>
> > + plane_state->ccval = ((u64)*(ccaddr +
> CC_VAL_HIGHER_OFFSET) << 32)
> > + | *(ccaddr + CC_VAL_LOWER_OFFSET);
>
> Is there more data in the clear color page besides the color itself? If so,
> maybe we should just use a struct to make the memory layout explicit?
According to BSpec: 43854 the first 3 offsets are for the raw color which acts as an input to
3d engine which fills the info in the later 2 offsets in DE compatible format. The other data
Therefore is redundant and cannot be consumed by the DE hence ignoring.
>
> > + kunmap_atomic(ccaddr);
> > + }
> > +
> > return 0;
> > }
> >
> > @@ -15709,6 +15749,7 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> > * tile widths.
> > */
> > if ((fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > + fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
> > i == 0)
> > stride_alignment *= 4;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d5cc4b810d9e..a82695a3e0b8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -579,6 +579,9 @@ struct intel_plane_state {
> > u32 slave;
> >
> > struct drm_intel_sprite_colorkey ckey;
> > +
> > + /* Clear Color Value */
> > + u64 ccval;
> > };
> >
> > struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 1655984955ca..3672e8b9c0bc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> > u32 plane_color_ctl = 0;
> > unsigned long irqflags;
> > u32 keymsk, keymax;
> > + u64 ccval = plane_state->ccval;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >
> > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > icl_program_input_csc(plane, crtc_state, plane_state);
> >
> > + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > + intel_uncore_write64_fw(&dev_priv->uncore,
> > + PLANE_CC_VAL(pipe, plane_id),
> ccval);
> > +
> > skl_write_plane_wm(plane, crtc_state);
> >
> > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@
> > -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS))
> {
> > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> ||
> > + fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
> > return -EINVAL;
> > }
> > @@ -2153,6 +2159,7 @@ static const u64
> > skl_plane_format_modifiers_ccs[] = { static const u64
> gen12_plane_format_modifiers_ccs[] = {
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > I915_FORMAT_MOD_Y_TILED,
> > I915_FORMAT_MOD_X_TILED,
> > DRM_FORMAT_MOD_LINEAR,
> > @@ -2321,6 +2328,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > break;
> > default:
> > return false;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 096be95ec7f9..00c59ed8b114
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6681,6 +6681,7 @@ enum {
> > #define PLANE_CTL_YUV422_VYUY (3 << 16)
> > #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> > #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > +#define ICL_PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13)
>
> Looks like the whitespace is off here.
Will fix it next rev.
Thanks,
RK
>
>
> Matt
>
> > #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /*
> Pre-GLK */
> > #define PLANE_CTL_TILED_MASK (0x7 << 10)
> > #define PLANE_CTL_TILED_LINEAR (0 << 10)
> > @@ -6721,6 +6722,8 @@ enum {
> > #define _PLANE_KEYMAX_1_A 0x701a0
> > #define _PLANE_KEYMAX_2_A 0x702a0
> > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> > +#define _PLANE_CC_VAL_1_A 0x701b4
> > +#define _PLANE_CC_VAL_2_A 0x702b4
> > #define _PLANE_AUX_DIST_1_A 0x701c0
> > #define _PLANE_AUX_DIST_2_A 0x702c0
> > #define _PLANE_AUX_OFFSET_1_A 0x701c4
> > @@ -6760,6 +6763,16 @@ enum {
> > #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> > #define _PLANE_NV12_BUF_CFG_2_A 0x70378
> >
> > +#define _PLANE_CC_VAL_1_B 0x711b4
> > +#define _PLANE_CC_VAL_2_B 0x712b4
> > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B)
> > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B)
> > +#define PLANE_CC_VAL(pipe, plane) \
> > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe),
> _PLANE_CC_VAL_2(pipe))
> > +
> > +#define CC_VAL_LOWER_OFFSET 4
> > +#define CC_VAL_HIGHER_OFFSET 5
> > +
> > /* Input CSC Register Definitions */
> > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> > --
> > 2.20.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-09-19 22:16 ` Sripada, Radhakrishna
@ 2019-09-19 22:38 ` Matt Roper
0 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2019-09-19 22:38 UTC (permalink / raw)
To: Sripada, Radhakrishna
Cc: Chery, Nanley G, intel-gfx, Pandiyan, Dhinakaran, Syrjala, Ville
On Thu, Sep 19, 2019 at 03:16:34PM -0700, Sripada, Radhakrishna wrote:
> Hi Matt,
> > -----Original Message-----
> > From: Roper, Matthew D
> > Sent: Tuesday, September 17, 2019 2:53 PM
> > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> > <dhinakaran.pandiyan@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> > Sharma, Shashank <shashank.sharma@intel.com>; Antognolli, Rafael
> > <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> > Subject: Re: [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL
> > Render Decompression
> >
> > On Tue, Sep 17, 2019 at 05:11:55AM -0700, Radhakrishna Sripada wrote:
> > > Render Decompression is supported with Y-Tiled main surface. The CCS
> > > is linear and has 4 bits of data for each main surface cache line
> > > pair, a ratio of 1:256. Additional Clear Color information is passed
> > > from the user-space through an offset in the GEM BO. Add a new
> > > modifier to identify and parse new Clear Color information and extend
> > > Gen12 render decompression functionality to the newly added modifier.
> > >
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 47 +++++++++++++++++--
> > > .../drm/i915/display/intel_display_types.h | 3 ++
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 10 +++-
> > > drivers/gpu/drm/i915/i915_reg.h | 13 +++++
> > > 4 files changed, 69 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 2da721a6abab..725b9724da49 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int color_plane)
> > > /* fall through */
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > if (color_plane == 1)
> > > return cpp;
> > > /* fall through */
> > > @@ -2051,6 +2052,7 @@ static unsigned int intel_surf_alignment(const
> > struct drm_framebuffer *fb,
> > > return 0;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return 4 * 4 * 1024;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > @@ -2256,6 +2258,7 @@ static bool is_surface_linear(u64 modifier, int
> > color_plane)
> > > return true;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return color_plane == 1;
> > > default:
> > > return false;
> > > @@ -2448,6 +2451,7 @@ static unsigned int
> > intel_fb_modifier_to_tiling(u64 fb_modifier)
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return I915_TILING_Y;
> > > default:
> > > return I915_TILING_NONE;
> > > @@ -2497,6 +2501,21 @@ static const struct drm_format_info
> > gen12_ccs_formats[] = {
> > > .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true }, };
> > >
> > > +/*
> > > + * Gen-12 compression uses 4 bits of CCS data for each cache line
> > > +pair in the
> > > + * main surface. And each 64B CCS cache line represents an area of
> > > +4x1 Y-tiles
> > > + * in the main surface. With 4 byte pixels and each Y-tile having
> > > +dimensions of
> > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x
> > > +32 pixels in
> > > + * the main surface. Additional surface is used to pass the Clear
> > > +Color
> > > + * structure for the driver to program the DE.
> > > + */
> > > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > .cpp = { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > .cpp
> > > += { 4, 1, 0}, .hsub = 2, .vsub = 32, },
> >
> > I think these last two were supposed to have .has_alpha = true?
> Sure will include in the next rev.
>
> >
> > > +};
> > > +
> > > static const struct drm_format_info * lookup_format_info(const
> > > struct drm_format_info formats[],
> > > int num_formats, u32 format)
> > > @@ -2525,6 +2544,10 @@ intel_get_format_info(const struct
> > drm_mode_fb_cmd2 *cmd)
> > > return lookup_format_info(gen12_ccs_formats,
> > > ARRAY_SIZE(gen12_ccs_formats),
> > > cmd->pixel_format);
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + return lookup_format_info(gen12_ccs_formats,
> > > +
> > ARRAY_SIZE(gen12_ccs_cc_formats),
> > > + cmd->pixel_format);
> > > default:
> > > return NULL;
> > > }
> > > @@ -2534,6 +2557,7 @@ bool is_ccs_modifier(u64 modifier) {
> > > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > ||
> > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -4120,6
> > > +4144,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > /* fall through */
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > + return PLANE_CTL_TILED_Y |
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> > > + ICL_PLANE_CTL_CLEAR_COLOR_DISABLE;
> >
> > I think this needs to be squashed back into the previous patch that added
> > general gen12 CCS.
> Sure. I will work with DK to get this changes.
> >
> >
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return PLANE_CTL_TILED_Y |
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > return PLANE_CTL_TILED_Y |
> > PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> > > @@ -9897,9 +9924,13 @@ skylake_get_initial_plane_config(struct
> > intel_crtc *crtc,
> > > case PLANE_CTL_TILED_Y:
> > > plane_config->tiling = I915_TILING_Y;
> > > if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > - fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> > > -
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> > > - I915_FORMAT_MOD_Y_TILED_CCS;
> > > + if (INTEL_GEN(dev_priv) >= 12)
> > > + fb->modifier = val &
> > > +
> > ICL_PLANE_CTL_CLEAR_COLOR_DISABLE ?
> > > +
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> > > +
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> > > + else
> > > + fb->modifier =
> > I915_FORMAT_MOD_Y_TILED_CCS;
> > > else if (val &
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > fb->modifier =
> > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > > else
> > > @@ -14322,6 +14353,15 @@ static int intel_plane_pin_fb(struct
> > > intel_plane_state *plane_state)
> > >
> > > plane_state->vma = vma;
> > >
> > > + if (fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > > + u32 *ccaddr =
> > kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > > + fb-
> > >offsets[2] >> PAGE_SHIFT));
> > > +
> >
> > Will this work on framebuffers in stolen memory? Not that it's likely a regular
> > BIOS would actually setup compressed framebuffers to begin with...
> It is unlikely that BIOS sets up a compressed fb. However FBC could impact as it works with
> Stolen memory. I am not sure about the interaction between fbc and render compression
> working at the same time. Apart from that I am unable to think of an issue. Will try to figure
> out during testing.
My main worry here was that if the BIOS or pre-OS bootloader setup a
framebuffer in stolen memory (which is probably unlikely, but
theoretically possible in some highly specialized embedded
environments), we wouldn't be able to kmap the buffer since stolen
memory isn't accessible by the CPU (i.e., the CPU can only access it
indirectly through the aperture). So if we tried to flip back to a
RC_CCS_CC fb located in stolen memory, the i915_gem_object_get_page()
above would GEM_BUG_ON() because i915_gem_object_stolen_ops.flags
doesn't have I915_GEM_OBJECT_HAS_STRUCT_PAGE.
We don't currently allow direct allocation of framebuffers in stolen
memory, so the only place those can come from is the initial config we
inherit from the BIOS. Probably the simplest way forward is to just
bail out of skylake_get_initial_plane_config() and give up on inheriting
the fb in the very unlikely case we notice that the BIOS is claiming
that render compression + clear color is enabled.
Matt
>
> >
> > > + plane_state->ccval = ((u64)*(ccaddr +
> > CC_VAL_HIGHER_OFFSET) << 32)
> > > + | *(ccaddr + CC_VAL_LOWER_OFFSET);
> >
> > Is there more data in the clear color page besides the color itself? If so,
> > maybe we should just use a struct to make the memory layout explicit?
> According to BSpec: 43854 the first 3 offsets are for the raw color which acts as an input to
> 3d engine which fills the info in the later 2 offsets in DE compatible format. The other data
> Therefore is redundant and cannot be consumed by the DE hence ignoring.
> >
> > > + kunmap_atomic(ccaddr);
> > > + }
> > > +
> > > return 0;
> > > }
> > >
> > > @@ -15709,6 +15749,7 @@ static int intel_framebuffer_init(struct
> > intel_framebuffer *intel_fb,
> > > * tile widths.
> > > */
> > > if ((fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > + fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > > fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
> > > i == 0)
> > > stride_alignment *= 4;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index d5cc4b810d9e..a82695a3e0b8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -579,6 +579,9 @@ struct intel_plane_state {
> > > u32 slave;
> > >
> > > struct drm_intel_sprite_colorkey ckey;
> > > +
> > > + /* Clear Color Value */
> > > + u64 ccval;
> > > };
> > >
> > > struct intel_initial_plane_config {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 1655984955ca..3672e8b9c0bc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> > > u32 plane_color_ctl = 0;
> > > unsigned long irqflags;
> > > u32 keymsk, keymax;
> > > + u64 ccval = plane_state->ccval;
> > >
> > > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > >
> > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > > icl_program_input_csc(plane, crtc_state, plane_state);
> > >
> > > + if (fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > > + intel_uncore_write64_fw(&dev_priv->uncore,
> > > + PLANE_CC_VAL(pipe, plane_id),
> > ccval);
> > > +
> > > skl_write_plane_wm(plane, crtc_state);
> > >
> > > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> > @@
> > > -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct
> > intel_crtc_state *crtc_state,
> > > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS))
> > {
> > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> > ||
> > > + fb->modifier ==
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> > > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> > mode\n");
> > > return -EINVAL;
> > > }
> > > @@ -2153,6 +2159,7 @@ static const u64
> > > skl_plane_format_modifiers_ccs[] = { static const u64
> > gen12_plane_format_modifiers_ccs[] = {
> > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > > I915_FORMAT_MOD_Y_TILED,
> > > I915_FORMAT_MOD_X_TILED,
> > > DRM_FORMAT_MOD_LINEAR,
> > > @@ -2321,6 +2328,7 @@ static bool
> > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > break;
> > > default:
> > > return false;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 096be95ec7f9..00c59ed8b114
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6681,6 +6681,7 @@ enum {
> > > #define PLANE_CTL_YUV422_VYUY (3 << 16)
> > > #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> > > #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > > +#define ICL_PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13)
> >
> > Looks like the whitespace is off here.
> Will fix it next rev.
>
> Thanks,
> RK
> >
> >
> > Matt
> >
> > > #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /*
> > Pre-GLK */
> > > #define PLANE_CTL_TILED_MASK (0x7 << 10)
> > > #define PLANE_CTL_TILED_LINEAR (0 << 10)
> > > @@ -6721,6 +6722,8 @@ enum {
> > > #define _PLANE_KEYMAX_1_A 0x701a0
> > > #define _PLANE_KEYMAX_2_A 0x702a0
> > > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> > > +#define _PLANE_CC_VAL_1_A 0x701b4
> > > +#define _PLANE_CC_VAL_2_A 0x702b4
> > > #define _PLANE_AUX_DIST_1_A 0x701c0
> > > #define _PLANE_AUX_DIST_2_A 0x702c0
> > > #define _PLANE_AUX_OFFSET_1_A 0x701c4
> > > @@ -6760,6 +6763,16 @@ enum {
> > > #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> > > #define _PLANE_NV12_BUF_CFG_2_A 0x70378
> > >
> > > +#define _PLANE_CC_VAL_1_B 0x711b4
> > > +#define _PLANE_CC_VAL_2_B 0x712b4
> > > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A,
> > _PLANE_CC_VAL_1_B)
> > > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A,
> > _PLANE_CC_VAL_2_B)
> > > +#define PLANE_CC_VAL(pipe, plane) \
> > > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe),
> > _PLANE_CC_VAL_2(pipe))
> > > +
> > > +#define CC_VAL_LOWER_OFFSET 4
> > > +#define CC_VAL_HIGHER_OFFSET 5
> > > +
> > > /* Input CSC Register Definitions */
> > > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> > > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> > > --
> > > 2.20.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2019-09-17 12:11 [PATCH 0/6] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 1/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 2/6] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 3/6] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 4/6] drm/i915/tgl: " Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 5/6] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-09-17 12:11 ` [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
2019-09-17 21:52 ` Matt Roper
2019-09-19 22:16 ` Sripada, Radhakrishna
2019-09-19 22:38 ` Matt Roper
2019-09-19 0:53 ` Jordan Justen
2019-09-17 15:05 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support " Patchwork
2019-09-17 15:27 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-18 2:09 ` ✓ Fi.CI.IGT: " Patchwork
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