[CI v2 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

[CI v2 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

[Manasi Navare]

In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.

v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 105 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.h  |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 3 files changed, 112 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c05ba6af6226..dcea0a935952 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11773,6 +11773,91 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
 	return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
 }
 
+static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc,
+				   struct intel_crtc_state *crtc_state,
+				   struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_connector *master_connector, *connector;
+	struct drm_connector_state *connector_state;
+	struct drm_connector_list_iter conn_iter;
+	struct drm_crtc *master_crtc = NULL;
+	struct drm_crtc_state *master_crtc_state;
+	struct intel_crtc_state *master_pipe_config;
+	int i, tile_group_id;
+
+	if (INTEL_GEN(dev_priv) < 11)
+		return 0;
+
+	/*
+	 * In case of tiled displays there could be one or more slaves but there is
+	 * only one master. Lets make the CRTC used by the connector corresponding
+	 * to the last horizonal and last vertical tile a master/genlock CRTC.
+	 * All the other CRTCs corresponding to other tiles of the same Tile group
+	 * are the slave CRTCs and hold a pointer to their genlock CRTC.
+	 */
+	for_each_new_connector_in_state(state, connector, connector_state, i) {
+		if (connector_state->crtc != crtc)
+			continue;
+		if (!connector->has_tile)
+			continue;
+		if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+		    crtc_state->base.mode.vdisplay != connector->tile_v_size)
+			return 0;
+		if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+		    connector->tile_v_loc == connector->num_v_tile - 1)
+			continue;
+		crtc_state->sync_mode_slaves_mask = 0;
+		tile_group_id = connector->tile_group->id;
+		drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+		drm_for_each_connector_iter(master_connector, &conn_iter) {
+			struct drm_connector_state *master_conn_state = NULL;
+
+			if (!master_connector->has_tile)
+				continue;
+			if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
+			    master_connector->tile_v_loc != master_connector->num_v_tile - 1)
+				continue;
+			if (master_connector->tile_group->id != tile_group_id)
+				continue;
+
+			master_conn_state = drm_atomic_get_connector_state(state,
+									   master_connector);
+			if (IS_ERR(master_conn_state)) {
+				drm_connector_list_iter_end(&conn_iter);
+				return PTR_ERR(master_conn_state);
+			}
+			if (master_conn_state->crtc) {
+				master_crtc = master_conn_state->crtc;
+				break;
+			}
+		}
+		drm_connector_list_iter_end(&conn_iter);
+
+		if (!master_crtc) {
+			DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
+				      connector_state->crtc->base.id);
+			return -EINVAL;
+		}
+
+		master_crtc_state = drm_atomic_get_crtc_state(state,
+							      master_crtc);
+		if (IS_ERR(master_crtc_state))
+			return PTR_ERR(master_crtc_state);
+
+		master_pipe_config = to_intel_crtc_state(master_crtc_state);
+		crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
+		master_pipe_config->sync_mode_slaves_mask |=
+			BIT(crtc_state->cpu_transcoder);
+		DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
+			      transcoder_name(crtc_state->master_transcoder),
+			      crtc_state->base.crtc->base.id,
+			      master_pipe_config->sync_mode_slaves_mask);
+	}
+
+	return 0;
+}
+
 static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
 				   struct drm_crtc_state *_crtc_state)
 {
@@ -12276,6 +12361,12 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 	if (IS_G4X(dev_priv) ||
 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		saved_state->wm = crtc_state->wm;
+	/* Save the slave bitmask which gets filled for master crtc state during
+	 * slave atomic check call.
+	 */
+	if (is_trans_port_sync_master(dev_priv, crtc_state))
+		saved_state->sync_mode_slaves_mask =
+			crtc_state->sync_mode_slaves_mask;
 
 	/* Keep base drm_crtc_state intact, only clear our extended struct */
 	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
@@ -12369,6 +12460,15 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
 			      CRTC_STEREO_DOUBLE);
 
+	/* Set the crtc_state defaults for trans_port_sync */
+	pipe_config->master_transcoder = INVALID_TRANSCODER;
+	ret = icl_add_sync_mode_crtcs(crtc, pipe_config, state);
+	if (ret) {
+		DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
+			      ret);
+		return ret;
+	}
+
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
 	 * adjust it according to limitations or connector properties, and also
 	 * a chance to reject the mode entirely.
@@ -12882,6 +12982,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
 	PIPE_CONF_CHECK_INFOFRAME(drm);
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
+		PIPE_CONF_CHECK_I(master_transcoder);
+	}
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_BOOL
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b1ae0e59c715..f303009c0170 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -93,6 +93,7 @@ enum pipe {
 #define pipe_name(p) ((p) + 'A')
 
 enum transcoder {
+	INVALID_TRANSCODER = -1,
 	/*
 	 * The following transcoders have a 1:1 transcoder -> pipe mapping,
 	 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..17ff34ca298b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -991,6 +991,12 @@ struct intel_crtc_state {
 
 	/* Forward Error correction State */
 	bool fec_enable;
+
+	/* Pointer to master transcoder in case of tiled displays */
+	enum transcoder master_transcoder;
+
+	/* Bitmask to indicate slaves attached */
+	u8 sync_mode_slaves_mask;
 };
 
 struct intel_crtc {
-- 
2.19.1

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[CI v2 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports

[Manasi Navare]

In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave transcoder
and the master transcoder is unaware that it is operating
in this mode.
This has been tested with tiled display connected to ICL.

v5:
* Add TRANSCODER_D case and MISSING_CASE (Maarten)
v4:
Rebase
v3:
* Check of DP_MST moved to atomic_check (Maarten)
v2:
* Do not use RMW, just write to the register in commit (Jani N)

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dcea0a935952..7d4a33db5ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4408,6 +4408,49 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
 	I915_WRITE(PIPE_CHICKEN(pipe), tmp);
 }
 
+static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 trans_ddi_func_ctl2_val;
+	u8 master_select;
+
+	/*
+	 * Configure the master select and enable Transcoder Port Sync for
+	 * Slave CRTCs transcoder.
+	 */
+	if (crtc_state->master_transcoder == INVALID_TRANSCODER)
+		return;
+
+	switch (crtc_state->master_transcoder) {
+	case TRANSCODER_A:
+		master_select = 1;
+		break;
+	case TRANSCODER_B:
+		master_select = 2;
+		break;
+	case TRANSCODER_C:
+		master_select = 3;
+		break;
+	case TRANSCODER_D:
+		master_select = 4;
+		break;
+	case TRANSCODER_EDP:
+	default:
+		MISSING_CASE(crtc_state->master_transcoder);
+		master_select = 0;
+	}
+	/* Set the master select bits for Tranascoder Port Sync */
+	trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
+				   PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
+		PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+	/* Enable Transcoder Port Sync */
+	trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
+
+	I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
+		   trans_ddi_func_ctl2_val);
+}
+
 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
 				     const struct intel_crtc_state *new_crtc_state)
 {
@@ -6476,6 +6519,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_set_pipe_timings(pipe_config);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_enable_trans_port_sync(pipe_config);
+
 	intel_set_pipe_src_size(pipe_config);
 
 	if (cpu_transcoder != TRANSCODER_EDP &&
-- 
2.19.1

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[CI v2 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config

[Manasi Navare]

After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.

v3:
* Add TRANSCODER_D (Maarten)
v2:
* Add Transcoder_D and MISSING_CASE (Maarten)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 49 ++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d4a33db5ebc..877df39b8fa3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10452,6 +10452,52 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 	}
 }
 
+static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
+					       struct intel_crtc_state *pipe_config)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 trans_port_sync, transcoders, master_select;
+	enum transcoder cpu_transcoder;
+
+	trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(pipe_config->cpu_transcoder));
+	if (trans_port_sync & PORT_SYNC_MODE_ENABLE) {
+		master_select = trans_port_sync &
+			PORT_SYNC_MODE_MASTER_SELECT_MASK;
+		switch (master_select) {
+		case 1:
+			pipe_config->master_transcoder = TRANSCODER_A;
+			break;
+		case 2:
+			pipe_config->master_transcoder = TRANSCODER_B;
+			break;
+		case 3:
+			pipe_config->master_transcoder = TRANSCODER_C;
+			break;
+		case 4:
+			pipe_config->master_transcoder = TRANSCODER_D;
+			break;
+		default:
+			MISSING_CASE(master_select);
+		}
+
+		pipe_config->sync_mode_slaves_mask = 0;
+	} else {
+		pipe_config->master_transcoder = INVALID_TRANSCODER;
+
+		transcoders = BIT(TRANSCODER_A) |
+			BIT(TRANSCODER_B) |
+			BIT(TRANSCODER_C) |
+			BIT(TRANSCODER_D);
+		for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+			trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+			if (trans_port_sync & PORT_SYNC_MODE_ENABLE)
+				pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder);
+		}
+	}
+}
+
 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 				    struct intel_crtc_state *pipe_config)
 {
@@ -10548,6 +10594,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier = 1;
 	}
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icelake_get_trans_port_sync_config(crtc, pipe_config);
+
 out:
 	for_each_power_domain(power_domain, power_domain_mask)
 		intel_display_power_put(dev_priv,
-- 
2.19.1

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[CI v2 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync

[Manasi Navare]

As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.

v6:
* Modeset implies active_changed, remove one condition (Maarten)
v5:
* Fix checkpatch warning (Manasi)
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_display.c | 159 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.h |   4 +
 3 files changed, 162 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..62e9f5602b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3347,7 +3347,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
 					      true);
 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
 	intel_dp_start_link_train(intel_dp);
-	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+	if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+	    !is_trans_port_sync_mode(dev_priv, crtc_state))
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 877df39b8fa3..ef5a4921619e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
 	return drm_atomic_crtc_needs_modeset(&state->base);
 }
 
+bool
+is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
+			const struct intel_crtc_state *state)
+{
+	return (INTEL_GEN(dev_priv) >= 11 &&
+		(state->master_transcoder != INVALID_TRANSCODER ||
+		 state->sync_mode_slaves_mask));
+}
+
+static bool
+is_trans_port_sync_master(struct drm_i915_private *dev_priv,
+			  const struct intel_crtc_state *state)
+{
+	return (INTEL_GEN(dev_priv) >= 11 &&
+		(state->master_transcoder == INVALID_TRANSCODER &&
+		 state->sync_mode_slaves_mask));
+}
+
 /*
  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -13890,6 +13908,30 @@ static void intel_update_crtc(struct intel_crtc *crtc,
 	intel_finish_crtc_commit(state, crtc);
 }
 
+static struct intel_crtc *intel_get_slave_crtc(struct drm_i915_private *dev_priv,
+					       struct intel_crtc_state *new_crtc_state)
+{
+	if (new_crtc_state->sync_mode_slaves_mask &
+	    BIT(TRANSCODER_A))
+		return intel_get_crtc_for_pipe(dev_priv,
+					       PIPE_A);
+	else if (new_crtc_state->sync_mode_slaves_mask &
+		 BIT(TRANSCODER_B))
+		return intel_get_crtc_for_pipe(dev_priv,
+					       PIPE_B);
+	else if (new_crtc_state->sync_mode_slaves_mask &
+		 BIT(TRANSCODER_C))
+		return intel_get_crtc_for_pipe(dev_priv,
+					       PIPE_C);
+	else if (new_crtc_state->sync_mode_slaves_mask &
+		 BIT(TRANSCODER_D))
+		return intel_get_crtc_for_pipe(dev_priv,
+					       PIPE_D);
+	/* should never happen */
+	WARN_ON(1);
+	return NULL;
+}
+
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 					  struct intel_crtc_state *old_crtc_state,
 					  struct intel_crtc_state *new_crtc_state,
@@ -13968,6 +14010,104 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
 	}
 }
 
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+					      struct intel_atomic_state *state,
+					      struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+	update_scanline_offset(new_crtc_state);
+	dev_priv->display.crtc_enable(new_crtc_state, state);
+	intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+				       struct intel_atomic_state *state)
+{
+	struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
+	struct intel_dp *intel_dp;
+	int i;
+
+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+		if (conn_state->crtc == &crtc->base)
+			break;
+	}
+	intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
+	intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+					   struct intel_atomic_state *state,
+					   struct intel_crtc_state *old_crtc_state,
+					   struct intel_crtc_state *new_crtc_state)
+{
+	struct intel_plane_state *new_plane_state =
+		intel_atomic_get_new_plane_state(state,
+						 to_intel_plane(crtc->base.primary));
+
+	if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
+		intel_fbc_disable(crtc);
+	else if (new_plane_state)
+		intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
+
+	intel_begin_crtc_commit(state, crtc);
+	skl_update_planes_on_crtc(state, crtc);
+	intel_finish_crtc_commit(state, crtc);
+}
+
+static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
+					       struct intel_atomic_state *state,
+					       struct intel_crtc_state *old_crtc_state,
+					       struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+							     new_crtc_state);
+	struct intel_crtc_state *new_slave_crtc_state =
+		intel_atomic_get_new_crtc_state(state, slave_crtc);
+	struct intel_crtc_state *old_slave_crtc_state =
+		intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+	WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+		!old_slave_crtc_state);
+
+	DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
+		      crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
+		      slave_crtc->base.name);
+
+	/* Enable seq for slave with with DP_TP_CTL left Idle until the
+	 * master is ready
+	 */
+	intel_crtc_enable_trans_port_sync(slave_crtc,
+					  state,
+					  new_slave_crtc_state);
+
+	/* Enable seq for master with with DP_TP_CTL left Idle */
+	intel_crtc_enable_trans_port_sync(crtc,
+					  state,
+					  new_crtc_state);
+
+	/* Set Slave's DP_TP_CTL to Normal */
+	intel_set_dp_tp_ctl_normal(slave_crtc,
+				   state);
+
+	/* Set Master's DP_TP_CTL To Normal */
+	usleep_range(200, 400);
+	intel_set_dp_tp_ctl_normal(crtc,
+				   state);
+
+	/* Now do the post crtc enable for all master and slaves */
+	intel_post_crtc_enable_updates(slave_crtc,
+				       state,
+				       new_slave_crtc_state,
+				       old_slave_crtc_state);
+	intel_post_crtc_enable_updates(crtc,
+				       state,
+				       new_crtc_state,
+				       old_crtc_state);
+}
+
 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14002,6 +14142,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 			bool vbl_wait = false;
 			unsigned int cmask = drm_crtc_mask(&crtc->base);
+			bool modeset = needs_modeset(new_crtc_state);
 
 			pipe = crtc->pipe;
 
@@ -14024,12 +14165,24 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 			 */
 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
 						 &old_crtc_state->wm.skl.ddb) &&
-			    !new_crtc_state->base.active_changed &&
+			    !modeset &&
 			    state->wm_results.dirty_pipes != updated)
 				vbl_wait = true;
 
-			intel_update_crtc(crtc, state, old_crtc_state,
-					  new_crtc_state);
+			if (modeset && is_trans_port_sync_mode(dev_priv,
+							       new_crtc_state)) {
+				if (is_trans_port_sync_master(dev_priv,
+							      new_crtc_state))
+					intel_update_trans_port_sync_crtcs(crtc,
+									   state,
+									   old_crtc_state,
+									   new_crtc_state);
+				else
+					continue;
+			} else {
+				intel_update_crtc(crtc, state, old_crtc_state,
+						  new_crtc_state);
+			}
 
 			if (vbl_wait)
 				intel_wait_for_vblank(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index f303009c0170..efa4d62514ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,6 +27,7 @@
 
 #include <drm/drm_util.h>
 #include <drm/i915_drm.h>
+#include "intel_dp_link_training.h"
 
 enum link_m_n_set;
 struct dpll;
@@ -54,6 +55,7 @@ struct intel_plane;
 struct intel_plane_state;
 struct intel_remapped_info;
 struct intel_rotation_info;
+struct intel_crtc_state;
 
 enum i915_gpio {
 	GPIOA,
@@ -454,6 +456,8 @@ enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 				const struct drm_display_mode *mode);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
+bool is_trans_port_sync_mode(struct drm_i915_private *i915,
+			     const struct intel_crtc_state *state);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
-- 
2.19.1

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[CI v2 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence

[Manasi Navare]

This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().

v2:
* Directly write the trans_port_sync reg value (Maarten)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef5a4921619e..45eea11b0853 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4469,6 +4469,25 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
 		   trans_ddi_func_ctl2_val);
 }
 
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	i915_reg_t reg;
+	u32 trans_ddi_func_ctl2_val;
+
+	if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+		return;
+
+	DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+		      transcoder_name(old_crtc_state->cpu_transcoder));
+
+	reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+	trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
+				    PORT_SYNC_MODE_MASTER_SELECT_MASK);
+	I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
 				     const struct intel_crtc_state *new_crtc_state)
 {
@@ -6718,6 +6737,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_disable_transcoder_port_sync(old_crtc_state);
+
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_disable_transcoder_func(old_crtc_state);
 
-- 
2.19.1

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[CI v2 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master

[Manasi Navare]

In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.

v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++++++++++--
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 45eea11b0853..2e804312f1ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13989,8 +13989,42 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 						     new_crtc_state);
 }
 
+static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
+						   struct intel_crtc *crtc,
+						   struct intel_crtc_state *old_crtc_state,
+						   struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+							     new_crtc_state);
+	struct intel_crtc_state *new_slave_crtc_state =
+		intel_atomic_get_new_crtc_state(state, slave_crtc);
+	struct intel_crtc_state *old_slave_crtc_state =
+		intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+	WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+		!old_slave_crtc_state);
+
+	/* Disable Slave first */
+	intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+	if (old_slave_crtc_state->base.active)
+		intel_old_crtc_state_disables(state,
+					      old_slave_crtc_state,
+					      new_slave_crtc_state,
+					      slave_crtc);
+
+	/* Disable Master */
+	intel_pre_plane_update(old_crtc_state, new_crtc_state);
+	if (old_crtc_state->base.active)
+		intel_old_crtc_state_disables(state,
+					      old_crtc_state,
+					      new_crtc_state,
+					      crtc);
+}
+
 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 {
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
@@ -14007,13 +14041,29 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		if (!needs_modeset(new_crtc_state))
 			continue;
 
-		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		/* In case of Transcoder port Sync master slave CRTCs can be
+		 * assigned in any order and we need to make sure that
+		 * slave CRTCs are disabled first and then master CRTC since
+		 * Slave vblanks are masked till Master Vblanks.
+		 */
+		if (is_trans_port_sync_mode(dev_priv, new_crtc_state)) {
+			if (is_trans_port_sync_master(dev_priv,
+						      new_crtc_state))
+				intel_trans_port_sync_modeset_disables(state,
+								       crtc,
+								       old_crtc_state,
+								       new_crtc_state);
+			else
+				continue;
+		} else {
+			intel_pre_plane_update(old_crtc_state, new_crtc_state);
 
-		if (old_crtc_state->base.active)
-			intel_old_crtc_state_disables(state,
-						      old_crtc_state,
-						      new_crtc_state,
-						      crtc);
+			if (old_crtc_state->base.active)
+				intel_old_crtc_state_disables(state,
+							      old_crtc_state,
+							      new_crtc_state,
+							      crtc);
+		}
 	}
 }
 
-- 
2.19.1

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✗ Fi.CI.SPARSE: warning for series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
URL   : https://patchwork.freedesktop.org/series/66956/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0

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✗ Fi.CI.BAT: failure for series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
URL   : https://patchwork.freedesktop.org/series/66956/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14467
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14467 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14467, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14467:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@basic-flip-a:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@kms_busy@basic-flip-a.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/fi-icl-u3/igt@kms_busy@basic-flip-a.html
    - fi-icl-u2:          [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u2/igt@kms_busy@basic-flip-a.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/fi-icl-u2/igt@kms_busy@basic-flip-a.html

  
Known issues
------------

  Here are the changes found in Patchwork_14467 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-process:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@gem_close_race@basic-process.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/fi-icl-u3/igt@gem_close_race@basic-process.html

  
#### Possible fixes ####

  * igt@gem_cpu_reloc@basic:
    - fi-bxt-dsi:         [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-bxt-dsi/igt@gem_cpu_reloc@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/fi-bxt-dsi/igt@gem_cpu_reloc@basic.html

  * igt@gem_render_linear_blits@basic:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@gem_render_linear_blits@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/fi-icl-u3/igt@gem_render_linear_blits@basic.html

  
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6925 -> Patchwork_14467

  CI-20190529: 20190529
  CI_DRM_6925: ccd2c9cb3fd35f9654cdf6743bdecfb489fba70a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5193: 924e5c59dbb82938e743efd6b0812eeb5760b70d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14467: a9f7c227d65a27fc1728da1939771ae43fc11788 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a9f7c227d65a drm/i915/display/icl: In port sync mode disable slaves first then master
76716232759c drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
068522385605 drm/i915/display/icl: Enable master-slaves in trans port sync
3e6425595cb8 drm/i915/display/icl: HW state readout for transcoder port sync config
d73535487771 drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
f1311b5bbb45 drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14467/index.html
_______________________________________________
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✗ Fi.CI.SPARSE: warning for series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL   : https://patchwork.freedesktop.org/series/66956/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0

_______________________________________________
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✗ Fi.CI.BAT: failure for series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL   : https://patchwork.freedesktop.org/series/66956/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6929 -> Patchwork_14481
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14481 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14481, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14481:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@basic-flip-a:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-icl-u3/igt@kms_busy@basic-flip-a.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-icl-u3/igt@kms_busy@basic-flip-a.html
    - fi-icl-u2:          NOTRUN -> [DMESG-WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-icl-u2/igt@kms_busy@basic-flip-a.html

  
Known issues
------------

  Here are the changes found in Patchwork_14481 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-write:
    - fi-icl-u3:          [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-icl-u2:          [INCOMPLETE][6] ([fdo#107713] / [fdo#111381]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
    - fi-bxt-dsi:         [INCOMPLETE][8] ([fdo#103927] / [fdo#111381]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledy:
    - fi-icl-u3:          [DMESG-WARN][10] ([fdo#107724]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][12] ([fdo#111407]) -> [FAIL][13] ([fdo#111045] / [fdo#111096])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6929/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (55 -> 47)
------------------------------

  Missing    (8): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6929 -> Patchwork_14481

  CI-20190529: 20190529
  CI_DRM_6929: fceeceeb45e97b2e6e635c0e4459e4217f9f35a4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5195: ea29372bb4e261a0a8da371a1f434131750f18e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14481: dec0139687417a2aae3f1cc79f81282f1d34817a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

dec013968741 drm/i915/display/icl: In port sync mode disable slaves first then master
fb75692e7764 drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
92d6d741851b drm/i915/display/icl: Enable master-slaves in trans port sync
91d5494eec0a drm/i915/display/icl: HW state readout for transcoder port sync config
a8e0571f3ea6 drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
46735a5193f0 drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14481/index.html
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