* [PATCH v9 01/10] drm/i915/dsb: feature flag added for display state buffer.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 02/10] drm/i915/dsb: DSB context creation Animesh Manna
` (12 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4faec2f94e19..84b9b138d7ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1863,6 +1863,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d4c288860aed..0cdc2465534b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 02/10] drm/i915/dsb: DSB context creation.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
2019-09-20 11:59 ` [PATCH v9 01/10] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-23 7:37 ` Jani Nikula
2019-09-20 11:59 ` [PATCH v9 03/10] drm/i915/dsb: single register write function for DSB Animesh Manna
` (11 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
v4: for simplification and based on current usage added single dsb
object in intel_crtc. (Shashank)
v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
v6:
- refcount machanism added.
- Used atomic_add_return and atomic_dec_and_test instead of
atomic_inc and atomic_dec. (Jani)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 80 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 116 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..49c902b00484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1033,6 +1033,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index 000000000000..2ed277670f15
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_dsb *dsb = &crtc->dsb;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_DSB(i915))
+ return dsb;
+
+ if (atomic_add_return(1, &dsb->refcount) != 1)
+ return dsb;
+
+ dsb->id = DSB1;
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Gem object creation failed\n");
+ goto err;
+ }
+
+ mutex_lock(&i915->drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ i915_vma_unpin_and_release(&vma, 0);
+ dsb->cmd_buf = NULL;
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!HAS_DSB(i915))
+ return;
+
+ if (WARN_ON(atomic_read(&dsb->refcount) == 0))
+ return;
+
+ if (atomic_dec_and_test(&dsb->refcount)) {
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_gem_object_unpin_map(dsb->vma->obj);
+ i915_vma_unpin_and_release(&dsb->vma, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
+ dsb->cmd_buf = NULL;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
new file mode 100644
index 000000000000..2c0f60c5f66c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+ INVALID_DSB = -1,
+ DSB1,
+ DSB2,
+ DSB3,
+ MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+ atomic_t refcount;
+ enum dsb_id id;
+ u32 *cmd_buf;
+ struct i915_vma *vma;
+};
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc);
+void intel_dsb_put(struct intel_dsb *dsb);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84b9b138d7ac..07f1e89a55ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
+#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v9 02/10] drm/i915/dsb: DSB context creation.
2019-09-20 11:59 ` [PATCH v9 02/10] drm/i915/dsb: DSB context creation Animesh Manna
@ 2019-09-23 7:37 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2019-09-23 7:37 UTC (permalink / raw)
To: Animesh Manna, intel-gfx; +Cc: Michel Thierry
On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> This patch adds a function, which will internally get the gem buffer
> for DSB engine. The GEM buffer is from global GTT, and is mapped into
> CPU domain, contains the data + opcode to be feed to DSB engine.
>
> v1: Initial version.
>
> v2:
> - removed some unwanted code. (Chris)
> - Used i915_gem_object_create_internal instead of _shmem. (Chris)
> - cmd_buf_tail removed and can be derived through vma object. (Chris)
>
> v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
>
> v4: for simplification and based on current usage added single dsb
> object in intel_crtc. (Shashank)
>
> v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
>
> v6:
> - refcount machanism added.
> - Used atomic_add_return and atomic_dec_and_test instead of
> atomic_inc and atomic_dec. (Jani)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 80 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 5 files changed, 116 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 658b930d34a8..6313e7b4bd78 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -172,6 +172,7 @@ i915-y += \
> display/intel_display_power.o \
> display/intel_dpio_phy.o \
> display/intel_dpll_mgr.o \
> + display/intel_dsb.o \
> display/intel_fbc.o \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..49c902b00484 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1033,6 +1033,9 @@ struct intel_crtc {
>
> /* scalers available on this crtc */
> int num_scalers;
> +
> + /* per pipe DSB related info */
> + struct intel_dsb dsb;
> };
>
> struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> new file mode 100644
> index 000000000000..2ed277670f15
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +
> +#define DSB_BUF_SIZE (2 * PAGE_SIZE)
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct intel_dsb *dsb = &crtc->dsb;
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + intel_wakeref_t wakeref;
> +
> + if (!HAS_DSB(i915))
> + return dsb;
> +
> + if (atomic_add_return(1, &dsb->refcount) != 1)
> + return dsb;
> +
> + dsb->id = DSB1;
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> +
> + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> + if (IS_ERR(obj)) {
> + DRM_ERROR("Gem object creation failed\n");
> + goto err;
> + }
> +
> + mutex_lock(&i915->drm.struct_mutex);
> + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
> + mutex_unlock(&i915->drm.struct_mutex);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("Vma creation failed\n");
> + i915_gem_object_put(obj);
> + atomic_dec(&dsb->refcount);
> + goto err;
> + }
> +
> + dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> + if (IS_ERR(dsb->cmd_buf)) {
> + DRM_ERROR("Command buffer creation failed\n");
> + i915_vma_unpin_and_release(&vma, 0);
> + dsb->cmd_buf = NULL;
> + atomic_dec(&dsb->refcount);
> + goto err;
> + }
> + dsb->vma = vma;
> +
> +err:
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> + return dsb;
> +}
> +
> +void intel_dsb_put(struct intel_dsb *dsb)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + if (!HAS_DSB(i915))
> + return;
> +
> + if (WARN_ON(atomic_read(&dsb->refcount) == 0))
> + return;
> +
> + if (atomic_dec_and_test(&dsb->refcount)) {
> + mutex_lock(&i915->drm.struct_mutex);
> + i915_gem_object_unpin_map(dsb->vma->obj);
> + i915_vma_unpin_and_release(&dsb->vma, 0);
> + mutex_unlock(&i915->drm.struct_mutex);
> + dsb->cmd_buf = NULL;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> new file mode 100644
> index 000000000000..2c0f60c5f66c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef _INTEL_DSB_H
> +#define _INTEL_DSB_H
> +
> +struct intel_crtc;
> +struct i915_vma;
> +
> +enum dsb_id {
> + INVALID_DSB = -1,
> + DSB1,
> + DSB2,
> + DSB3,
> + MAX_DSB_PER_PIPE
> +};
> +
> +struct intel_dsb {
> + atomic_t refcount;
> + enum dsb_id id;
> + u32 *cmd_buf;
atomic_t and u32 required #include <linux/types.h> here, added while
applying.
Please consider using DRM_I915_WERROR=y config option while developing.
BR,
Jani.
> + struct i915_vma *vma;
> +};
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc);
> +void intel_dsb_put(struct intel_dsb *dsb);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 84b9b138d7ac..07f1e89a55ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -67,6 +67,7 @@
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> #include "display/intel_dpll_mgr.h"
> +#include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v9 03/10] drm/i915/dsb: single register write function for DSB.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
2019-09-20 11:59 ` [PATCH v9 01/10] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-09-20 11:59 ` [PATCH v9 02/10] drm/i915/dsb: DSB context creation Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 04/10] drm/i915/dsb: Indexed " Animesh Manna
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
v4: macro of indexed-write is moved. (Shashank)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 29 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++++++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2ed277670f15..f94cd6dc98b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,12 @@
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_BYTE_EN 0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -76,5 +82,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(&dsb->vma, 0);
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 2c0f60c5f66c..0686d67b34d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -22,10 +24,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+ * free_pos will point the first free entry position
+ * and help in calculating tail of command buffer.
+ */
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (2 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 03/10] drm/i915/dsb: single register write function for DSB Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 12:18 ` Jani Nikula
2019-09-20 11:59 ` [PATCH v9 05/10] drm/i915/dsb: Check DSB engine status Animesh Manna
` (9 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code comment. (Shashank)
v4: cosmetic changes done. (Shashank)
v5: reset ins_start_offset. (Jani)
v6: update ins_start_offset in inel_dsb_reg_write.
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index f94cd6dc98b6..faa853b08458 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -12,8 +12,10 @@
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_BYTE_EN 0xF
#define DSB_BYTE_EN_SHIFT 20
+#define DSB_REG_VALUE_MASK 0xfffff
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+ u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
+ }
+
+ /*
+ * For example the buffer will look like below for 3 dwords for auto
+ * increment register:
+ * +--------------------------------------------------------+
+ * | size = 3 | offset &| value1 | value2 | value3 | zero |
+ * | | opcode | | | | |
+ * +--------------------------------------------------------+
+ * + + + + + + +
+ * 0 4 8 12 16 20 24
+ * Byte
+ *
+ * As every instruction is 8 byte aligned the index of dsb instruction
+ * will start always from even number while dealing with u32 array. If
+ * we are writing odd no of dwords, Zeros will be added in the end for
+ * padding.
+ */
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ dsb->ins_start_offset = dsb->free_pos;
+
+ /* Update the size. */
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
return;
}
+ dsb->ins_start_offset = dsb->free_pos;
buf[dsb->free_pos++] = val;
buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 0686d67b34d5..2ae22f7309a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -30,11 +30,20 @@ struct intel_dsb {
* and help in calculating tail of command buffer.
*/
int free_pos;
+
+ /*
+ * ins_start_offset will help to store start address of the dsb
+ * instuction and help in identifying the batch of auto-increment
+ * register.
+ */
+ u32 ins_start_offset;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+ u32 val);
#endif
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
2019-09-20 11:59 ` [PATCH v9 04/10] drm/i915/dsb: Indexed " Animesh Manna
@ 2019-09-20 12:18 ` Jani Nikula
2019-09-20 15:58 ` Animesh Manna
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2019-09-20 12:18 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by using ALIGN(). (Chris)
> v3: ascii table added as code comment. (Shashank)
> v4: cosmetic changes done. (Shashank)
> v5: reset ins_start_offset. (Jani)
> v6: update ins_start_offset in inel_dsb_reg_write.
>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index f94cd6dc98b6..faa853b08458 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -12,8 +12,10 @@
> /* DSB opcodes. */
> #define DSB_OPCODE_SHIFT 24
> #define DSB_OPCODE_MMIO_WRITE 0x1
> +#define DSB_OPCODE_INDEXED_WRITE 0x9
> #define DSB_BYTE_EN 0xF
> #define DSB_BYTE_EN_SHIFT 20
> +#define DSB_REG_VALUE_MASK 0xfffff
>
> struct intel_dsb *
> intel_dsb_get(struct intel_crtc *crtc)
> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
> mutex_unlock(&i915->drm.struct_mutex);
> dsb->cmd_buf = NULL;
> dsb->free_pos = 0;
> + dsb->ins_start_offset = 0;
> }
> }
>
> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> + u32 val)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 *buf = dsb->cmd_buf;
> + u32 reg_val;
> +
> + if (!buf) {
> + I915_WRITE(reg, val);
> + return;
> + }
> +
> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
> + DRM_DEBUG_KMS("DSB buffer overflow\n");
> + return;
> + }
> +
> + /*
> + * For example the buffer will look like below for 3 dwords for auto
> + * increment register:
> + * +--------------------------------------------------------+
> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
> + * | | opcode | | | | |
> + * +--------------------------------------------------------+
> + * + + + + + + +
> + * 0 4 8 12 16 20 24
> + * Byte
> + *
> + * As every instruction is 8 byte aligned the index of dsb instruction
> + * will start always from even number while dealing with u32 array. If
> + * we are writing odd no of dwords, Zeros will be added in the end for
> + * padding.
> + */
> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
> + if (reg_val != i915_mmio_reg_offset(reg)) {
> + /* Every instruction should be 8 byte aligned. */
> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +
> + dsb->ins_start_offset = dsb->free_pos;
> +
> + /* Update the size. */
> + buf[dsb->free_pos++] = 1;
> +
> + /* Update the opcode and reg. */
> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
> + DSB_OPCODE_SHIFT) |
> + i915_mmio_reg_offset(reg);
> +
> + /* Update the value. */
> + buf[dsb->free_pos++] = val;
> + } else {
> + /* Update the new value. */
> + buf[dsb->free_pos++] = val;
> +
> + /* Update the size. */
> + buf[dsb->ins_start_offset]++;
> + }
> +
> + /* if number of data words is odd, then the last dword should be 0.*/
> + if (dsb->free_pos & 0x1)
> + buf[dsb->free_pos] = 0;
> +}
> +
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> {
> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> @@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> return;
> }
>
> + dsb->ins_start_offset = dsb->free_pos;
Okay, I'm being a pedant, but that's kind of part of the job
description, I'm afraid.
What if:
intel_dsb_get()
intel_dsb_reg_write(dsb, FOO, 0);
intel_dsb_indexed_reg_write(dsb, FOO, 0);
intel_dsb_commit()
intel_dsb_put()
BR,
Jani.
> buf[dsb->free_pos++] = val;
> buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 0686d67b34d5..2ae22f7309a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -30,11 +30,20 @@ struct intel_dsb {
> * and help in calculating tail of command buffer.
> */
> int free_pos;
> +
> + /*
> + * ins_start_offset will help to store start address of the dsb
> + * instuction and help in identifying the batch of auto-increment
> + * register.
> + */
> + u32 ins_start_offset;
> };
>
> struct intel_dsb *
> intel_dsb_get(struct intel_crtc *crtc);
> void intel_dsb_put(struct intel_dsb *dsb);
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> + u32 val);
>
> #endif
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
2019-09-20 12:18 ` Jani Nikula
@ 2019-09-20 15:58 ` Animesh Manna
2019-09-23 7:35 ` Jani Nikula
0 siblings, 1 reply; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 15:58 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 9/20/2019 5:48 PM, Jani Nikula wrote:
> On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> DSB can program large set of data through indexed register write
>> (opcode 0x9) in one shot. DSB feature can be used for bulk register
>> programming e.g. gamma lut programming, HDR meta data programming.
>>
>> v1: initial version.
>> v2: simplified code by using ALIGN(). (Chris)
>> v3: ascii table added as code comment. (Shashank)
>> v4: cosmetic changes done. (Shashank)
>> v5: reset ins_start_offset. (Jani)
>> v6: update ins_start_offset in inel_dsb_reg_write.
>>
>> Cc: Shashank Sharma <shashank.sharma@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++
>> 2 files changed, 77 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index f94cd6dc98b6..faa853b08458 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -12,8 +12,10 @@
>> /* DSB opcodes. */
>> #define DSB_OPCODE_SHIFT 24
>> #define DSB_OPCODE_MMIO_WRITE 0x1
>> +#define DSB_OPCODE_INDEXED_WRITE 0x9
>> #define DSB_BYTE_EN 0xF
>> #define DSB_BYTE_EN_SHIFT 20
>> +#define DSB_REG_VALUE_MASK 0xfffff
>>
>> struct intel_dsb *
>> intel_dsb_get(struct intel_crtc *crtc)
>> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
>> mutex_unlock(&i915->drm.struct_mutex);
>> dsb->cmd_buf = NULL;
>> dsb->free_pos = 0;
>> + dsb->ins_start_offset = 0;
>> }
>> }
>>
>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>> + u32 val)
>> +{
>> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + u32 *buf = dsb->cmd_buf;
>> + u32 reg_val;
>> +
>> + if (!buf) {
>> + I915_WRITE(reg, val);
>> + return;
>> + }
>> +
>> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
>> + DRM_DEBUG_KMS("DSB buffer overflow\n");
>> + return;
>> + }
>> +
>> + /*
>> + * For example the buffer will look like below for 3 dwords for auto
>> + * increment register:
>> + * +--------------------------------------------------------+
>> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
>> + * | | opcode | | | | |
>> + * +--------------------------------------------------------+
>> + * + + + + + + +
>> + * 0 4 8 12 16 20 24
>> + * Byte
>> + *
>> + * As every instruction is 8 byte aligned the index of dsb instruction
>> + * will start always from even number while dealing with u32 array. If
>> + * we are writing odd no of dwords, Zeros will be added in the end for
>> + * padding.
>> + */
>> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
>> + if (reg_val != i915_mmio_reg_offset(reg)) {
>> + /* Every instruction should be 8 byte aligned. */
>> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
>> +
>> + dsb->ins_start_offset = dsb->free_pos;
>> +
>> + /* Update the size. */
>> + buf[dsb->free_pos++] = 1;
>> +
>> + /* Update the opcode and reg. */
>> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
>> + DSB_OPCODE_SHIFT) |
>> + i915_mmio_reg_offset(reg);
>> +
>> + /* Update the value. */
>> + buf[dsb->free_pos++] = val;
>> + } else {
>> + /* Update the new value. */
>> + buf[dsb->free_pos++] = val;
>> +
>> + /* Update the size. */
>> + buf[dsb->ins_start_offset]++;
>> + }
>> +
>> + /* if number of data words is odd, then the last dword should be 0.*/
>> + if (dsb->free_pos & 0x1)
>> + buf[dsb->free_pos] = 0;
>> +}
>> +
>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>> {
>> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> @@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>> return;
>> }
>>
>> + dsb->ins_start_offset = dsb->free_pos;
> Okay, I'm being a pedant, but that's kind of part of the job
> description, I'm afraid.
>
> What if:
>
> intel_dsb_get()
> intel_dsb_reg_write(dsb, FOO, 0);
> intel_dsb_indexed_reg_write(dsb, FOO, 0);
> intel_dsb_commit()
> intel_dsb_put()
Hi Jani,
I am trying to think a scenario where may write the same register which
is having auto-increment capability using both intel_dsb_reg_write and
intel_dsb_indexed_reg_write.
To set the auto increment mode we may need to write a different register
to control auto-increment mode.
If there is any practical scenario, do you want to me to add now?
Currently checking register value only while creating buffer for
auto-increment register. If we want to add the above then we might need
like below because we are introducing a variability factor regarding
dsb-api to write the same register in consequent call.
enum dsb_write_type {
NORMAL,
INDEX
};
struct last_write {
u32 reg_val;
enum dsb_write_type type;
}
then, last write can be updated in intel_dsb_reg_write() as NORMAL write
and later will check in intel_dsb_indexed_reg_write() to identify above
mentioned case.
Please let me know your suggestion, will do accordingly.
Regards,
Animesh
>
> BR,
> Jani.
>
>> buf[dsb->free_pos++] = val;
>> buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
>> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 0686d67b34d5..2ae22f7309a7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -30,11 +30,20 @@ struct intel_dsb {
>> * and help in calculating tail of command buffer.
>> */
>> int free_pos;
>> +
>> + /*
>> + * ins_start_offset will help to store start address of the dsb
>> + * instuction and help in identifying the batch of auto-increment
>> + * register.
>> + */
>> + u32 ins_start_offset;
>> };
>>
>> struct intel_dsb *
>> intel_dsb_get(struct intel_crtc *crtc);
>> void intel_dsb_put(struct intel_dsb *dsb);
>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>> + u32 val);
>>
>> #endif
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
2019-09-20 15:58 ` Animesh Manna
@ 2019-09-23 7:35 ` Jani Nikula
2019-09-23 9:13 ` Animesh Manna
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2019-09-23 7:35 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> On 9/20/2019 5:48 PM, Jani Nikula wrote:
>> On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>>> DSB can program large set of data through indexed register write
>>> (opcode 0x9) in one shot. DSB feature can be used for bulk register
>>> programming e.g. gamma lut programming, HDR meta data programming.
>>>
>>> v1: initial version.
>>> v2: simplified code by using ALIGN(). (Chris)
>>> v3: ascii table added as code comment. (Shashank)
>>> v4: cosmetic changes done. (Shashank)
>>> v5: reset ins_start_offset. (Jani)
>>> v6: update ins_start_offset in inel_dsb_reg_write.
>>>
>>> Cc: Shashank Sharma <shashank.sharma@intel.com>
>>> Cc: Imre Deak <imre.deak@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
>>> drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++
>>> 2 files changed, 77 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>>> index f94cd6dc98b6..faa853b08458 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>>> @@ -12,8 +12,10 @@
>>> /* DSB opcodes. */
>>> #define DSB_OPCODE_SHIFT 24
>>> #define DSB_OPCODE_MMIO_WRITE 0x1
>>> +#define DSB_OPCODE_INDEXED_WRITE 0x9
>>> #define DSB_BYTE_EN 0xF
>>> #define DSB_BYTE_EN_SHIFT 20
>>> +#define DSB_REG_VALUE_MASK 0xfffff
>>>
>>> struct intel_dsb *
>>> intel_dsb_get(struct intel_crtc *crtc)
>>> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
>>> mutex_unlock(&i915->drm.struct_mutex);
>>> dsb->cmd_buf = NULL;
>>> dsb->free_pos = 0;
>>> + dsb->ins_start_offset = 0;
>>> }
>>> }
>>>
>>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>>> + u32 val)
>>> +{
>>> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>> + u32 *buf = dsb->cmd_buf;
>>> + u32 reg_val;
>>> +
>>> + if (!buf) {
>>> + I915_WRITE(reg, val);
>>> + return;
>>> + }
>>> +
>>> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
>>> + DRM_DEBUG_KMS("DSB buffer overflow\n");
>>> + return;
>>> + }
>>> +
>>> + /*
>>> + * For example the buffer will look like below for 3 dwords for auto
>>> + * increment register:
>>> + * +--------------------------------------------------------+
>>> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
>>> + * | | opcode | | | | |
>>> + * +--------------------------------------------------------+
>>> + * + + + + + + +
>>> + * 0 4 8 12 16 20 24
>>> + * Byte
>>> + *
>>> + * As every instruction is 8 byte aligned the index of dsb instruction
>>> + * will start always from even number while dealing with u32 array. If
>>> + * we are writing odd no of dwords, Zeros will be added in the end for
>>> + * padding.
>>> + */
>>> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
>>> + if (reg_val != i915_mmio_reg_offset(reg)) {
>>> + /* Every instruction should be 8 byte aligned. */
>>> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
>>> +
>>> + dsb->ins_start_offset = dsb->free_pos;
>>> +
>>> + /* Update the size. */
>>> + buf[dsb->free_pos++] = 1;
>>> +
>>> + /* Update the opcode and reg. */
>>> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
>>> + DSB_OPCODE_SHIFT) |
>>> + i915_mmio_reg_offset(reg);
>>> +
>>> + /* Update the value. */
>>> + buf[dsb->free_pos++] = val;
>>> + } else {
>>> + /* Update the new value. */
>>> + buf[dsb->free_pos++] = val;
>>> +
>>> + /* Update the size. */
>>> + buf[dsb->ins_start_offset]++;
>>> + }
>>> +
>>> + /* if number of data words is odd, then the last dword should be 0.*/
>>> + if (dsb->free_pos & 0x1)
>>> + buf[dsb->free_pos] = 0;
>>> +}
>>> +
>>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>>> {
>>> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>>> @@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>>> return;
>>> }
>>>
>>> + dsb->ins_start_offset = dsb->free_pos;
>> Okay, I'm being a pedant, but that's kind of part of the job
>> description, I'm afraid.
>>
>> What if:
>>
>> intel_dsb_get()
>> intel_dsb_reg_write(dsb, FOO, 0);
>> intel_dsb_indexed_reg_write(dsb, FOO, 0);
>> intel_dsb_commit()
>> intel_dsb_put()
>
> Hi Jani,
>
> I am trying to think a scenario where may write the same register which
> is having auto-increment capability using both intel_dsb_reg_write and
> intel_dsb_indexed_reg_write.
> To set the auto increment mode we may need to write a different register
> to control auto-increment mode.
> If there is any practical scenario, do you want to me to add now?
It's not a likely scenario, I've pushed the series, thanks for the
patches and review.
I think you should be able to look at the contents of the buffer and
decide based on that.
BR,
Jani.
>
> Currently checking register value only while creating buffer for
> auto-increment register. If we want to add the above then we might need
> like below because we are introducing a variability factor regarding
> dsb-api to write the same register in consequent call.
>
> enum dsb_write_type {
> NORMAL,
> INDEX
> };
>
> struct last_write {
> u32 reg_val;
> enum dsb_write_type type;
> }
>
> then, last write can be updated in intel_dsb_reg_write() as NORMAL write
> and later will check in intel_dsb_indexed_reg_write() to identify above
> mentioned case.
> Please let me know your suggestion, will do accordingly.
>
> Regards,
> Animesh
>
>>
>> BR,
>> Jani.
>>
>>> buf[dsb->free_pos++] = val;
>>> buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
>>> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>>> index 0686d67b34d5..2ae22f7309a7 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>>> @@ -30,11 +30,20 @@ struct intel_dsb {
>>> * and help in calculating tail of command buffer.
>>> */
>>> int free_pos;
>>> +
>>> + /*
>>> + * ins_start_offset will help to store start address of the dsb
>>> + * instuction and help in identifying the batch of auto-increment
>>> + * register.
>>> + */
>>> + u32 ins_start_offset;
>>> };
>>>
>>> struct intel_dsb *
>>> intel_dsb_get(struct intel_crtc *crtc);
>>> void intel_dsb_put(struct intel_dsb *dsb);
>>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>>> + u32 val);
>>>
>>> #endif
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
2019-09-23 7:35 ` Jani Nikula
@ 2019-09-23 9:13 ` Animesh Manna
0 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-23 9:13 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 9/23/2019 1:05 PM, Jani Nikula wrote:
> On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> On 9/20/2019 5:48 PM, Jani Nikula wrote:
>>> On Fri, 20 Sep 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>>>> DSB can program large set of data through indexed register write
>>>> (opcode 0x9) in one shot. DSB feature can be used for bulk register
>>>> programming e.g. gamma lut programming, HDR meta data programming.
>>>>
>>>> v1: initial version.
>>>> v2: simplified code by using ALIGN(). (Chris)
>>>> v3: ascii table added as code comment. (Shashank)
>>>> v4: cosmetic changes done. (Shashank)
>>>> v5: reset ins_start_offset. (Jani)
>>>> v6: update ins_start_offset in inel_dsb_reg_write.
>>>>
>>>> Cc: Shashank Sharma <shashank.sharma@intel.com>
>>>> Cc: Imre Deak <imre.deak@intel.com>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
>>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++++
>>>> 2 files changed, 77 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> index f94cd6dc98b6..faa853b08458 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>>>> @@ -12,8 +12,10 @@
>>>> /* DSB opcodes. */
>>>> #define DSB_OPCODE_SHIFT 24
>>>> #define DSB_OPCODE_MMIO_WRITE 0x1
>>>> +#define DSB_OPCODE_INDEXED_WRITE 0x9
>>>> #define DSB_BYTE_EN 0xF
>>>> #define DSB_BYTE_EN_SHIFT 20
>>>> +#define DSB_REG_VALUE_MASK 0xfffff
>>>>
>>>> struct intel_dsb *
>>>> intel_dsb_get(struct intel_crtc *crtc)
>>>> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
>>>> mutex_unlock(&i915->drm.struct_mutex);
>>>> dsb->cmd_buf = NULL;
>>>> dsb->free_pos = 0;
>>>> + dsb->ins_start_offset = 0;
>>>> }
>>>> }
>>>>
>>>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>>>> + u32 val)
>>>> +{
>>>> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>>>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>>> + u32 *buf = dsb->cmd_buf;
>>>> + u32 reg_val;
>>>> +
>>>> + if (!buf) {
>>>> + I915_WRITE(reg, val);
>>>> + return;
>>>> + }
>>>> +
>>>> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
>>>> + DRM_DEBUG_KMS("DSB buffer overflow\n");
>>>> + return;
>>>> + }
>>>> +
>>>> + /*
>>>> + * For example the buffer will look like below for 3 dwords for auto
>>>> + * increment register:
>>>> + * +--------------------------------------------------------+
>>>> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
>>>> + * | | opcode | | | | |
>>>> + * +--------------------------------------------------------+
>>>> + * + + + + + + +
>>>> + * 0 4 8 12 16 20 24
>>>> + * Byte
>>>> + *
>>>> + * As every instruction is 8 byte aligned the index of dsb instruction
>>>> + * will start always from even number while dealing with u32 array. If
>>>> + * we are writing odd no of dwords, Zeros will be added in the end for
>>>> + * padding.
>>>> + */
>>>> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
>>>> + if (reg_val != i915_mmio_reg_offset(reg)) {
>>>> + /* Every instruction should be 8 byte aligned. */
>>>> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
>>>> +
>>>> + dsb->ins_start_offset = dsb->free_pos;
>>>> +
>>>> + /* Update the size. */
>>>> + buf[dsb->free_pos++] = 1;
>>>> +
>>>> + /* Update the opcode and reg. */
>>>> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
>>>> + DSB_OPCODE_SHIFT) |
>>>> + i915_mmio_reg_offset(reg);
>>>> +
>>>> + /* Update the value. */
>>>> + buf[dsb->free_pos++] = val;
>>>> + } else {
>>>> + /* Update the new value. */
>>>> + buf[dsb->free_pos++] = val;
>>>> +
>>>> + /* Update the size. */
>>>> + buf[dsb->ins_start_offset]++;
>>>> + }
>>>> +
>>>> + /* if number of data words is odd, then the last dword should be 0.*/
>>>> + if (dsb->free_pos & 0x1)
>>>> + buf[dsb->free_pos] = 0;
>>>> +}
>>>> +
>>>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>>>> {
>>>> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>>>> @@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
>>>> return;
>>>> }
>>>>
>>>> + dsb->ins_start_offset = dsb->free_pos;
>>> Okay, I'm being a pedant, but that's kind of part of the job
>>> description, I'm afraid.
>>>
>>> What if:
>>>
>>> intel_dsb_get()
>>> intel_dsb_reg_write(dsb, FOO, 0);
>>> intel_dsb_indexed_reg_write(dsb, FOO, 0);
>>> intel_dsb_commit()
>>> intel_dsb_put()
>> Hi Jani,
>>
>> I am trying to think a scenario where may write the same register which
>> is having auto-increment capability using both intel_dsb_reg_write and
>> intel_dsb_indexed_reg_write.
>> To set the auto increment mode we may need to write a different register
>> to control auto-increment mode.
>> If there is any practical scenario, do you want to me to add now?
> It's not a likely scenario, I've pushed the series, thanks for the
> patches and review.
Thanks Jani and everyone who helped in review.
>
> I think you should be able to look at the contents of the buffer and
> decide based on that.
Yes, got the idea.
Regards,
Animesh
>
> BR,
> Jani.
>
>
>> Currently checking register value only while creating buffer for
>> auto-increment register. If we want to add the above then we might need
>> like below because we are introducing a variability factor regarding
>> dsb-api to write the same register in consequent call.
>>
>> enum dsb_write_type {
>> NORMAL,
>> INDEX
>> };
>>
>> struct last_write {
>> u32 reg_val;
>> enum dsb_write_type type;
>> }
>>
>> then, last write can be updated in intel_dsb_reg_write() as NORMAL write
>> and later will check in intel_dsb_indexed_reg_write() to identify above
>> mentioned case.
>> Please let me know your suggestion, will do accordingly.
>>
>> Regards,
>> Animesh
>>
>>> BR,
>>> Jani.
>>>
>>>> buf[dsb->free_pos++] = val;
>>>> buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
>>>> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>>>> index 0686d67b34d5..2ae22f7309a7 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>>>> @@ -30,11 +30,20 @@ struct intel_dsb {
>>>> * and help in calculating tail of command buffer.
>>>> */
>>>> int free_pos;
>>>> +
>>>> + /*
>>>> + * ins_start_offset will help to store start address of the dsb
>>>> + * instuction and help in identifying the batch of auto-increment
>>>> + * register.
>>>> + */
>>>> + u32 ins_start_offset;
>>>> };
>>>>
>>>> struct intel_dsb *
>>>> intel_dsb_get(struct intel_crtc *crtc);
>>>> void intel_dsb_put(struct intel_dsb *dsb);
>>>> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
>>>> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
>>>> + u32 val);
>>>>
>>>> #endif
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v9 05/10] drm/i915/dsb: Check DSB engine status.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (3 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 04/10] drm/i915/dsb: Indexed " Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 06/10] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
` (8 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index faa853b08458..6000050b18a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,15 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xfffff
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f8f52ae6cc6f..01952fae5348 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11684,4 +11684,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+ (pipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.22.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (4 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 05/10] drm/i915/dsb: Check DSB engine status Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 07/10] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Jani Nikula
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40 ++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6000050b18a6..6fb4529689f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 01952fae5348..0ef2f3be5d30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11689,6 +11689,7 @@ enum skl_power_gate {
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
#endif /* _I915_REG_H_ */
--
2.22.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (5 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 06/10] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 08/10] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
` (6 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
v4: reset ins_start_offset after commit. (Jani)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 43 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6fb4529689f1..f4c0b37683a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -224,3 +224,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(&dsb->cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 2ae22f7309a7..c77ce76fd226 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -45,5 +45,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ef2f3be5d30..22e3e610c649 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,6 +11688,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
--
2.22.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (6 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 07/10] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 09/10] drm/i915/dsb: Enable DSB for gen12 Animesh Manna
` (5 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in future
based on need.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
v3:
- modified the code as per single dsb instance per crtc. (Shashank)
- Added dsb get/put call in platform specific load_lut hook. (Jani)
- removed dsb pointer from dev_priv. (Jani)
v4: simplified code by dropping ref-count implementation. (Shashank)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 63 ++++++++++++++--------
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 318308dc136c..40af3fe2c3c9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,10 +625,15 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
+
+ intel_dsb_put(dsb);
}
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -787,22 +793,23 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_put(dsb);
}
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
u32 i;
@@ -813,26 +820,29 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
* Superfine segment has 9 entries, corresponding to values
* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
*/
- I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = &lut[i];
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
+ ilk_lut_12p4_ldw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
+ ilk_lut_12p4_udw(entry));
}
+
+ intel_dsb_put(dsb);
}
static void
icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
const struct drm_color_lut *entry;
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
u32 i;
@@ -847,11 +857,13 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
* PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
* with seg2[0] being unused by the hardware.
*/
- I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
for (i = 1; i < 257; i++) {
entry = &lut[i * 8];
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_ldw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_udw(entry));
}
/*
@@ -868,20 +880,24 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
*/
for (i = 0; i < 256; i++) {
entry = &lut[i * 8 * 128];
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_ldw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_udw(entry));
}
/* The last entry in the LUT is to be programmed in GCMAX */
entry = &lut[256 * 8 * 128];
icl_load_gcmax(crtc_state, entry);
ivb_load_lut_ext_max(crtc);
+ intel_dsb_put(dsb);
}
static void icl_load_luts(const struct intel_crtc_state *crtc_state)
{
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
if (crtc_state->base.degamma_lut)
glk_load_degamma_lut(crtc_state);
@@ -900,6 +916,9 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
ivb_load_lut_ext_max(crtc);
}
+
+ intel_dsb_commit(dsb);
+ intel_dsb_put(dsb);
}
static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
--
2.22.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 09/10] drm/i915/dsb: Enable DSB for gen12.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (7 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 08/10] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 11:59 ` [PATCH v9 10/10] drm/i915/dsb: Documentation for DSB Animesh Manna
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fe6941c8fc99..c2faa679658c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
--
2.22.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 10/10] drm/i915/dsb: Documentation for DSB.
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (8 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 09/10] drm/i915/dsb: Enable DSB for gen12 Animesh Manna
@ 2019-09-20 11:59 ` Animesh Manna
2019-09-20 15:20 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev9) Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Animesh Manna @ 2019-09-20 11:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
Documentation/gpu/i915.rst | 9 ++++
drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index e249ea7b0ec7..465779670fd4 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+--------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
========================================
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index f4c0b37683a5..0a0a1536ac96 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,23 @@
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
@@ -66,6 +83,17 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate DSB context and return a DSB instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function provides handle of a DSB instance, for the further DSB
+ * operations.
+ *
+ * Returns: address of Intel_dsb instance requested for.
+ * Failure: Returns the same DSB instance, but without a command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -116,6 +144,14 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function destroys the DSB context allocated by a dsb_get(), by
+ * unpinning and releasing the VMA object associated with it.
+ */
+
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -138,6 +174,19 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+/**
+ * intel_dsb_indexed_reg_write() -Write to the DSB context for auto
+ * increment register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB for auto-increment register. During command buffer overflow,
+ * a warning is thrown and rest all erroneous condition register programming
+ * is done through mmio write.
+ */
+
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
@@ -202,6 +251,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the DSB context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning is thrown
+ * and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -225,6 +286,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev9)
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (9 preceding siblings ...)
2019-09-20 11:59 ` [PATCH v9 10/10] drm/i915/dsb: Documentation for DSB Animesh Manna
@ 2019-09-20 15:20 ` Patchwork
2019-09-20 15:22 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-09-20 15:20 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
396d115d8cc6 drm/i915/dsb: feature flag added for display state buffer.
5a60554c2d5d drm/i915/dsb: DSB context creation.
-:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#63:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 134 lines checked
32156cd99f53 drm/i915/dsb: single register write function for DSB.
6cebb40b0c3d drm/i915/dsb: Indexed register write function for DSB.
82006824a268 drm/i915/dsb: Check DSB engine status.
c6d05e53a15d drm/i915/dsb: functions to enable/disable DSB engine.
f3f9d6a4f641 drm/i915/dsb: function to trigger workload execution of DSB.
dc74e0b1bce3 drm/i915/dsb: Enable gamma lut programming using DSB.
6ccd2217aa11 drm/i915/dsb: Enable DSB for gen12.
89ca6c89252a drm/i915/dsb: Documentation for DSB.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* ✗ Fi.CI.SPARSE: warning for DSB enablement. (rev9)
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (10 preceding siblings ...)
2019-09-20 15:20 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev9) Patchwork
@ 2019-09-20 15:22 ` Patchwork
2019-09-20 15:43 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-21 16:52 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-09-20 15:22 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* ✓ Fi.CI.BAT: success for DSB enablement. (rev9)
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (11 preceding siblings ...)
2019-09-20 15:22 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-09-20 15:43 ` Patchwork
2019-09-21 16:52 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-09-20 15:43 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14477
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/
Known issues
------------
Here are the changes found in Patchwork_14477 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@bad-open:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@gem_flink_basic@bad-open.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/fi-icl-u3/igt@gem_flink_basic@bad-open.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713] / [fdo#111381]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-blb-e6850/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@kms_addfb_basic@addfb25-x-tiled:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@kms_addfb_basic@addfb25-x-tiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/fi-icl-u3/igt@kms_addfb_basic@addfb25-x-tiled.html
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 48)
------------------------------
Additional (1): fi-hsw-4770r
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6928 -> Patchwork_14477
CI-20190529: 20190529
CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14477: 89ca6c89252aa3e8b3e3fe65ce0d39cf953e642b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
89ca6c89252a drm/i915/dsb: Documentation for DSB.
6ccd2217aa11 drm/i915/dsb: Enable DSB for gen12.
dc74e0b1bce3 drm/i915/dsb: Enable gamma lut programming using DSB.
f3f9d6a4f641 drm/i915/dsb: function to trigger workload execution of DSB.
c6d05e53a15d drm/i915/dsb: functions to enable/disable DSB engine.
82006824a268 drm/i915/dsb: Check DSB engine status.
6cebb40b0c3d drm/i915/dsb: Indexed register write function for DSB.
32156cd99f53 drm/i915/dsb: single register write function for DSB.
5a60554c2d5d drm/i915/dsb: DSB context creation.
396d115d8cc6 drm/i915/dsb: feature flag added for display state buffer.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* ✓ Fi.CI.IGT: success for DSB enablement. (rev9)
2019-09-20 11:59 [PATCH v9 00/10] DSB enablement Animesh Manna
` (12 preceding siblings ...)
2019-09-20 15:43 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-21 16:52 ` Patchwork
13 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-09-21 16:52 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928_full -> Patchwork_14477_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14477_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_dc@dc6-psr}:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
Known issues
------------
Here are the changes found in Patchwork_14477_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +21 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#105767])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@busy-flip:
- shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-hsw5/igt@kms_flip@busy-flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-hsw4/igt@kms_flip@busy-flip.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][23] -> [FAIL][24] ([fdo#99912])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl7/igt@kms_setmode@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([fdo#108566])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([fdo#103313])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
#### Possible fixes ####
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][29] ([fdo#111325]) -> [PASS][30] +6 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html
* {igt@gem_mmap_gtt@close-race}:
- shard-apl: [INCOMPLETE][31] ([fdo#103927]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-apl3/igt@gem_mmap_gtt@close-race.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-apl7/igt@gem_mmap_gtt@close-race.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [DMESG-WARN][33] ([fdo#108686]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-glk4/igt@gem_tiled_swapping@non-threaded.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-glk3/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-apl1/igt@i915_suspend@sysfs-reader.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-apl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][37] ([fdo#110741]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-dpms-interruptible:
- shard-iclb: [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb1/igt@kms_flip@flip-vs-dpms-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb5/igt@kms_flip@flip-vs-dpms-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][41] ([fdo#103167]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][43] ([fdo#104108] / [fdo#106978]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-skl10/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-primary-size-128:
- shard-kbl: [DMESG-WARN][47] ([fdo#103558] / [fdo#105602]) -> [PASS][48] +37 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl6/igt@kms_plane_cursor@pipe-a-primary-size-128.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl4/igt@kms_plane_cursor@pipe-a-primary-size-128.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@perf@polling:
- shard-skl: [FAIL][51] ([fdo#110728]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-skl1/igt@perf@polling.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-skl9/igt@perf@polling.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][53] ([fdo#109276]) -> [PASS][54] +9 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [FAIL][55] ([fdo#111330]) -> [SKIP][56] ([fdo#109276])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][57] ([fdo#109276]) -> [FAIL][58] ([fdo#111330]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d:
- shard-kbl: [SKIP][59] ([fdo#105602] / [fdo#109271] / [fdo#109278]) -> [SKIP][60] ([fdo#109271] / [fdo#109278]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl4/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-snb: [DMESG-WARN][61] ([fdo#102365]) -> [INCOMPLETE][62] ([fdo#105411])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_panel_fitting@legacy:
- shard-kbl: [SKIP][63] ([fdo#105602] / [fdo#109271]) -> [SKIP][64] ([fdo#109271]) +30 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/shard-kbl6/igt@kms_panel_fitting@legacy.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/shard-kbl4/igt@kms_panel_fitting@legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6928 -> Patchwork_14477
CI-20190529: 20190529
CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14477: 89ca6c89252aa3e8b3e3fe65ce0d39cf953e642b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14477/
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