* [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers José Roberto de Souza
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clinton A Taylor <clinton.a.taylor@intel.com>
Step 4.b was complete missed because it is only required to TC and TBT.
Bspec: 49190
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0c0da9f6c2e8..dfd6b064cbc3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3230,11 +3230,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_edp_panel_on(intel_dp);
/*
- * 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by:
+ * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
* haswell_crtc_enable()->intel_enable_shared_dpll()
*/
+ /* 4.b */
+ intel_ddi_clk_select(encoder, crtc_state);
+
/* 5. */
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
--
2.23.0
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll José Roberto de Souza
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
If platform supports and has modular FIA is enabled, the registers
bits also change, example: reading TC3 registers with modular FIA
enabled, driver should read from FIA2 but with TC1 bits offsets.
It is described in BSpec 50231 for DFLEXDPSP, other registers don't
have the BSpec description but testing in real hardware have proven
that it had moved for all other registers too.
v2:
- Caching index in tc_phy_fia_idx, instead of calculate it each time
v3:
- Setting tc_phy_fia and tc_phy_fia_idx in the same function
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 72 ++++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 28 ++++----
3 files changed, 53 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..d258a48f77d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1285,6 +1285,7 @@ struct intel_digital_port {
char tc_port_name[8];
enum tc_port_mode tc_mode;
enum phy_fia tc_phy_fia;
+ u8 tc_phy_fia_idx;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 85743a43bee2..f923f9cbd33c 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -23,32 +23,38 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
-static bool has_modular_fia(struct drm_i915_private *i915)
-{
- if (!INTEL_INFO(i915)->display.has_modular_fia)
- return false;
-
- return intel_uncore_read(&i915->uncore,
- PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
-}
-
-static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
- enum tc_port tc_port)
+static void
+tc_port_load_fia_params(struct drm_i915_private *i915,
+ struct intel_digital_port *dig_port)
{
- if (!has_modular_fia(i915))
- return FIA1;
+ enum port port = dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(i915, port);
+ u32 modular_fia;
+
+ if (INTEL_INFO(i915)->display.has_modular_fia) {
+ modular_fia = intel_uncore_read(&i915->uncore,
+ PORT_TX_DFLEXDPSP(FIA1));
+ modular_fia &= MODULAR_FIA_MASK;
+ } else {
+ modular_fia = 0;
+ }
/*
* Each Modular FIA instance houses 2 TC ports. In SOC that has more
* than two TC ports, there are multiple instances of Modular FIA.
*/
- return tc_port / 2;
+ if (modular_fia) {
+ dig_port->tc_phy_fia = tc_port / 2;
+ dig_port->tc_phy_fia_idx = tc_port % 2;
+ } else {
+ dig_port->tc_phy_fia = FIA1;
+ dig_port->tc_phy_fia_idx = tc_port;
+ }
}
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = &i915->uncore;
u32 lane_mask;
@@ -57,8 +63,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
WARN_ON(lane_mask == 0xffffffff);
- return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
- DP_LANE_ASSIGNMENT_SHIFT(tc_port);
+ lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
+ return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
}
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
@@ -95,7 +101,6 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
struct intel_uncore *uncore = &i915->uncore;
u32 val;
@@ -104,19 +109,21 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
val = intel_uncore_read(uncore,
PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
- val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
switch (required_lanes) {
case 1:
- val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+ val |= lane_reversal ?
+ DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
+ DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
break;
case 2:
- val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
+ val |= lane_reversal ?
+ DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
+ DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
break;
case 4:
- val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
+ val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
break;
default:
MISSING_CASE(required_lanes);
@@ -164,9 +171,9 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
return mask;
}
- if (val & TC_LIVE_STATE_TBT(tc_port))
+ if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
mask |= BIT(TC_PORT_TBT_ALT);
- if (val & TC_LIVE_STATE_TC(tc_port))
+ if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
mask |= BIT(TC_PORT_DP_ALT);
if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
@@ -182,7 +189,6 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = &i915->uncore;
u32 val;
@@ -194,14 +200,13 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
return false;
}
- return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port);
+ return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
bool enable)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = &i915->uncore;
u32 val;
@@ -215,9 +220,9 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
return false;
}
- val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
if (!enable)
- val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
+ val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
@@ -232,7 +237,6 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = &i915->uncore;
u32 val;
@@ -244,7 +248,7 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
return true;
}
- return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port));
+ return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
}
/*
@@ -540,5 +544,5 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
mutex_init(&dig_port->tc_lock);
dig_port->tc_legacy_port = is_legacy;
dig_port->tc_link_refcount = 0;
- dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
+ tc_port_load_fia_params(i915, dig_port);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acbda6d89a9b..a6acda945e56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2166,13 +2166,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
-#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
-#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
-#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
-#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
-#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
-#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
@@ -11678,16 +11678,16 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
#define MODULAR_FIA_MASK (1 << 4)
-#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
-#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
-#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
-#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
-#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
+#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
+#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
+#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
+#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
+#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
-#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
+#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
-#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
#endif /* _I915_REG_H_ */
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers José Roberto de Souza
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clinton A Taylor <clinton.a.taylor@intel.com>
Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
port is active") added this new hook while in parallel TGL upstream was
happening and this was missed.
Without this driver will crash when TC DDI is added and driver is
preparing to do a full modeset.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 98288edf88f0..84e734d44828 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3479,6 +3479,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dpll_info = tgl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
+ .update_active_dpll = icl_update_active_dpll,
.dump_hw_state = icl_dump_hw_state,
};
--
2.23.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (2 preceding siblings ...)
2019-09-20 20:58 ` [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions José Roberto de Souza
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
These are the registers needed to program Dekel phy. Some register
definitions will be reused from MG PHY definitions, so adding a
comment on those.
Bspec: 49295
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 162 ++++++++++++++++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6acda945e56..b82cf4725c05 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10111,6 +10111,168 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PLL_DIV0 0x200
+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
+#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+
+#define _DKL_PLL_DIV1 0x204
+#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+
+#define _DKL_PLL_SSC 0x210
+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
+#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
+#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
+#define DKL_PLL_SSC_EN (1 << 9)
+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_SSC)
+
+#define _DKL_PLL_BIAS 0x214
+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
+#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_BIAS)
+
+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_TDC_COLDST_BIAS)
+
+#define _DKL_REFCLKIN_CTL 0x12C
+/* Bits are the same as MG_REFCLKIN_CTL */
+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_REFCLKIN_CTL)
+
+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_HSCLKCTL)
+
+#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
+/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
+#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_CORECLKCTL1)
+
+#define _DKL_TX_DPCNTL0 0x2C0
+#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
+#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
+#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
+#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
+#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
+#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
+#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_DPCNTL0)
+
+#define _DKL_TX_DPCNTL1 0x2C4
+/* Bits are the same as DKL_TX_DPCNTRL0 */
+#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_DPCNTL1)
+
+#define _DKL_TX_DPCNTL2 0x2C8
+#define DKL_TX_DP20BITMODE (1 << 2)
+#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_DPCNTL2)
+
+#define _DKL_TX_FW_CALIB 0x2F8
+#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
+#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_FW_CALIB)
+
+#define _DKL_TX_DW17 0xDC4
+#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_DW17)
+
+#define _DKL_TX_DW18 0xDC8
+#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_TX_DW18)
+
+#define _DKL_DP_MODE 0xA0
+#define DKL_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
+#define DKL_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
+#define DKL_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
+#define DKL_DP_MODE_CFG_TRPWR_GATING (1 << 4)
+#define DKL_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
+#define DKL_DP_MODE_CFG_GATING_CTRL_MASK (0x1f << 1)
+#define DKL_DP_MODE_CFG_DP_X1_MODE (1 << 6)
+#define DKL_DP_MODE_CFG_DP_X2_MODE (1 << 7)
+#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_DP_MODE)
+
+#define _DKL_CMN_UC_DW27 0x36C
+#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
+#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CMN_UC_DW27)
+
+/*
+ * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
+ * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
+ * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
+ * bits that point the 4KB window into the full PHY register space.
+ */
+#define _HIP_INDEX_REG0 0x1010A0
+#define _HIP_INDEX_REG1 0x1010A4
+#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
+ : _HIP_INDEX_REG1)
+#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
+#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.23.0
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (3 preceding siblings ...)
2019-09-20 20:58 ` [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 20:58 ` [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on José Roberto de Souza
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Adding a enable parameters allow us to share most of the code between
enable and disable functions.
v3:
Renamed icl_phy_clock_gating() to icl_phy_set_clock_gating()
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 73 ++++++++----------------
1 file changed, 23 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dfd6b064cbc3..33cd766f9eea 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3033,67 +3033,40 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
}
}
-static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
+static void
+icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
{
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- u32 val;
+ u32 val, bits;
int ln;
if (tc_port == PORT_TC_NONE)
return;
- for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_DP_MODE(ln, port));
- val |= MG_DP_MODE_CFG_TR2PWR_GATING |
- MG_DP_MODE_CFG_TRPWR_GATING |
- MG_DP_MODE_CFG_CLNPWR_GATING |
- MG_DP_MODE_CFG_DIGPWR_GATING |
- MG_DP_MODE_CFG_GAONPWR_GATING;
- I915_WRITE(MG_DP_MODE(ln, port), val);
- }
-
- val = I915_READ(MG_MISC_SUS0(tc_port));
- val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
- MG_MISC_SUS0_CFG_TR2PWR_GATING |
- MG_MISC_SUS0_CFG_CL2PWR_GATING |
- MG_MISC_SUS0_CFG_GAONPWR_GATING |
- MG_MISC_SUS0_CFG_TRPWR_GATING |
- MG_MISC_SUS0_CFG_CL1PWR_GATING |
- MG_MISC_SUS0_CFG_DGPWR_GATING;
- I915_WRITE(MG_MISC_SUS0(tc_port), val);
-}
-
-static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
-{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum port port = dig_port->base.port;
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- u32 val;
- int ln;
-
- if (tc_port == PORT_TC_NONE)
- return;
+ bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
+ MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
+ MG_DP_MODE_CFG_GAONPWR_GATING;
for (ln = 0; ln < 2; ln++) {
val = I915_READ(MG_DP_MODE(ln, port));
- val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
- MG_DP_MODE_CFG_TRPWR_GATING |
- MG_DP_MODE_CFG_CLNPWR_GATING |
- MG_DP_MODE_CFG_DIGPWR_GATING |
- MG_DP_MODE_CFG_GAONPWR_GATING);
+ if (enable)
+ val |= bits;
+ else
+ val &= ~bits;
I915_WRITE(MG_DP_MODE(ln, port), val);
}
+ bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
+ MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
+ MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
+
val = I915_READ(MG_MISC_SUS0(tc_port));
- val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
- MG_MISC_SUS0_CFG_TR2PWR_GATING |
- MG_MISC_SUS0_CFG_CL2PWR_GATING |
- MG_MISC_SUS0_CFG_GAONPWR_GATING |
- MG_MISC_SUS0_CFG_TRPWR_GATING |
- MG_MISC_SUS0_CFG_CL1PWR_GATING |
- MG_MISC_SUS0_CFG_DGPWR_GATING);
+ if (enable)
+ val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
+ else
+ val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
I915_WRITE(MG_MISC_SUS0(tc_port), val);
}
@@ -3258,7 +3231,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_ddi_config_transcoder_func(crtc_state);
/* 7.d */
- icl_disable_phy_clock_gating(dig_port);
+ icl_phy_set_clock_gating(dig_port, false);
/* 7.e */
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
@@ -3328,7 +3301,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
dig_port->ddi_io_power_domain);
icl_program_mg_dp_mode(dig_port);
- icl_disable_phy_clock_gating(dig_port);
+ icl_phy_set_clock_gating(dig_port, false);
if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
@@ -3361,7 +3334,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_ddi_enable_fec(encoder, crtc_state);
- icl_enable_phy_clock_gating(dig_port);
+ icl_phy_set_clock_gating(dig_port, true);
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
@@ -3398,7 +3371,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
icl_program_mg_dp_mode(dig_port);
- icl_disable_phy_clock_gating(dig_port);
+ icl_phy_set_clock_gating(dig_port, false);
if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
@@ -3410,7 +3383,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
else
intel_prepare_hdmi_ddi_buffers(encoder, level);
- icl_enable_phy_clock_gating(dig_port);
+ icl_phy_set_clock_gating(dig_port, true);
if (IS_GEN9_BC(dev_priv))
skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
--
2.23.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (4 preceding siblings ...)
2019-09-20 20:58 ` [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions José Roberto de Souza
@ 2019-09-20 20:58 ` José Roberto de Souza
2019-09-20 22:02 ` ✗ Fi.CI.BAT: failure for TGL TC enabling v2-CI Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: José Roberto de Souza @ 2019-09-20 20:58 UTC (permalink / raw)
To: intel-gfx
New step added for TGL, required for us to check the TC
microcontroller health after power on TC aux.
BSpec: 49294
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce88a27229ef..f1186bc23542 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -562,6 +562,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
#endif
+#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
+
static void
icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -578,6 +580,17 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
hsw_power_well_enable(dev_priv, power_well);
+
+ if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
+ enum tc_port tc_port;
+
+ tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2));
+
+ if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
+ DKL_CMN_UC_DW27_UC_HEALTH, 1))
+ DRM_WARN("Timeout waiting TC uC health\n");
+ }
}
static void
--
2.23.0
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^ permalink raw reply related [flat|nested] 11+ messages in thread* ✗ Fi.CI.BAT: failure for TGL TC enabling v2-CI
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (5 preceding siblings ...)
2019-09-20 20:58 ` [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on José Roberto de Souza
@ 2019-09-20 22:02 ` Patchwork
2019-09-20 23:21 ` ✓ Fi.CI.BAT: success for TGL TC enabling v2-CI (rev2) Patchwork
2019-09-22 13:56 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-09-20 22:02 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: TGL TC enabling v2-CI
URL : https://patchwork.freedesktop.org/series/67022/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14485
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14485 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14485, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14485:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-r: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-kbl-r/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-kbl-r/igt@gem_exec_suspend@basic-s3.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
* igt@runner@aborted:
- {fi-cml-s}: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-cml-s/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_14485 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927] / [fdo#111381])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@i915_module_load@reload-no-display.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u3/igt@i915_module_load@reload-no-display.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][10] -> [FAIL][11] ([fdo#109483] / [fdo#109635 ])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic:
- {fi-icl-u4}: [FAIL][12] ([fdo#111699]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u4/igt@gem_exec_suspend@basic.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u4/igt@gem_exec_suspend@basic.html
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][14] ([fdo#107724]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][16] ([fdo#107724] / [fdo#111214]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@i915_module_load@reload.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u3/igt@i915_module_load@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][18] ([fdo#109483]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][20] ([fdo#111407]) -> [FAIL][21] ([fdo#111045] / [fdo#111096])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699
Participating hosts (54 -> 47)
------------------------------
Additional (1): fi-tgl-u2
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6932 -> Patchwork_14485
CI-20190529: 20190529
CI_DRM_6932: f539beb004edb5b82925c10324f7cf4c5b4dbcc5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5195: ea29372bb4e261a0a8da371a1f434131750f18e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14485: 40f91c49ad22b04ec8391bfa821ec6f2dc2f6053 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
40f91c49ad22 drm/i915/tgl: Check the UC health of tc controllers after power on
e373d5b62d48 drm/i915/icl: Unify disable and enable phy clock gating functions
cde78ed940ad drm/i915/tgl: Add dkl phy registers
5e54aa2f5027 drm/i915/tgl/pll: Set update_active_dpll
56b6dfb1ff89 drm/i915/tgl: Finish modular FIA support on registers
dfa77bda3bc3 drm/i915/tgl: Add missing ddi clock select during DP init sequence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14485/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* ✓ Fi.CI.BAT: success for TGL TC enabling v2-CI (rev2)
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (6 preceding siblings ...)
2019-09-20 22:02 ` ✗ Fi.CI.BAT: failure for TGL TC enabling v2-CI Patchwork
@ 2019-09-20 23:21 ` Patchwork
2019-09-22 13:56 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-09-20 23:21 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: TGL TC enabling v2-CI (rev2)
URL : https://patchwork.freedesktop.org/series/67022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14486
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/
Known issues
------------
Here are the changes found in Patchwork_14486 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@gem_ctx_param@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-icl-u3/igt@gem_ctx_param@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic:
- {fi-icl-u4}: [FAIL][3] ([fdo#111699]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u4/igt@gem_exec_suspend@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-icl-u4/igt@gem_exec_suspend@basic.html
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u3/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-icl-u3/igt@i915_module_load@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][9] ([fdo#109483]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#111045] / [fdo#111096])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699
Participating hosts (54 -> 48)
------------------------------
Additional (1): fi-tgl-u2
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6932 -> Patchwork_14486
CI-20190529: 20190529
CI_DRM_6932: f539beb004edb5b82925c10324f7cf4c5b4dbcc5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5195: ea29372bb4e261a0a8da371a1f434131750f18e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14486: c58daa59cae523d8718750d0654e95c0c804ea5d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c58daa59cae5 drm/i915/tgl: Check the UC health of tc controllers after power on
4afd3248a8aa drm/i915/icl: Unify disable and enable phy clock gating functions
0c886504b50c drm/i915/tgl: Add dkl phy registers
3ef7487b0704 drm/i915/tgl/pll: Set update_active_dpll
fce11fcea1ff drm/i915/tgl: Finish modular FIA support on registers
dfbb456a4492 drm/i915/tgl: Add missing ddi clock select during DP init sequence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* ✓ Fi.CI.IGT: success for TGL TC enabling v2-CI (rev2)
2019-09-20 20:58 [PATCH CI 0/6] TGL TC enabling v2-CI José Roberto de Souza
` (7 preceding siblings ...)
2019-09-20 23:21 ` ✓ Fi.CI.BAT: success for TGL TC enabling v2-CI (rev2) Patchwork
@ 2019-09-22 13:56 ` Patchwork
2019-09-23 17:52 ` Souza, Jose
8 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2019-09-22 13:56 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: TGL TC enabling v2-CI (rev2)
URL : https://patchwork.freedesktop.org/series/67022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932_full -> Patchwork_14486_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14486_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_dc@dc5-dpms}:
- shard-iclb: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb8/igt@i915_pm_dc@dc5-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
Known issues
------------
Here are the changes found in Patchwork_14486_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-snb7/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-snb7/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +15 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +5 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-hsw: [PASS][13] -> [DMESG-FAIL][14] ([fdo#102614])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-hsw6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-hsw5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][25] -> [FAIL][26] ([fdo#99912])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-hsw6/igt@kms_setmode@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-hsw5/igt@kms_setmode@basic.html
- shard-kbl: [PASS][27] -> [FAIL][28] ([fdo#99912])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-kbl7/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-kbl1/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-skl: [DMESG-WARN][29] ([fdo#106107]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-skl1/igt@gem_exec_reloc@basic-gtt-cpu-active.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-skl8/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][31] ([fdo#109276]) -> [PASS][32] +10 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][33] ([fdo#111325]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_vm_create@isolation:
- shard-apl: [INCOMPLETE][35] ([fdo#103927]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-apl7/igt@gem_vm_create@isolation.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-apl6/igt@gem_vm_create@isolation.html
* igt@kms_cursor_crc@pipe-b-cursor-size-change:
- shard-skl: [FAIL][37] ([fdo#103232]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][39] ([fdo#104873]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
- shard-iclb: [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [DMESG-WARN][43] ([fdo#103313]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][45] ([fdo#108566]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][47] ([fdo#103166]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][49] ([fdo#99912]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-apl3/igt@kms_setmode@basic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-apl4/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][51] ([fdo#111330]) -> [SKIP][52] ([fdo#109276])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@kms_setmode@basic:
- shard-skl: [DMESG-FAIL][53] ([fdo#106107] / [fdo#99912]) -> [FAIL][54] ([fdo#99912])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6932/shard-skl7/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/shard-skl3/igt@kms_setmode@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111757]: https://bugs.freedesktop.org/show_bug.cgi?id=111757
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6932 -> Patchwork_14486
CI-20190529: 20190529
CI_DRM_6932: f539beb004edb5b82925c10324f7cf4c5b4dbcc5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5195: ea29372bb4e261a0a8da371a1f434131750f18e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14486: c58daa59cae523d8718750d0654e95c0c804ea5d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14486/
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