[MODERATED] Re: [PATCH v4 01/10] TAAv4 1

[Borislav Petkov <bp@suse.de>]

On Tue, Sep 03, 2019 at 02:11:32PM -0700, speck for Pawan Gupta wrote:
> From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> Subject: [PATCH v4 01/10] x86/tsx: Add enumeration support for IA32_TSX_CTRL
>  MSR
> 
> Transactional Synchronization Extensions (TSX) may be used on certain
> processors as part of a speculative side channel attack.  A microcode
> update for existing processors that are vulnerable to this attack will
> add a new MSR, IA32_TSX_CTRL to allow the system administrator the option
> to disable TSX as one of the possible mitigations.  [Note that future
> processors that are not vulnerable will also support the IA32_TSX_CTRL
> MSR].  This patch adds the defines for the new IA32_TSX_CTRL MSR and its

Avoid having "This patch" or "This commit" in the commit message. It is
tautologically useless.

Also, do

$ git grep 'This patch' Documentation/process

for more details.

> bits.
> 
> Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the
> IA32_TSX_CTRL MSR.
> 
> There are two control bits in IA32_TSX_CTRL MSR:
> 
>   Bit 0: Can be written to "1" to disable the Restricted Transactional

"Bit 0: When set, it disables ... "

>          Memory (RTM) sub-feature of TSX (will force all transactions
>          to abort on the XBEGIN instruction).
> 
>   Bit 1: Can be written to "1" to disable enumeration of the RTM feature

Ditto.

>          (i.e. will make CPUID(EAX=7).EBX{bit11} read as 0).
> 
> The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally
> disabled but still enumerated as present by CPUID(EAX=7).EBX{bit4}.
> 
> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> ---
>  arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 271d837d69a8..9163eb67962e 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -93,6 +93,7 @@
>  						  * Microarchitectural Data
>  						  * Sampling (MDS) vulnerabilities.
>  						  */
> +#define ARCH_CAP_TSX_CTRL_MSR		BIT(7)	/* MSR for TSX control is available. */
>  
>  #define MSR_IA32_FLUSH_CMD		0x0000010b
>  #define L1D_FLUSH			BIT(0)	/*
> @@ -103,6 +104,10 @@
>  #define MSR_IA32_BBL_CR_CTL		0x00000119
>  #define MSR_IA32_BBL_CR_CTL3		0x0000011e
>  
> +#define MSR_IA32_TSX_CTRL		0x00000122


> +#define MSR_TSX_CTRL_RTM_DISABLE	BIT(0)	/* Disable RTM feature */
> +#define MSR_TSX_CTRL_CPUID_CLEAR	BIT(1)	/* Disable TSX enumeration */

For those last two:

s/MSR_//

Thx.

-- 
Regards/Gruss,
    Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 247165, AG München
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