From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v4 02/10] TAAv4 2
Date: Mon, 30 Sep 2019 16:26:15 -0700 [thread overview]
Message-ID: <20190930232602.GA8582@guptapadev.amr> (raw)
In-Reply-To: <20190925223014.3diomop66p4efm36@treble>
On Wed, Sep 25, 2019 at 05:30:14PM -0500, speck for Josh Poimboeuf wrote:
> On Tue, Sep 03, 2019 at 02:12:32PM -0700, speck for Pawan Gupta wrote:
> > From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> > Subject: [PATCH v4 02/10] x86/tsx: Add TSX control initialization
> >
> > Add a new file to host TSX feature controls. TSX control has three
>
> "Add a new file" makes it sound like a sysfs file rather than a .c file.
>
> And it would probably be better to lead off with a description of the
> *functional* change of the patch, rather than the not-so-interesting
> aspect of adding a .c file. For example, this patch disables TSX by
> default. That should also be reflected in the patch subject.
>
> (This is of course pending the other discussion about what defaults make
> sense.)
>
> > valid states ENABLE, DISABLE and NOT_SUPPORTED. TSX may be used on
> > certain processors as part of a speculative side channel attack.
>
> How is that relevant to this patch?
This is why we are defaulting to off.
>
> > Set the boot time default to DISABLE or NOT_SUPPORTED based on the
> > presence of IA32_TSX_CTRL MSR.
>
> This should say *why* it's changing the default to disabled, assuming
> that's what we decide to do.
Ok. Updating commit log to below:
x86/tsx: Disable TSX by default
Disable TSX by default on bootup. If IA32_TSX_CTRL MSR is not present,
TSX state stays the compile time default which is NOT_SUPPORTED,
otherwise change TSX state to DISABLE. This is because on certain
processsors TSX may be used as a part of a speculative side channel
attack.
>
> > +void tsx_init(struct cpuinfo_x86 *c)
> > +{
> > + tsx_ctrl_check_support(c);
> > +
> > + switch (tsx_ctrl_state) {
> > + case TSX_CTRL_DISABLE:
> > + tsx_disable();
> > + clear_cpu_cap(c, X86_FEATURE_RTM);
> > + setup_clear_cpu_cap(X86_FEATURE_RTM);
>
> Can you clarify why setup_clear_cpu_cap() is needed?
>
> AFAICT, setup_clear_cpu_cap() would be used for forcing a feature to be
> cleared on all CPUs, but this function already calls clear_cpu_cap() for
> every CPU anyway.
clear_cpu_cap() would update per-cpu capability bit for a particular CPU (used
by this_cpu_has()). setup_clear_cpu_cap() updates the common (boot_cpu_data)
capability bit so that boot_cpu_has() tests are evaluated correctly. We need to
update both data structures.
Thanks,
Pawan
next prev parent reply other threads:[~2019-09-30 23:31 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1567543894.git.pawan.kumar.gupta@linux.intel.com>
2019-09-23 12:47 ` [MODERATED] Re: [PATCH v4 01/10] TAAv4 1 Borislav Petkov
[not found] ` <20190904060028.GD7212@kroah.com>
[not found] ` <20190906072835.GD13480@guptapadev.amr>
[not found] ` <20190906092727.GA16843@kroah.com>
[not found] ` <20190910184223.GA7543@guptapadev.amr>
[not found] ` <20190910223334.GA21301@kroah.com>
[not found] ` <20190910233449.GA10041@agluck-desk2.amr.corp.intel.com>
2019-09-23 19:10 ` [MODERATED] Re: [PATCH v4 04/10] TAAv4 4 Greg KH
[not found] ` <20190911023223.GA8305@guptapadev.amr>
2019-09-23 19:13 ` Greg KH
2019-09-23 22:25 ` Pawan Gupta
2019-09-24 5:04 ` Greg KH
2019-09-24 10:48 ` Jiri Kosina
2019-09-24 13:31 ` Greg KH
2019-09-24 13:38 ` Jiri Kosina
2019-09-24 13:47 ` Greg KH
2019-09-24 23:25 ` Pawan Gupta
2019-09-27 7:01 ` Greg KH
2019-09-25 21:10 ` [MODERATED] Re: [PATCH v4 06/10] TAAv4 6 Kanth Ghatraju
2019-09-25 21:11 ` [MODERATED] [AUTOREPLY] [AUTOREPLY] Automatic reply: " Hatle, Mark
2019-09-26 1:15 ` [MODERATED] " Pawan Gupta
[not found] ` <20190904055711.GC7212@kroah.com>
[not found] ` <nycvar.YFH.7.76.1909040759580.31470@cbobk.fhfr.pm>
[not found] ` <20190904061155.GI7212@kroah.com>
[not found] ` <20190904075846.GD1321@guptapadev.amr>
[not found] ` <20190904084306.GA4925@kroah.com>
[not found] ` <20190904112758.GP3838@dhcp22.suse.cz>
2019-09-25 22:05 ` [MODERATED] Re: ***UNCHECKED*** Re: [PATCH v4 03/10] TAAv4 3 Josh Poimboeuf
2019-10-01 0:20 ` [MODERATED] " Pawan Gupta
2019-10-02 14:55 ` Borislav Petkov
2019-10-05 5:16 ` Pawan Gupta
2019-10-08 2:59 ` Josh Poimboeuf
2019-10-08 6:15 ` Pawan Gupta
2019-10-08 18:06 ` Dave Hansen
2019-10-08 18:36 ` [MODERATED] Re: ***UNCHECKED*** " Jiri Kosina
[not found] ` <20190904055406.GA7212@kroah.com>
[not found] ` <20190904074326.GB1321@guptapadev.amr>
[not found] ` <bfe6f7e0-22db-ce4d-ac3a-875482b43489@intel.com>
2019-09-25 22:13 ` [MODERATED] Re: [PATCH v4 02/10] TAAv4 2 Josh Poimboeuf
2019-09-26 0:46 ` Pawan Gupta
2019-09-25 22:30 ` Josh Poimboeuf
2019-09-30 23:26 ` Pawan Gupta [this message]
2019-09-30 23:32 ` [MODERATED] [AUTOREPLY] [MODERATED] [AUTOREPLY] Automatic reply: " James, Hengameh M
[not found] ` <5b6df5ee-a5b7-c281-de29-af6544b8abb6@intel.com>
[not found] ` <20190906074645.GE13480@guptapadev.amr>
2019-09-25 22:48 ` [MODERATED] Re: [PATCH v4 03/10] TAAv4 3 Josh Poimboeuf
2019-09-25 23:12 ` Dave Hansen
2019-09-25 23:22 ` Andrew Cooper
2019-09-26 1:13 ` Pawan Gupta
2019-09-26 2:34 ` Josh Poimboeuf
2019-09-26 7:15 ` Pawan Gupta
2019-09-26 13:54 ` Josh Poimboeuf
2019-09-26 17:57 ` Pawan Gupta
[not found] ` <d6fd9ad7-79f7-aab9-db31-a9a2ca03aa10@intel.com>
[not found] ` <20190906080828.GF13480@guptapadev.amr>
[not found] ` <00170736-0d97-4a48-2141-ffba4bb67199@intel.com>
2019-09-25 22:58 ` [MODERATED] Re: [PATCH v4 04/10] TAAv4 4 Josh Poimboeuf
2019-09-26 0:48 ` Pawan Gupta
2019-09-25 23:06 ` [MODERATED] Re: [PATCH v4 06/10] TAAv4 6 Josh Poimboeuf
2019-09-30 23:00 ` Pawan Gupta
2019-10-01 18:26 ` [MODERATED] Re: [PATCH v4 05/10] TAAv4 5 Pawan Gupta
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