[PATCH v2 00/11] Clear Color Support for TGL Render Decompression

[PATCH v2 00/11] Clear Color Support for TGL Render Decompression

[Radhakrishna Sripada]

Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 9 patches are
currently undergoing review/revision changes. The first 9 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/67078/

Expecting feedback for the last 2 patches. The infrastructure to
test the patch series is WIP.

Dhinakaran Pandiyan (9):
  drm/framebuffer: Format modifier for Intel Gen-12 render compression
  drm/i915: Use intel_tile_height() instead of re-implementing
  drm/i915: Move CCS stride alignment W/A inside
    intel_fb_stride_alignment
  drm/i915/tgl: Gen-12 render decompression
  drm/i915: Extract framebufer CCS offset checks into a function
  drm/framebuffer: Format modifier for Intel Gen-12 media compression
  drm/i915: Skip rotated offset adjustment for unsupported modifiers
  drm/fb: Extend format_info member arrays to handle four planes
  Gen-12 display can decompress surfaces compressed by the media engine.

Radhakrishna Sripada (2):
  drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
    compression with Clear Color
  drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

 drivers/gpu/drm/i915/display/intel_display.c  | 424 ++++++++++++++----
 .../drm/i915/display/intel_display_types.h    |   5 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  70 ++-
 drivers/gpu/drm/i915/i915_reg.h               |  14 +
 include/drm/drm_fourcc.h                      |   8 +-
 include/uapi/drm/drm_fourcc.h                 |  35 ++
 6 files changed, 441 insertions(+), 115 deletions(-)

-- 
2.20.1

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[PATCH v2 01/11] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..1f0fbf0398f6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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[PATCH v2 02/11] drm/i915: Use intel_tile_height() instead of re-implementing

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5ecf54270181..a94d145dd048 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1957,7 +1957,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
 	unsigned int cpp = fb->format->cpp[color_plane];
 
 	*tile_width = tile_width_bytes / cpp;
-	*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+	*tile_height = intel_tile_height(fb, color_plane);
 }
 
 unsigned int
-- 
2.20.1

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[PATCH v2 03/11] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Easier to read if all the alignment changes are in one place and contained
within a function.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a94d145dd048..c437f00c2072 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2551,7 +2551,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 64;
 	} else {
-		return intel_tile_width_bytes(fb, color_plane);
+		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+		/*
+		 * Display WA #0531: skl,bxt,kbl,glk
+		 *
+		 * Render decompression and plane width > 3840
+		 * combined with horizontal panning requires the
+		 * plane stride to be a multiple of 4. We'll just
+		 * require the entire fb to accommodate that to avoid
+		 * potential runtime errors at plane configuration time.
+		 */
+		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+		    color_plane == 0 && fb->width > 3840)
+			tile_width *= 4;
+
+		return tile_width;
 	}
 }
 
@@ -15705,20 +15720,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		}
 
 		stride_alignment = intel_fb_stride_alignment(fb, i);
-
-		/*
-		 * Display WA #0531: skl,bxt,kbl,glk
-		 *
-		 * Render decompression and plane width > 3840
-		 * combined with horizontal panning requires the
-		 * plane stride to be a multiple of 4. We'll just
-		 * require the entire fb to accommodate that to avoid
-		 * potential runtime errors at plane configuration time.
-		 */
-		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
-		    is_ccs_modifier(fb->modifier))
-			stride_alignment *= 4;
-
 		if (fb->pitches[i] & (stride_alignment - 1)) {
 			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 				      i, fb->pitches[i], stride_alignment);
-- 
2.20.1

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[PATCH v2 04/11] drm/i915/tgl: Gen-12 render decompression

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.

v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++--
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 84 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c437f00c2072..6fec43cdddf4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (color_plane == 1)
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -1944,8 +1948,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
-	return intel_tile_size(to_i915(fb->dev)) /
-		intel_tile_width_bytes(fb, color_plane);
+	switch (fb->modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (color_plane == 1)
+			return 1;
+		/* fall through */
+	default:
+		return intel_tile_size(to_i915(fb->dev)) /
+			intel_tile_width_bytes(fb, color_plane);
+	}
 }
 
 /* Return the tile dimensions in pixel units */
@@ -2044,6 +2055,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2243,7 +2256,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return modifier == DRM_FORMAT_MOD_LINEAR ||
+	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2430,6 +2444,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2450,7 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2461,6 +2476,24 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2481,8 +2514,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2491,7 +2528,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2536,8 +2574,9 @@ static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	u32 tile_width;
 
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	if (is_surface_linear(fb->modifier, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2546,13 +2585,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * To make remapping with linear generally feasible
 		 * we need the stride to be page aligned.
 		 */
-		if (fb->pitches[color_plane] > max_stride)
+		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
 			return intel_tile_size(dev_priv);
 		else
 			return 64;
-	} else {
-		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+	}
 
+	tile_width = intel_tile_width_bytes(fb, color_plane);
+	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2562,12 +2602,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
-		    color_plane == 0 && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+			tile_width *= 4;
+		/*
+		 * The main surface pitch must be padded to a multiple of four
+		 * tile widths.
+		 */
+		else if (INTEL_GEN(dev_priv) >= 12)
 			tile_width *= 4;
-
-		return tile_width;
 	}
+	return tile_width;
 }
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2676,6 +2720,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			int ccs_x, ccs_y;
 
 			intel_tile_dims(fb, i, &tile_width, &tile_height);
+
 			tile_width *= hsub;
 			tile_height *= vsub;
 
@@ -3972,7 +4017,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+	if (is_surface_linear(fb->modifier, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4098,6 +4143,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return PLANE_CTL_TILED_Y |
+		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+		       PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9899,7 +9948,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7a7078d0ba23..866d25d38d04 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -535,6 +535,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->base.dst.x1;
 	int crtc_y = plane_state->base.dst.y1;
@@ -576,8 +577,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		u32 cus_ctl = 0;
@@ -1733,7 +1736,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2145,7 +2149,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2307,6 +2312,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2317,6 +2323,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2525,13 +2534,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a69c19aae5bb..ae58ce066776 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6688,6 +6688,7 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
-- 
2.20.1

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[PATCH v2 05/11] drm/i915: Extract framebufer CCS offset checks into a function

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
 1 file changed, 40 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6fec43cdddf4..e1f5170205bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	int hsub = fb->format->hsub;
+	int vsub = fb->format->vsub;
+	int tile_width, tile_height;
+	int ccs_x, ccs_y;
+	int main_x, main_y;
+
+	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+	tile_width *= hsub;
+	tile_height *= vsub;
+
+	ccs_x = (x * hsub) % tile_width;
+	ccs_y = (y * vsub) % tile_height;
+	main_x = intel_fb->normal[0].x % tile_width;
+	main_y = intel_fb->normal[0].y % tile_height;
+
+	/*
+	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
+	 * x/y offsets must match between CCS and the main surface.
+	 */
+	if (main_x != ccs_x || main_y != ccs_y) {
+		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+			      main_x, main_y,
+			      ccs_x, ccs_y,
+			      intel_fb->normal[0].x,
+			      intel_fb->normal[0].y,
+			      x, y);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
@@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		}
 
 		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			int hsub = fb->format->hsub;
-			int vsub = fb->format->vsub;
-			int tile_width, tile_height;
-			int main_x, main_y;
-			int ccs_x, ccs_y;
-
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
-
-			tile_width *= hsub;
-			tile_height *= vsub;
-
-			ccs_x = (x * hsub) % tile_width;
-			ccs_y = (y * vsub) % tile_height;
-			main_x = intel_fb->normal[0].x % tile_width;
-			main_y = intel_fb->normal[0].y % tile_height;
-
-			/*
-			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
-			 * x/y offsets must match between CCS and the main surface.
-			 */
-			if (main_x != ccs_x || main_y != ccs_y) {
-				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
-					      main_x, main_y,
-					      ccs_x, ccs_y,
-					      intel_fb->normal[0].x,
-					      intel_fb->normal[0].y,
-					      x, y);
-				return -EINVAL;
-			}
+			ret = intel_fb_check_ccs_xy(fb, x, y);
+			if (ret)
+				return ret;
 		}
 
 		/*
-- 
2.20.1

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[PATCH v2 06/11] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1f0fbf0398f6..c4a4e0fdbee5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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[PATCH v2 07/11] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

During framebuffer creation, we pre-compute offsets for 90/270 plane
rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
skip the calculations for other modifiers.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e1f5170205bf..c7e41fb04919 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2784,7 +2784,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb->modifier, i)) {
+		/* Y or Yf modifiers required for 90/270 rotation */
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
-- 
2.20.1

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[PATCH v2 08/11] drm/fb: Extend format_info member arrays to handle four planes

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 include/drm/drm_fourcc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
 		 * triplet @char_per_block, @block_w, @block_h for better
 		 * describing the pixel format.
 		 */
-		u8 cpp[3];
+		u8 cpp[4];
 
 		/**
 		 * @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
 		 * information from their drm_mode_config.get_format_info hook
 		 * if they want the core to be validating the pitch.
 		 */
-		u8 char_per_block[3];
+		u8 char_per_block[4];
 	};
 
 	/**
@@ -113,7 +113,7 @@ struct drm_format_info {
 	 * Block width in pixels, this is intended to be accessed through
 	 * drm_format_info_block_width()
 	 */
-	u8 block_w[3];
+	u8 block_w[4];
 
 	/**
 	 * @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
 	 * Block height in pixels, this is intended to be accessed through
 	 * drm_format_info_block_height()
 	 */
-	u8 block_h[3];
+	u8 block_h[4];
 
 	/** @hsub: Horizontal chroma subsampling factor */
 	u8 hsub;
-- 
2.20.1

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[PATCH v2 09/11] Gen-12 display can decompress surfaces compressed by the media engine.

[Radhakrishna Sripada]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
support media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

From DK:
Separate modifier array for planes that cannot decompress media (Ville)

v3: Support planar formats

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 237 +++++++++++++-----
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  44 +++-
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 4 files changed, 220 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c7e41fb04919..21db6539de64 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (color_plane == 3)
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		if (color_plane == 1)
 			return 64;
@@ -2256,8 +2260,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR ||
-	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+	switch (modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+		return true;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return color_plane == 1;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return color_plane == 1 || color_plane == 3;
+	default:
+		return false;
+	}
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2445,6 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2492,6 +2505,10 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
+	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
+	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
 static const struct drm_format_info *
@@ -2529,6 +2546,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -2592,7 +2610,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	}
 
 	tile_width = intel_tile_width_bytes(fb, color_plane);
-	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+	if (is_ccs_modifier(fb->modifier)) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2602,7 +2620,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
 			tile_width *= 4;
 		/*
 		 * The main surface pitch must be padded to a multiple of four
@@ -2682,25 +2700,71 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+		static const struct {
+			int cpp[4];
+			int vsub[4];
+			int hsub[4];
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
+
+		*hsub = mc_ccs_subsampling.hsub[color_plane];
+		*vsub = mc_ccs_subsampling.vsub[color_plane];
+	} else {
+		*hsub = fb->format->hsub;
+		*vsub = fb->format->vsub;
+	}
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+	int hsub, vsub;
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	*w = fb->width / hsub;
+	*h = fb->height / vsub;
+}
+
+static bool is_ccs_plane(u64 modifier, int color_plane)
+{
+	if (!is_ccs_modifier(modifier))
+		return false;
+	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+		return color_plane == 3 || color_plane == 1;
+	else
+		return color_plane == 1;
+}
+
 static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int color_plane, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int hsub, vsub;
+	int hsub_main, vsub_main;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	if (!is_ccs_plane(fb->modifier, color_plane))
+		return 0;
+
+	intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb, color_plane - 1);
+
+	hsub /= hsub_main;
+	vsub /= vsub_main;
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+	main_x = intel_fb->normal[color_plane - 1].x % tile_width;
+	main_y = intel_fb->normal[color_plane - 1].y % tile_height;
 
 	/*
 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2710,8 +2774,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[color_plane - 1].x,
+			      intel_fb->normal[color_plane - 1].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2739,8 +2803,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int ret;
 
 		cpp = fb->format->cpp[i];
-		width = drm_framebuffer_plane_width(fb->width, fb, i);
-		height = drm_framebuffer_plane_height(fb->height, fb, i);
+		intel_fb_plane_dims(&width, &height, fb, i);
 
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
@@ -2749,11 +2812,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			ret = intel_fb_check_ccs_xy(fb, x, y);
-			if (ret)
-				return ret;
-		}
+		ret = intel_fb_check_ccs_xy(fb, i, x, y);
+		if (ret)
+			return ret;
 
 		/*
 		 * The fence (if used) is aligned to the start of the object
@@ -3371,6 +3432,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
 			return 5120;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		/* FIXME AUX plane? */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -3430,16 +3492,18 @@ static int icl_max_plane_height(void)
 }
 
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
-					   int main_x, int main_y, u32 main_offset)
+					   int main_x, int main_y, u32 main_offset,
+					   int aux_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int aux_x = plane_state->color_plane[1].x;
-	int aux_y = plane_state->color_plane[1].y;
-	u32 aux_offset = plane_state->color_plane[1].offset;
-	u32 alignment = intel_surf_alignment(fb, 1);
-
+	int hsub;
+	int vsub;
+	int aux_x = plane_state->color_plane[aux_plane].x;
+	int aux_y = plane_state->color_plane[aux_plane].y;
+	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+	u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3451,7 +3515,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 
 		x = aux_x / hsub;
 		y = aux_y / vsub;
-		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
 							       aux_offset, aux_offset - alignment);
 		aux_x = x * hsub + aux_x % hsub;
 		aux_y = y * vsub + aux_y % vsub;
@@ -3460,9 +3524,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 	if (aux_x != main_x || aux_y != main_y)
 		return false;
 
-	plane_state->color_plane[1].offset = aux_offset;
-	plane_state->color_plane[1].x = aux_x;
-	plane_state->color_plane[1].y = aux_y;
+	plane_state->color_plane[aux_plane].offset = aux_offset;
+	plane_state->color_plane[aux_plane].x = aux_x;
+	plane_state->color_plane[aux_plane].y = aux_y;
 
 	return true;
 }
@@ -3536,7 +3600,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * they match with the main surface x/y offsets.
 	 */
 	if (is_ccs_modifier(fb->modifier)) {
-		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 1)) {
 			if (offset == 0)
 				break;
 
@@ -3569,7 +3633,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	unsigned int rotation = plane_state->base.rotation;
-	int max_width = skl_max_plane_width(fb, 1, rotation);
+	int uv = is_ccs_modifier(fb->modifier) ? 2 : 1;
+	int max_width = skl_max_plane_width(fb, uv, rotation);
 	int max_height = 4096;
 	int x = plane_state->base.src.x1 >> 17;
 	int y = plane_state->base.src.y1 >> 17;
@@ -3577,8 +3642,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->base.src) >> 17;
 	u32 offset;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	intel_add_fb_offsets(&x, &y, plane_state, uv);
+	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv);
 
 	/* FIXME not quite sure how/if these apply to the chroma plane */
 	if (w > max_width || h > max_height) {
@@ -3587,9 +3652,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 		return -EINVAL;
 	}
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x;
-	plane_state->color_plane[1].y = y;
+	if (is_ccs_modifier(fb->modifier)) {
+		int aux_offset = plane_state->color_plane[3].offset;
+		int alignment = intel_surf_alignment(fb, uv);
+
+		if (offset > aux_offset) {
+			int hsub, vsub;
+			int main_x = x, main_y = y;
+
+			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, uv);
+			x = main_x / hsub;
+			y = main_y / vsub;
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+								   offset,
+								   aux_offset & ~(alignment - 1));
+			x = x * hsub + main_x % hsub;
+			y = y * vsub + main_y % vsub;
+		}
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+			if (offset == 0)
+				break;
+
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+								   offset, offset - alignment);
+		}
+
+		if (x != plane_state->color_plane[3].x || y != plane_state->color_plane[3].y) {
+			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+			return -EINVAL;
+		}
+	}
+
+	plane_state->color_plane[uv].offset = offset;
+	plane_state->color_plane[uv].x = x;
+	plane_state->color_plane[uv].y = y;
 
 	return 0;
 }
@@ -3599,19 +3696,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int src_x = plane_state->base.src.x1 >> 16;
 	int src_y = plane_state->base.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
 	u32 offset;
+	int ccs;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
-	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+	for (ccs = 1; ccs < fb->format->num_planes; ccs += 2) {
+		int hsub, vsub;
+		int main_hsub, main_vsub;
+		int x, y;
+
+		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, ccs - 1);
 
+		hsub /= main_hsub;
+		vsub /= main_vsub;
+		x = src_x / hsub;
+		y = src_y / vsub;
+
+		intel_add_fb_offsets(&x, &y, plane_state, ccs);
+		offset = intel_plane_compute_aligned_offset(&x, &y,
+							    plane_state, ccs);
+		plane_state->color_plane[ccs].offset = offset;
+		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+	}
 	return 0;
 }
 
@@ -3619,6 +3727,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int ret;
+	bool needs_aux = false;
 
 	ret = intel_plane_compute_gtt(plane_state);
 	if (ret)
@@ -3628,21 +3737,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 		return 0;
 
 	/*
-	 * Handle the AUX surface first since
-	 * the main surface setup depends on it.
+	 * Handle the AUX surface first since the main surface setup depends on
+	 * it.
 	 */
-	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
-		ret = skl_check_nv12_aux_surface(plane_state);
+	if (is_ccs_modifier(fb->modifier)) {
+		needs_aux = true;
+		ret = skl_check_ccs_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else if (is_ccs_modifier(fb->modifier)) {
-		ret = skl_check_ccs_aux_surface(plane_state);
+	}
+
+	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+		needs_aux = true;
+		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else {
-		plane_state->color_plane[1].offset = ~0xfff;
-		plane_state->color_plane[1].x = 0;
-		plane_state->color_plane[1].y = 0;
+	}
+
+	if (!needs_aux) {
+		int i;
+
+		for (i = 1; i < fb->format->num_planes; i++) {
+			plane_state->color_plane[i].offset = ~0xfff;
+			plane_state->color_plane[i].x = 0;
+			plane_state->color_plane[i].y = 0;
+		}
 	}
 
 	ret = skl_check_main_surface(plane_state);
@@ -4160,6 +4279,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y |
 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9964,6 +10085,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b0a646f0170..60a040c39d97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -530,7 +530,7 @@ struct intel_plane_state {
 		 */
 		u32 stride;
 		int x, y;
-	} color_plane[2];
+	} color_plane[4];
 
 	/* plane control register */
 	u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 866d25d38d04..ad28ee94c968 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1737,7 +1737,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2149,7 +2150,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
@@ -2305,10 +2315,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+	return plane_id < PLANE_SPRITE4;
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (!gen12_plane_supports_mc_ccs(plane->id))
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2326,14 +2347,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_P010:
 	case DRM_FORMAT_P012:
 	case DRM_FORMAT_P016:
@@ -2470,6 +2494,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	}
 }
 
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+	if (gen12_plane_supports_mc_ccs(plane_id))
+		return gen12_plane_format_modifiers_mc_ccs;
+	else
+		return gen12_plane_format_modifiers_rc_ccs;
+}
+
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2536,7 +2568,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		modifiers = gen12_plane_format_modifiers_ccs;
+		modifiers = gen12_get_plane_modifiers(plane_id);
 		plane_funcs = &gen12_plane_funcs;
 	} else {
 		if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae58ce066776..65a1f59c3170 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6696,6 +6696,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.20.1

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[PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Radhakrishna Sripada]

Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.

V2: Description changes as suggested by Rafael.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index c4a4e0fdbee5..99c61ee9b61f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,17 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
+ * main surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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[PATCH v2 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Radhakrishna Sripada]

Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.

v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
    plane config(Matt). Fix Lookup error.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 38 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  3 ++
 drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++++-
 drivers/gpu/drm/i915/i915_reg.h               | 12 ++++++
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 21db6539de64..5c5dadcd02d1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1916,6 +1916,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 64;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		if (color_plane == 1)
 			return 64;
 		/* fall through */
@@ -2060,6 +2061,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2264,6 +2266,7 @@ static bool is_surface_linear(u64 modifier, int color_plane)
 	case DRM_FORMAT_MOD_LINEAR:
 		return true;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return color_plane == 1;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return color_plane == 1 || color_plane == 3;
@@ -2458,6 +2461,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2511,6 +2515,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface. Additional surface is used to pass the Clear Color
+ * structure for the driver to program the DE.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2538,6 +2561,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+		return lookup_format_info(gen12_ccs_cc_formats,
+					  ARRAY_SIZE(gen12_ccs_cc_formats),
+					  cmd->pixel_format);
 	default:
 		return NULL;
 	}
@@ -2547,6 +2574,7 @@ bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -4274,6 +4302,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y |
@@ -14539,6 +14568,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 
 	plane_state->vma = vma;
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+								  fb->offsets[2] >> PAGE_SHIFT));
+
+		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
+		kunmap_atomic(ccaddr);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 60a040c39d97..58772a625f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -579,6 +579,9 @@ struct intel_plane_state {
 	u32 slave;
 
 	struct drm_intel_sprite_colorkey ckey;
+
+	/* Clear Color Value */
+	u64 ccval;
 };
 
 struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index ad28ee94c968..fae624887156 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
+	u64 ccval = plane_state->ccval;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 		icl_program_input_csc(plane, crtc_state, plane_state);
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		intel_uncore_write64_fw(&dev_priv->uncore,
+					PLANE_CC_VAL(pipe, plane_id), ccval);
+
 	skl_write_plane_wm(plane, crtc_state);
 
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 
 static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		break;
 	default:
 		return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65a1f59c3170..a68c75db5653 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6729,6 +6729,8 @@ enum {
 #define _PLANE_KEYMAX_1_A			0x701a0
 #define _PLANE_KEYMAX_2_A			0x702a0
 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
+#define _PLANE_CC_VAL_1_A			0x701b4
+#define _PLANE_CC_VAL_2_A			0x702b4
 #define _PLANE_AUX_DIST_1_A			0x701c0
 #define _PLANE_AUX_DIST_2_A			0x702c0
 #define _PLANE_AUX_OFFSET_1_A			0x701c4
@@ -6768,6 +6770,16 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
 
+#define _PLANE_CC_VAL_1_B			0x711b4
+#define _PLANE_CC_VAL_2_B			0x712b4
+#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET		4
+#define CC_VAL_HIGHER_OFFSET		5
+
 /* Input CSC Register Definitions */
 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
-- 
2.20.1

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✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev2)

[Patchwork]

== Series Details ==

Series: Clear Color Support for TGL Render Decompression (rev2)
URL   : https://patchwork.freedesktop.org/series/66814/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4706ae48bc8d drm/framebuffer: Format modifier for Intel Gen-12 render compression
526735a4860b drm/i915: Use intel_tile_height() instead of re-implementing
ce9382f23e62 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
dbdf41118454 drm/i915/tgl: Gen-12 render decompression
f59bf40903d1 drm/i915: Extract framebufer CCS offset checks into a function
bc2c3819f8a9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
13725d0dc466 drm/i915: Skip rotated offset adjustment for unsupported modifiers
5953c08cd2f0 drm/fb: Extend format_info member arrays to handle four planes
cacd4434d14b Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2704:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2711:
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };

total: 0 errors, 3 warnings, 0 checks, 509 lines checked
a4463972aec5 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
07177893b7b4 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:222: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#222: FILE: drivers/gpu/drm/i915/i915_reg.h:6777:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 172 lines checked

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✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev2)

[Patchwork]

== Series Details ==

Series: Clear Color Support for TGL Render Decompression (rev2)
URL   : https://patchwork.freedesktop.org/series/66814/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6945 -> Patchwork_14510
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14510 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14510, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14510:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-blb-e6850:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-x1275:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bwr-2160:        [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6260u:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2600:        [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-gvtdvm:      [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-peppy:       [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2520m:       [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-pnv-d510:        [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8109u:       [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-7500u:       [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-gdg-551:         [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cml-u2:          [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bxt-dsi:         [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u3:          [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-iommu:       [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6700k2:      [PASS][75] -> [FAIL][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - {fi-icl-u4}:        [PASS][77] -> [FAIL][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-dsi}:       [PASS][79] -> [FAIL][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u}:         [PASS][81] -> [FAIL][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u2}:        [PASS][83] -> [FAIL][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-h}:         [PASS][85] -> [FAIL][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cml-h/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cml-h/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-kbl-soraka}:    [PASS][87] -> [FAIL][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-s}:         [PASS][89] -> [FAIL][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_14510 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u2:          [PASS][91] -> [INCOMPLETE][92] ([fdo#107713] / [fdo#109100])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u2/igt@gem_ctx_create@basic-files.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u2/igt@gem_ctx_create@basic-files.html

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [PASS][93] -> [DMESG-WARN][94] ([fdo#107724]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-apl-guc:         [PASS][95] -> [DMESG-WARN][96] ([fdo#108566])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - fi-icl-u3:          [DMESG-WARN][97] ([fdo#107724]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [DMESG-WARN][99] ([fdo#107724] / [fdo#111214]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-icl-u3/igt@i915_module_load@reload.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_hangcheck:
    - fi-kbl-7500u:       [INCOMPLETE][101] ([fdo#108744]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][103] ([fdo#107718]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][105] ([fdo#111407]) -> [FAIL][106] ([fdo#111045] / [fdo#111096])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6945/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 47)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6945 -> Patchwork_14510

  CI-20190529: 20190529
  CI_DRM_6945: f11d819264a3fab210498a4920ef34a891da39e0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5197: aa534ff47fd2f455c8be9e59eae807695b87fcdd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14510: 07177893b7b448fdc913c88c3540dd59c756d4be @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

07177893b7b4 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
a4463972aec5 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
cacd4434d14b Gen-12 display can decompress surfaces compressed by the media engine.
5953c08cd2f0 drm/fb: Extend format_info member arrays to handle four planes
13725d0dc466 drm/i915: Skip rotated offset adjustment for unsupported modifiers
bc2c3819f8a9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
f59bf40903d1 drm/i915: Extract framebufer CCS offset checks into a function
dbdf41118454 drm/i915/tgl: Gen-12 render decompression
ce9382f23e62 drm/i915:

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14510/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Radhakrishna Sripada]

Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.

v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
    plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  3 ++
 drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++-
 drivers/gpu/drm/i915/i915_reg.h               | 12 +++++
 4 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4971c296f951..822237e98f00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 64;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+		if (color_plane == 1 || color_plane == 2)
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
 		return true;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return color_plane == 1;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+		return color_plane == 1 || color_plane == 2;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return color_plane == 1 || color_plane == 3;
 	default:
@@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface. Additional surface is used to pass the Clear Color
+ * structure for the driver to program the DE.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+		return lookup_format_info(gen12_ccs_cc_formats,
+					  ARRAY_SIZE(gen12_ccs_cc_formats),
+					  cmd->pixel_format);
 	default:
 		return NULL;
 	}
@@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
 		return false;
 	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
 		return color_plane == 3 || color_plane == 1;
+	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		return color_plane == 1 || color_plane == 2;
 	else
 		return color_plane == 1;
 }
@@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		cpp = fb->format->cpp[i];
 		intel_fb_plane_dims(&width, &height, fb, i);
 
+		/*
+		 * Plane 2 of Render Compression with Clear Color fb modifier is consumed
+		 * by the driver and not passed to DE. Skip the arithmetic related to
+		 * alignment and offset calculation.
+		 */
+		if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+			continue;
+
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
 			DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
@@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y |
@@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 
 	plane_state->vma = vma;
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+								  fb->offsets[2] >> PAGE_SHIFT));
+
+		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
+		kunmap_atomic(ccaddr);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5998b959225c..77d3f6b634b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -579,6 +579,9 @@ struct intel_plane_state {
 	u32 planar_slave;
 
 	struct drm_intel_sprite_colorkey ckey;
+
+	/* Clear Color Value */
+	u64 ccval;
 };
 
 struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index ce79373154fc..24ae8bf9744d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
+	u64 ccval = plane_state->ccval;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 		icl_program_input_csc(plane, crtc_state, plane_state);
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		intel_uncore_write64_fw(&dev_priv->uncore,
+					PLANE_CC_VAL(pipe, plane_id), ccval);
+
 	skl_write_plane_wm(plane, crtc_state);
 
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 
 static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		break;
 	default:
 		return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0abf9a3917ed..01023fc880c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6734,6 +6734,8 @@ enum {
 #define _PLANE_KEYMAX_1_A			0x701a0
 #define _PLANE_KEYMAX_2_A			0x702a0
 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
+#define _PLANE_CC_VAL_1_A			0x701b4
+#define _PLANE_CC_VAL_2_A			0x702b4
 #define _PLANE_AUX_DIST_1_A			0x701c0
 #define _PLANE_AUX_DIST_2_A			0x702c0
 #define _PLANE_AUX_OFFSET_1_A			0x701c4
@@ -6773,6 +6775,16 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
 
+#define _PLANE_CC_VAL_1_B			0x711b4
+#define _PLANE_CC_VAL_2_B			0x712b4
+#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET		4
+#define CC_VAL_HIGHER_OFFSET		5
+
 /* Input CSC Register Definitions */
 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
-- 
2.20.1

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✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev3)

[Patchwork]

== Series Details ==

Series: Clear Color Support for TGL Render Decompression (rev3)
URL   : https://patchwork.freedesktop.org/series/66814/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fa405794ca6b drm/framebuffer: Format modifier for Intel Gen-12 render compression
dc89777e0306 drm/i915: Use intel_tile_height() instead of re-implementing
a54ed04cc4d8 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
9d840b1281fb drm/i915/tgl: Gen-12 render decompression
d752e75805e5 drm/i915: Extract framebufer CCS offset checks into a function
8f42a26a0fb0 drm/framebuffer: Format modifier for Intel Gen-12 media compression
3db40490ca8f drm/i915: Skip rotated offset adjustment for unsupported modifiers
32f56db73bf2 drm/fb: Extend format_info member arrays to handle four planes
6e5a61ea78da Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2704:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2711:
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };

total: 0 errors, 3 warnings, 0 checks, 509 lines checked
f872ae0f29f7 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
82473beafe08 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:251: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#251: FILE: drivers/gpu/drm/i915/i915_reg.h:6782:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 198 lines checked

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✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev3)

[Patchwork]

== Series Details ==

Series: Clear Color Support for TGL Render Decompression (rev3)
URL   : https://patchwork.freedesktop.org/series/66814/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14576
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14576 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14576, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14576:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-blb-e6850:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-x1275:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bwr-2160:        [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6260u:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2600:        [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-gvtdvm:      [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-peppy:       [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u2:          [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2520m:       [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8109u:       [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-7500u:       [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-gdg-551:         [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cml-u2:          [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-iommu:       [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770r:       [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6700k2:      [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - {fi-icl-u4}:        [PASS][75] -> [FAIL][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-dsi}:       [PASS][77] -> [FAIL][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-kbl-soraka}:    [PASS][79] -> [FAIL][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-guc}:       NOTRUN -> [FAIL][81]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-s}:         [PASS][82] -> [FAIL][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_14576 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [PASS][84] -> [INCOMPLETE][85] ([fdo#107713] / [fdo#109100])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [PASS][86] -> [INCOMPLETE][87] ([fdo#103927] / [fdo#111381])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][88] -> [FAIL][89] ([fdo#111045] / [fdo#111096])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6973 -> Patchwork_14576

  CI-20190529: 20190529
  CI_DRM_6973: 7462c58bba0fb6e85bd380591c3fd86e298c0f95 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14576: 82473beafe084fb5633fa5fe090cf33a9fe5983e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

82473beafe08 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
f872ae0f29f7 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
6e5a61ea78da Gen-12 display can decompress surfaces compressed by the media engine.
32f56db73bf2 drm/fb: Extend format_info member arrays to handle four planes
3db40490ca8f drm/i915: Skip rotated offset adjustment for unsupported modifiers
8f42a26a0fb0 drm/framebuffer: Format modifier for Intel Gen-12 media compression
d752e75805e5 drm/i915: Extract framebufer CCS offset checks into a function
9d840b1281fb drm/i915/tgl: Gen-12 render decompression
a54ed04cc4d8 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
dc89777e0306 drm/i915: Use intel_tile_height() instead of re-implementing
fa405794ca6b drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Matt Roper]

On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
> 
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
>     plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  3 ++
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++-
>  drivers/gpu/drm/i915/i915_reg.h               | 12 +++++
>  4 files changed, 77 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4971c296f951..822237e98f00 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		if (color_plane == 1)
>  			return 64;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> +		if (color_plane == 1 || color_plane == 2)
> +			return 64;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  			return 256 * 1024;
>  		return 0;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
>  		return true;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return color_plane == 1;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> +		return color_plane == 1 || color_plane == 2;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return color_plane == 1 || color_plane == 3;
>  	default:
> @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
>  	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
>  };
>  
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> + * the main surface. Additional surface is used to pass the Clear Color
> + * structure for the driver to program the DE.
> + */

Rather than duplicating the previous comment's text I'd just say

"Same as gen12_ccs_formats[] above, but with an additional surface used
to pass..."

> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  		return lookup_format_info(gen12_ccs_formats,
>  					  ARRAY_SIZE(gen12_ccs_formats),
>  					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> +		return lookup_format_info(gen12_ccs_cc_formats,
> +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> +					  cmd->pixel_format);
>  	default:
>  		return NULL;
>  	}
> @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier)
>  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
> @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
>  		return false;
>  	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
>  		return color_plane == 3 || color_plane == 1;
> +	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +		return color_plane == 1 || color_plane == 2;
>  	else
>  		return color_plane == 1;
>  }
> @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		cpp = fb->format->cpp[i];
>  		intel_fb_plane_dims(&width, &height, fb, i);
>  
> +		/*
> +		 * Plane 2 of Render Compression with Clear Color fb modifier is consumed
> +		 * by the driver and not passed to DE. Skip the arithmetic related to
> +		 * alignment and offset calculation.
> +		 */
> +		if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +			continue;
> +

We might as well do this before the cpp and width/height assignments too?

Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)?  We seem
to rely on that after kmap'ing below.


Matt

>  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
>  		if (ret) {
>  			DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
> @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return PLANE_CTL_TILED_Y |
> @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>  
>  	plane_state->vma = vma;
>  
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> +		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> +								  fb->offsets[2] >> PAGE_SHIFT));
> +
> +		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> +		kunmap_atomic(ccaddr);
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5998b959225c..77d3f6b634b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -579,6 +579,9 @@ struct intel_plane_state {
>  	u32 planar_slave;
>  
>  	struct drm_intel_sprite_colorkey ckey;
> +
> +	/* Clear Color Value */
> +	u64 ccval;
>  };
>  
>  struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index ce79373154fc..24ae8bf9744d 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
>  	u32 keymsk, keymax;
> +	u64 ccval = plane_state->ccval;
>  
>  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>  
> @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
>  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
>  		icl_program_input_csc(plane, crtc_state, plane_state);
>  
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +		intel_uncore_write64_fw(&dev_priv->uncore,
> +					PLANE_CC_VAL(pipe, plane_id), ccval);
> +
>  	skl_write_plane_wm(plane, crtc_state);
>  
>  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
>  
>  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		break;
>  	default:
>  		return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0abf9a3917ed..01023fc880c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6734,6 +6734,8 @@ enum {
>  #define _PLANE_KEYMAX_1_A			0x701a0
>  #define _PLANE_KEYMAX_2_A			0x702a0
>  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> +#define _PLANE_CC_VAL_1_A			0x701b4
> +#define _PLANE_CC_VAL_2_A			0x702b4
>  #define _PLANE_AUX_DIST_1_A			0x701c0
>  #define _PLANE_AUX_DIST_2_A			0x702c0
>  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> @@ -6773,6 +6775,16 @@ enum {
>  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
>  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
>  
> +#define _PLANE_CC_VAL_1_B			0x711b4
> +#define _PLANE_CC_VAL_2_B			0x712b4
> +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> +#define PLANE_CC_VAL(pipe, plane)	\
> +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +
> +#define CC_VAL_LOWER_OFFSET		4
> +#define CC_VAL_HIGHER_OFFSET		5
> +
>  /* Input CSC Register Definitions */
>  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
>  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> -- 
> 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Dhinakaran Pandiyan]

On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
> a new modifier as the driver needs to know the surface was compressed by render engine.
> 
> V2: Description changes as suggested by Rafael.
> 
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index c4a4e0fdbee5..99c61ee9b61f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,17 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>  
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
> + * and at index 1. 

Clear color data is fixed size - 64b, that should be in the documentation here.


> The clear color is stored at index 2, and the pitch should
> + * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
That's a CCS cache line, not a CCS_CC cache line, right?

> + * main surface. The main surface pitch is required to be a multiple of 4 tile
> + * widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *

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Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Dhinakaran Pandiyan]

On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > linear and has 4 bits of data for each main surface cache line pair, a
> > ratio of 1:256. Additional Clear Color information is passed from the
> > user-space through an offset in the GEM BO. Add a new modifier to identify
> > and parse new Clear Color information and extend Gen12 render decompression
> > functionality to the newly added modifier.
> > 
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> >     plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++++++++++
> >  .../drm/i915/display/intel_display_types.h    |  3 ++
> >  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++-
> >  drivers/gpu/drm/i915/i915_reg.h               | 12 +++++
> >  4 files changed, 77 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		if (color_plane == 1)
> >  			return 64;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		if (color_plane == 1 || color_plane == 2)
> > +			return 64;
> > +		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> >  			return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  			return 256 * 1024;
> >  		return 0;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return 16 * 1024;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
> >  		return true;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return color_plane == 1;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		return color_plane == 1 || color_plane == 2;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return color_plane == 1 || color_plane == 3;
> >  	default:
> > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return I915_TILING_Y;
> >  	default:
> >  		return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> >  	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> >  };
> >  
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> > + * the main surface. Additional surface is used to pass the Clear Color
> > + * structure for the driver to program the DE.
> > + */
> 
> Rather than duplicating the previous comment's text I'd just say
> 
> "Same as gen12_ccs_formats[] above, but with an additional surface used
> to pass..."
> 
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +};
> > +
> >  static const struct drm_format_info *
> >  lookup_format_info(const struct drm_format_info formats[],
> >  		   int num_formats, u32 format)
> > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  		return lookup_format_info(gen12_ccs_formats,
> >  					  ARRAY_SIZE(gen12_ccs_formats),
> >  					  cmd->pixel_format);
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		return lookup_format_info(gen12_ccs_cc_formats,
> > +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> > +					  cmd->pixel_format);
> >  	default:
> >  		return NULL;
> >  	}
> > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier)
> >  {
> >  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> >  }
> > @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
> >  		return false;
> >  	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> >  		return color_plane == 3 || color_plane == 1;
> > +	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +		return color_plane == 1 || color_plane == 2;
> >  	else
> >  		return color_plane == 1;
> >  }
> > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  		cpp = fb->format->cpp[i];
> >  		intel_fb_plane_dims(&width, &height, fb, i);
> >  
> > +		/*
> > +		 * Plane 2 of Render Compression with Clear Color fb modifier is consumed
> > +		 * by the driver and not passed to DE. Skip the arithmetic related to
> > +		 * alignment and offset calculation.
> > +		 */
> > +		if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +			continue;
> > +
> 
> We might as well do this before the cpp and width/height assignments too?
> 
> Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)?  We seem
> to rely on that after kmap'ing below.

I am wondering if it needs to be page aligned. Since Clear Color data follows a linear CCS, would a
64B alignment suffice?

-DK

> 
> 
> Matt
> 
> >  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
> >  		if (ret) {
> >  			DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
> > @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		return PLANE_CTL_TILED_Y;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return PLANE_CTL_TILED_Y |
> > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> >  
> >  	plane_state->vma = vma;
> >  
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > +		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > +								  fb->offsets[2] >> PAGE_SHIFT));
> > +
> > +		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> > +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> > +		kunmap_atomic(ccaddr);
> > +	}
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5998b959225c..77d3f6b634b0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -579,6 +579,9 @@ struct intel_plane_state {
> >  	u32 planar_slave;
> >  
> >  	struct drm_intel_sprite_colorkey ckey;
> > +
> > +	/* Clear Color Value */
> > +	u64 ccval;
> >  };
> >  
> >  struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index ce79373154fc..24ae8bf9744d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> >  	u32 plane_color_ctl = 0;
> >  	unsigned long irqflags;
> >  	u32 keymsk, keymax;
> > +	u64 ccval = plane_state->ccval;
> >  
> >  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >  
> > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> >  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> >  		icl_program_input_csc(plane, crtc_state, plane_state);
> >  
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +		intel_uncore_write64_fw(&dev_priv->uncore,
> > +					PLANE_CC_VAL(pipe, plane_id), ccval);
> > +
> >  	skl_write_plane_wm(plane, crtc_state);
> >  
> >  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> > @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> >  		return -EINVAL;
> >  	}
> > @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> >  static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> >  
> >  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		break;
> >  	default:
> >  		return false;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0abf9a3917ed..01023fc880c8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6734,6 +6734,8 @@ enum {
> >  #define _PLANE_KEYMAX_1_A			0x701a0
> >  #define _PLANE_KEYMAX_2_A			0x702a0
> >  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> > +#define _PLANE_CC_VAL_1_A			0x701b4
> > +#define _PLANE_CC_VAL_2_A			0x702b4
> >  #define _PLANE_AUX_DIST_1_A			0x701c0
> >  #define _PLANE_AUX_DIST_2_A			0x702c0
> >  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> > @@ -6773,6 +6775,16 @@ enum {
> >  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
> >  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
> >  
> > +#define _PLANE_CC_VAL_1_B			0x711b4
> > +#define _PLANE_CC_VAL_2_B			0x712b4
> > +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> > +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> > +#define PLANE_CC_VAL(pipe, plane)	\
> > +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> > +
> > +#define CC_VAL_LOWER_OFFSET		4
> > +#define CC_VAL_HIGHER_OFFSET		5
> > +
> >  /* Input CSC Register Definitions */
> >  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
> >  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> > -- 
> > 2.20.1
> > 
> 
> 

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Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Matt Roper]

On Fri, Oct 04, 2019 at 05:17:07PM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > > linear and has 4 bits of data for each main surface cache line pair, a
> > > ratio of 1:256. Additional Clear Color information is passed from the
> > > user-space through an offset in the GEM BO. Add a new modifier to identify
> > > and parse new Clear Color information and extend Gen12 render decompression
> > > functionality to the newly added modifier.
> > > 
> > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > >     plane config(Matt). Fix Lookup error.
> > > v3: Fix the panic while running kms_cube
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++++++++++
> > >  .../drm/i915/display/intel_display_types.h    |  3 ++
> > >  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++-
> > >  drivers/gpu/drm/i915/i915_reg.h               | 12 +++++
> > >  4 files changed, 77 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 4971c296f951..822237e98f00 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > >  		if (color_plane == 1)
> > >  			return 64;
> > >  		/* fall through */
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > +		if (color_plane == 1 || color_plane == 2)
> > > +			return 64;
> > > +		/* fall through */
> > >  	case I915_FORMAT_MOD_Y_TILED:
> > >  		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> > >  			return 128;
> > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > >  			return 256 * 1024;
> > >  		return 0;
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >  		return 16 * 1024;
> > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
> > >  		return true;
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > >  		return color_plane == 1;
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > +		return color_plane == 1 || color_plane == 2;
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > >  		return color_plane == 1 || color_plane == 3;
> > >  	default:
> > > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >  		return I915_TILING_Y;
> > >  	default:
> > >  		return I915_TILING_NONE;
> > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> > >  	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > >  };
> > >  
> > > +/*
> > > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> > > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> > > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> > > + * the main surface. Additional surface is used to pass the Clear Color
> > > + * structure for the driver to program the DE.
> > > + */
> > 
> > Rather than duplicating the previous comment's text I'd just say
> > 
> > "Same as gen12_ccs_formats[] above, but with an additional surface used
> > to pass..."
> > 
> > > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > +};
> > > +
> > >  static const struct drm_format_info *
> > >  lookup_format_info(const struct drm_format_info formats[],
> > >  		   int num_formats, u32 format)
> > > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> > >  		return lookup_format_info(gen12_ccs_formats,
> > >  					  ARRAY_SIZE(gen12_ccs_formats),
> > >  					  cmd->pixel_format);
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > +		return lookup_format_info(gen12_ccs_cc_formats,
> > > +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> > > +					  cmd->pixel_format);
> > >  	default:
> > >  		return NULL;
> > >  	}
> > > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier)
> > >  {
> > >  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > >  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > >  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > >  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > >  }
> > > @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
> > >  		return false;
> > >  	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> > >  		return color_plane == 3 || color_plane == 1;
> > > +	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > > +		return color_plane == 1 || color_plane == 2;
> > >  	else
> > >  		return color_plane == 1;
> > >  }
> > > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> > >  		cpp = fb->format->cpp[i];
> > >  		intel_fb_plane_dims(&width, &height, fb, i);
> > >  
> > > +		/*
> > > +		 * Plane 2 of Render Compression with Clear Color fb modifier is consumed
> > > +		 * by the driver and not passed to DE. Skip the arithmetic related to
> > > +		 * alignment and offset calculation.
> > > +		 */
> > > +		if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > > +			continue;
> > > +
> > 
> > We might as well do this before the cpp and width/height assignments too?
> > 
> > Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)?  We seem
> > to rely on that after kmap'ing below.
> 
> I am wondering if it needs to be page aligned. Since Clear Color data follows a linear CCS, would a
> 64B alignment suffice?
> 
> -DK

The kmap_atomic() farther down gives you a pointer to the beginning of
the page that holds the CC.  So if you don't require page alignment,
you'll just need to account for that when extracting ccval below.


Matt

> 
> > 
> > 
> > Matt
> > 
> > >  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
> > >  		if (ret) {
> > >  			DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
> > > @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > >  	case I915_FORMAT_MOD_Y_TILED:
> > >  		return PLANE_CTL_TILED_Y;
> > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > >  		return PLANE_CTL_TILED_Y |
> > > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> > >  
> > >  	plane_state->vma = vma;
> > >  
> > > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > > +		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > > +								  fb->offsets[2] >> PAGE_SHIFT));
> > > +
> > > +		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> > > +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> > > +		kunmap_atomic(ccaddr);
> > > +	}
> > > +
> > >  	return 0;
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5998b959225c..77d3f6b634b0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -579,6 +579,9 @@ struct intel_plane_state {
> > >  	u32 planar_slave;
> > >  
> > >  	struct drm_intel_sprite_colorkey ckey;
> > > +
> > > +	/* Clear Color Value */
> > > +	u64 ccval;
> > >  };
> > >  
> > >  struct intel_initial_plane_config {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index ce79373154fc..24ae8bf9744d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> > >  	u32 plane_color_ctl = 0;
> > >  	unsigned long irqflags;
> > >  	u32 keymsk, keymax;
> > > +	u64 ccval = plane_state->ccval;
> > >  
> > >  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > >  
> > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> > >  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > >  		icl_program_input_csc(plane, crtc_state, plane_state);
> > >  
> > > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > > +		intel_uncore_write64_fw(&dev_priv->uncore,
> > > +					PLANE_CC_VAL(pipe, plane_id), ccval);
> > > +
> > >  	skl_write_plane_wm(plane, crtc_state);
> > >  
> > >  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> > > @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> > >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> > > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> > >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> > >  		return -EINVAL;
> > >  	}
> > > @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> > >  static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> > >  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > >  	I915_FORMAT_MOD_Y_TILED,
> > >  	I915_FORMAT_MOD_X_TILED,
> > >  	DRM_FORMAT_MOD_LINEAR,
> > > @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> > >  
> > >  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> > >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > >  	I915_FORMAT_MOD_Y_TILED,
> > >  	I915_FORMAT_MOD_X_TILED,
> > >  	DRM_FORMAT_MOD_LINEAR,
> > > @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > >  	case I915_FORMAT_MOD_X_TILED:
> > >  	case I915_FORMAT_MOD_Y_TILED:
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >  		break;
> > >  	default:
> > >  		return false;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0abf9a3917ed..01023fc880c8 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6734,6 +6734,8 @@ enum {
> > >  #define _PLANE_KEYMAX_1_A			0x701a0
> > >  #define _PLANE_KEYMAX_2_A			0x702a0
> > >  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> > > +#define _PLANE_CC_VAL_1_A			0x701b4
> > > +#define _PLANE_CC_VAL_2_A			0x702b4
> > >  #define _PLANE_AUX_DIST_1_A			0x701c0
> > >  #define _PLANE_AUX_DIST_2_A			0x702c0
> > >  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> > > @@ -6773,6 +6775,16 @@ enum {
> > >  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
> > >  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
> > >  
> > > +#define _PLANE_CC_VAL_1_B			0x711b4
> > > +#define _PLANE_CC_VAL_2_B			0x712b4
> > > +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> > > +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> > > +#define PLANE_CC_VAL(pipe, plane)	\
> > > +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> > > +
> > > +#define CC_VAL_LOWER_OFFSET		4
> > > +#define CC_VAL_HIGHER_OFFSET		5
> > > +
> > >  /* Input CSC Register Definitions */
> > >  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
> > >  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> > > -- 
> > > 2.20.1
> > > 
> > 
> > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

[Sripada, Radhakrishna]

Hi Matt,

> -----Original Message-----
> From: Roper, Matthew D
> Sent: Friday, October 4, 2019 4:53 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Sharma, Shashank <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> Subject: Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL
> Render Decompression
> 
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS
> > is linear and has 4 bits of data for each main surface cache line
> > pair, a ratio of 1:256. Additional Clear Color information is passed
> > from the user-space through an offset in the GEM BO. Add a new
> > modifier to identify and parse new Clear Color information and extend
> > Gen12 render decompression functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> >     plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++++++++++
> >  .../drm/i915/display/intel_display_types.h    |  3 ++
> >  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 +++-
> >  drivers/gpu/drm/i915/i915_reg.h               | 12 +++++
> >  4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> >  		if (color_plane == 1)
> >  			return 64;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		if (color_plane == 1 || color_plane == 2)
> > +			return 64;
> > +		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> >  			return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> >  			return 256 * 1024;
> >  		return 0;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return 16 * 1024;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> >  		return true;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return color_plane == 1;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		return color_plane == 1 || color_plane == 2;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return color_plane == 1 || color_plane == 3;
> >  	default:
> > @@ -2458,6 +2465,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return I915_TILING_Y;
> >  	default:
> >  		return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> >  	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },  };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line
> > +pair in the
> > + * main surface. And each 64B CCS cache line represents an area of
> > +4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > +dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x
> > +32 pixels in
> > + * the main surface. Additional surface is used to pass the Clear
> > +Color
> > + * structure for the driver to program the DE.
> > + */
> 
> Rather than duplicating the previous comment's text I'd just say
> 
> "Same as gen12_ccs_formats[] above, but with an additional surface used to
> pass..."
Sure will update that in the next rev.
> 
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > +	  .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +};
> > +
> >  static const struct drm_format_info *  lookup_format_info(const
> > struct drm_format_info formats[],
> >  		   int num_formats, u32 format)
> > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
> >  		return lookup_format_info(gen12_ccs_formats,
> >  					  ARRAY_SIZE(gen12_ccs_formats),
> >  					  cmd->pixel_format);
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		return lookup_format_info(gen12_ccs_cc_formats,
> > +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> > +					  cmd->pixel_format);
> >  	default:
> >  		return NULL;
> >  	}
> > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier)  {
> >  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;  } @@ -2734,6
> > +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
> >  		return false;
> >  	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> >  		return color_plane == 3 || color_plane == 1;
> > +	else if (modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +		return color_plane == 1 || color_plane == 2;
> >  	else
> >  		return color_plane == 1;
> >  }
> > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
> >  		cpp = fb->format->cpp[i];
> >  		intel_fb_plane_dims(&width, &height, fb, i);
> >
> > +		/*
> > +		 * Plane 2 of Render Compression with Clear Color fb
> modifier is consumed
> > +		 * by the driver and not passed to DE. Skip the arithmetic
> related to
> > +		 * alignment and offset calculation.
> > +		 */
> > +		if (i == 2 && fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +			continue;
> > +
> 
> We might as well do this before the cpp and width/height assignments too?
> 
> Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)?  We seem to
> rely on that after kmap'ing below.
Will make the changes in next rev.

Thanks,
Radhakrishna(RK) Sripada
> 
> 
> Matt
> 
> >  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
> >  		if (ret) {
> >  			DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
> @@ -4274,6 +4316,7
> > @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		return PLANE_CTL_TILED_Y;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return PLANE_CTL_TILED_Y |
> > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct
> > intel_plane_state *plane_state)
> >
> >  	plane_state->vma = vma;
> >
> > +	if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > +		u32 *ccaddr =
> kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > +								  fb-
> >offsets[2] >> PAGE_SHIFT));
> > +
> > +		plane_state->ccval = ((u64)*(ccaddr +
> CC_VAL_HIGHER_OFFSET) << 32)
> > +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> > +		kunmap_atomic(ccaddr);
> > +	}
> > +
> >  	return 0;
> >  }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5998b959225c..77d3f6b634b0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -579,6 +579,9 @@ struct intel_plane_state {
> >  	u32 planar_slave;
> >
> >  	struct drm_intel_sprite_colorkey ckey;
> > +
> > +	/* Clear Color Value */
> > +	u64 ccval;
> >  };
> >
> >  struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index ce79373154fc..24ae8bf9744d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> >  	u32 plane_color_ctl = 0;
> >  	unsigned long irqflags;
> >  	u32 keymsk, keymax;
> > +	u64 ccval = plane_state->ccval;
> >
> >  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >
> > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> >  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> >  		icl_program_input_csc(plane, crtc_state, plane_state);
> >
> > +	if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +		intel_uncore_write64_fw(&dev_priv->uncore,
> > +					PLANE_CC_VAL(pipe, plane_id),
> ccval);
> > +
> >  	skl_write_plane_wm(plane, crtc_state);
> >
> >  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@
> > -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	     fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
> >  		return -EINVAL;
> >  	}
> > @@ -2153,6 +2159,7 @@ static const u64
> > skl_plane_format_modifiers_ccs[] = {  static const u64
> gen12_plane_format_modifiers_mc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2161,6 +2168,7 @@ static const u64
> > gen12_plane_format_modifiers_mc_ccs[] = {
> >
> >  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2334,6 +2342,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		break;
> >  	default:
> >  		return false;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 0abf9a3917ed..01023fc880c8
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6734,6 +6734,8 @@ enum {
> >  #define _PLANE_KEYMAX_1_A			0x701a0
> >  #define _PLANE_KEYMAX_2_A			0x702a0
> >  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> > +#define _PLANE_CC_VAL_1_A			0x701b4
> > +#define _PLANE_CC_VAL_2_A			0x702b4
> >  #define _PLANE_AUX_DIST_1_A			0x701c0
> >  #define _PLANE_AUX_DIST_2_A			0x702c0
> >  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> > @@ -6773,6 +6775,16 @@ enum {
> >  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
> >  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
> >
> > +#define _PLANE_CC_VAL_1_B			0x711b4
> > +#define _PLANE_CC_VAL_2_B			0x712b4
> > +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B)
> > +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B)
> > +#define PLANE_CC_VAL(pipe, plane)	\
> > +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe),
> _PLANE_CC_VAL_2(pipe))
> > +
> > +#define CC_VAL_LOWER_OFFSET		4
> > +#define CC_VAL_HIGHER_OFFSET		5
> > +
> >  /* Input CSC Register Definitions */
> >  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
> >  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> > --
> > 2.20.1
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Sripada, Radhakrishna]

HI,

> -----Original Message-----
> From: Pandiyan, Dhinakaran
> Sent: Friday, October 4, 2019 5:08 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Sharma, Shashank
> <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Chery, Nanley G
> <nanley.g.chery@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> Kondapally, Kalyan <kalyan.kondapally@intel.com>
> Subject: Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel
> Gen 12 render compression with Clear Color
> 
> On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h index c4a4e0fdbee5..99c61ee9b61f
> > 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -434,6 +434,17 @@ extern "C" {
> >   */
> >  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL,
> > 7)
> >
> > +/*
> > + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render
> compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC
> > +is linear
> > + * and at index 1.
> 
> Clear color data is fixed size - 64b, that should be in the documentation here.
Sure will update the documentation in next rev.

Thanks,
Radhakrishna(RK) Sripada
> 
> 
> > The clear color is stored at index 2, and the pitch should
> > + * be ignored. A CCS_CC cache line corresponds to an area of 4x1
> > + tiles in the
> That's a CCS cache line, not a CCS_CC cache line, right?
> 
> > + * main surface. The main surface pitch is required to be a multiple
> > +of 4 tile
> > + * widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > +fourcc_mod_code(INTEL, 8)
> > +
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> >   *

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