All of lore.kernel.org
 help / color / mirror / Atom feed
* [v2][PATCH] drm/i915: Add Pipe D cursor ctrl register for Gen12
@ 2019-09-24  7:31 Nautiyal, Ankit K
  2019-09-24  7:44 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Pipe D cursor ctrl register for Gen12 (rev2) Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Nautiyal, Ankit K @ 2019-09-24  7:31 UTC (permalink / raw)
  To: intel-gfx

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Currently the offset for PIPE D cursor control register is missing in
i915_reg.h due to which the cursor plane cannot be enabled for Pipe D.
This also causes kernel Warning, when a user requests to enable cursor
plane for PIPE D for Gen 12 platforms.

This patch adds the CURSOR_CTL_D register in the i915_reg.h.

v2: Rebase

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111640
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c2faa67..dc048d9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -118,6 +118,15 @@
 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
 	}
 
+#define TGL_CURSOR_OFFSETS \
+	.cursor_offsets = { \
+		[PIPE_A] = CURSOR_A_OFFSET, \
+		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
+		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
+		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
+	}
+
+
 #define I9XX_COLORS \
 	.color = { .gamma_lut_size = 256 }
 #define I965_COLORS \
@@ -787,6 +796,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 	}, \
+	TGL_CURSOR_OFFSETS, \
 	.has_global_mocs = 1, \
 	.display.has_dsb = 1
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a69c19a..28c483a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6240,6 +6240,7 @@ enum {
 #define CHV_CURSOR_C_OFFSET 0x700e0
 #define IVB_CURSOR_B_OFFSET 0x71080
 #define IVB_CURSOR_C_OFFSET 0x72080
+#define TGL_CURSOR_D_OFFSET 0x73080
 
 /* Display A control */
 #define _DSPACNTR				0x70180
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-09-24 17:12 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-24  7:31 [v2][PATCH] drm/i915: Add Pipe D cursor ctrl register for Gen12 Nautiyal, Ankit K
2019-09-24  7:44 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Pipe D cursor ctrl register for Gen12 (rev2) Patchwork
2019-09-24  8:06 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-24 15:46 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-24 16:46 ` [v2][PATCH] drm/i915: Add Pipe D cursor ctrl register for Gen12 Lucas De Marchi
2019-09-24 17:13 ` James Ausmus

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.