* [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state.
@ 2019-09-25 12:12 Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers Jeevan B
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Jeevan B @ 2019-09-25 12:12 UTC (permalink / raw)
To: igt-dev; +Cc: Jeevan B
This test is creating a vpb scenario for
selective frame update and validating
that DC state stays in DC3CO during execution.
Anshuman Gupta (1):
igt/i915/i915_pm_dc: DC3CO PSR2 helpers
Jeevan B (1):
Add a new IGT test to validate DC3CO state
lib/igt_psr.c | 11 +++
lib/igt_psr.h | 1 +
tests/i915/i915_pm_dc.c | 181 +++++++++++++++++++++++++++++++++++++++++++++---
3 files changed, 183 insertions(+), 10 deletions(-)
--
2.7.4
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers
2019-09-25 12:12 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
@ 2019-09-25 12:12 ` Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state Jeevan B
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: Jeevan B @ 2019-09-25 12:12 UTC (permalink / raw)
To: igt-dev; +Cc: Jeevan B
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add DC3CO IGT validation prerequisites stuff
so we can enable DC3CO IGT test.
v2: Removed psr2_idle_wait_entry and get_psr2_status function.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
tests/i915/i915_pm_dc.c | 34 +++++++++++++++++++++++++++++-----
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b..19d8a78 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -36,6 +36,7 @@
/* DC State Flags */
#define CHECK_DC5 1
#define CHECK_DC6 2
+#define CHECK_DC3CO 4
typedef struct {
int drm_fd;
@@ -88,6 +89,20 @@ static bool edp_psr_sink_support(data_t *data)
return strstr(buf, "Sink support: yes");
}
+static bool edp_psr2_enabled(data_t *data)
+
+{
+ char buf[512];
+
+ igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+ buf, sizeof(buf));
+
+ if (data->op_psr_mode == PSR_MODE_2)
+ return strstr(buf, "PSR mode: PSR2 enabled");
+
+ return false;
+}
+
static void cleanup_dc_psr(data_t *data)
{
igt_plane_t *primary;
@@ -141,12 +156,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
str = strstr(buf, "DC3 -> DC5 count");
else if (dc_flag & CHECK_DC6)
str = strstr(buf, "DC5 -> DC6 count");
+ else if (dc_flag & CHECK_DC3CO)
+ str = strstr(buf, "DC3CO count");
- /* Check DC5/DC6 counter is available for the platform.
+ /* Check DC counter is available for the platform.
* Skip the test if counter is not available.
*/
- igt_skip_on_f(!str, "DC%d counter is not available\n",
- dc_flag & CHECK_DC5 ? 5 : 6);
+ if (dc_flag & CHECK_DC3CO)
+ igt_skip_on_f(!str, "DC3CO counter is not available\n");
+ else
+ igt_skip_on_f(!str, "DC%d counter is not available\n",
+ dc_flag & CHECK_DC5 ? 5 : 6);
+
return get_dc_counter(str);
}
@@ -158,9 +179,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
{
+ char tmp[64];
+
+ snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+ (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
- "DC%d state is not achieved\n",
- dc_flag & CHECK_DC5 ? 5 : 6);
+ "%s state is not achieved\n", tmp);
}
static void test_dc_state_psr(data_t *data, int dc_flag)
--
2.7.4
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-09-25 12:12 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers Jeevan B
@ 2019-09-25 12:12 ` Jeevan B
2019-09-26 7:52 ` Anshuman Gupta
2019-09-25 13:16 ` [igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state. (rev2) Patchwork
2019-09-26 2:36 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 1 reply; 13+ messages in thread
From: Jeevan B @ 2019-09-25 12:12 UTC (permalink / raw)
To: igt-dev; +Cc: Jeevan B
Add a subtest for DC3CO video playback case
to generate selective frame update and validate
that system stays in DC3CO state during execution.
v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
(Anshuman)
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
lib/igt_psr.c | 11 ++++
lib/igt_psr.h | 1 +
tests/i915/i915_pm_dc.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 154 insertions(+), 5 deletions(-)
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index b92ea73..7806ce9 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
return strstr(buf, state);
}
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+ char buf[PSR_STATUS_MAX_LEN];
+ const char *state = "SLEEP";
+
+ igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+ sizeof(buf));
+
+ return strstr(buf, state);
+}
+
static inline const char *psr_active_state_get(enum psr_mode mode)
{
return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index ca38573..a0627dc 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -35,6 +35,7 @@ enum psr_mode {
PSR_MODE_2
};
+bool psr2_active_sleep_check(int debugfs_fd);
bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 19d8a78..7f93792 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -38,13 +38,22 @@
#define CHECK_DC6 2
#define CHECK_DC3CO 4
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 100
+
+typedef struct {
+ double r, g, b;
+} color_t;
+
+igt_plane_t *primary;
+
typedef struct {
int drm_fd;
int msr_fd;
int debugfs_fd;
uint32_t devid;
igt_display_t display;
- struct igt_fb fb_white;
+ struct igt_fb fb_white, fb_rgb, fb_rgr;
enum psr_mode op_psr_mode;
drmModeModeInfo *mode;
igt_output_t *output;
@@ -53,6 +62,7 @@ typedef struct {
static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count);
+static bool psr2_wait_sleep_update(int debugfs_fd);
static void setup_output(data_t *data)
{
@@ -105,8 +115,6 @@ static bool edp_psr2_enabled(data_t *data)
static void cleanup_dc_psr(data_t *data)
{
- igt_plane_t *primary;
-
primary = igt_output_get_plane_type(data->output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
@@ -114,10 +122,43 @@ static void cleanup_dc_psr(data_t *data)
igt_remove_fb(data->drm_fd, &data->fb_white);
}
-static void setup_primary(data_t *data)
+static void cleanup_dc3co(data_t *data)
+{
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ /*Clear Frame Buffers*/
+ igt_display_commit(&data->display);
+ igt_remove_fb(data->drm_fd, &data->fb_rgb);
+
+ igt_display_commit(&data->display);
+ igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+ drmModeModeInfo *mode,
+ color_t *colors,
+ igt_fb_t *fb)
{
- igt_plane_t *primary;
+ cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+ int i, l = mode->hdisplay / 3;
+ int rows_remaining = mode->hdisplay % 3;
+
+ /* Paint 3 solid rectangles. */
+ for (i = 0 ; i < 3; i++) {
+ igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+ colors[i].r, colors[i].g, colors[i].b);
+ }
+ if (rows_remaining > 0)
+ igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+ colors[i-1].r, colors[i-1].g, colors[i-1].b);
+
+ igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
+static void setup_primary(data_t *data)
+{
primary = igt_output_get_plane_type(data->output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
@@ -131,6 +172,24 @@ static void setup_primary(data_t *data)
igt_display_commit(&data->display);
}
+static void create_clr_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+ int fb_id;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(primary, NULL);
+ fb_id = igt_create_fb(data->drm_fd,
+ data->mode->hdisplay,
+ data->mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ LOCAL_DRM_FORMAT_MOD_NONE,
+ fb);
+ igt_assert(fb_id);
+ paint_rectangles(data, data->mode, fb_color, fb);
+}
+
static uint32_t get_dc_counter(char *dc_data)
{
char *e;
@@ -171,6 +230,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
return get_dc_counter(str);
}
+static bool psr2_wait_sleep_update(int debugfs_fd)
+{
+ return igt_wait(psr2_active_sleep_check(debugfs_fd), 100, 10);
+}
+
static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
{
return igt_wait(read_dc_counter(drm_fd, dc_flag) >
@@ -187,6 +251,73 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
"%s state is not achieved\n", tmp);
}
+static void setup_vpb(data_t *data)
+{
+ color_t red_green_blue[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 0.0, 0.0, 1.0 },
+ };
+ color_t red_green_red[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 1.0, 0.0, 0.0 },
+ };
+
+ setup_output(data);
+
+ create_clr_fb(data, &data->fb_rgb, red_green_blue);
+ create_clr_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void run_videoplayback(data_t *data, int dc_flag)
+{
+ uint32_t dc3co_cnt_before_psr;
+ int i, delay;
+
+ igt_plane_set_fb(primary, NULL);
+
+ dc3co_cnt_before_psr = read_dc_counter(data->drm_fd, dc_flag);
+ /*Calculate delay to generate idle frame*/
+ delay = ((1000*1000)/data->mode->vrefresh);
+
+ for (i = 0; i < VIDEO_FRAMES; i++) {
+ if (i % 2 == 0) {
+ igt_plane_set_fb(primary, &data->fb_rgb);
+ igt_display_commit(&data->display);
+ } else {
+ igt_plane_set_fb(primary, &data->fb_rgr);
+ igt_display_commit(&data->display);
+ }
+ usleep(delay);
+ igt_assert(psr2_wait_sleep_update(data->debugfs_fd));
+ }
+ check_dc_counter(data->drm_fd, dc_flag, dc3co_cnt_before_psr);
+}
+
+static void setup_dc3co(data_t *data)
+{
+ igt_require(IS_TIGERLAKE(data->devid));
+ data->op_psr_mode = PSR_MODE_2;
+ psr_enable(data->debugfs_fd, data->op_psr_mode);
+ igt_require_f(edp_psr2_enabled(data),
+ "PSR2 is not enabled\n");
+}
+
+static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
+{
+ uint32_t dc5_cnt_before, dc5_cnt_after;
+
+ setup_dc3co(data);
+ setup_vpb(data);
+ dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
+ run_videoplayback(data, dc_flag);
+ dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
+ igt_assert_f(dc5_cnt_after == dc5_cnt_before,
+ "DC State moved to DC5\n");
+ cleanup_dc3co(data);
+}
+
static void test_dc_state_psr(data_t *data, int dc_flag)
{
uint32_t dc_counter_before_psr;
@@ -288,6 +419,12 @@ int main(int argc, char *argv[])
"Can't open /dev/cpu/0/msr.\n");
}
+ igt_describe("This tests is to stimulate videoplay back "
+ "to validate DC3CO state while PSR2 is active");
+ igt_subtest("dc3co-vpb-simulation") {
+ test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while PSR is active");
igt_subtest("dc5-psr") {
--
2.7.4
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state. (rev2)
2019-09-25 12:12 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state Jeevan B
@ 2019-09-25 13:16 ` Patchwork
2019-09-26 2:36 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-09-25 13:16 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
== Series Details ==
Series: Add a new IGT test to validate DC3CO state. (rev2)
URL : https://patchwork.freedesktop.org/series/66648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6955 -> IGTPW_3499
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_3499 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3499, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/66648/revisions/2/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3499:
### IGT changes ###
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][1] ([fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
Known issues
------------
Here are the changes found in IGTPW_3499 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109635 ])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@kms_busy@basic-flip-a:
- {fi-kbl-soraka}: [DMESG-WARN][7] ([fdo#105763]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/fi-kbl-soraka/igt@kms_busy@basic-flip-a.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/fi-kbl-soraka/igt@kms_busy@basic-flip-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-tgl-u
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5202 -> IGTPW_3499
CI-20190529: 20190529
CI_DRM_6955: f3993c8f51b1e56a981cc387028986e09d62cb64 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3499: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/
IGT_5202: 3499c5eb17054e2abd88023fe962768140d24302 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@i915_pm_dc@dc3co-vpb-simulation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add a new IGT test to validate DC3CO state. (rev2)
2019-09-25 12:12 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
` (2 preceding siblings ...)
2019-09-25 13:16 ` [igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state. (rev2) Patchwork
@ 2019-09-26 2:36 ` Patchwork
3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-09-26 2:36 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
== Series Details ==
Series: Add a new IGT test to validate DC3CO state. (rev2)
URL : https://patchwork.freedesktop.org/series/66648/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6955_full -> IGTPW_3499_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3499_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3499_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/66648/revisions/2/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3499_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_pm_dc@dc3co-vpb-simulation} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
New tests
---------
New tests have been introduced between CI_DRM_6955_full and IGTPW_3499_full:
### New IGT tests (1) ###
* igt@i915_pm_dc@dc3co-vpb-simulation:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_3499_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-apl8/igt@gem_ctx_isolation@bcs0-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276]) +20 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#111325]) +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_pwrite@big-gtt-fbr:
- shard-hsw: [PASS][8] -> [INCOMPLETE][9] ([fdo#103540])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-hsw4/igt@gem_pwrite@big-gtt-fbr.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-hsw8/igt@gem_pwrite@big-gtt-fbr.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-kbl7/igt@i915_suspend@forcewake.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-kbl3/igt@i915_suspend@forcewake.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][12] -> [FAIL][13] ([fdo#105767])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb6/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][18] -> [FAIL][19] ([fdo#99912])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-apl3/igt@kms_setmode@basic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-apl1/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][20] ([fdo#108566]) -> [PASS][21] +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [SKIP][22] ([fdo#111325]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb6/igt@gem_exec_schedule@preempt-bsd.html
* {igt@i915_pm_dc@dc5-dpms}:
- shard-iclb: [FAIL][24] ([fdo#111795 ]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb7/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_pm_rps@reset:
- shard-apl: [FAIL][26] ([fdo#102250]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-apl2/igt@i915_pm_rps@reset.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-apl2/igt@i915_pm_rps@reset.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][28] ([fdo#104873]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [FAIL][30] ([fdo#103167]) -> [PASS][31] +4 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][32] ([fdo#108566]) -> [PASS][33] +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][34] ([fdo#103166]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][36] ([fdo#109441]) -> [PASS][37] +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][38] ([fdo#99912]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-glk9/igt@kms_setmode@basic.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-glk5/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][40] ([fdo#99912]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-kbl6/igt@kms_setmode@basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-kbl7/igt@kms_setmode@basic.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][42] ([fdo#109276]) -> [PASS][43] +13 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb8/igt@prime_busy@hang-bsd2.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [SKIP][44] ([fdo#109276]) -> [FAIL][45] ([fdo#111330])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6955/shard-iclb3/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (15 -> 6)
------------------------------
ERROR: It appears as if the changes made in IGTPW_3499_full prevented too many machines from booting.
Missing (9): shard-skl pig-hsw-4770r shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6 pig-skl-6260u
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5202 -> IGTPW_3499
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_6955: f3993c8f51b1e56a981cc387028986e09d62cb64 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3499: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/
IGT_5202: 3499c5eb17054e2abd88023fe962768140d24302 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3499/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state Jeevan B
@ 2019-09-26 7:52 ` Anshuman Gupta
0 siblings, 0 replies; 13+ messages in thread
From: Anshuman Gupta @ 2019-09-26 7:52 UTC (permalink / raw)
To: Jeevan B, y; +Cc: igt-dev
On 2019-09-25 at 17:42:17 +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> (Anshuman)
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
> lib/igt_psr.c | 11 ++++
> lib/igt_psr.h | 1 +
> tests/i915/i915_pm_dc.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++--
> 3 files changed, 154 insertions(+), 5 deletions(-)
>
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index b92ea73..7806ce9 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
> return strstr(buf, state);
> }
>
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> + char buf[PSR_STATUS_MAX_LEN];
> + const char *state = "SLEEP";
> +
> + igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> + sizeof(buf));
> +
> + return strstr(buf, state);
> +}
> +
> static inline const char *psr_active_state_get(enum psr_mode mode)
> {
> return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..a0627dc 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -35,6 +35,7 @@ enum psr_mode {
> PSR_MODE_2
> };
>
> +bool psr2_active_sleep_check(int debugfs_fd);
> bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
> bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
> bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 19d8a78..7f93792 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,13 +38,22 @@
> #define CHECK_DC6 2
> #define CHECK_DC3CO 4
>
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 100
> +
> +typedef struct {
> + double r, g, b;
> +} color_t;
> +
> +igt_plane_t *primary;
> +
> typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -53,6 +62,7 @@ typedef struct {
>
> static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count);
> static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count);
> +static bool psr2_wait_sleep_update(int debugfs_fd);
>
> static void setup_output(data_t *data)
> {
> @@ -105,8 +115,6 @@ static bool edp_psr2_enabled(data_t *data)
>
> static void cleanup_dc_psr(data_t *data)
> {
> - igt_plane_t *primary;
unwanted change, how will this build if u remove primary ?
> -
> primary = igt_output_get_plane_type(data->output,
> DRM_PLANE_TYPE_PRIMARY);
> igt_plane_set_fb(primary, NULL);
> @@ -114,10 +122,43 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> -static void setup_primary(data_t *data)
> +static void cleanup_dc3co(data_t *data)
> +{
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /*Clear Frame Buffers*/
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> +
> + igt_display_commit(&data->display);
we do not need the second commit.
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> {
> - igt_plane_t *primary;
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
>
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i-1].r, colors[i-1].g, colors[i-1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> +static void setup_primary(data_t *data)
> +{
> primary = igt_output_get_plane_type(data->output,
> DRM_PLANE_TYPE_PRIMARY);
> igt_plane_set_fb(primary, NULL);
> @@ -131,6 +172,24 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_clr_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> +
> + igt_plane_set_fb(primary, NULL);
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -171,6 +230,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> return get_dc_counter(str);
> }
>
> +static bool psr2_wait_sleep_update(int debugfs_fd)
psr2_wait_sleep_entry looks suitable ?
> +{
> + return igt_wait(psr2_active_sleep_check(debugfs_fd), 100, 10);
I think our plan was to have a total delay less then 100?
> +}
> +
> static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> {
> return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -187,6 +251,73 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_vpb(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + setup_output(data);
> +
> + create_clr_fb(data, &data->fb_rgb, red_green_blue);
> + create_clr_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void run_videoplayback(data_t *data, int dc_flag)
> +{
> + uint32_t dc3co_cnt_before_psr;
> + int i, delay;
> +
> + igt_plane_set_fb(primary, NULL);
> +
> + dc3co_cnt_before_psr = read_dc_counter(data->drm_fd, dc_flag);
> + /*Calculate delay to generate idle frame*/
> + delay = ((1000*1000)/data->mode->vrefresh);
> +
> + for (i = 0; i < VIDEO_FRAMES; i++) {
> + if (i % 2 == 0) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + } else {
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + }
> + usleep(delay);
> + igt_assert(psr2_wait_sleep_update(data->debugfs_fd));
> + }
> + check_dc_counter(data->drm_fd, dc_flag, dc3co_cnt_before_psr);
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + igt_require(IS_TIGERLAKE(data->devid));
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
> +{
> + uint32_t dc5_cnt_before, dc5_cnt_after;
> +
> + setup_dc3co(data);
> + setup_vpb(data);
> + dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
> + run_videoplayback(data, dc_flag);
> + dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
> + igt_assert_f(dc5_cnt_after == dc5_cnt_before,
> + "DC State moved to DC5\n");
> + cleanup_dc3co(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
> @@ -288,6 +419,12 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("This tests is to stimulate videoplay back "
typo it is simulate, u can use "This test simulate video playback in order to validate
DC3CO state while PSR2 is active and in SLEEP state"
Thanks,
Anshuman Gupta.
> + "to validate DC3CO state while PSR2 is active");
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
[not found] ` <1572355751-24313-3-git-send-email-jeevan.b@intel.com>
@ 2019-11-05 5:27 ` Ramalingam C
0 siblings, 0 replies; 13+ messages in thread
From: Ramalingam C @ 2019-11-05 5:27 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
On 2019-10-29 at 18:59:11 +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> v3: Renamed a function and restructured code.
> v4: Cosmetic changes.
> v5: Removed DC5 check, Platform check and a function parameter.
> Renamed a function name as per Arek and Imre's Comments.
> v6: Added a new function require_dc_counter as per Arek's Comments.
> The test is now running based on time instead of the number of frames
> increased frame delay from 1 to 1.5 as per Imre's Comments.
> v7: Removed psr2_active_sleep_check and corrected the switch indentation.
> v8: Changed skip to assert in read_dc_counter function and changed
> IGT description
>
Thanks for the patch. Merged with Arkadiusz's Ack.
-Ram
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> tests/i915/i915_pm_dc.c | 159 ++++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 155 insertions(+), 4 deletions(-)
>
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 6132ebd..90d81cf 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -32,6 +32,7 @@
> #include "igt_psr.h"
> #include "igt_sysfs.h"
> #include "limits.h"
> +#include "time.h"
>
> /* DC State Flags */
> #define CHECK_DC5 (1 << 0)
> @@ -39,12 +40,16 @@
> #define CHECK_DC3CO (1 << 2)
>
> typedef struct {
> + double r, g, b;
> +} color_t;
> +
> +typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -110,6 +115,42 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> +static void cleanup_dc3co_fbs(data_t *data)
> +{
> + igt_plane_t *primary;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /* Clear Frame Buffers */
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> +{
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
> +
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i - 1].r, colors[i - 1].g,
> + colors[i - 1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> static void setup_primary(data_t *data)
> {
> igt_plane_t *primary;
> @@ -127,6 +168,20 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -150,13 +205,13 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
>
> if (dc_flag & CHECK_DC5) {
> str = strstr(buf, "DC3 -> DC5 count");
> - igt_skip_on_f(!str, "DC5 counter is not available\n");
> + igt_assert_f(str, "DC5 counter is not available\n");
> } else if (dc_flag & CHECK_DC6) {
> str = strstr(buf, "DC5 -> DC6 count");
> - igt_skip_on_f(!str, "DC6 counter is not available\n");
> + igt_assert_f(str, "DC6 counter is not available\n");
> } else if (dc_flag & CHECK_DC3CO) {
> str = strstr(buf, "DC3CO count");
> - igt_skip_on_f(!str, "DC3CO counter is not available\n");
> + igt_assert_f(str, "DC3CO counter is not available\n");
> }
>
> return get_dc_counter(str);
> @@ -178,10 +233,99 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_videoplayback(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + create_color_fb(data, &data->fb_rgb, red_green_blue);
> + create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void check_dc3co_with_videoplayback_like_load(data_t *data)
> +{
> + igt_plane_t *primary;
> + uint32_t dc3co_prev_cnt;
> + int delay;
> + time_t secs = 6;
> + time_t startTime = time(NULL);
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
> + /* Calculate delay to generate idle frame in usec*/
> + delay = 1.5 * ((1000 * 1000) / data->mode->vrefresh);
> +
> + while (time(NULL) - startTime < secs) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + usleep(delay);
> +
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + usleep(delay);
> + }
> +
> + check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
> +}
> +
> +static void require_dc_counter(int drm_fd, int dc_flag)
> +{
> + char buf[4096];
> +
> + igt_debugfs_simple_read(drm_fd, "i915_dmc_info",
> + buf, sizeof(buf));
> +
> + switch (dc_flag) {
> + case CHECK_DC3CO:
> + igt_skip_on_f(strstr(buf, "DC3CO count"),
> + "DC3CO counter is not available\n");
> + break;
> + case CHECK_DC5:
> + igt_skip_on_f(strstr(buf, "DC3 -> DC5 count"),
> + "DC5 counter is not available\n");
> + break;
> + case CHECK_DC6:
> + igt_skip_on_f(strstr(buf, "DC5 -> DC6 count"),
> + "DC6 counter is not available\n");
> + break;
> + default:
> + igt_assert_f(0, "Unknown DC counter %d\n", dc_flag);
> + }
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data)
> +{
> + require_dc_counter(data->drm_fd, CHECK_DC3CO);
> + setup_output(data);
> + setup_dc3co(data);
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co_fbs(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
>
> + require_dc_counter(data->drm_fd, dc_flag);
> dc_counter_before_psr = read_dc_counter(data->drm_fd, dc_flag);
> setup_output(data);
> setup_primary(data);
> @@ -243,6 +387,7 @@ static void test_dc_state_dpms(data_t *data, int dc_flag)
> {
> uint32_t dc_counter;
>
> + require_dc_counter(data->drm_fd, dc_flag);
> setup_dc_dpms(data);
> dc_counter = read_dc_counter(data->drm_fd, dc_flag);
> dpms_off(data);
> @@ -279,6 +424,12 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("In this test we make sure that system enters DC3CO "
> + "when PSR2 is active and system is in SLEEP state");
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
[not found] ` <1572343926-22949-3-git-send-email-jeevan.b@intel.com>
@ 2019-10-29 12:37 ` Arkadiusz Hiler
0 siblings, 0 replies; 13+ messages in thread
From: Arkadiusz Hiler @ 2019-10-29 12:37 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
On Tue, Oct 29, 2019 at 03:42:06PM +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> v3: Renamed a function and restructured code according to Anshuman’s comments.
> v4: Cosmetic changes.
> v5: Removed DC5 check, Platform check and a function parameter.
> Renamed a function name as per Arek and Imre's Comments.
> v6: Added a new function require_dc_counter as per Arek's Comments.
> The test is now running based on time instead of the number of frames
> increased frame delay from 1 to 1.5 as per Imre's Comments.
> v7: Removed psr2_active_sleep_check and corrected the switch indentation.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> tests/i915/i915_pm_dc.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 151 insertions(+), 1 deletion(-)
>
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 44c6538..46db135 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -32,6 +32,7 @@
> #include "igt_psr.h"
> #include "igt_sysfs.h"
> #include "limits.h"
> +#include "time.h"
>
> /* DC State Flags */
> #define CHECK_DC5 (1 << 0)
> @@ -39,12 +40,16 @@
> #define CHECK_DC3CO (1 << 2)
>
> typedef struct {
> + double r, g, b;
> +} color_t;
> +
> +typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -110,6 +115,42 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> +static void cleanup_dc3co_fbs(data_t *data)
> +{
> + igt_plane_t *primary;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /* Clear Frame Buffers */
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> +{
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
> +
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i - 1].r, colors[i - 1].g,
> + colors[i - 1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> static void setup_primary(data_t *data)
> {
> igt_plane_t *primary;
> @@ -127,6 +168,20 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -183,6 +238,94 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_videoplayback(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + create_color_fb(data, &data->fb_rgb, red_green_blue);
> + create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void check_dc3co_with_videoplayback_like_load(data_t *data)
> +{
> + igt_plane_t *primary;
> + uint32_t dc3co_prev_cnt;
> + int delay;
> + time_t secs = 6;
> + time_t startTime = time(NULL);
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
> + /* Calculate delay to generate idle frame in usec*/
> + delay = 1.5 * ((1000 * 1000) / data->mode->vrefresh);
> +
> + while (time(NULL) - startTime < secs) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + usleep(delay);
> +
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + usleep(delay);
> + }
> +
> + check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
> +}
> +
> +static void require_dc_counter(int drm_fd, int dc_flag)
Nice! Thanks for introducing this. Now we should use that for the tests
that are using other counters so they have the requirements up-front and
don't skip on reading.
As a general rule of thumb:
* skip only from functions that have *skip* or *require* in the name
* let *read* and other functions to fail
Something like:
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 43af86d4..64d81440 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -205,13 +205,13 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
if (dc_flag & CHECK_DC5) {
str = strstr(buf, "DC3 -> DC5 count");
- igt_skip_on_f(!str, "DC5 counter is not available\n");
+ igt_assert_f(str, "DC5 counter is not available\n");
} else if (dc_flag & CHECK_DC6) {
str = strstr(buf, "DC5 -> DC6 count");
- igt_skip_on_f(!str, "DC6 counter is not available\n");
+ igt_assert_f(str, "DC6 counter is not available\n");
} else if (dc_flag & CHECK_DC3CO) {
str = strstr(buf, "DC3CO count");
- igt_skip_on_f(!str, "DC3CO counter is not available\n");
+ igt_assert_f(str, "DC3CO counter is not available\n");
}
return get_dc_counter(str);
@@ -305,7 +305,6 @@ static void require_dc_counter(int drm_fd, int dc_flag)
static void setup_dc3co(data_t *data)
{
- require_dc_counter(data->drm_fd, CHECK_DC3CO);
data->op_psr_mode = PSR_MODE_2;
psr_enable(data->debugfs_fd, data->op_psr_mode);
igt_require_f(edp_psr2_enabled(data),
@@ -314,6 +313,7 @@ static void setup_dc3co(data_t *data)
static void test_dc3co_vpb_simulation(data_t *data)
{
+ require_dc_counter(data->drm_fd, CHECK_DC3CO);
setup_output(data);
setup_dc3co(data);
setup_videoplayback(data);
@@ -325,6 +325,7 @@ static void test_dc_state_psr(data_t *data, int dc_flag)
{
uint32_t dc_counter_before_psr;
+ require_dc_counter(data->drm_fd, dc_flag);
dc_counter_before_psr = read_dc_counter(data->drm_fd, dc_flag);
setup_output(data);
setup_primary(data);
@@ -386,6 +387,7 @@ static void test_dc_state_dpms(data_t *data, int dc_flag)
{
uint32_t dc_counter;
+ require_dc_counter(data->drm_fd, dc_flag);
setup_dc_dpms(data);
dc_counter = read_dc_counter(data->drm_fd, dc_flag);
dpms_off(data);
> +{
> + char buf[4096];
> +
> + igt_debugfs_simple_read(drm_fd, "i915_dmc_info",
> + buf, sizeof(buf));
> +
> + switch (dc_flag) {
> + case CHECK_DC3CO:
> + igt_skip_on_f(strstr(buf, "DC3CO count"),
> + "DC3CO counter is not available\n");
> + break;
> + case CHECK_DC5:
> + igt_skip_on_f(strstr(buf, "DC3 -> DC5 count"),
> + "DC5 counter is not available\n");
> + break;
> + case CHECK_DC6:
> + igt_skip_on_f(strstr(buf, "DC5 -> DC6 count"),
> + "DC6 counter is not available\n");
> + break;
> + default:
> + igt_assert_f(0, "Unknown DC counter %d\n", dc_flag);
> + }
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + require_dc_counter(data->drm_fd, CHECK_DC3CO);
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data)
> +{
> + setup_output(data);
> + setup_dc3co(data);
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co_fbs(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
> @@ -284,6 +427,13 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("This test simulate video playback "
> + "in order to validate DC3CO state "
> + "while PSR2 is active and in SLEEP state");
"This test" is something that the reader already knows. Using this kind of
reference makes sense when you need to address the whole thing few
sentences down the line. Here it just unecessarily inflates the word
count.
I suggest you to rephrase it like that:
"Make sure that we enter DC3CO when PSR2 is active and we are in SLEEP
state."
There are few more tests here that could use similar treatement so feel
free to do that in some follow up series later.
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
[not found] ` <1572333869-14389-3-git-send-email-jeevan.b@intel.com>
@ 2019-10-29 8:54 ` Imre Deak
0 siblings, 0 replies; 13+ messages in thread
From: Imre Deak @ 2019-10-29 8:54 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
On Tue, Oct 29, 2019 at 12:54:29PM +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> v3: Renamed a function and restructured code according to Anshuman’s comments.
> v4: Cosmetic changes.
> v5: Removed DC5 check, Platform check and a function parameter.
> Renamed a function name as per Arek and Imre's Comments.
> v6: Added a new function require_dc_counter as per Arek's Comments.
> The test is now running based on time instead of the number of frames
> increased frame delay from 1 to 1.5 as per Imre's Comments.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> lib/igt_psr.c | 10 +++
> lib/igt_psr.h | 1 +
> tests/i915/i915_pm_dc.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 169 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index 6d19268..5276ff4 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -38,6 +38,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
> return strstr(buf, state);
> }
>
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> + char buf[PSR_STATUS_MAX_LEN];
> + const char *state = "SLEEP";
> +
> + igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> + sizeof(buf));
> + return strstr(buf, state);
> +}
> +
> /*
> * For PSR1, we wait until PSR is active. We wait until DEEP_SLEEP for PSR2.
> */
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..e022434 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -36,6 +36,7 @@ enum psr_mode {
> };
>
> bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
> +bool psr2_active_sleep_check(int debugfs_fd);
> bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
> bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> bool psr_enable(int debugfs_fd, enum psr_mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 44c6538..10148cd 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -32,6 +32,7 @@
> #include "igt_psr.h"
> #include "igt_sysfs.h"
> #include "limits.h"
> +#include "time.h"
>
> /* DC State Flags */
> #define CHECK_DC5 (1 << 0)
> @@ -39,12 +40,16 @@
> #define CHECK_DC3CO (1 << 2)
>
> typedef struct {
> + double r, g, b;
> +} color_t;
> +
> +typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -110,6 +115,42 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> +static void cleanup_dc3co_fbs(data_t *data)
> +{
> + igt_plane_t *primary;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /* Clear Frame Buffers */
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> +{
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
> +
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i - 1].r, colors[i - 1].g,
> + colors[i - 1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> static void setup_primary(data_t *data)
> {
> igt_plane_t *primary;
> @@ -127,6 +168,20 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -167,6 +222,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> return get_dc_counter(str);
> }
>
> +static bool psr2_wait_sleep_entry(int debugfs_fd)
> +{
> + return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
> +}
> +
> static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> {
> return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -183,6 +243,96 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_videoplayback(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + create_color_fb(data, &data->fb_rgb, red_green_blue);
> + create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void check_dc3co_with_videoplayback_like_load(data_t *data)
> +{
> + igt_plane_t *primary;
> + uint32_t dc3co_prev_cnt;
> + int delay;
> + time_t secs = 6;
> + time_t startTime = time(NULL);
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
> + /* Calculate delay to generate idle frame in usec*/
> + delay = 1.5 * ((1000 * 1000) / data->mode->vrefresh);
> +
> + while (time(NULL) - startTime < secs) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + usleep(delay);
> +
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + usleep(delay);
> +
> + igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
The above wait was not remove (while you still increased the delay
between flips to 1.5 frame time as we agreed).
> + }
> +
> + check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
> +}
> +
> +static void require_dc_counter(int drm_fd, int dc_flag)
> +{
> + char buf[4096];
> +
> + igt_debugfs_simple_read(drm_fd, "i915_dmc_info",
> + buf, sizeof(buf));
> +
> + switch (dc_flag) {
> + case CHECK_DC3CO:
> + igt_skip_on_f(strstr(buf, "DC3CO count"),
> + "DC3CO counter is not available\n");
> + break;
Please use the kernel coding style, break needs one more indent.
> + case CHECK_DC5:
> + igt_skip_on_f(strstr(buf, "DC3 -> DC5 count"),
> + "DC5 counter is not available\n");
> + break;
> + case CHECK_DC6:
> + igt_skip_on_f(strstr(buf, "DC5 -> DC6 count"),
> + "DC6 counter is not available\n");
> + break;
> + default:
> + igt_assert_f(0, "Unknown DC counter %d\n", dc_flag);
> + }
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + require_dc_counter(data->drm_fd, CHECK_DC3CO);
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data)
> +{
> + setup_output(data);
> + setup_dc3co(data);
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co_fbs(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
> @@ -284,6 +434,13 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("This test simulate video playback "
> + "in order to validate DC3CO state "
> + "while PSR2 is active and in SLEEP state");
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-10-17 10:35 ` [igt-dev] [PATCH i-g-t 2/2] " Jeevan B
2019-10-22 13:27 ` Arkadiusz Hiler
@ 2019-10-23 17:34 ` Imre Deak
1 sibling, 0 replies; 13+ messages in thread
From: Imre Deak @ 2019-10-23 17:34 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
On Thu, Oct 17, 2019 at 04:05:00PM +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> v3: Renamed a function and restructured code according to Anshuman’s comments.
> v4: Cosmetic changes.
> v5: Removed DC5 check, Platform check and a function parameter.
> Renamed a function name as per Arek and Imre's Comments.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
> lib/igt_psr.c | 10 ++++
> lib/igt_psr.h | 1 +
> tests/i915/i915_pm_dc.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 145 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index b92ea73..9127a0b 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -36,6 +36,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
> return strstr(buf, state);
> }
>
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> + char buf[PSR_STATUS_MAX_LEN];
> + const char *state = "SLEEP";
> +
> + igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> + sizeof(buf));
> + return strstr(buf, state);
> +}
> +
> static inline const char *psr_active_state_get(enum psr_mode mode)
> {
> return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..a0627dc 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -35,6 +35,7 @@ enum psr_mode {
> PSR_MODE_2
> };
>
> +bool psr2_active_sleep_check(int debugfs_fd);
> bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
> bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
> bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 0ddd6b3..ac6270f 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,13 +38,20 @@
> #define CHECK_DC6 (1 << 1)
> #define CHECK_DC3CO (1 << 2)
>
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 130
> +
> +typedef struct {
> + double r, g, b;
> +} color_t;
> +
> typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -113,6 +120,42 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> +static void cleanup_dc3co(data_t *data)
> +{
> + igt_plane_t *primary;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /* Clear Frame Buffers */
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> +{
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
> +
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i - 1].r, colors[i - 1].g,
> + colors[i - 1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> static void setup_primary(data_t *data)
> {
> igt_plane_t *primary;
> @@ -130,6 +173,20 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -170,6 +227,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> return get_dc_counter(str);
> }
>
> +static bool psr2_wait_sleep_entry(int debugfs_fd)
> +{
> + return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
> +}
> +
> static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> {
> return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -186,6 +248,70 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_videoplayback(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + create_color_fb(data, &data->fb_rgb, red_green_blue);
> + create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void check_dc3co_with_videoplayback_like_load(data_t *data)
> +{
> + igt_plane_t *primary;
> + uint32_t dc3co_prev_cnt;
> + int i, delay;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
> + /* Calculate delay to generate idle frame in usec*/
> + delay = ((1000 * 1000) / data->mode->vrefresh);
> +
> + for (i = 0; i < VIDEO_FRAMES; i++) {
Please run the loop for a given amount of time, 130 frames is too
arbitrary.
> + if (i % 2 == 0) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + } else {
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + }
You could simplify the above.
> +
> + usleep(delay);
> + igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
The above will wait up to 50 ms, whereas DC3co should be entered already
in the first idle frame. We also don't want to test PSR here, it belongs
to a separate test case. Waiting one and a half frame instead of one after
the flip should make sure DC3co is entered.
> + }
> +
> + check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> + igt_require(read_dc_counter(data->drm_fd, CHECK_DC3CO));
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data)
> +{
> + setup_output(data);
> + setup_dc3co(data);
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
> @@ -287,6 +413,13 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("This test simulate video playback "
> + "in order to validate DC3CO state "
> + "while PSR2 is active and in SLEEP state");
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-10-17 10:35 ` [igt-dev] [PATCH i-g-t 2/2] " Jeevan B
@ 2019-10-22 13:27 ` Arkadiusz Hiler
2019-10-23 17:34 ` Imre Deak
1 sibling, 0 replies; 13+ messages in thread
From: Arkadiusz Hiler @ 2019-10-22 13:27 UTC (permalink / raw)
To: Jeevan B; +Cc: igt-dev
On Thu, Oct 17, 2019 at 04:05:00PM +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
>
> v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
> v3: Renamed a function and restructured code according to Anshuman’s comments.
> v4: Cosmetic changes.
> v5: Removed DC5 check, Platform check and a function parameter.
> Renamed a function name as per Arek and Imre's Comments.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
> lib/igt_psr.c | 10 ++++
> lib/igt_psr.h | 1 +
> tests/i915/i915_pm_dc.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 145 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index b92ea73..9127a0b 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -36,6 +36,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
> return strstr(buf, state);
> }
>
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> + char buf[PSR_STATUS_MAX_LEN];
> + const char *state = "SLEEP";
> +
> + igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> + sizeof(buf));
> + return strstr(buf, state);
> +}
> +
> static inline const char *psr_active_state_get(enum psr_mode mode)
> {
> return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..a0627dc 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -35,6 +35,7 @@ enum psr_mode {
> PSR_MODE_2
> };
>
> +bool psr2_active_sleep_check(int debugfs_fd);
> bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
> bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
> bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 0ddd6b3..ac6270f 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,13 +38,20 @@
> #define CHECK_DC6 (1 << 1)
> #define CHECK_DC3CO (1 << 2)
>
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 130
> +
> +typedef struct {
> + double r, g, b;
> +} color_t;
> +
> typedef struct {
> int drm_fd;
> int msr_fd;
> int debugfs_fd;
> uint32_t devid;
> igt_display_t display;
> - struct igt_fb fb_white;
> + struct igt_fb fb_white, fb_rgb, fb_rgr;
> enum psr_mode op_psr_mode;
> drmModeModeInfo *mode;
> igt_output_t *output;
> @@ -113,6 +120,42 @@ static void cleanup_dc_psr(data_t *data)
> igt_remove_fb(data->drm_fd, &data->fb_white);
> }
>
> +static void cleanup_dc3co(data_t *data)
> +{
> + igt_plane_t *primary;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + /* Clear Frame Buffers */
> + igt_display_commit(&data->display);
> + igt_remove_fb(data->drm_fd, &data->fb_rgb);
> + igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> + drmModeModeInfo *mode,
> + color_t *colors,
> + igt_fb_t *fb)
> +{
> + cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> + int i, l = mode->hdisplay / 3;
> + int rows_remaining = mode->hdisplay % 3;
> +
> + /* Paint 3 solid rectangles. */
> + for (i = 0 ; i < 3; i++) {
> + igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> + colors[i].r, colors[i].g, colors[i].b);
> + }
> +
> + if (rows_remaining > 0)
> + igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> + colors[i - 1].r, colors[i - 1].g,
> + colors[i - 1].b);
> +
> + igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
> static void setup_primary(data_t *data)
> {
> igt_plane_t *primary;
> @@ -130,6 +173,20 @@ static void setup_primary(data_t *data)
> igt_display_commit(&data->display);
> }
>
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> + int fb_id;
> +
> + fb_id = igt_create_fb(data->drm_fd,
> + data->mode->hdisplay,
> + data->mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + fb);
> + igt_assert(fb_id);
> + paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
> static uint32_t get_dc_counter(char *dc_data)
> {
> char *e;
> @@ -170,6 +227,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> return get_dc_counter(str);
> }
>
> +static bool psr2_wait_sleep_entry(int debugfs_fd)
> +{
> + return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
> +}
> +
> static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> {
> return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -186,6 +248,70 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> "%s state is not achieved\n", tmp);
> }
>
> +static void setup_videoplayback(data_t *data)
> +{
> + color_t red_green_blue[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 0.0, 0.0, 1.0 },
> + };
> + color_t red_green_red[] = {
> + { 1.0, 0.0, 0.0 },
> + { 0.0, 1.0, 0.0 },
> + { 1.0, 0.0, 0.0 },
> + };
> +
> + create_color_fb(data, &data->fb_rgb, red_green_blue);
> + create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void check_dc3co_with_videoplayback_like_load(data_t *data)
> +{
> + igt_plane_t *primary;
> + uint32_t dc3co_prev_cnt;
> + int i, delay;
> +
> + primary = igt_output_get_plane_type(data->output,
> + DRM_PLANE_TYPE_PRIMARY);
> + igt_plane_set_fb(primary, NULL);
> + dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
> + /* Calculate delay to generate idle frame in usec*/
> + delay = ((1000 * 1000) / data->mode->vrefresh);
> +
> + for (i = 0; i < VIDEO_FRAMES; i++) {
> + if (i % 2 == 0) {
> + igt_plane_set_fb(primary, &data->fb_rgb);
> + igt_display_commit(&data->display);
> + } else {
> + igt_plane_set_fb(primary, &data->fb_rgr);
> + igt_display_commit(&data->display);
> + }
> +
> + usleep(delay);
> + igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
> + }
> +
> + check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> + data->op_psr_mode = PSR_MODE_2;
> + psr_enable(data->debugfs_fd, data->op_psr_mode);
> + igt_require_f(edp_psr2_enabled(data),
> + "PSR2 is not enabled\n");
> + igt_require(read_dc_counter(data->drm_fd, CHECK_DC3CO));
read_dc_counter() returns the counter value and skips internally
and then this igt_require() which will skip if the counter value is 0.
This does not look like intended behavior.
I still think that we should just introduce another function,
require_dc_counter(int counter) that would check for the string presence
in the debugfs.
And then read_dc_counter() would just assert if we cannot read the
counter.
so the final test would look something like this:
igt_describe("This test simulate video playback "
"in order to make sure we enter DC3CO state "
"while PSR2 is active and we are in SLEEP state");
igt_subtest("dc3co-vpb-simulation") {
require_dc_counter(CHECK_DC3CO);
psr_enable(data->debugfs_fd, PSR_MODE_2);
igt_require(is_edp_psr2_enabled(data));
setup_videoplayback_like_load(data);
check_dc3co_with_videoplayback_like_load(data);
cleanup_videoplayback_fbs(data);
}
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data)
> +{
> + setup_output(data);
> + setup_dc3co(data);
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co(data);
> +}
> +
> static void test_dc_state_psr(data_t *data, int dc_flag)
> {
> uint32_t dc_counter_before_psr;
> @@ -287,6 +413,13 @@ int main(int argc, char *argv[])
> "Can't open /dev/cpu/0/msr.\n");
> }
>
> + igt_describe("This test simulate video playback "
> + "in order to validate DC3CO state "
> + "while PSR2 is active and in SLEEP state");
> + igt_subtest("dc3co-vpb-simulation") {
> + test_dc3co_vpb_simulation(&data);
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
> --
> 2.7.4
>
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-10-17 10:34 [igt-dev] [PATCH i-g-t 0/2] " Jeevan B
@ 2019-10-17 10:35 ` Jeevan B
2019-10-22 13:27 ` Arkadiusz Hiler
2019-10-23 17:34 ` Imre Deak
0 siblings, 2 replies; 13+ messages in thread
From: Jeevan B @ 2019-10-17 10:35 UTC (permalink / raw)
To: igt-dev; +Cc: Jeevan B
Add a subtest for DC3CO video playback case
to generate selective frame update and validate
that system stays in DC3CO state during execution.
v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
v3: Renamed a function and restructured code according to Anshuman’s comments.
v4: Cosmetic changes.
v5: Removed DC5 check, Platform check and a function parameter.
Renamed a function name as per Arek and Imre's Comments.
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
lib/igt_psr.c | 10 ++++
lib/igt_psr.h | 1 +
tests/i915/i915_pm_dc.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index b92ea73..9127a0b 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -36,6 +36,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
return strstr(buf, state);
}
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+ char buf[PSR_STATUS_MAX_LEN];
+ const char *state = "SLEEP";
+
+ igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+ sizeof(buf));
+ return strstr(buf, state);
+}
+
static inline const char *psr_active_state_get(enum psr_mode mode)
{
return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index ca38573..a0627dc 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -35,6 +35,7 @@ enum psr_mode {
PSR_MODE_2
};
+bool psr2_active_sleep_check(int debugfs_fd);
bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 0ddd6b3..ac6270f 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -38,13 +38,20 @@
#define CHECK_DC6 (1 << 1)
#define CHECK_DC3CO (1 << 2)
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 130
+
+typedef struct {
+ double r, g, b;
+} color_t;
+
typedef struct {
int drm_fd;
int msr_fd;
int debugfs_fd;
uint32_t devid;
igt_display_t display;
- struct igt_fb fb_white;
+ struct igt_fb fb_white, fb_rgb, fb_rgr;
enum psr_mode op_psr_mode;
drmModeModeInfo *mode;
igt_output_t *output;
@@ -113,6 +120,42 @@ static void cleanup_dc_psr(data_t *data)
igt_remove_fb(data->drm_fd, &data->fb_white);
}
+static void cleanup_dc3co(data_t *data)
+{
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ /* Clear Frame Buffers */
+ igt_display_commit(&data->display);
+ igt_remove_fb(data->drm_fd, &data->fb_rgb);
+ igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+ drmModeModeInfo *mode,
+ color_t *colors,
+ igt_fb_t *fb)
+{
+ cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+ int i, l = mode->hdisplay / 3;
+ int rows_remaining = mode->hdisplay % 3;
+
+ /* Paint 3 solid rectangles. */
+ for (i = 0 ; i < 3; i++) {
+ igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+ colors[i].r, colors[i].g, colors[i].b);
+ }
+
+ if (rows_remaining > 0)
+ igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+ colors[i - 1].r, colors[i - 1].g,
+ colors[i - 1].b);
+
+ igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
static void setup_primary(data_t *data)
{
igt_plane_t *primary;
@@ -130,6 +173,20 @@ static void setup_primary(data_t *data)
igt_display_commit(&data->display);
}
+static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+ int fb_id;
+
+ fb_id = igt_create_fb(data->drm_fd,
+ data->mode->hdisplay,
+ data->mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ LOCAL_DRM_FORMAT_MOD_NONE,
+ fb);
+ igt_assert(fb_id);
+ paint_rectangles(data, data->mode, fb_color, fb);
+}
+
static uint32_t get_dc_counter(char *dc_data)
{
char *e;
@@ -170,6 +227,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
return get_dc_counter(str);
}
+static bool psr2_wait_sleep_entry(int debugfs_fd)
+{
+ return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
+}
+
static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
{
return igt_wait(read_dc_counter(drm_fd, dc_flag) >
@@ -186,6 +248,70 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
"%s state is not achieved\n", tmp);
}
+static void setup_videoplayback(data_t *data)
+{
+ color_t red_green_blue[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 0.0, 0.0, 1.0 },
+ };
+ color_t red_green_red[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 1.0, 0.0, 0.0 },
+ };
+
+ create_color_fb(data, &data->fb_rgb, red_green_blue);
+ create_color_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void check_dc3co_with_videoplayback_like_load(data_t *data)
+{
+ igt_plane_t *primary;
+ uint32_t dc3co_prev_cnt;
+ int i, delay;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
+ /* Calculate delay to generate idle frame in usec*/
+ delay = ((1000 * 1000) / data->mode->vrefresh);
+
+ for (i = 0; i < VIDEO_FRAMES; i++) {
+ if (i % 2 == 0) {
+ igt_plane_set_fb(primary, &data->fb_rgb);
+ igt_display_commit(&data->display);
+ } else {
+ igt_plane_set_fb(primary, &data->fb_rgr);
+ igt_display_commit(&data->display);
+ }
+
+ usleep(delay);
+ igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
+ }
+
+ check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
+}
+
+static void setup_dc3co(data_t *data)
+{
+ data->op_psr_mode = PSR_MODE_2;
+ psr_enable(data->debugfs_fd, data->op_psr_mode);
+ igt_require_f(edp_psr2_enabled(data),
+ "PSR2 is not enabled\n");
+ igt_require(read_dc_counter(data->drm_fd, CHECK_DC3CO));
+}
+
+static void test_dc3co_vpb_simulation(data_t *data)
+{
+ setup_output(data);
+ setup_dc3co(data);
+ setup_videoplayback(data);
+ check_dc3co_with_videoplayback_like_load(data);
+ cleanup_dc3co(data);
+}
+
static void test_dc_state_psr(data_t *data, int dc_flag)
{
uint32_t dc_counter_before_psr;
@@ -287,6 +413,13 @@ int main(int argc, char *argv[])
"Can't open /dev/cpu/0/msr.\n");
}
+ igt_describe("This test simulate video playback "
+ "in order to validate DC3CO state "
+ "while PSR2 is active and in SLEEP state");
+ igt_subtest("dc3co-vpb-simulation") {
+ test_dc3co_vpb_simulation(&data);
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while PSR is active");
igt_subtest("dc5-psr") {
--
2.7.4
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state
2019-10-01 11:32 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
@ 2019-10-01 11:32 ` Jeevan B
0 siblings, 0 replies; 13+ messages in thread
From: Jeevan B @ 2019-10-01 11:32 UTC (permalink / raw)
To: igt-dev; +Cc: Jeevan B
Add a subtest for DC3CO video playback case
to generate selective frame update and validate
that system stays in DC3CO state during execution.
v2: Changed PSR2 idle check to sleep check and addressed
cosmetic changes.
v3: Renamed a function and restructured code according
to Anshuman’s comments.
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
lib/igt_psr.c | 11 ++++
lib/igt_psr.h | 1 +
tests/i915/i915_pm_dc.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 157 insertions(+), 1 deletion(-)
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index b92ea73..7806ce9 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
return strstr(buf, state);
}
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+ char buf[PSR_STATUS_MAX_LEN];
+ const char *state = "SLEEP";
+
+ igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+ sizeof(buf));
+
+ return strstr(buf, state);
+}
+
static inline const char *psr_active_state_get(enum psr_mode mode)
{
return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index ca38573..a0627dc 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -35,6 +35,7 @@ enum psr_mode {
PSR_MODE_2
};
+bool psr2_active_sleep_check(int debugfs_fd);
bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 19d8a78..dc0a215 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -38,13 +38,20 @@
#define CHECK_DC6 2
#define CHECK_DC3CO 4
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 100
+
+typedef struct {
+ double r, g, b;
+} color_t;
+
typedef struct {
int drm_fd;
int msr_fd;
int debugfs_fd;
uint32_t devid;
igt_display_t display;
- struct igt_fb fb_white;
+ struct igt_fb fb_white, fb_rgb, fb_rgr;
enum psr_mode op_psr_mode;
drmModeModeInfo *mode;
igt_output_t *output;
@@ -114,6 +121,41 @@ static void cleanup_dc_psr(data_t *data)
igt_remove_fb(data->drm_fd, &data->fb_white);
}
+static void cleanup_dc3co(data_t *data)
+{
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ /*Clear Frame Buffers*/
+ igt_display_commit(&data->display);
+ igt_remove_fb(data->drm_fd, &data->fb_rgb);
+ igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+ drmModeModeInfo *mode,
+ color_t *colors,
+ igt_fb_t *fb)
+{
+ cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+ int i, l = mode->hdisplay / 3;
+ int rows_remaining = mode->hdisplay % 3;
+
+ /* Paint 3 solid rectangles. */
+ for (i = 0 ; i < 3; i++) {
+ igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+ colors[i].r, colors[i].g, colors[i].b);
+ }
+
+ if (rows_remaining > 0)
+ igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+ colors[i-1].r, colors[i-1].g, colors[i-1].b);
+
+ igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
static void setup_primary(data_t *data)
{
igt_plane_t *primary;
@@ -131,6 +173,25 @@ static void setup_primary(data_t *data)
igt_display_commit(&data->display);
}
+static void create_clr_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+ igt_plane_t *primary;
+ int fb_id;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(primary, NULL);
+ fb_id = igt_create_fb(data->drm_fd,
+ data->mode->hdisplay,
+ data->mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ LOCAL_DRM_FORMAT_MOD_NONE,
+ fb);
+ igt_assert(fb_id);
+ paint_rectangles(data, data->mode, fb_color, fb);
+}
+
static uint32_t get_dc_counter(char *dc_data)
{
char *e;
@@ -171,6 +232,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
return get_dc_counter(str);
}
+static bool psr2_wait_sleep_entry(int debugfs_fd)
+{
+ return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
+}
+
static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
{
return igt_wait(read_dc_counter(drm_fd, dc_flag) >
@@ -187,6 +253,77 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
"%s state is not achieved\n", tmp);
}
+static void setup_vpb(data_t *data)
+{
+ color_t red_green_blue[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 0.0, 0.0, 1.0 },
+ };
+ color_t red_green_red[] = {
+ { 1.0, 0.0, 0.0 },
+ { 0.0, 1.0, 0.0 },
+ { 1.0, 0.0, 0.0 },
+ };
+
+ setup_output(data);
+
+ create_clr_fb(data, &data->fb_rgb, red_green_blue);
+ create_clr_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void run_videoplayback(data_t *data, int dc_flag)
+{
+ igt_plane_t *primary;
+ uint32_t dc3co_cnt_before_psr;
+ int i, delay;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(primary, NULL);
+
+ dc3co_cnt_before_psr = read_dc_counter(data->drm_fd, dc_flag);
+ /*Calculate delay to generate idle frame*/
+ delay = ((1000*1000)/data->mode->vrefresh);
+
+ for (i = 0; i < VIDEO_FRAMES; i++) {
+ if (i % 2 == 0) {
+ igt_plane_set_fb(primary, &data->fb_rgb);
+ igt_display_commit(&data->display);
+ } else {
+ igt_plane_set_fb(primary, &data->fb_rgr);
+ igt_display_commit(&data->display);
+ }
+ usleep(delay);
+ igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
+ }
+ check_dc_counter(data->drm_fd, dc_flag, dc3co_cnt_before_psr);
+}
+
+static void setup_dc3co(data_t *data)
+{
+ igt_require(IS_TIGERLAKE(data->devid));
+ data->op_psr_mode = PSR_MODE_2;
+ psr_enable(data->debugfs_fd, data->op_psr_mode);
+ igt_require_f(edp_psr2_enabled(data),
+ "PSR2 is not enabled\n");
+}
+
+static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
+{
+ uint32_t dc5_cnt_before, dc5_cnt_after;
+
+ setup_dc3co(data);
+ setup_vpb(data);
+ dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
+ run_videoplayback(data, dc_flag);
+ dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
+ igt_assert_f(dc5_cnt_after == dc5_cnt_before,
+ "DC State moved to DC5\n");
+ cleanup_dc3co(data);
+}
+
static void test_dc_state_psr(data_t *data, int dc_flag)
{
uint32_t dc_counter_before_psr;
@@ -288,6 +425,13 @@ int main(int argc, char *argv[])
"Can't open /dev/cpu/0/msr.\n");
}
+ igt_describe("This test simulate videoplay back "
+ "in order to validate DC3CO state "
+ "while PSR2 is active and in SLEEP state");
+ igt_subtest("dc3co-vpb-simulation") {
+ test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while PSR is active");
igt_subtest("dc5-psr") {
--
2.7.4
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-11-05 5:26 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-25 12:12 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 1/2] igt/i915/i915_pm_dc: DC3CO PSR2 helpers Jeevan B
2019-09-25 12:12 ` [igt-dev] [PATCH i-g-t 2/2] Add a new IGT test to validate DC3CO state Jeevan B
2019-09-26 7:52 ` Anshuman Gupta
2019-09-25 13:16 ` [igt-dev] ✓ Fi.CI.BAT: success for Add a new IGT test to validate DC3CO state. (rev2) Patchwork
2019-09-26 2:36 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2019-10-01 11:32 [igt-dev] [PATCH i-g-t 0/2] Add a new IGT test to validate DC3CO state Jeevan B
2019-10-01 11:32 ` [igt-dev] [PATCH i-g-t 2/2] " Jeevan B
2019-10-17 10:34 [igt-dev] [PATCH i-g-t 0/2] " Jeevan B
2019-10-17 10:35 ` [igt-dev] [PATCH i-g-t 2/2] " Jeevan B
2019-10-22 13:27 ` Arkadiusz Hiler
2019-10-23 17:34 ` Imre Deak
[not found] <1572333869-14389-1-git-send-email-jeevan.b@intel.com>
[not found] ` <1572333869-14389-3-git-send-email-jeevan.b@intel.com>
2019-10-29 8:54 ` Imre Deak
[not found] <1572343926-22949-1-git-send-email-jeevan.b@intel.com>
[not found] ` <1572343926-22949-3-git-send-email-jeevan.b@intel.com>
2019-10-29 12:37 ` Arkadiusz Hiler
[not found] <1572355751-24313-1-git-send-email-jeevan.b@intel.com>
[not found] ` <1572355751-24313-3-git-send-email-jeevan.b@intel.com>
2019-11-05 5:27 ` Ramalingam C
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