From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno <kholk11@gmail.com> Subject: [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context Date: Thu, 26 Sep 2019 14:05:13 +0200 [thread overview] Message-ID: <20190926120516.4981-4-kholk11@gmail.com> (raw) In-Reply-To: <20190926120516.4981-1-kholk11@gmail.com> From: AngeloGioacchino Del Regno <kholk11@gmail.com> To avoid context faults reset the context entirely on detach and to ensure a fresh clean start also do a complete reset before programming the context for domain initialization. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> --- drivers/iommu/qcom_iommu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 8431fb97a50f..2f31da2e7add 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -198,6 +198,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev) return IRQ_HANDLED; } +static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx) +{ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0); + iommu_writel(ctx, ARM_SMMU_CB_PAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0); + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); + + /* Should we issue a TLBSYNC there instead? */ + mb(); +} + static int qcom_iommu_init_domain(struct iommu_domain *domain, struct qcom_iommu_dev *qcom_iommu, struct iommu_fwspec *fwspec) @@ -245,6 +262,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + qcom_iommu_reset_ctx(ctx); + /* TCR */ iommu_writel(ctx, ARM_SMMU_CB_TCR2, (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | @@ -390,8 +409,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de for (i = 0; i < fwspec->num_ids; i++) { struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); - /* Disable the context bank: */ - iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + /* Disable and reset the context bank */ + qcom_iommu_reset_ctx(ctx); ctx->domain = NULL; } -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: marijns95@gmail.com, iommu@lists.linux-foundation.org, agross@kernel.org, AngeloGioacchino Del Regno <kholk11@gmail.com> Subject: [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context Date: Thu, 26 Sep 2019 14:05:13 +0200 [thread overview] Message-ID: <20190926120516.4981-4-kholk11@gmail.com> (raw) In-Reply-To: <20190926120516.4981-1-kholk11@gmail.com> From: AngeloGioacchino Del Regno <kholk11@gmail.com> To avoid context faults reset the context entirely on detach and to ensure a fresh clean start also do a complete reset before programming the context for domain initialization. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> --- drivers/iommu/qcom_iommu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 8431fb97a50f..2f31da2e7add 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -198,6 +198,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev) return IRQ_HANDLED; } +static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx) +{ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0); + iommu_writel(ctx, ARM_SMMU_CB_PAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0); + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); + + /* Should we issue a TLBSYNC there instead? */ + mb(); +} + static int qcom_iommu_init_domain(struct iommu_domain *domain, struct qcom_iommu_dev *qcom_iommu, struct iommu_fwspec *fwspec) @@ -245,6 +262,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + qcom_iommu_reset_ctx(ctx); + /* TCR */ iommu_writel(ctx, ARM_SMMU_CB_TCR2, (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | @@ -390,8 +409,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de for (i = 0; i < fwspec->num_ids; i++) { struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); - /* Disable the context bank: */ - iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + /* Disable and reset the context bank */ + qcom_iommu_reset_ctx(ctx); ctx->domain = NULL; } -- 2.21.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2019-09-26 12:05 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-26 12:05 [PATCH 0/6] Add support for QCOM IOMMU v2 and 500 kholk11 2019-09-26 12:05 ` kholk11 2019-09-26 12:05 ` [PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified kholk11 2019-09-26 12:05 ` kholk11 2019-09-26 20:06 ` Rob Clark 2019-09-26 20:06 ` Rob Clark 2019-09-26 20:06 ` Rob Clark 2019-09-26 12:05 ` [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior kholk11 2019-09-26 12:05 ` kholk11 2019-09-26 12:05 ` kholk11 [this message] 2019-09-26 12:05 ` [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context kholk11 2019-09-26 12:05 ` [PATCH 4/6] iommu/qcom: Add support for AArch64 IOMMU pagetables kholk11 2019-09-26 12:05 ` kholk11 2019-09-26 12:05 ` [PATCH 5/6] iommu/qcom: Index contexts by asid number to allow asid 0 kholk11 2019-09-26 12:05 ` kholk11 2019-09-26 12:05 ` [PATCH 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts kholk11 2019-09-26 12:05 ` kholk11 2022-05-27 21:28 [PATCH 0/6] Fix and extend Qualcomm IOMMU support Konrad Dybcio 2022-05-27 21:28 ` [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context Konrad Dybcio 2022-05-27 21:28 ` Konrad Dybcio 2022-05-27 21:28 ` Konrad Dybcio
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