[PATCH v4 0/4] TGL TC enabling v4

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* [PATCH v4 0/4] TGL TC enabling v4
@ 2019-09-25 23:45 José Roberto de Souza
  2019-09-25 23:45 ` [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
                   ` (4 more replies)
  0 siblings, 5 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-25 23:45 UTC (permalink / raw)
  To: intel-gfx

TGL TC enabling v4

v1: https://patchwork.freedesktop.org/series/66695/#rev1
v2: https://patchwork.freedesktop.org/series/66695/#rev2
v2 patches merged: https://patchwork.freedesktop.org/series/67022/
v3: https://patchwork.freedesktop.org/series/66695/#rev3
v3 patches merged: https://patchwork.freedesktop.org/series/67181/

Clinton A Taylor (2):
  drm/i915/tc: Update DP_MODE programming
  drm/i915/tgl: Add dkl phy programming sequences

José Roberto de Souza (1):
  drm/i915/tgl: Fix dkl link training

Lucas De Marchi (1):
  drm/i915/tgl: initialize TC and TBT ports

 drivers/gpu/drm/i915/display/intel_ddi.c      | 257 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  14 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |  15 +
 drivers/gpu/drm/i915/display/intel_tc.h       |   1 +
 drivers/gpu/drm/i915/i915_reg.h               |  13 +-
 6 files changed, 234 insertions(+), 73 deletions(-)

-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming
  2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
@ 2019-09-25 23:45 ` José Roberto de Souza
  2019-09-26 12:02   ` Imre Deak
  2019-09-25 23:45 ` [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-25 23:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Clinton A Taylor <clinton.a.taylor@intel.com>

BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
now taking in consideration the pin assignment and allowing us to
optimize power by shutting down available but not needed lanes.

It was tested on ICL and TGL, with adaptors that used pin assignment
C and B, reversing the connector and going to different modes testing
the not needed lane shutdown.

BSpec: 21735
BSpec: 49292

Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 82 +++++++++++++-----------
 drivers/gpu/drm/i915/display/intel_tc.c  | 15 +++++
 drivers/gpu/drm/i915/display/intel_tc.h  |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  5 ++
 4 files changed, 66 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa470c70a198..316cedb16935 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3095,7 +3095,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 	enum port port = intel_dig_port->base.port;
-	u32 ln0, ln1, lane_mask;
+	u32 ln0, ln1, pin_assignment;
+	u8 width;
 
 	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
 		return;
@@ -3103,50 +3104,57 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 	ln0 = I915_READ(MG_DP_MODE(0, port));
 	ln1 = I915_READ(MG_DP_MODE(1, port));
 
-	switch (intel_dig_port->tc_mode) {
-	case TC_PORT_DP_ALT:
-		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
-		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
+	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
+	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 
-		lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
+	/* DPPATC */
+	pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
+	width = intel_dig_port->dp.lane_count;
 
-		switch (lane_mask) {
-		case 0x1:
-		case 0x4:
-			break;
-		case 0x2:
+	switch (pin_assignment) {
+	case 0x0:
+		WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
+		if (width == 1) {
+			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
+		} else {
+			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+		}
+		break;
+	case 0x1:
+		if (width == 4) {
+			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+		}
+		break;
+	case 0x2:
+		if (width == 2) {
+			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+		}
+		break;
+	case 0x3:
+	case 0x5:
+		if (width == 1) {
 			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
-			break;
-		case 0x3:
-			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
-			       MG_DP_MODE_CFG_DP_X2_MODE;
-			break;
-		case 0x8:
 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
-			break;
-		case 0xC:
-			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
-			       MG_DP_MODE_CFG_DP_X2_MODE;
-			break;
-		case 0xF:
-			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
-			       MG_DP_MODE_CFG_DP_X2_MODE;
-			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
-			       MG_DP_MODE_CFG_DP_X2_MODE;
-			break;
-		default:
-			MISSING_CASE(lane_mask);
+		} else {
+			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
 		}
 		break;
-
-	case TC_PORT_LEGACY:
-		ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
-		ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
+	case 0x4:
+	case 0x6:
+		if (width == 1) {
+			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
+		} else {
+			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+		}
 		break;
-
 	default:
-		MISSING_CASE(intel_dig_port->tc_mode);
-		return;
+		MISSING_CASE(pin_assignment);
 	}
 
 	I915_WRITE(MG_DP_MODE(0, port), ln0);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index f923f9cbd33c..7773169b7331 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -67,6 +67,21 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
 }
 
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_uncore *uncore = &i915->uncore;
+	u32 pin_mask;
+
+	pin_mask = intel_uncore_read(uncore,
+				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
+
+	WARN_ON(pin_mask == 0xffffffff);
+
+	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
+	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
+}
+
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 783d75531435..463f1b3c836f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -13,6 +13,7 @@ struct intel_digital_port;
 
 bool intel_tc_port_connected(struct intel_digital_port *dig_port);
 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 				      int required_lanes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..bcf449c1d152 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11857,6 +11857,11 @@ enum skl_power_gate {
 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
 
+#define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
+#define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
+#define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
+#define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
+
 /* This register controls the Display State Buffer (DSB) engines. */
 #define _DSBSL_INSTANCE_BASE		0x70B00
 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences
  2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
  2019-09-25 23:45 ` [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
@ 2019-09-25 23:45 ` José Roberto de Souza
  2019-09-26 15:34   ` Imre Deak
  2019-09-25 23:45 ` [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-25 23:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Clinton A Taylor <clinton.a.taylor@intel.com>

Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.

It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the following trainings to fail
so not enabling it for.

v2:
Setting the right HIP_INDEX_REG bits (José)

v3:
Adding the meaning of each column of tgl_dkl_phy_ddi_translations
Adding if gen >= 12 on intel_ddi_hdmi_level() and
intel_ddi_pre_enable_hdmi() instead of reuse part of gen >= 11 if

v4:
Moved the DP_MODE lane programing to another patch as ICL also
needed it
Sharing icl_phy_set_clock_gating() and icl_program_mg_dp_mode() with
TGL as bits and programing as now it almost identical to ICL

BSpec: 49292
BSpec: 49190

Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 175 ++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h          |   8 --
 2 files changed, 155 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 316cedb16935..4da7940f1fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -586,6 +586,26 @@ static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 	{ 0x0, 0x00, 0x00 },	/* 3              0   */
 };
 
+struct tgl_dkl_phy_ddi_buf_trans {
+	u32 dkl_vswing_control;
+	u32 dkl_preshoot_control;
+	u32 dkl_de_emphasis_control;
+};
+
+static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
+				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
+	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
+	{ 0x5, 0x0, 0x03 },	/* 0	1	400mV		3.5 dB */
+	{ 0x2, 0x0, 0x0b },	/* 0	2	400mV		6 dB */
+	{ 0x0, 0x0, 0x19 },	/* 0	3	400mV		9.5 dB */
+	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
+	{ 0x2, 0x0, 0x03 },	/* 1	1	600mV		3.5 dB */
+	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
+	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
+	{ 0x0, 0x0, 0x0B },	/* 2	1	800mV		3.5 dB */
+	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB HDMI default */
+};
+
 static const struct ddi_buf_trans *
 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
@@ -872,7 +892,14 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		if (intel_phy_is_combo(dev_priv, phy))
+			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+						0, &n_entries);
+		else
+			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+		default_entry = n_entries - 1;
+	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
@@ -2334,7 +2361,13 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int n_entries;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		if (intel_phy_is_combo(dev_priv, phy))
+			icl_get_combo_buf_trans(dev_priv, encoder->type,
+						intel_dp->link_rate, &n_entries);
+		else
+			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2776,6 +2809,63 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
 }
 
+static void
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
+				u32 level)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
+	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
+	u32 n_entries, val, ln;
+
+	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+	ddi_translations = tgl_dkl_phy_ddi_translations;
+
+	if (level >= n_entries)
+		level = n_entries - 1;
+
+	for (ln = 0; ln < 2; ln++) {
+		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
+
+		/* All the registers are RMW */
+		val = I915_READ(DKL_TX_DPCNTL0(tc_port));
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
+		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
+		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
+		I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
+
+		val = I915_READ(DKL_TX_DPCNTL1(tc_port));
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
+		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
+		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
+		I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
+
+		val = I915_READ(DKL_TX_DPCNTL2(tc_port));
+		val &= ~DKL_TX_DP20BITMODE;
+		I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
+	}
+}
+
+static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
+				    int link_clock,
+				    u32 level,
+				    enum intel_output_type type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (intel_phy_is_combo(dev_priv, phy))
+		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+	else
+		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
+}
+
 static u32 translate_signal_level(int signal_levels)
 {
 	int i;
@@ -2807,7 +2897,10 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dport->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
+					level, encoder->type);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
 					level, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv))
@@ -3071,38 +3164,61 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
 	       MG_DP_MODE_CFG_GAONPWR_GATING;
 
 	for (ln = 0; ln < 2; ln++) {
-		val = I915_READ(MG_DP_MODE(ln, port));
+		if (INTEL_GEN(dev_priv) >= 12) {
+			I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
+			val = I915_READ(DKL_DP_MODE(tc_port));
+		} else {
+			val = I915_READ(MG_DP_MODE(ln, port));
+		}
+
 		if (enable)
 			val |= bits;
 		else
 			val &= ~bits;
-		I915_WRITE(MG_DP_MODE(ln, port), val);
+
+		if (INTEL_GEN(dev_priv) >= 12)
+			I915_WRITE(DKL_DP_MODE(tc_port), val);
+		else
+			I915_WRITE(MG_DP_MODE(ln, port), val);
 	}
 
-	bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
-	       MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
-	       MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
+	if (INTEL_GEN(dev_priv) == 11) {
+		bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
+		       MG_MISC_SUS0_CFG_CL2PWR_GATING |
+		       MG_MISC_SUS0_CFG_GAONPWR_GATING |
+		       MG_MISC_SUS0_CFG_TRPWR_GATING |
+		       MG_MISC_SUS0_CFG_CL1PWR_GATING |
+		       MG_MISC_SUS0_CFG_DGPWR_GATING;
 
-	val = I915_READ(MG_MISC_SUS0(tc_port));
-	if (enable)
-		val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
-	else
-		val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
-	I915_WRITE(MG_MISC_SUS0(tc_port), val);
+		val = I915_READ(MG_MISC_SUS0(tc_port));
+		if (enable)
+			val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
+		else
+			val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
+		I915_WRITE(MG_MISC_SUS0(tc_port), val);
+	}
 }
 
 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 	enum port port = intel_dig_port->base.port;
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 	u32 ln0, ln1, pin_assignment;
 	u8 width;
 
 	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
 		return;
 
-	ln0 = I915_READ(MG_DP_MODE(0, port));
-	ln1 = I915_READ(MG_DP_MODE(1, port));
+	if (INTEL_GEN(dev_priv) >= 12) {
+		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
+		ln0 = I915_READ(DKL_DP_MODE(tc_port));
+		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
+		ln1 = I915_READ(DKL_DP_MODE(tc_port));
+	} else {
+		ln0 = I915_READ(MG_DP_MODE(0, port));
+		ln1 = I915_READ(MG_DP_MODE(1, port));
+	}
 
 	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
 	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -3157,8 +3273,15 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
 		MISSING_CASE(pin_assignment);
 	}
 
-	I915_WRITE(MG_DP_MODE(0, port), ln0);
-	I915_WRITE(MG_DP_MODE(1, port), ln1);
+	if (INTEL_GEN(dev_priv) >= 12) {
+		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
+		I915_WRITE(DKL_DP_MODE(tc_port), ln0);
+		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
+		I915_WRITE(DKL_DP_MODE(tc_port), ln1);
+	} else {
+		I915_WRITE(MG_DP_MODE(0, port), ln0);
+		I915_WRITE(MG_DP_MODE(1, port), ln1);
+	}
 }
 
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
@@ -3263,7 +3386,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	icl_phy_set_clock_gating(dig_port, false);
 
 	/* 7.e */
-	icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
+	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
 				encoder->type);
 
 	/* 7.f */
@@ -3295,6 +3418,15 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	/* 7.k */
 	intel_dp_stop_link_train(intel_dp);
 
+	/*
+	 * TODO: enable clock gating
+	 *
+	 * It is not written in DP enabling sequence but "PHY Clockgating
+	 * programming" states that clock gating should be enabled after the
+	 * link training but doing so causes all the following trainings to fail
+	 * so not enabling it for now.
+	 */
+
 	/* 7.l */
 	intel_ddi_enable_fec(encoder, crtc_state);
 	intel_dsc_enable(encoder, crtc_state);
@@ -3402,7 +3534,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	icl_program_mg_dp_mode(dig_port);
 	icl_phy_set_clock_gating(dig_port, false);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
+					level, INTEL_OUTPUT_HDMI);
+	else if (INTEL_GEN(dev_priv) == 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
 					level, INTEL_OUTPUT_HDMI);
 	else if (IS_CANNONLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcf449c1d152..7f6b59aa6348 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10245,14 +10245,6 @@ enum skl_power_gate {
 						     _DKL_TX_DW18)
 
 #define _DKL_DP_MODE					0xA0
-#define  DKL_DP_MODE_CFG_GAONPWR_GATING		(1 << 1)
-#define  DKL_DP_MODE_CFG_DIGPWR_GATING		(1 << 2)
-#define  DKL_DP_MODE_CFG_CLNPWR_GATING		(1 << 3)
-#define  DKL_DP_MODE_CFG_TRPWR_GATING		(1 << 4)
-#define  DKL_DP_MODE_CFG_TR2PWR_GATING		(1 << 5)
-#define  DKL_DP_MODE_CFG_GATING_CTRL_MASK	(0x1f << 1)
-#define  DKL_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
-#define  DKL_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
 						     _DKL_PHY1_BASE, \
 						     _DKL_PHY2_BASE) + \
-- 
2.23.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training
  2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
  2019-09-25 23:45 ` [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
  2019-09-25 23:45 ` [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
@ 2019-09-25 23:45 ` José Roberto de Souza
  2019-09-26 13:06   ` Imre Deak
  2019-09-25 23:45 ` [PATCH v4 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
  2019-09-26  0:58 ` ✓ Fi.CI.BAT: success for TGL TC enabling (rev4) Patchwork
  4 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-25 23:45 UTC (permalink / raw)
  To: intel-gfx

Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.

Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
div2 value, that matches with dkl hardcoded table.

So implementing this way as it proved to work in HW and leaving a
comment so we know why it do not match BSpec.

v4:
Using the same is_dp check as ICL, need testing on HDMI over tc port

Issue reported on BSpec 49204.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 69abafa45ce9..be69a2344294 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2630,13 +2630,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 				continue;
 
 			if (div2 >= 2) {
-				if (is_dkl) {
-					a_divratio = 5;
-					tlinedrv = 1;
-				} else {
-					a_divratio = is_dp ? 10 : 5;
-					tlinedrv = 2;
-				}
+				/*
+				 * Note: a_divratio not matching TGL BSpec
+				 * algorithm but matching hardcoded values and
+				 * working on HW for DP alt-mode at least
+				 */
+				a_divratio = is_dp ? 10 : 5;
+				tlinedrv = is_dkl ? 1 : 2;
 			} else {
 				a_divratio = 5;
 				tlinedrv = 0;
-- 
2.23.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 4/4] drm/i915/tgl: initialize TC and TBT ports
  2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
                   ` (2 preceding siblings ...)
  2019-09-25 23:45 ` [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
@ 2019-09-25 23:45 ` José Roberto de Souza
  2019-09-26  0:58 ` ✓ Fi.CI.BAT: success for TGL TC enabling (rev4) Patchwork
  4 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-25 23:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Lucas De Marchi <lucas.demarchi@intel.com>

Now that TC support was added, initialize DDIs.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f125f1624bd..bbe088b9d057 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15340,9 +15340,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		return;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: initialize TC ports as well */
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_D);
+		intel_ddi_init(dev_priv, PORT_E);
+		intel_ddi_init(dev_priv, PORT_F);
+		intel_ddi_init(dev_priv, PORT_G);
+		intel_ddi_init(dev_priv, PORT_H);
+		intel_ddi_init(dev_priv, PORT_I);
 		icl_dsi_init(dev_priv);
 	} else if (IS_ELKHARTLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* ✓ Fi.CI.BAT: success for TGL TC enabling (rev4)
  2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
                   ` (3 preceding siblings ...)
  2019-09-25 23:45 ` [PATCH v4 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
@ 2019-09-26  0:58 ` Patchwork
  4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-09-26  0:58 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: TGL TC enabling (rev4)
URL   : https://patchwork.freedesktop.org/series/66695/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6961 -> Patchwork_14544
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14544:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_selftest@live_gt_timelines}:
    - {fi-tgl-u2}:        NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/fi-tgl-u2/igt@i915_selftest@live_gt_timelines.html

  
Known issues
------------

  Here are the changes found in Patchwork_14544 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [INCOMPLETE][2] ([fdo#107718]) -> [PASS][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6961/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_sync@basic-all:
    - {fi-tgl-u2}:        [INCOMPLETE][4] ([fdo#111647]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6961/fi-tgl-u2/igt@gem_sync@basic-all.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/fi-tgl-u2/igt@gem_sync@basic-all.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][6] ([fdo#111045] / [fdo#111096]) -> [FAIL][7] ([fdo#111407])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6961/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647


Participating hosts (51 -> 44)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6961 -> Patchwork_14544

  CI-20190529: 20190529
  CI_DRM_6961: d4a6e5482ea2429e4a9322c185eeebdd3c83a077 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5203: 82326332f7af336d390e00ae87187bc207fd33dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14544: ba0040eab5c92df64b4315cf680452febb89dc62 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ba0040eab5c9 drm/i915/tgl: initialize TC and TBT ports
a8bbfaeac6d6 drm/i915/tgl: Fix dkl link training
c7b3d1243169 drm/i915/tgl: Add dkl phy programming sequences
d034f381e8e0 drm/i915/tc: Update DP_MODE programming

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14544/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming
  2019-09-25 23:45 ` [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
@ 2019-09-26 12:02   ` Imre Deak
  2019-09-26 19:35     ` Souza, Jose
  0 siblings, 1 reply; 12+ messages in thread
From: Imre Deak @ 2019-09-26 12:02 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi

On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor <clinton.a.taylor@intel.com>
> 
> BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> now taking in consideration the pin assignment and allowing us to
> optimize power by shutting down available but not needed lanes.
> 
> It was tested on ICL and TGL, with adaptors that used pin assignment
> C and B, reversing the connector and going to different modes testing
> the not needed lane shutdown.
> 
> BSpec: 21735
> BSpec: 49292
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 82 +++++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_tc.c  | 15 +++++
>  drivers/gpu/drm/i915/display/intel_tc.h  |  1 +
>  drivers/gpu/drm/i915/i915_reg.h          |  5 ++
>  4 files changed, 66 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa470c70a198..316cedb16935 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3095,7 +3095,8 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
>  	enum port port = intel_dig_port->base.port;
> -	u32 ln0, ln1, lane_mask;
> +	u32 ln0, ln1, pin_assignment;
> +	u8 width;
>  
>  	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
>  		return;
> @@ -3103,50 +3104,57 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>  	ln0 = I915_READ(MG_DP_MODE(0, port));
>  	ln1 = I915_READ(MG_DP_MODE(1, port));
>  
> -	switch (intel_dig_port->tc_mode) {
> -	case TC_PORT_DP_ALT:
> -		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> -		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> +	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
> +	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>  
> -		lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
> +	/* DPPATC */
> +	pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
> +	width = intel_dig_port->dp.lane_count;

Should be crtc_state->lane_count. (dp.lane_count makes no sense for HDMI
and it's also only set for link training)

>  
> -		switch (lane_mask) {
> -		case 0x1:
> -		case 0x4:
> -			break;
> -		case 0x2:
> +	switch (pin_assignment) {
> +	case 0x0:
> +		WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
> +		if (width == 1) {
> +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> +		} else {
> +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +		}
> +		break;
> +	case 0x1:
> +		if (width == 4) {
> +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +		}
> +		break;
> +	case 0x2:
> +		if (width == 2) {
> +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +		}

nit: WARN_ON(width==4)?

> +		break;
> +	case 0x3:
> +	case 0x5:
> +		if (width == 1) {
>  			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> -			break;
> -		case 0x3:
> -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> -			       MG_DP_MODE_CFG_DP_X2_MODE;
> -			break;
> -		case 0x8:
>  			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> -			break;
> -		case 0xC:
> -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> -			       MG_DP_MODE_CFG_DP_X2_MODE;
> -			break;
> -		case 0xF:
> -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> -			       MG_DP_MODE_CFG_DP_X2_MODE;
> -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> -			       MG_DP_MODE_CFG_DP_X2_MODE;
> -			break;
> -		default:
> -			MISSING_CASE(lane_mask);
> +		} else {
> +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  		}
>  		break;
> -
> -	case TC_PORT_LEGACY:
> -		ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
> -		ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
> +	case 0x4:
> +	case 0x6:
> +		if (width == 1) {
> +			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> +		} else {
> +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> +		}

WARN_ON(width==4)?

With the lane_count fix:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  		break;
> -
>  	default:
> -		MISSING_CASE(intel_dig_port->tc_mode);
> -		return;
> +		MISSING_CASE(pin_assignment);
>  	}
>  
>  	I915_WRITE(MG_DP_MODE(0, port), ln0);
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index f923f9cbd33c..7773169b7331 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -67,6 +67,21 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
>  }
>  
> +u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_uncore *uncore = &i915->uncore;
> +	u32 pin_mask;
> +
> +	pin_mask = intel_uncore_read(uncore,
> +				     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
> +
> +	WARN_ON(pin_mask == 0xffffffff);
> +
> +	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
> +	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> +}
> +
>  int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
> index 783d75531435..463f1b3c836f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -13,6 +13,7 @@ struct intel_digital_port;
>  
>  bool intel_tc_port_connected(struct intel_digital_port *dig_port);
>  u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
> +u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
>  int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
>  void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>  				      int required_lanes);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..bcf449c1d152 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11857,6 +11857,11 @@ enum skl_power_gate {
>  #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
>  #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
>  
> +#define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
> +#define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
> +#define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
> +#define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
> +
>  /* This register controls the Display State Buffer (DSB) engines. */
>  #define _DSBSL_INSTANCE_BASE		0x70B00
>  #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
> -- 
> 2.23.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training
  2019-09-25 23:45 ` [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
@ 2019-09-26 13:06   ` Imre Deak
  0 siblings, 0 replies; 12+ messages in thread
From: Imre Deak @ 2019-09-26 13:06 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

On Wed, Sep 25, 2019 at 04:45:08PM -0700, José Roberto de Souza wrote:
> Link training is failling when running link at 2.7GHz and 1.62GHz and
> following BSpec pll algorithm.
> 
> Comparing the values calculated and the ones from the reference table
> it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
> to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
> div2 value, that matches with dkl hardcoded table.
> 
> So implementing this way as it proved to work in HW and leaving a
> comment so we know why it do not match BSpec.
> 
> v4:
> Using the same is_dp check as ICL, need testing on HDMI over tc port
> 
> Issue reported on BSpec 49204.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 69abafa45ce9..be69a2344294 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2630,13 +2630,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  				continue;
>  
>  			if (div2 >= 2) {
> -				if (is_dkl) {
> -					a_divratio = 5;
> -					tlinedrv = 1;
> -				} else {
> -					a_divratio = is_dp ? 10 : 5;
> -					tlinedrv = 2;
> -				}
> +				/*
> +				 * Note: a_divratio not matching TGL BSpec
> +				 * algorithm but matching hardcoded values and
> +				 * working on HW for DP alt-mode at least
> +				 */
> +				a_divratio = is_dp ? 10 : 5;
> +				tlinedrv = is_dkl ? 1 : 2;
>  			} else {
>  				a_divratio = 5;
>  				tlinedrv = 0;
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences
  2019-09-25 23:45 ` [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
@ 2019-09-26 15:34   ` Imre Deak
  2019-09-26 21:02     ` Souza, Jose
  0 siblings, 1 reply; 12+ messages in thread
From: Imre Deak @ 2019-09-26 15:34 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi

On Wed, Sep 25, 2019 at 04:45:07PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor <clinton.a.taylor@intel.com>
> 
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
> 
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that clock gating should be enabled after the
> link training but doing so causes all the following trainings to fail
> so not enabling it for.
> 
> v2:
> Setting the right HIP_INDEX_REG bits (José)
> 
> v3:
> Adding the meaning of each column of tgl_dkl_phy_ddi_translations
> Adding if gen >= 12 on intel_ddi_hdmi_level() and
> intel_ddi_pre_enable_hdmi() instead of reuse part of gen >= 11 if
> 
> v4:
> Moved the DP_MODE lane programing to another patch as ICL also
> needed it
> Sharing icl_phy_set_clock_gating() and icl_program_mg_dp_mode() with
> TGL as bits and programing as now it almost identical to ICL
> 
> BSpec: 49292
> BSpec: 49190
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 175 ++++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h          |   8 --
>  2 files changed, 155 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 316cedb16935..4da7940f1fcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -586,6 +586,26 @@ static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
>  	{ 0x0, 0x00, 0x00 },	/* 3              0   */
>  };
>  
> +struct tgl_dkl_phy_ddi_buf_trans {
> +	u32 dkl_vswing_control;
> +	u32 dkl_preshoot_control;
> +	u32 dkl_de_emphasis_control;
> +};
> +
> +static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
> +				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
> +	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
> +	{ 0x5, 0x0, 0x03 },	/* 0	1	400mV		3.5 dB */
> +	{ 0x2, 0x0, 0x0b },	/* 0	2	400mV		6 dB */
> +	{ 0x0, 0x0, 0x19 },	/* 0	3	400mV		9.5 dB */
> +	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
> +	{ 0x2, 0x0, 0x03 },	/* 1	1	600mV		3.5 dB */
> +	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
> +	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
> +	{ 0x0, 0x0, 0x0B },	/* 2	1	800mV		3.5 dB */
> +	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB HDMI default */
> +};
> +
>  static const struct ddi_buf_trans *
>  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> @@ -872,7 +892,14 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
> -	if (INTEL_GEN(dev_priv) >= 11) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		if (intel_phy_is_combo(dev_priv, phy))
> +			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> +						0, &n_entries);
> +		else
> +			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> +		default_entry = n_entries - 1;
> +	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
>  						0, &n_entries);
> @@ -2334,7 +2361,13 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	int n_entries;
>  
> -	if (INTEL_GEN(dev_priv) >= 11) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		if (intel_phy_is_combo(dev_priv, phy))
> +			icl_get_combo_buf_trans(dev_priv, encoder->type,
> +						intel_dp->link_rate, &n_entries);
> +		else
> +			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> +	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(dev_priv, encoder->type,
>  						intel_dp->link_rate, &n_entries);
> @@ -2776,6 +2809,63 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
>  }
>  
> +static void
> +tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> +				u32 level)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> +	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
> +	u32 n_entries, val, ln;
> +
> +	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> +	ddi_translations = tgl_dkl_phy_ddi_translations;
> +
> +	if (level >= n_entries)
> +		level = n_entries - 1;
> +
> +	for (ln = 0; ln < 2; ln++) {

nit:
	dpcntl_val = DKL_TX_VSWING_CONTROL(...) | ...;
	dpcntl_mask = ~(DKL_TX_PRESHOOT_COEFF_MASK | ...);

> +		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
> +
> +		/* All the registers are RMW */
> +		val = I915_READ(DKL_TX_DPCNTL0(tc_port));

	val &= ~dpcnt_mask;
	val |= dpcnt_val;

> +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			 DKL_TX_VSWING_CONTROL_MASK);
> +		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
> +		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
> +		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
> +		I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
> +
> +		val = I915_READ(DKL_TX_DPCNTL1(tc_port));

	val &= ~dpcnt_mask;
	val |= dpcnt_val;

> +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			 DKL_TX_VSWING_CONTROL_MASK);
> +		val |= DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
> +		val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
> +		val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
> +		I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
> +
> +		val = I915_READ(DKL_TX_DPCNTL2(tc_port));
> +		val &= ~DKL_TX_DP20BITMODE;
> +		I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
> +	}
> +}
> +
> +static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
> +				    int link_clock,
> +				    u32 level,
> +				    enum intel_output_type type)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> +	if (intel_phy_is_combo(dev_priv, phy))
> +		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> +	else
> +		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
> +}
> +
>  static u32 translate_signal_level(int signal_levels)
>  {
>  	int i;
> @@ -2807,7 +2897,10 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
>  	struct intel_encoder *encoder = &dport->base;
>  	int level = intel_ddi_dp_level(intel_dp);
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> +					level, encoder->type);
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
>  					level, encoder->type);
>  	else if (IS_CANNONLAKE(dev_priv))
> @@ -3071,38 +3164,61 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
>  	       MG_DP_MODE_CFG_GAONPWR_GATING;
>  
>  	for (ln = 0; ln < 2; ln++) {
> -		val = I915_READ(MG_DP_MODE(ln, port));
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
> +			val = I915_READ(DKL_DP_MODE(tc_port));
> +		} else {
> +			val = I915_READ(MG_DP_MODE(ln, port));
> +		}
> +
>  		if (enable)
>  			val |= bits;
>  		else
>  			val &= ~bits;
> -		I915_WRITE(MG_DP_MODE(ln, port), val);
> +
> +		if (INTEL_GEN(dev_priv) >= 12)
> +			I915_WRITE(DKL_DP_MODE(tc_port), val);
> +		else
> +			I915_WRITE(MG_DP_MODE(ln, port), val);
>  	}
>  
> -	bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
> -	       MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
> -	       MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
> +	if (INTEL_GEN(dev_priv) == 11) {

nit:
	if (GEN >= 12)
		return;

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
> +		       MG_MISC_SUS0_CFG_CL2PWR_GATING |
> +		       MG_MISC_SUS0_CFG_GAONPWR_GATING |
> +		       MG_MISC_SUS0_CFG_TRPWR_GATING |
> +		       MG_MISC_SUS0_CFG_CL1PWR_GATING |
> +		       MG_MISC_SUS0_CFG_DGPWR_GATING;
>  
> -	val = I915_READ(MG_MISC_SUS0(tc_port));
> -	if (enable)
> -		val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
> -	else
> -		val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
> -	I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +		val = I915_READ(MG_MISC_SUS0(tc_port));
> +		if (enable)
> +			val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
> +		else
> +			val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
> +		I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +	}
>  }
>  
>  static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
>  	enum port port = intel_dig_port->base.port;
> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>  	u32 ln0, ln1, pin_assignment;
>  	u8 width;
>  
>  	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
>  		return;
>  
> -	ln0 = I915_READ(MG_DP_MODE(0, port));
> -	ln1 = I915_READ(MG_DP_MODE(1, port));
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
> +		ln0 = I915_READ(DKL_DP_MODE(tc_port));
> +		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
> +		ln1 = I915_READ(DKL_DP_MODE(tc_port));
> +	} else {
> +		ln0 = I915_READ(MG_DP_MODE(0, port));
> +		ln1 = I915_READ(MG_DP_MODE(1, port));
> +	}
>  
>  	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
>  	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> @@ -3157,8 +3273,15 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
>  		MISSING_CASE(pin_assignment);
>  	}
>  
> -	I915_WRITE(MG_DP_MODE(0, port), ln0);
> -	I915_WRITE(MG_DP_MODE(1, port), ln1);
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
> +		I915_WRITE(DKL_DP_MODE(tc_port), ln0);
> +		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
> +		I915_WRITE(DKL_DP_MODE(tc_port), ln1);
> +	} else {
> +		I915_WRITE(MG_DP_MODE(0, port), ln0);
> +		I915_WRITE(MG_DP_MODE(1, port), ln1);
> +	}
>  }
>  
>  static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> @@ -3263,7 +3386,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	icl_phy_set_clock_gating(dig_port, false);
>  
>  	/* 7.e */
> -	icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> +	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
>  				encoder->type);
>  
>  	/* 7.f */
> @@ -3295,6 +3418,15 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	/* 7.k */
>  	intel_dp_stop_link_train(intel_dp);
>  
> +	/*
> +	 * TODO: enable clock gating
> +	 *
> +	 * It is not written in DP enabling sequence but "PHY Clockgating
> +	 * programming" states that clock gating should be enabled after the
> +	 * link training but doing so causes all the following trainings to fail
> +	 * so not enabling it for now.
> +	 */
> +
>  	/* 7.l */
>  	intel_ddi_enable_fec(encoder, crtc_state);
>  	intel_dsc_enable(encoder, crtc_state);
> @@ -3402,7 +3534,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>  	icl_program_mg_dp_mode(dig_port);
>  	icl_phy_set_clock_gating(dig_port, false);
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> +					level, INTEL_OUTPUT_HDMI);
> +	else if (INTEL_GEN(dev_priv) == 11)
>  		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
>  					level, INTEL_OUTPUT_HDMI);
>  	else if (IS_CANNONLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcf449c1d152..7f6b59aa6348 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10245,14 +10245,6 @@ enum skl_power_gate {
>  						     _DKL_TX_DW18)
>  
>  #define _DKL_DP_MODE					0xA0
> -#define  DKL_DP_MODE_CFG_GAONPWR_GATING		(1 << 1)
> -#define  DKL_DP_MODE_CFG_DIGPWR_GATING		(1 << 2)
> -#define  DKL_DP_MODE_CFG_CLNPWR_GATING		(1 << 3)
> -#define  DKL_DP_MODE_CFG_TRPWR_GATING		(1 << 4)
> -#define  DKL_DP_MODE_CFG_TR2PWR_GATING		(1 << 5)
> -#define  DKL_DP_MODE_CFG_GATING_CTRL_MASK	(0x1f << 1)
> -#define  DKL_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
> -#define  DKL_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
>  #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
>  						     _DKL_PHY1_BASE, \
>  						     _DKL_PHY2_BASE) + \
> -- 
> 2.23.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming
  2019-09-26 12:02   ` Imre Deak
@ 2019-09-26 19:35     ` Souza, Jose
  2019-09-26 19:41       ` Imre Deak
  0 siblings, 1 reply; 12+ messages in thread
From: Souza, Jose @ 2019-09-26 19:35 UTC (permalink / raw)
  To: Deak, Imre; +Cc: intel-gfx, De Marchi, Lucas

On Thu, 2019-09-26 at 15:02 +0300, Imre Deak wrote:
> On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza
> wrote:
> > From: Clinton A Taylor <clinton.a.taylor@intel.com>
> > 
> > BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> > now taking in consideration the pin assignment and allowing us to
> > optimize power by shutting down available but not needed lanes.
> > 
> > It was tested on ICL and TGL, with adaptors that used pin
> > assignment
> > C and B, reversing the connector and going to different modes
> > testing
> > the not needed lane shutdown.
> > 
> > BSpec: 21735
> > BSpec: 49292
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 82 +++++++++++++-------
> > ----
> >  drivers/gpu/drm/i915/display/intel_tc.c  | 15 +++++
> >  drivers/gpu/drm/i915/display/intel_tc.h  |  1 +
> >  drivers/gpu/drm/i915/i915_reg.h          |  5 ++
> >  4 files changed, 66 insertions(+), 37 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index aa470c70a198..316cedb16935 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3095,7 +3095,8 @@ static void icl_program_mg_dp_mode(struct
> > intel_digital_port *intel_dig_port)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> > >base.base.dev);
> >  	enum port port = intel_dig_port->base.port;
> > -	u32 ln0, ln1, lane_mask;
> > +	u32 ln0, ln1, pin_assignment;
> > +	u8 width;
> >  
> >  	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> >  		return;
> > @@ -3103,50 +3104,57 @@ static void icl_program_mg_dp_mode(struct
> > intel_digital_port *intel_dig_port)
> >  	ln0 = I915_READ(MG_DP_MODE(0, port));
> >  	ln1 = I915_READ(MG_DP_MODE(1, port));
> >  
> > -	switch (intel_dig_port->tc_mode) {
> > -	case TC_PORT_DP_ALT:
> > -		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE);
> > -		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE);
> > +	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X1_MODE);
> > +	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE);
> >  
> > -		lane_mask =
> > intel_tc_port_get_lane_mask(intel_dig_port);
> > +	/* DPPATC */
> > +	pin_assignment =
> > intel_tc_port_get_pin_assignment_mask(intel_dig_port);
> > +	width = intel_dig_port->dp.lane_count;
> 
> Should be crtc_state->lane_count. (dp.lane_count makes no sense for
> HDMI
> and it's also only set for link training)

Done

> 
> >  
> > -		switch (lane_mask) {
> > -		case 0x1:
> > -		case 0x4:
> > -			break;
> > -		case 0x2:
> > +	switch (pin_assignment) {
> > +	case 0x0:
> > +		WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
> > +		if (width == 1) {
> > +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > +		} else {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +		}
> > +		break;
> > +	case 0x1:
> > +		if (width == 4) {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +		}
> > +		break;
> > +	case 0x2:
> > +		if (width == 2) {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +		}
> 
> nit: WARN_ON(width==4)?

This lane assignment only has 2 lanes, so it will never be 4.

> 
> > +		break;
> > +	case 0x3:
> > +	case 0x5:
> > +		if (width == 1) {
> >  			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > -			break;
> > -		case 0x3:
> > -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > -			break;
> > -		case 0x8:
> >  			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > -			break;
> > -		case 0xC:
> > -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > -			break;
> > -		case 0xF:
> > -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > -			break;
> > -		default:
> > -			MISSING_CASE(lane_mask);
> > +		} else {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> >  		}
> >  		break;
> > -
> > -	case TC_PORT_LEGACY:
> > -		ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE;
> > -		ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE;
> > +	case 0x4:
> > +	case 0x6:
> > +		if (width == 1) {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > +		} else {
> > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > +		}
> 
> WARN_ON(width==4)?

Same as above.

> 
> With the lane_count fix:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks

> 
> >  		break;
> > -
> >  	default:
> > -		MISSING_CASE(intel_dig_port->tc_mode);
> > -		return;
> > +		MISSING_CASE(pin_assignment);
> >  	}
> >  
> >  	I915_WRITE(MG_DP_MODE(0, port), ln0);
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index f923f9cbd33c..7773169b7331 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -67,6 +67,21 @@ u32 intel_tc_port_get_lane_mask(struct
> > intel_digital_port *dig_port)
> >  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port-
> > >tc_phy_fia_idx);
> >  }
> >  
> > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > intel_digital_port *dig_port)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > +	struct intel_uncore *uncore = &i915->uncore;
> > +	u32 pin_mask;
> > +
> > +	pin_mask = intel_uncore_read(uncore,
> > +				     PORT_TX_DFLEXPA1(dig_port-
> > >tc_phy_fia));
> > +
> > +	WARN_ON(pin_mask == 0xffffffff);
> > +
> > +	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port-
> > >tc_phy_fia_idx)) >>
> > +	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> > +}
> > +
> >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port-
> > >base.base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> > b/drivers/gpu/drm/i915/display/intel_tc.h
> > index 783d75531435..463f1b3c836f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> > @@ -13,6 +13,7 @@ struct intel_digital_port;
> >  
> >  bool intel_tc_port_connected(struct intel_digital_port *dig_port);
> >  u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > *dig_port);
> > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > intel_digital_port *dig_port);
> >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > *dig_port);
> >  void intel_tc_port_set_fia_lane_count(struct intel_digital_port
> > *dig_port,
> >  				      int required_lanes);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index e752de9470bd..bcf449c1d152 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -11857,6 +11857,11 @@ enum skl_power_gate {
> >  #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia),
> > 0x00894)
> >  #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
> >  
> > +#define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia)
> > , 0x00880)
> > +#define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
> > +#define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx)
> > * 4))
> > +#define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx)
> > * 4))
> > +
> >  /* This register controls the Display State Buffer (DSB) engines.
> > */
> >  #define _DSBSL_INSTANCE_BASE		0x70B00
> >  #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
> > -- 
> > 2.23.0
> > 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming
  2019-09-26 19:35     ` Souza, Jose
@ 2019-09-26 19:41       ` Imre Deak
  0 siblings, 0 replies; 12+ messages in thread
From: Imre Deak @ 2019-09-26 19:41 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx, De Marchi, Lucas

On Thu, Sep 26, 2019 at 10:35:16PM +0300, Souza, Jose wrote:
> On Thu, 2019-09-26 at 15:02 +0300, Imre Deak wrote:
> > On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza
> > wrote:
> > > From: Clinton A Taylor <clinton.a.taylor@intel.com>
> > > 
> > > BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> > > now taking in consideration the pin assignment and allowing us to
> > > optimize power by shutting down available but not needed lanes.
> > > 
> > > It was tested on ICL and TGL, with adaptors that used pin
> > > assignment
> > > C and B, reversing the connector and going to different modes
> > > testing
> > > the not needed lane shutdown.
> > > 
> > > BSpec: 21735
> > > BSpec: 49292
> > > 
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 82 +++++++++++++-------
> > > ----
> > >  drivers/gpu/drm/i915/display/intel_tc.c  | 15 +++++
> > >  drivers/gpu/drm/i915/display/intel_tc.h  |  1 +
> > >  drivers/gpu/drm/i915/i915_reg.h          |  5 ++
> > >  4 files changed, 66 insertions(+), 37 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index aa470c70a198..316cedb16935 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -3095,7 +3095,8 @@ static void icl_program_mg_dp_mode(struct
> > > intel_digital_port *intel_dig_port)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> > > >base.base.dev);
> > >  	enum port port = intel_dig_port->base.port;
> > > -	u32 ln0, ln1, lane_mask;
> > > +	u32 ln0, ln1, pin_assignment;
> > > +	u8 width;
> > >  
> > >  	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> > >  		return;
> > > @@ -3103,50 +3104,57 @@ static void icl_program_mg_dp_mode(struct
> > > intel_digital_port *intel_dig_port)
> > >  	ln0 = I915_READ(MG_DP_MODE(0, port));
> > >  	ln1 = I915_READ(MG_DP_MODE(1, port));
> > >  
> > > -	switch (intel_dig_port->tc_mode) {
> > > -	case TC_PORT_DP_ALT:
> > > -		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X2_MODE);
> > > -		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X2_MODE);
> > > +	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X1_MODE);
> > > +	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X2_MODE);
> > >  
> > > -		lane_mask =
> > > intel_tc_port_get_lane_mask(intel_dig_port);
> > > +	/* DPPATC */
> > > +	pin_assignment =
> > > intel_tc_port_get_pin_assignment_mask(intel_dig_port);
> > > +	width = intel_dig_port->dp.lane_count;
> > 
> > Should be crtc_state->lane_count. (dp.lane_count makes no sense for
> > HDMI
> > and it's also only set for link training)
> 
> Done
> 
> > 
> > >  
> > > -		switch (lane_mask) {
> > > -		case 0x1:
> > > -		case 0x4:
> > > -			break;
> > > -		case 0x2:
> > > +	switch (pin_assignment) {
> > > +	case 0x0:
> > > +		WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
> > > +		if (width == 1) {
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > > +		} else {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +		}
> > > +		break;
> > > +	case 0x1:
> > > +		if (width == 4) {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +		}
> > > +		break;
> > > +	case 0x2:
> > > +		if (width == 2) {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +		}
> > 
> > nit: WARN_ON(width==4)?
> 
> This lane assignment only has 2 lanes, so it will never be 4.

Yes, hence the warn in case we attempted to configure 4 lanes.

> 
> > 
> > > +		break;
> > > +	case 0x3:
> > > +	case 0x5:
> > > +		if (width == 1) {
> > >  			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > > -			break;
> > > -		case 0x3:
> > > -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > > -			break;
> > > -		case 0x8:
> > >  			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > > -			break;
> > > -		case 0xC:
> > > -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > > -			break;
> > > -		case 0xF:
> > > -			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > > -			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > -			       MG_DP_MODE_CFG_DP_X2_MODE;
> > > -			break;
> > > -		default:
> > > -			MISSING_CASE(lane_mask);
> > > +		} else {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > >  		}
> > >  		break;
> > > -
> > > -	case TC_PORT_LEGACY:
> > > -		ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X2_MODE;
> > > -		ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> > > MG_DP_MODE_CFG_DP_X2_MODE;
> > > +	case 0x4:
> > > +	case 0x6:
> > > +		if (width == 1) {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> > > +		} else {
> > > +			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> > > +		}
> > 
> > WARN_ON(width==4)?
> 
> Same as above.
> 
> > 
> > With the lane_count fix:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> Thanks
> 
> > 
> > >  		break;
> > > -
> > >  	default:
> > > -		MISSING_CASE(intel_dig_port->tc_mode);
> > > -		return;
> > > +		MISSING_CASE(pin_assignment);
> > >  	}
> > >  
> > >  	I915_WRITE(MG_DP_MODE(0, port), ln0);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > > b/drivers/gpu/drm/i915/display/intel_tc.c
> > > index f923f9cbd33c..7773169b7331 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > > @@ -67,6 +67,21 @@ u32 intel_tc_port_get_lane_mask(struct
> > > intel_digital_port *dig_port)
> > >  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port-
> > > >tc_phy_fia_idx);
> > >  }
> > >  
> > > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > > intel_digital_port *dig_port)
> > > +{
> > > +	struct drm_i915_private *i915 = to_i915(dig_port-
> > > >base.base.dev);
> > > +	struct intel_uncore *uncore = &i915->uncore;
> > > +	u32 pin_mask;
> > > +
> > > +	pin_mask = intel_uncore_read(uncore,
> > > +				     PORT_TX_DFLEXPA1(dig_port-
> > > >tc_phy_fia));
> > > +
> > > +	WARN_ON(pin_mask == 0xffffffff);
> > > +
> > > +	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port-
> > > >tc_phy_fia_idx)) >>
> > > +	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> > > +}
> > > +
> > >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > > *dig_port)
> > >  {
> > >  	struct drm_i915_private *i915 = to_i915(dig_port-
> > > >base.base.dev);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> > > b/drivers/gpu/drm/i915/display/intel_tc.h
> > > index 783d75531435..463f1b3c836f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_tc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> > > @@ -13,6 +13,7 @@ struct intel_digital_port;
> > >  
> > >  bool intel_tc_port_connected(struct intel_digital_port *dig_port);
> > >  u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > > *dig_port);
> > > +u32 intel_tc_port_get_pin_assignment_mask(struct
> > > intel_digital_port *dig_port);
> > >  int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > > *dig_port);
> > >  void intel_tc_port_set_fia_lane_count(struct intel_digital_port
> > > *dig_port,
> > >  				      int required_lanes);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index e752de9470bd..bcf449c1d152 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -11857,6 +11857,11 @@ enum skl_power_gate {
> > >  #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia),
> > > 0x00894)
> > >  #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
> > >  
> > > +#define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia)
> > > , 0x00880)
> > > +#define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
> > > +#define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx)
> > > * 4))
> > > +#define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx)
> > > * 4))
> > > +
> > >  /* This register controls the Display State Buffer (DSB) engines.
> > > */
> > >  #define _DSBSL_INSTANCE_BASE		0x70B00
> > >  #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
> > > -- 
> > > 2.23.0
> > > 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences
  2019-09-26 15:34   ` Imre Deak
@ 2019-09-26 21:02     ` Souza, Jose
  0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-09-26 21:02 UTC (permalink / raw)
  To: Deak, Imre; +Cc: intel-gfx, De Marchi, Lucas

On Thu, 2019-09-26 at 18:34 +0300, Imre Deak wrote:
> On Wed, Sep 25, 2019 at 04:45:07PM -0700, José Roberto de Souza
> wrote:
> > From: Clinton A Taylor <clinton.a.taylor@intel.com>
> > 
> > Added DKL Phy sequences and helpers functions to program voltage
> > swing, clock gating and dp mode.
> > 
> > It is not written in DP enabling sequence but "PHY Clockgating
> > programming" states that clock gating should be enabled after the
> > link training but doing so causes all the following trainings to
> > fail
> > so not enabling it for.
> > 
> > v2:
> > Setting the right HIP_INDEX_REG bits (José)
> > 
> > v3:
> > Adding the meaning of each column of tgl_dkl_phy_ddi_translations
> > Adding if gen >= 12 on intel_ddi_hdmi_level() and
> > intel_ddi_pre_enable_hdmi() instead of reuse part of gen >= 11 if
> > 
> > v4:
> > Moved the DP_MODE lane programing to another patch as ICL also
> > needed it
> > Sharing icl_phy_set_clock_gating() and icl_program_mg_dp_mode()
> > with
> > TGL as bits and programing as now it almost identical to ICL
> > 
> > BSpec: 49292
> > BSpec: 49190
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 175
> > ++++++++++++++++++++---
> >  drivers/gpu/drm/i915/i915_reg.h          |   8 --
> >  2 files changed, 155 insertions(+), 28 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 316cedb16935..4da7940f1fcf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -586,6 +586,26 @@ static const struct icl_mg_phy_ddi_buf_trans
> > icl_mg_phy_ddi_translations[] = {
> >  	{ 0x0, 0x00, 0x00 },	/* 3              0   */
> >  };
> >  
> > +struct tgl_dkl_phy_ddi_buf_trans {
> > +	u32 dkl_vswing_control;
> > +	u32 dkl_preshoot_control;
> > +	u32 dkl_de_emphasis_control;
> > +};
> > +
> > +static const struct tgl_dkl_phy_ddi_buf_trans
> > tgl_dkl_phy_ddi_translations[] = {
> > +				/* VS	pre-emp	Non-trans mV	Pre
> > -emph dB */
> > +	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
> > +	{ 0x5, 0x0, 0x03 },	/* 0	1	400mV		3.5 dB */
> > +	{ 0x2, 0x0, 0x0b },	/* 0	2	400mV		6 dB */
> > +	{ 0x0, 0x0, 0x19 },	/* 0	3	400mV		9.5 dB */
> > +	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
> > +	{ 0x2, 0x0, 0x03 },	/* 1	1	600mV		3.5 dB */
> > +	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
> > +	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
> > +	{ 0x0, 0x0, 0x0B },	/* 2	1	800mV		3.5 dB */
> > +	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB HDMI
> > default */
> > +};
> > +
> >  static const struct ddi_buf_trans *
> >  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int
> > *n_entries)
> >  {
> > @@ -872,7 +892,14 @@ static int intel_ddi_hdmi_level(struct
> > drm_i915_private *dev_priv, enum port por
> >  
> >  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> >  
> > -	if (INTEL_GEN(dev_priv) >= 11) {
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		if (intel_phy_is_combo(dev_priv, phy))
> > +			icl_get_combo_buf_trans(dev_priv,
> > INTEL_OUTPUT_HDMI,
> > +						0, &n_entries);
> > +		else
> > +			n_entries =
> > ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> > +		default_entry = n_entries - 1;
> > +	} else if (INTEL_GEN(dev_priv) == 11) {
> >  		if (intel_phy_is_combo(dev_priv, phy))
> >  			icl_get_combo_buf_trans(dev_priv,
> > INTEL_OUTPUT_HDMI,
> >  						0, &n_entries);
> > @@ -2334,7 +2361,13 @@ u8 intel_ddi_dp_voltage_max(struct
> > intel_encoder *encoder)
> >  	enum phy phy = intel_port_to_phy(dev_priv, port);
> >  	int n_entries;
> >  
> > -	if (INTEL_GEN(dev_priv) >= 11) {
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		if (intel_phy_is_combo(dev_priv, phy))
> > +			icl_get_combo_buf_trans(dev_priv, encoder-
> > >type,
> > +						intel_dp->link_rate,
> > &n_entries);
> > +		else
> > +			n_entries =
> > ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> > +	} else if (INTEL_GEN(dev_priv) == 11) {
> >  		if (intel_phy_is_combo(dev_priv, phy))
> >  			icl_get_combo_buf_trans(dev_priv, encoder-
> > >type,
> >  						intel_dp->link_rate,
> > &n_entries);
> > @@ -2776,6 +2809,63 @@ static void icl_ddi_vswing_sequence(struct
> > intel_encoder *encoder,
> >  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> > level);
> >  }
> >  
> > +static void
> > +tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int
> > link_clock,
> > +				u32 level)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder-
> > >port);
> > +	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
> > +	u32 n_entries, val, ln;
> > +
> > +	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> > +	ddi_translations = tgl_dkl_phy_ddi_translations;
> > +
> > +	if (level >= n_entries)
> > +		level = n_entries - 1;
> > +
> > +	for (ln = 0; ln < 2; ln++) {
> 
> nit:
> 	dpcntl_val = DKL_TX_VSWING_CONTROL(...) | ...;
> 	dpcntl_mask = ~(DKL_TX_PRESHOOT_COEFF_MASK | ...);
> 
> > +		I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, ln));
> > +
> > +		/* All the registers are RMW */
> > +		val = I915_READ(DKL_TX_DPCNTL0(tc_port));
> 
> 	val &= ~dpcnt_mask;
> 	val |= dpcnt_val;
> 

Nice idea, moved dpcntl_val/mask even out of the loop.

> > +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> > +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> > +			 DKL_TX_VSWING_CONTROL_MASK);
> > +		val |=
> > DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
> > +		val |=
> > DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_co
> > ntrol);
> > +		val |=
> > DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control)
> > ;
> > +		I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
> > +
> > +		val = I915_READ(DKL_TX_DPCNTL1(tc_port));
> 
> 	val &= ~dpcnt_mask;
> 	val |= dpcnt_val;
> 
> > +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> > +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> > +			 DKL_TX_VSWING_CONTROL_MASK);
> > +		val |=
> > DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
> > +		val |=
> > DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_co
> > ntrol);
> > +		val |=
> > DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control)
> > ;
> > +		I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
> > +
> > +		val = I915_READ(DKL_TX_DPCNTL2(tc_port));
> > +		val &= ~DKL_TX_DP20BITMODE;
> > +		I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
> > +	}
> > +}
> > +
> > +static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
> > +				    int link_clock,
> > +				    u32 level,
> > +				    enum intel_output_type type)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > +
> > +	if (intel_phy_is_combo(dev_priv, phy))
> > +		icl_combo_phy_ddi_vswing_sequence(encoder, level,
> > type);
> > +	else
> > +		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock,
> > level);
> > +}
> > +
> >  static u32 translate_signal_level(int signal_levels)
> >  {
> >  	int i;
> > @@ -2807,7 +2897,10 @@ u32 bxt_signal_levels(struct intel_dp
> > *intel_dp)
> >  	struct intel_encoder *encoder = &dport->base;
> >  	int level = intel_ddi_dp_level(intel_dp);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 11)
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> > +					level, encoder->type);
> > +	else if (INTEL_GEN(dev_priv) >= 11)
> >  		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> >  					level, encoder->type);
> >  	else if (IS_CANNONLAKE(dev_priv))
> > @@ -3071,38 +3164,61 @@ icl_phy_set_clock_gating(struct
> > intel_digital_port *dig_port, bool enable)
> >  	       MG_DP_MODE_CFG_GAONPWR_GATING;
> >  
> >  	for (ln = 0; ln < 2; ln++) {
> > -		val = I915_READ(MG_DP_MODE(ln, port));
> > +		if (INTEL_GEN(dev_priv) >= 12) {
> > +			I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, ln));
> > +			val = I915_READ(DKL_DP_MODE(tc_port));
> > +		} else {
> > +			val = I915_READ(MG_DP_MODE(ln, port));
> > +		}
> > +
> >  		if (enable)
> >  			val |= bits;
> >  		else
> >  			val &= ~bits;
> > -		I915_WRITE(MG_DP_MODE(ln, port), val);
> > +
> > +		if (INTEL_GEN(dev_priv) >= 12)
> > +			I915_WRITE(DKL_DP_MODE(tc_port), val);
> > +		else
> > +			I915_WRITE(MG_DP_MODE(ln, port), val);
> >  	}
> >  
> > -	bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
> > MG_MISC_SUS0_CFG_CL2PWR_GATING |
> > -	       MG_MISC_SUS0_CFG_GAONPWR_GATING |
> > MG_MISC_SUS0_CFG_TRPWR_GATING |
> > -	       MG_MISC_SUS0_CFG_CL1PWR_GATING |
> > MG_MISC_SUS0_CFG_DGPWR_GATING;
> > +	if (INTEL_GEN(dev_priv) == 11) {
> 
> nit:
> 	if (GEN >= 12)
> 		return;
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks

> 
> > +		bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
> > +		       MG_MISC_SUS0_CFG_CL2PWR_GATING |
> > +		       MG_MISC_SUS0_CFG_GAONPWR_GATING |
> > +		       MG_MISC_SUS0_CFG_TRPWR_GATING |
> > +		       MG_MISC_SUS0_CFG_CL1PWR_GATING |
> > +		       MG_MISC_SUS0_CFG_DGPWR_GATING;
> >  
> > -	val = I915_READ(MG_MISC_SUS0(tc_port));
> > -	if (enable)
> > -		val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
> > -	else
> > -		val &= ~(bits |
> > MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
> > -	I915_WRITE(MG_MISC_SUS0(tc_port), val);
> > +		val = I915_READ(MG_MISC_SUS0(tc_port));
> > +		if (enable)
> > +			val |= (bits |
> > MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
> > +		else
> > +			val &= ~(bits |
> > MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
> > +		I915_WRITE(MG_MISC_SUS0(tc_port), val);
> > +	}
> >  }
> >  
> >  static void icl_program_mg_dp_mode(struct intel_digital_port
> > *intel_dig_port)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> > >base.base.dev);
> >  	enum port port = intel_dig_port->base.port;
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> >  	u32 ln0, ln1, pin_assignment;
> >  	u8 width;
> >  
> >  	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> >  		return;
> >  
> > -	ln0 = I915_READ(MG_DP_MODE(0, port));
> > -	ln1 = I915_READ(MG_DP_MODE(1, port));
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, 0x0));
> > +		ln0 = I915_READ(DKL_DP_MODE(tc_port));
> > +		I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, 0x1));
> > +		ln1 = I915_READ(DKL_DP_MODE(tc_port));
> > +	} else {
> > +		ln0 = I915_READ(MG_DP_MODE(0, port));
> > +		ln1 = I915_READ(MG_DP_MODE(1, port));
> > +	}
> >  
> >  	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X1_MODE);
> >  	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> > MG_DP_MODE_CFG_DP_X2_MODE);
> > @@ -3157,8 +3273,15 @@ static void icl_program_mg_dp_mode(struct
> > intel_digital_port *intel_dig_port)
> >  		MISSING_CASE(pin_assignment);
> >  	}
> >  
> > -	I915_WRITE(MG_DP_MODE(0, port), ln0);
> > -	I915_WRITE(MG_DP_MODE(1, port), ln1);
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, 0x0));
> > +		I915_WRITE(DKL_DP_MODE(tc_port), ln0);
> > +		I915_WRITE(HIP_INDEX_REG(tc_port),
> > HIP_INDEX_VAL(tc_port, 0x1));
> > +		I915_WRITE(DKL_DP_MODE(tc_port), ln1);
> > +	} else {
> > +		I915_WRITE(MG_DP_MODE(0, port), ln0);
> > +		I915_WRITE(MG_DP_MODE(1, port), ln1);
> > +	}
> >  }
> >  
> >  static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> > @@ -3263,7 +3386,7 @@ static void tgl_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> >  	icl_phy_set_clock_gating(dig_port, false);
> >  
> >  	/* 7.e */
> > -	icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > +	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> >  				encoder->type);
> >  
> >  	/* 7.f */
> > @@ -3295,6 +3418,15 @@ static void tgl_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> >  	/* 7.k */
> >  	intel_dp_stop_link_train(intel_dp);
> >  
> > +	/*
> > +	 * TODO: enable clock gating
> > +	 *
> > +	 * It is not written in DP enabling sequence but "PHY
> > Clockgating
> > +	 * programming" states that clock gating should be enabled
> > after the
> > +	 * link training but doing so causes all the following
> > trainings to fail
> > +	 * so not enabling it for now.
> > +	 */
> > +
> >  	/* 7.l */
> >  	intel_ddi_enable_fec(encoder, crtc_state);
> >  	intel_dsc_enable(encoder, crtc_state);
> > @@ -3402,7 +3534,10 @@ static void intel_ddi_pre_enable_hdmi(struct
> > intel_encoder *encoder,
> >  	icl_program_mg_dp_mode(dig_port);
> >  	icl_phy_set_clock_gating(dig_port, false);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 11)
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		tgl_ddi_vswing_sequence(encoder, crtc_state-
> > >port_clock,
> > +					level, INTEL_OUTPUT_HDMI);
> > +	else if (INTEL_GEN(dev_priv) == 11)
> >  		icl_ddi_vswing_sequence(encoder, crtc_state-
> > >port_clock,
> >  					level, INTEL_OUTPUT_HDMI);
> >  	else if (IS_CANNONLAKE(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index bcf449c1d152..7f6b59aa6348 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10245,14 +10245,6 @@ enum skl_power_gate {
> >  						     _DKL_TX_DW18)
> >  
> >  #define _DKL_DP_MODE					0xA0
> > -#define  DKL_DP_MODE_CFG_GAONPWR_GATING		(1 << 1)
> > -#define  DKL_DP_MODE_CFG_DIGPWR_GATING		(1 << 2)
> > -#define  DKL_DP_MODE_CFG_CLNPWR_GATING		(1 << 3)
> > -#define  DKL_DP_MODE_CFG_TRPWR_GATING		(1 << 4)
> > -#define  DKL_DP_MODE_CFG_TR2PWR_GATING		(1 << 5)
> > -#define  DKL_DP_MODE_CFG_GATING_CTRL_MASK	(0x1f << 1)
> > -#define  DKL_DP_MODE_CFG_DP_X1_MODE			(1 <<
> > 6)
> > -#define  DKL_DP_MODE_CFG_DP_X2_MODE			(1 <<
> > 7)
> >  #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
> >  						     _DKL_PHY1_BASE, \
> >  						     _DKL_PHY2_BASE) +
> > \
> > -- 
> > 2.23.0
> > 
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^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2019-09-26 21:02 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-25 23:45 [PATCH v4 0/4] TGL TC enabling v4 José Roberto de Souza
2019-09-25 23:45 ` [PATCH v4 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
2019-09-26 12:02   ` Imre Deak
2019-09-26 19:35     ` Souza, Jose
2019-09-26 19:41       ` Imre Deak
2019-09-25 23:45 ` [PATCH v4 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
2019-09-26 15:34   ` Imre Deak
2019-09-26 21:02     ` Souza, Jose
2019-09-25 23:45 ` [PATCH v4 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
2019-09-26 13:06   ` Imre Deak
2019-09-25 23:45 ` [PATCH v4 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
2019-09-26  0:58 ` ✓ Fi.CI.BAT: success for TGL TC enabling (rev4) Patchwork

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