* [PATCH 0/5] TriCore fixes and gdbstub
@ 2019-09-30 12:46 Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 1/5] target/tricore: Don't save pc in generate_qemu_excp Bastian Koppelmann
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: david.brenken
Hi,
this series fixes a few TriCore problems:
- Segfault due to non initialized ctx->env ptr (see
https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg03527.html)
I fixed this by properly detangling any reference of the env pointer in the
translate functions. (as suggested by Peter Maydell)
- Unimplemented tricore_cpu_get_phys_page_debug() which lead to a temporary fix
(see b190f477e29c7cd03a8fee49c96d27f160e3f5b0)
The last patch implements a gdbstub for TriCore.
Cheers,
Bastian
Bastian Koppelmann (5):
target/tricore: Don't save pc in generate_qemu_excp
target/tricore: Move translate feature check to ctx
target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep
target/tricore: Implement tricore_cpu_get_phys_page_debug
target/tricore: Implement gdbstub
target/tricore/Makefile.objs | 2 +-
target/tricore/cpu.c | 18 +++--
target/tricore/cpu.h | 2 +
target/tricore/gdbstub.c | 138 +++++++++++++++++++++++++++++++++++
target/tricore/helper.c | 13 ++++
target/tricore/translate.c | 79 ++++++++++----------
6 files changed, 206 insertions(+), 46 deletions(-)
create mode 100644 target/tricore/gdbstub.c
--
2.23.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/5] target/tricore: Don't save pc in generate_qemu_excp
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
@ 2019-09-30 12:46 ` Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 2/5] target/tricore: Move translate feature check to ctx Bastian Koppelmann
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: david.brenken
EXCP_DEBUG is the only user. If we encounter a jump in tricore-gdb it's
target was overwritten by generate_qemu_excp() and we would never leave.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c574638c9f..c556e9a7ab 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3264,7 +3264,6 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
static void generate_qemu_excp(DisasContext *ctx, int excp)
{
TCGv_i32 tmp = tcg_const_i32(excp);
- gen_save_pc(ctx->base.pc_next);
gen_helper_qemu_excp(cpu_env, tmp);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tmp);
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/5] target/tricore: Move translate feature check to ctx
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 1/5] target/tricore: Don't save pc in generate_qemu_excp Bastian Koppelmann
@ 2019-09-30 12:46 ` Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 3/5] target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep Bastian Koppelmann
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Konopik, david.brenken
this allows us to remove the references to env from ctx. This also fixes
a segfault that was due to the unititalized ctx->env ptr.
Reported-by: Andreas Konopik <andreas.konopik@fau.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 60 +++++++++++++++++++++-----------------
1 file changed, 33 insertions(+), 27 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c556e9a7ab..832ff6328d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -66,14 +66,19 @@ static const char *regnames_d[] = {
typedef struct DisasContext {
DisasContextBase base;
- CPUTriCoreState *env;
target_ulong pc_succ_insn;
uint32_t opcode;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
+ uint64_t features;
} DisasContext;
+static int has_feature(DisasContext *ctx, int feature)
+{
+ return (ctx->features & (1ULL << feature)) != 0;
+}
+
enum {
MODE_LL = 0,
MODE_LU = 1,
@@ -370,7 +375,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
These makros also specify in which ISA version the csfr was introduced. */
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
- if (tricore_feature(ctx->env, FEATURE)) { \
+ if (has_feature(ctx, FEATURE)) { \
tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
@@ -395,7 +400,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
since no execption occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
- if (tricore_feature(ctx->env, FEATURE)) { \
+ if (has_feature(ctx, FEATURE)) { \
tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
@@ -3158,7 +3163,7 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
- if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
@@ -3173,7 +3178,7 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
- if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
@@ -3655,7 +3660,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_MOV_E:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
} else {
@@ -4106,7 +4111,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
break;
case OPC1_16_SBC_JEQ2:
case OPC1_16_SBC_JNE2:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
address = MASK_OP_SBC_DISP4(ctx->opcode);
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
@@ -4124,7 +4129,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
/* SBR-format */
case OPC1_16_SBR_JEQ2:
case OPC1_16_SBR_JNE2:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
r1 = MASK_OP_SBR_S2(ctx->opcode);
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
@@ -4704,13 +4709,13 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
- if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (!has_feature(ctx, TRICORE_FEATURE_131)) {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (has_feature(ctx, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4718,7 +4723,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (has_feature(ctx, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -5372,7 +5377,7 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
break;
case OPC1_32_BOL_ST_A_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -5382,42 +5387,42 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
case OPC1_32_BOL_LD_B_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6022,7 +6027,7 @@ static void decode_rlc_opc(DisasContext *ctx,
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_64:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r2);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
@@ -6248,7 +6253,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_64:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
temp = tcg_temp_new();
CHECK_REG_PAIR(r3);
@@ -6262,7 +6267,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
}
break;
case OPC2_32_RR_MOVS_64:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
@@ -6602,7 +6607,7 @@ static void decode_rr_divide(DisasContext *ctx)
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
- if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (!has_feature(ctx, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_abs_tl(temp, temp3);
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
@@ -6635,7 +6640,7 @@ static void decode_rr_divide(DisasContext *ctx)
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
- if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
+ if (!has_feature(ctx, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_abs_tl(temp, temp3);
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
@@ -6698,14 +6703,14 @@ static void decode_rr_divide(DisasContext *ctx)
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CRC32:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_161)) {
+ if (has_feature(ctx, TRICORE_FEATURE_161)) {
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_DIV:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
} else {
@@ -6713,7 +6718,7 @@ static void decode_rr_divide(DisasContext *ctx)
}
break;
case OPC2_32_RR_DIV_U:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
@@ -8411,7 +8416,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
gen_helper_svlcx(cpu_env);
break;
case OPC2_32_SYS_RESTORE:
- if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
@@ -8792,6 +8797,7 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
CPUTriCoreState *env = cs->env_ptr;
ctx->mem_idx = cpu_mmu_index(env, false);
ctx->hflags = (uint32_t)ctx->base.tb->flags;
+ ctx->features = env->features;
}
static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/5] target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 1/5] target/tricore: Don't save pc in generate_qemu_excp Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 2/5] target/tricore: Move translate feature check to ctx Bastian Koppelmann
@ 2019-09-30 12:46 ` Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 4/5] target/tricore: Implement tricore_cpu_get_phys_page_debug Bastian Koppelmann
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: david.brenken
this is needed for remote gdb connections.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 832ff6328d..6c6303795d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3238,6 +3238,14 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
#endif
}
+static void generate_qemu_excp(DisasContext *ctx, int excp)
+{
+ TCGv_i32 tmp = tcg_const_i32(excp);
+ gen_helper_qemu_excp(cpu_env, tmp);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ tcg_temp_free(tmp);
+}
+
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
@@ -3247,7 +3255,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
} else {
gen_save_pc(dest);
if (ctx->base.singlestep_enabled) {
- /* raise exception debug */
+ generate_qemu_excp(ctx, EXCP_DEBUG);
}
tcg_gen_exit_tb(NULL, 0);
}
@@ -3266,14 +3274,6 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
tcg_temp_free(tintemp);
}
-static void generate_qemu_excp(DisasContext *ctx, int excp)
-{
- TCGv_i32 tmp = tcg_const_i32(excp);
- gen_helper_qemu_excp(cpu_env, tmp);
- ctx->base.is_jmp = DISAS_NORETURN;
- tcg_temp_free(tmp);
-}
-
static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/5] target/tricore: Implement tricore_cpu_get_phys_page_debug
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
` (2 preceding siblings ...)
2019-09-30 12:46 ` [PATCH 3/5] target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep Bastian Koppelmann
@ 2019-09-30 12:46 ` Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 5/5] target/tricore: Implement gdbstub Bastian Koppelmann
2019-09-30 14:38 ` [PATCH 0/5] TriCore fixes and gdbstub no-reply
5 siblings, 0 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: david.brenken
this also removes tricore_cpu_get_phys_page_attrs_debug() as it was a
temporary fix from b190f477e29c7cd03a8fee49c96d27f160e3f5b0.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/cpu.c | 10 +---------
target/tricore/helper.c | 13 +++++++++++++
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index df807c1d74..7159d9cf8f 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -23,14 +23,6 @@
#include "exec/exec-all.h"
#include "qemu/error-report.h"
-static hwaddr tricore_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- error_report("function cpu_get_phys_page_attrs_debug not "
- "implemented, aborting");
- return -1;
-}
-
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
@@ -161,7 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
- cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug;
+ cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
}
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index d5db7b2c03..7715293263 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -42,6 +42,19 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
return ret;
}
+
+hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+{
+ TriCoreCPU *cpu = TRICORE_CPU(cs);
+ hwaddr phys_addr;
+ int prot;
+ int mmu_idx = cpu_mmu_index(&cpu->env, false);
+
+ if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
+ return -1;
+ }
+ return phys_addr;
+}
#endif
/* TODO: Add exeption support*/
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 5/5] target/tricore: Implement gdbstub
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
` (3 preceding siblings ...)
2019-09-30 12:46 ` [PATCH 4/5] target/tricore: Implement tricore_cpu_get_phys_page_debug Bastian Koppelmann
@ 2019-09-30 12:46 ` Bastian Koppelmann
2019-09-30 14:38 ` [PATCH 0/5] TriCore fixes and gdbstub no-reply
5 siblings, 0 replies; 7+ messages in thread
From: Bastian Koppelmann @ 2019-09-30 12:46 UTC (permalink / raw)
To: qemu-devel; +Cc: david.brenken
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/Makefile.objs | 2 +-
target/tricore/cpu.c | 10 +++
target/tricore/cpu.h | 2 +
target/tricore/gdbstub.c | 138 +++++++++++++++++++++++++++++++++++
4 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 target/tricore/gdbstub.c
diff --git a/target/tricore/Makefile.objs b/target/tricore/Makefile.objs
index 7a05670718..281b55f08d 100644
--- a/target/tricore/Makefile.objs
+++ b/target/tricore/Makefile.objs
@@ -1 +1 @@
-obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o
+obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o gdbstub.o
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 7159d9cf8f..fee2f0f5d7 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -28,6 +28,11 @@ static inline void set_feature(CPUTriCoreState *env, int feature)
env->features |= 1ULL << feature;
}
+static gchar *tricore_gdb_arch_name(CPUState *cs)
+{
+ return g_strdup("tricore");
+}
+
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
@@ -150,6 +155,11 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = tricore_cpu_class_by_name;
cc->has_work = tricore_cpu_has_work;
+ cc->gdb_read_register = tricore_cpu_gdb_read_register;
+ cc->gdb_write_register = tricore_cpu_gdb_write_register;
+ cc->gdb_num_core_regs = 44;
+ cc->gdb_arch_name = tricore_gdb_arch_name;
+
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 8c014fad07..49d282f728 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -353,6 +353,8 @@ enum {
uint32_t psw_read(CPUTriCoreState *env);
void psw_write(CPUTriCoreState *env, uint32_t val);
+int tricore_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n);
+int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void fpu_set_state(CPUTriCoreState *env);
diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c
new file mode 100644
index 0000000000..87761f20e9
--- /dev/null
+++ b/target/tricore/gdbstub.c
@@ -0,0 +1,138 @@
+/*
+ * TriCore gdb server stub
+ *
+ * Copyright (c) 2019 Bastian Koppelmann, Paderborn University
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+
+
+#define LCX_REGNUM 32
+#define FCX_REGNUM 33
+#define PCXI_REGNUM 34
+#define TRICORE_PSW_REGNUM 35
+#define TRICORE_PC_REGNUM 36
+#define ICR_REGNUM 37
+#define ISP_REGNUM 38
+#define BTV_REGNUM 39
+#define BIV_REGNUM 40
+#define SYSCON_REGNUM 41
+#define PMUCON0_REGNUM 42
+#define DMUCON_REGNUM 43
+
+static uint32_t tricore_cpu_gdb_read_csfr(CPUTriCoreState *env, int n)
+{
+ switch (n) {
+ case LCX_REGNUM:
+ return env->LCX;
+ case FCX_REGNUM:
+ return env->FCX;
+ case PCXI_REGNUM:
+ return env->PCXI;
+ case TRICORE_PSW_REGNUM:
+ return psw_read(env);
+ case TRICORE_PC_REGNUM:
+ return env->PC;
+ case ICR_REGNUM:
+ return env->ICR;
+ case ISP_REGNUM:
+ return env->ISP;
+ case BTV_REGNUM:
+ return env->BTV;
+ case BIV_REGNUM:
+ return env->BIV;
+ case SYSCON_REGNUM:
+ return env->SYSCON;
+ case PMUCON0_REGNUM:
+ return 0; /* PMUCON0 */
+ case DMUCON_REGNUM:
+ return 0; /* DMUCON0 */
+ default:
+ return 0;
+ }
+}
+
+static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n, uint32_t val)
+{
+ switch (n) {
+ case LCX_REGNUM:
+ env->LCX = val;
+ break;
+ case FCX_REGNUM:
+ env->FCX = val;
+ break;
+ case PCXI_REGNUM:
+ env->PCXI = val;
+ break;
+ case TRICORE_PSW_REGNUM:
+ psw_write(env, val);
+ break;
+ case TRICORE_PC_REGNUM:
+ env->PC = val;
+ break;
+ case ICR_REGNUM:
+ env->ICR = val;
+ break;
+ case ISP_REGNUM:
+ env->ISP = val;
+ break;
+ case BTV_REGNUM:
+ env->BTV = val;
+ break;
+ case BIV_REGNUM:
+ env->BIV = val;
+ break;
+ case SYSCON_REGNUM:
+ env->SYSCON = val;
+ break;
+ }
+}
+
+
+int tricore_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ TriCoreCPU *cpu = TRICORE_CPU(cs);
+ CPUTriCoreState *env = &cpu->env;
+
+ if (n < 16) { /* data registers */
+ return gdb_get_reg32(mem_buf, env->gpr_d[n]);
+ } else if (n < 32) { /* address registers */
+ return gdb_get_reg32(mem_buf, env->gpr_a[n-16]);
+ } else { /* csfr */
+ return gdb_get_reg32(mem_buf, tricore_cpu_gdb_read_csfr(env, n));
+ }
+ return 0;
+}
+
+int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ TriCoreCPU *cpu = TRICORE_CPU(cs);
+ CPUTriCoreState *env = &cpu->env;
+ uint32_t tmp;
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 16) { /* data registers */
+ env->gpr_d[n] = tmp;
+ } else if (n < 32) { /* address registers */
+ env->gpr_d[n-16] = tmp;
+ } else {
+ tricore_cpu_gdb_write_csfr(env, n, tmp);
+ }
+ return 4;
+}
--
2.23.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/5] TriCore fixes and gdbstub
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
` (4 preceding siblings ...)
2019-09-30 12:46 ` [PATCH 5/5] target/tricore: Implement gdbstub Bastian Koppelmann
@ 2019-09-30 14:38 ` no-reply
5 siblings, 0 replies; 7+ messages in thread
From: no-reply @ 2019-09-30 14:38 UTC (permalink / raw)
To: kbastian; +Cc: david.brenken, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190930124643.179695-1-kbastian@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190930124643.179695-1-kbastian@mail.uni-paderborn.de
Subject: [PATCH 0/5] TriCore fixes and gdbstub
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
e0ab359 target/tricore: Implement gdbstub
af906d6 target/tricore: Implement tricore_cpu_get_phys_page_debug
421ac82 target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep
5a6c845 target/tricore: Move translate feature check to ctx
69f10b4 target/tricore: Don't save pc in generate_qemu_excp
=== OUTPUT BEGIN ===
1/5 Checking commit 69f10b4a4d39 (target/tricore: Don't save pc in generate_qemu_excp)
2/5 Checking commit 5a6c84545f56 (target/tricore: Move translate feature check to ctx)
3/5 Checking commit 421ac8270548 (target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep)
4/5 Checking commit af906d6437cd (target/tricore: Implement tricore_cpu_get_phys_page_debug)
5/5 Checking commit e0ab359a6c96 (target/tricore: Implement gdbstub)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#59:
new file mode 100644
WARNING: line over 80 characters
#133: FILE: target/tricore/gdbstub.c:70:
+static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n, uint32_t val)
ERROR: spaces required around that '-' (ctx:VxV)
#178: FILE: target/tricore/gdbstub.c:115:
+ return gdb_get_reg32(mem_buf, env->gpr_a[n-16]);
^
ERROR: spaces required around that '-' (ctx:VxV)
#196: FILE: target/tricore/gdbstub.c:133:
+ env->gpr_d[n-16] = tmp;
^
total: 2 errors, 2 warnings, 170 lines checked
Patch 5/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190930124643.179695-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-09-30 14:40 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-30 12:46 [PATCH 0/5] TriCore fixes and gdbstub Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 1/5] target/tricore: Don't save pc in generate_qemu_excp Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 2/5] target/tricore: Move translate feature check to ctx Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 3/5] target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 4/5] target/tricore: Implement tricore_cpu_get_phys_page_debug Bastian Koppelmann
2019-09-30 12:46 ` [PATCH 5/5] target/tricore: Implement gdbstub Bastian Koppelmann
2019-09-30 14:38 ` [PATCH 0/5] TriCore fixes and gdbstub no-reply
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