All of lore.kernel.org
 help / color / mirror / Atom feed
From: Petri Latvala <petri.latvala@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: igt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Date: Wed, 2 Oct 2019 14:38:31 +0300	[thread overview]
Message-ID: <20191002113831.GG4019@platvala-desk.ger.corp.intel.com> (raw)
In-Reply-To: <20191002112648.12532-1-chris@chris-wilson.co.uk>

On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_ctx_isolation.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..819daafc3 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
>  #define GEN9 (ALL << 9)
>  #define GEN10 (ALL << 10)
>  #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>  
>  #define NOCTX 0
>  
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>  
>  static const struct named_register {
>  	const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
>  	{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
>  	{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
>  	{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> -	{ "L3_Config", GEN8, RCS0, 0x7034 },
> -	{ "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
> -	{ "TD_CTL2", GEN8, RCS0, 0xe404 },
> +	{ "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> +	{ "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff },
> +	{ "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
>  	{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
>  	{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
>  	{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -852,7 +853,7 @@ igt_main
>  		gen = intel_gen(intel_get_drm_devid(fd));
>  
>  		igt_warn_on_f(gen > LAST_KNOWN_GEN,
> -					  "GEN not recognized! Test needs to be updated to run.");
> +			      "GEN not recognized! Test needs to be updated to run.");
>  		igt_skip_on(gen > LAST_KNOWN_GEN);

Thanks to this editorial change, we're able to see that this string is
missing a newline character.


-- 
Petri Latvala
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Petri Latvala <petri.latvala@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: igt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Date: Wed, 2 Oct 2019 14:38:31 +0300	[thread overview]
Message-ID: <20191002113831.GG4019@platvala-desk.ger.corp.intel.com> (raw)
In-Reply-To: <20191002112648.12532-1-chris@chris-wilson.co.uk>

On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/i915/gem_ctx_isolation.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..819daafc3 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
>  #define GEN9 (ALL << 9)
>  #define GEN10 (ALL << 10)
>  #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>  
>  #define NOCTX 0
>  
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>  
>  static const struct named_register {
>  	const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
>  	{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
>  	{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
>  	{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> -	{ "L3_Config", GEN8, RCS0, 0x7034 },
> -	{ "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
> -	{ "TD_CTL2", GEN8, RCS0, 0xe404 },
> +	{ "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> +	{ "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff },
> +	{ "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
>  	{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
>  	{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
>  	{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -852,7 +853,7 @@ igt_main
>  		gen = intel_gen(intel_get_drm_devid(fd));
>  
>  		igt_warn_on_f(gen > LAST_KNOWN_GEN,
> -					  "GEN not recognized! Test needs to be updated to run.");
> +			      "GEN not recognized! Test needs to be updated to run.");
>  		igt_skip_on(gen > LAST_KNOWN_GEN);

Thanks to this editorial change, we're able to see that this string is
missing a newline character.


-- 
Petri Latvala
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-10-02 11:38 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-02 11:26 [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake Chris Wilson
2019-10-02 11:26 ` [igt-dev] " Chris Wilson
2019-10-02 11:38 ` Petri Latvala [this message]
2019-10-02 11:38   ` [Intel-gfx] " Petri Latvala
2019-10-03 23:26   ` Stimson, Dale B
2019-10-03 23:26     ` [Intel-gfx] " Stimson, Dale B
2019-10-04  8:16     ` Chris Wilson
2019-10-04  8:16       ` [igt-dev] [Intel-gfx] " Chris Wilson
2019-10-02 12:58 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-10-02 18:48 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2019-10-04 13:51 ` [igt-dev] [PATCH i-g-t] " Mika Kuoppala
2019-10-04 13:51   ` Mika Kuoppala
2019-10-04 13:57   ` Chris Wilson
2019-10-04 13:57     ` [Intel-gfx] " Chris Wilson
2019-10-04 15:17 ` Chris Wilson
2019-10-04 15:17   ` [igt-dev] " Chris Wilson
2019-10-04 15:19   ` Mika Kuoppala
2019-10-04 15:19     ` [igt-dev] " Mika Kuoppala
2019-10-04 16:14 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) Patchwork
2019-10-05  1:40 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191002113831.GG4019@platvala-desk.ger.corp.intel.com \
    --to=petri.latvala@intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=igt-dev@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.