* [PATCH 0/4] fix broken state checker and enable state checker for icl+
@ 2019-10-04 8:26 Swati Sharma
2019-10-04 8:26 ` [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot Swati Sharma
` (7 more replies)
0 siblings, 8 replies; 11+ messages in thread
From: Swati Sharma @ 2019-10-04 8:26 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch series, basically added 3 patches
1. Fixing broken state-checker during boot since legacy platforms
i.e. platforms for which state checker was already enabled
2. Moving gamma_enable checks in bit_precision func() to platform
specific func()
3. Enabling state checker for ICL and TGL
Swati Sharma (4):
[v2] drm/i915/color: fix broken gamma state-checker during boot
drm/i915/color: move check of gamma_enable to specific func/platform
[v5] drm/i915/color: Extract icl_read_luts()
FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
drivers/gpu/drm/i915/display/intel_color.c | 166 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 152 insertions(+), 20 deletions(-)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
@ 2019-10-04 8:26 ` Swati Sharma
2019-10-04 20:12 ` Ville Syrjälä
2019-10-04 8:26 ` [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform Swati Sharma
` (6 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Swati Sharma @ 2019-10-04 8:26 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
Premature gamma lut prepration and loading which was getting
reflected in first modeset causing different colors on
screen during boot.
Issue: In BIOS, gamma is disabled by default. However, legacy read_luts()
was setting crtc_state->base.gamma_lut and gamma_lut was programmed
with junk values which led to visual artifacts (different
colored screens instead of usual black during boot).
Fix: Calling read_luts() only when gamma is enabled which will happen
after first modeset.
This fix is independent from the revert 1b8588741fdc ("Revert
"drm/i915/color: Extract icl_read_luts()"") and should fix different colors
on screen in legacy platforms too.
-Added gamma_enable checks inside read_luts() [Ville/Jani N]
-Corrected gamma enable check for CHV [Ville]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111885
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 27 +++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 9ab34902663e..8f02313a7fef 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1613,6 +1613,9 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return;
+
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
}
@@ -1659,6 +1662,9 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
static void i965_read_luts(struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return;
+
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
else
@@ -1701,10 +1707,19 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
static void chv_read_luts(struct intel_crtc_state *crtc_state)
{
- if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
- else
+ if (crtc_state->cgm_mode) {
+ if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
+ return;
+
crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
+ }
+
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
+ if (!crtc_state->gamma_enable)
+ return;
+
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ }
}
static struct drm_property_blob *
@@ -1742,6 +1757,9 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
static void ilk_read_luts(struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return;
+
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
else
@@ -1788,6 +1806,9 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
static void glk_read_luts(struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return;
+
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
else
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
2019-10-04 8:26 ` [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot Swati Sharma
@ 2019-10-04 8:26 ` Swati Sharma
2019-10-04 20:14 ` Ville Syrjälä
2019-10-04 8:26 ` [PATCH 3/4] [v5] drm/i915/color: Extract icl_read_luts() Swati Sharma
` (5 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Swati Sharma @ 2019-10-04 8:26 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
Moved common code to check gamma_enable to specific funcs per platform
in bit_precision func. icl doesn't support that and chv has separate
enable knob for CGM LUT.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 23 +++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 8f02313a7fef..44ce75f051ad 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1420,6 +1420,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
switch (crtc_state->gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
@@ -1433,6 +1436,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
return 0;
@@ -1449,14 +1455,24 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
{
- if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
- return 10;
+ if (crtc_state->cgm_mode) {
+ if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
+ return 0;
+ else
+ return 10;
+ }
+
+ if (!crtc_state->gamma_enable)
+ return 0;
else
return i9xx_gamma_precision(crtc_state);
}
static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
switch (crtc_state->gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
@@ -1473,9 +1489,6 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!crtc_state->gamma_enable)
- return 0;
-
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv))
return chv_gamma_precision(crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] [v5] drm/i915/color: Extract icl_read_luts()
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
2019-10-04 8:26 ` [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot Swati Sharma
2019-10-04 8:26 ` [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform Swati Sharma
@ 2019-10-04 8:26 ` Swati Sharma
2019-10-04 8:26 ` [PATCH 4/4] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Swati Sharma @ 2019-10-04 8:26 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
Major change done-removal of readouts of coarse and fine segments
because PAL_PREC_DATA register isn't giving propoer values.
State checker limited only to "fine segment"
v2: -readout code for multisegmented gamma has to come
up with some intermediate entries that aren't preserved
in hardware (Jani N)
-linear interpolation (Ville)
-moved common code to check gamma_enable to specific funcs,
since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
-used single lut [Jani N]
-improved and more readable for loops [Jani N]
-read values directly to actual locations and then fill gaps [Jani N]
-moved cleaning to patch 1 [Jani N]
-renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
make it similar to icl_load_luts()
-renamed icl_compute_interpolated_gamma_blob() to
icl_compute_interpolated_gamma_lut_values() more sensible, I guess
v4: -removed interpolated func for creating gamma lut values
-removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA
correctly
v5: -added gamma_enable check inside read_luts()
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 114 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 108 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 44ce75f051ad..168e9daae3de 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1484,6 +1484,25 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
}
}
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+
+}
+
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -1495,7 +1514,9 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -1526,6 +1547,20 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
return true;
}
+static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
+ struct drm_color_lut *lut2,
+ int lut_size, u32 err)
+{
+ int i;
+
+ for (i = 0; i < 9; i++) {
+ if (!err_check(&lut1[i], &lut2[i], err))
+ return false;
+ }
+
+ return true;
+}
+
bool intel_color_lut_equal(struct drm_property_blob *blob1,
struct drm_property_blob *blob2,
u32 gamma_mode, u32 bit_precision)
@@ -1544,16 +1579,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
lut_size2 = drm_color_lut_size(blob2);
/* check sw and hw lut size */
- switch (gamma_mode) {
- case GAMMA_MODE_MODE_8BIT:
- case GAMMA_MODE_MODE_10BIT:
- if (lut_size1 != lut_size2)
- return false;
- break;
- default:
- MISSING_CASE(gamma_mode);
- return false;
- }
+ if (lut_size1 != lut_size2)
+ return false;
lut1 = blob1->data;
lut2 = blob2->data;
@@ -1561,13 +1588,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
err = 0xffff >> bit_precision;
/* check sw and hw lut entry to be equal */
- switch (gamma_mode) {
+ switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
case GAMMA_MODE_MODE_8BIT:
case GAMMA_MODE_MODE_10BIT:
if (!intel_color_lut_entry_equal(lut1, lut2,
lut_size2, err))
return false;
break;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ if (!intel_color_lut_entry_multi_equal(lut1, lut2,
+ lut_size2, err))
+ return false;
+ break;
default:
MISSING_CASE(gamma_mode);
return false;
@@ -1828,6 +1860,63 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static struct drm_property_blob *
+icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val1, val2;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < 9; i++) {
+ val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+
+ blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+ blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+ blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+ }
+
+ /*
+ * FIXME readouts from PAL_PREC_DATA register aren't giving correct values
+ * in the case of fine and coarse segments. Restricting readouts only for
+ * super fine segment as of now.
+ */
+
+ return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return;
+
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+ crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
+ else
+ crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1871,6 +1960,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
+ dev_priv->display.read_luts = icl_read_luts;
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..78766b378c0f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10571,6 +10571,12 @@ enum skl_power_gate {
#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
+#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
_PAL_PREC_MULTI_SEG_INDEX_A, \
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
` (2 preceding siblings ...)
2019-10-04 8:26 ` [PATCH 3/4] [v5] drm/i915/color: Extract icl_read_luts() Swati Sharma
@ 2019-10-04 8:26 ` Swati Sharma
2019-10-04 9:29 ` ✗ Fi.CI.CHECKPATCH: warning for fix broken state checker and enable state checker for icl+ Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Swati Sharma @ 2019-10-04 8:26 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
Only to print hw and sw lut values/channel.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 168e9daae3de..2b8706dba746 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1528,6 +1528,8 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
static bool err_check(struct drm_color_lut *lut1,
struct drm_color_lut *lut2, u32 err)
{
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
+
return ((abs((long)lut2->red - lut1->red)) <= err) &&
((abs((long)lut2->blue - lut1->blue)) <= err) &&
((abs((long)lut2->green - lut1->green)) <= err);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for fix broken state checker and enable state checker for icl+
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
` (3 preceding siblings ...)
2019-10-04 8:26 ` [PATCH 4/4] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
@ 2019-10-04 9:29 ` Patchwork
2019-10-04 11:12 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-10-04 9:29 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: fix broken state checker and enable state checker for icl+
URL : https://patchwork.freedesktop.org/series/67586/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a31640d6d4c0 drm/i915/color: fix broken gamma state-checker during boot
-:18: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 1b8588741fdc ("Revert "drm/i915/color: Extract icl_read_luts()"")'
#18:
This fix is independent from the revert 1b8588741fdc ("Revert
total: 1 errors, 0 warnings, 0 checks, 58 lines checked
f057269f5872 drm/i915/color: move check of gamma_enable to specific func/platform
af61150cc857 drm/i915/color: Extract icl_read_luts()
-:33: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#33:
-removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA
-:64: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#64: FILE: drivers/gpu/drm/i915/display/intel_color.c:1504:
+
+}
total: 0 errors, 1 warnings, 1 checks, 174 lines checked
da632c94f2e6 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:18: WARNING:LONG_LINE: line over 100 characters
#18: FILE: drivers/gpu/drm/i915/display/intel_color.c:1531:
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for fix broken state checker and enable state checker for icl+
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
` (4 preceding siblings ...)
2019-10-04 9:29 ` ✗ Fi.CI.CHECKPATCH: warning for fix broken state checker and enable state checker for icl+ Patchwork
@ 2019-10-04 11:12 ` Patchwork
2019-10-04 14:01 ` [PATCH 0/4] " Saarinen, Jani
2019-10-04 15:20 ` ✗ Fi.CI.IGT: failure for " Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-10-04 11:12 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: fix broken state checker and enable state checker for icl+
URL : https://patchwork.freedesktop.org/series/67586/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7003 -> Patchwork_14663
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/index.html
Known issues
------------
Here are the changes found in Patchwork_14663 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109483] / [fdo#109635 ])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Possible fixes ####
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
* igt@gem_sync@basic-all:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-tgl-u/igt@gem_sync@basic-all.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-tgl-u/igt@gem_sync@basic-all.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724] / [fdo#111214]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-icl-u3/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-icl-u3/igt@i915_module_load@reload.html
* igt@kms_chamelium@hdmi-crc-fast:
- {fi-icl-u4}: [FAIL][15] ([fdo#111045]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/fi-icl-u4/igt@kms_chamelium@hdmi-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/fi-icl-u4/igt@kms_chamelium@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (52 -> 45)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7003 -> Patchwork_14663
CI-20190529: 20190529
CI_DRM_7003: d76b206244f3c13898e65433720bb524c85fb832 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14663: da632c94f2e63be38f2a47e2aed64313a07145e8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
da632c94f2e6 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
af61150cc857 drm/i915/color: Extract icl_read_luts()
f057269f5872 drm/i915/color: move check of gamma_enable to specific func/platform
a31640d6d4c0 drm/i915/color: fix broken gamma state-checker during boot
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/4] fix broken state checker and enable state checker for icl+
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
` (5 preceding siblings ...)
2019-10-04 11:12 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-04 14:01 ` Saarinen, Jani
2019-10-04 15:20 ` ✗ Fi.CI.IGT: failure for " Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Saarinen, Jani @ 2019-10-04 14:01 UTC (permalink / raw)
To: Sharma, Swati2, intel-gfx; +Cc: Nikula, Jani, Nautiyal, Ankit K
Hi,
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Swati
> Sharma
> Sent: perjantai 4. lokakuuta 2019 11.26
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [Intel-gfx] [PATCH 0/4] fix broken state checker and enable state checker
> for icl+
>
> In this patch series, basically added 3 patches 1. Fixing broken state-checker during
> boot since legacy platforms
> i.e. platforms for which state checker was already enabled 2. Moving
> gamma_enable checks in bit_precision func() to platform
Tested in BSW that was showing fancy colors previously and now booting to console with clean colors.
Tested-by: Jani Saarinen <jani.saarinen@intel.com>
> specific func()
> 3. Enabling state checker for ICL and TGL
>
> Swati Sharma (4):
> [v2] drm/i915/color: fix broken gamma state-checker during boot
> drm/i915/color: move check of gamma_enable to specific func/platform
> [v5] drm/i915/color: Extract icl_read_luts()
> FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
>
> drivers/gpu/drm/i915/display/intel_color.c | 166 ++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 6 +
> 2 files changed, 152 insertions(+), 20 deletions(-)
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: failure for fix broken state checker and enable state checker for icl+
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
` (6 preceding siblings ...)
2019-10-04 14:01 ` [PATCH 0/4] " Saarinen, Jani
@ 2019-10-04 15:20 ` Patchwork
7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-10-04 15:20 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: fix broken state checker and enable state checker for icl+
URL : https://patchwork.freedesktop.org/series/67586/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14663_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14663_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14663_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14663_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl10/igt@gem_exec_reloc@basic-wc-cpu-active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl5/igt@gem_exec_reloc@basic-wc-cpu-active.html
* igt@gem_mmap_gtt@hang:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl1/igt@gem_mmap_gtt@hang.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-kbl7/igt@gem_mmap_gtt@hang.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- {shard-tglb}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb7/igt@kms_cursor_legacy@all-pipes-forked-bo.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb6/igt@kms_cursor_legacy@all-pipes-forked-bo.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- {shard-tglb}: [SKIP][7] ([fdo#111615]) -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-yf.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-yf.html
Known issues
------------
Here are the changes found in Patchwork_14663_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] / [fdo#111870])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
- shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108] / [fdo#107773])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl4/igt@gem_workarounds@suspend-resume.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl3/igt@gem_workarounds@suspend-resume.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
- shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][25] -> [FAIL][26] ([fdo#105767])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#105363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [PASS][29] -> [FAIL][30] ([fdo#103167]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][31] -> [INCOMPLETE][32] ([fdo#103927]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [fdo#110403])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103166])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][39] -> [FAIL][40] ([fdo#99912])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-glk3/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-glk1/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109276]) +13 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_create@create-clear:
- shard-hsw: [INCOMPLETE][43] ([fdo#103540] / [fdo#110401]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw5/igt@gem_create@create-clear.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw2/igt@gem_create@create-clear.html
* igt@gem_ctx_shared@q-smoketest-bsd2:
- shard-iclb: [SKIP][45] ([fdo#109276]) -> [PASS][46] +15 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb6/igt@gem_ctx_shared@q-smoketest-bsd2.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb2/igt@gem_ctx_shared@q-smoketest-bsd2.html
- {shard-tglb}: [INCOMPLETE][47] ([fdo# 111852 ]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb6/igt@gem_ctx_shared@q-smoketest-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb5/igt@gem_ctx_shared@q-smoketest-bsd2.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][49] ([fdo#111325]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb5/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_mmap_gtt@hang:
- shard-skl: [DMESG-WARN][51] -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl10/igt@gem_mmap_gtt@hang.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl5/igt@gem_mmap_gtt@hang.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- {shard-tglb}: [INCOMPLETE][53] ([fdo#111714]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-iclb: [INCOMPLETE][55] ([fdo#107713]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb7/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb2/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][57] ([fdo#111870]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-glk: [DMESG-WARN][59] ([fdo#111870]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-glk9/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-glk2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-kbl: [DMESG-WARN][61] ([fdo#111870]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-kbl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
- shard-skl: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-iclb: [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_userptr_blits@sync-unmap-cycles.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume:
- {shard-tglb}: [INCOMPLETE][69] ([fdo#111832]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb1/igt@gem_workarounds@suspend-resume.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb3/igt@gem_workarounds@suspend-resume.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-skl: [INCOMPLETE][71] -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-apl: [INCOMPLETE][73] ([fdo#103927]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- shard-kbl: [INCOMPLETE][75] ([fdo#103665]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [INCOMPLETE][77] ([fdo#103540]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw5/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- {shard-tglb}: [FAIL][79] ([fdo#103167]) -> [PASS][80] +5 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][81] ([fdo#103167]) -> [PASS][82] +5 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][83] ([fdo#103166]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][85] ([fdo#109642] / [fdo#111068]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb4/igt@kms_psr2_su@page_flip.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][87] ([fdo#109441]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- {shard-tglb}: [INCOMPLETE][89] ([fdo#111832] / [fdo#111850]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][91] ([fdo#104108]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_vgem@sync-render:
- {shard-tglb}: [DMESG-WARN][93] ([fdo#111600]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb4/igt@prime_vgem@sync-render.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb7/igt@prime_vgem@sync-render.html
* igt@tools_test@tools_test:
- shard-hsw: [SKIP][95] ([fdo#109271]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw7/igt@tools_test@tools_test.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw6/igt@tools_test@tools_test.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][97] ([fdo#109276]) -> [FAIL][98] ([fdo#111330])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][99] ([fdo#111330]) -> [SKIP][100] ([fdo#109276])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [INCOMPLETE][101] ([fdo#103927]) -> [DMESG-WARN][102] ([fdo#108566])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl7/igt@gem_softpin@noreloc-s3.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-apl7/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [DMESG-WARN][103] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][104] ([fdo#111870])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-hsw1/igt@gem_userptr_blits@dmabuf-unsync.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-hsw4/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@kms_frontbuffer_tracking@fbc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot
2019-10-04 8:26 ` [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot Swati Sharma
@ 2019-10-04 20:12 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2019-10-04 20:12 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx, ankit.k.nautiyal
On Fri, Oct 04, 2019 at 01:56:07PM +0530, Swati Sharma wrote:
> Premature gamma lut prepration and loading which was getting
> reflected in first modeset causing different colors on
> screen during boot.
>
> Issue: In BIOS, gamma is disabled by default. However, legacy read_luts()
> was setting crtc_state->base.gamma_lut and gamma_lut was programmed
> with junk values which led to visual artifacts (different
> colored screens instead of usual black during boot).
>
> Fix: Calling read_luts() only when gamma is enabled which will happen
> after first modeset.
>
> This fix is independent from the revert 1b8588741fdc ("Revert
> "drm/i915/color: Extract icl_read_luts()"") and should fix different colors
> on screen in legacy platforms too.
>
> -Added gamma_enable checks inside read_luts() [Ville/Jani N]
> -Corrected gamma enable check for CHV [Ville]
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111885
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 27 +++++++++++++++++++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 9ab34902663e..8f02313a7fef 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1613,6 +1613,9 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>
> static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> @@ -1659,6 +1662,9 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>
> static void i965_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> @@ -1701,10 +1707,19 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>
> static void chv_read_luts(struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> - else
> + if (crtc_state->cgm_mode) {
> + if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
> + return;
> +
> crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> + }
> +
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + }
I'd simply make this something like:
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) {
crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
} else {
i965_read_luts(crtc_state);
}
> }
>
> static struct drm_property_blob *
> @@ -1742,6 +1757,9 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>
> static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
We should check
if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
return;
here so we don't read the hw degamma into the state gmama_lut.
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> @@ -1788,6 +1806,9 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>
> static void glk_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> --
> 2.23.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform
2019-10-04 8:26 ` [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform Swati Sharma
@ 2019-10-04 20:14 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2019-10-04 20:14 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx, ankit.k.nautiyal
On Fri, Oct 04, 2019 at 01:56:08PM +0530, Swati Sharma wrote:
> Moved common code to check gamma_enable to specific funcs per platform
> in bit_precision func. icl doesn't support that and chv has separate
> enable knob for CGM LUT.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 23 +++++++++++++++++-----
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 8f02313a7fef..44ce75f051ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1420,6 +1420,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1433,6 +1436,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1449,14 +1455,24 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> - return 10;
> + if (crtc_state->cgm_mode) {
> + if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
> + return 0;
> + else
> + return 10;
> + }
> +
> + if (!crtc_state->gamma_enable)
> + return 0;
> else
> return i9xx_gamma_precision(crtc_state);
Again could simplify to just:
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
return 10;
else
return i9xx_gamma_precision(crtc_state);
> }
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1473,9 +1489,6 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> --
> 2.23.0
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-10-04 20:14 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-04 8:26 [PATCH 0/4] fix broken state checker and enable state checker for icl+ Swati Sharma
2019-10-04 8:26 ` [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot Swati Sharma
2019-10-04 20:12 ` Ville Syrjälä
2019-10-04 8:26 ` [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform Swati Sharma
2019-10-04 20:14 ` Ville Syrjälä
2019-10-04 8:26 ` [PATCH 3/4] [v5] drm/i915/color: Extract icl_read_luts() Swati Sharma
2019-10-04 8:26 ` [PATCH 4/4] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
2019-10-04 9:29 ` ✗ Fi.CI.CHECKPATCH: warning for fix broken state checker and enable state checker for icl+ Patchwork
2019-10-04 11:12 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-04 14:01 ` [PATCH 0/4] " Saarinen, Jani
2019-10-04 15:20 ` ✗ Fi.CI.IGT: failure for " Patchwork
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