From: Andrew Jeffery <andrew@aj.id.au>
To: linux-gpio@vger.kernel.org
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, joel@jms.id.au,
linux-aspeed@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, johnny_huang@aspeedtech.com,
ryanchen.aspeed@gmail.com
Subject: [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
Date: Tue, 8 Oct 2019 15:11:51 +1030 [thread overview]
Message-ID: <20191008044153.12734-6-andrew@aj.id.au> (raw)
In-Reply-To: <20191008044153.12734-1-andrew@aj.id.au>
Signal descriptors can represent multi-bit bitfields and so have
explicit "enable" and "disable" states. However many descriptor
instances only describe a single bit, and so the SIG_DESC_SET() macro is
provides an abstraction for the single-bit cases: Its expansion
configures the "enable" state to set the bit and "disable" to clear.
SIG_DESC_CLEAR() was introduced to provide a similar single-bit
abstraction for for descriptors to clear the bit of interest. However
its behaviour was defined as the literal inverse of SIG_DESC_SET() - the
impact is the bit of interest is set in the disable path. This behaviour
isn't intuitive and doesn't align with how we want to use the macro in
practice, so make it clear the bit for both the enable and disable
paths.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinmux-aspeed.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h
index a2c0d52e4f7b..d5202241f411 100644
--- a/drivers/pinctrl/aspeed/pinmux-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h
@@ -508,7 +508,7 @@ struct aspeed_pin_desc {
* @idx: The bit index in the register
*/
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
-#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0)
+#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jeffery <andrew@aj.id.au>
To: linux-gpio@vger.kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
johnny_huang@aspeedtech.com, linux-aspeed@lists.ozlabs.org,
linus.walleij@linaro.org, ryanchen.aspeed@gmail.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, joel@jms.id.au,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
Date: Tue, 8 Oct 2019 15:11:51 +1030 [thread overview]
Message-ID: <20191008044153.12734-6-andrew@aj.id.au> (raw)
In-Reply-To: <20191008044153.12734-1-andrew@aj.id.au>
Signal descriptors can represent multi-bit bitfields and so have
explicit "enable" and "disable" states. However many descriptor
instances only describe a single bit, and so the SIG_DESC_SET() macro is
provides an abstraction for the single-bit cases: Its expansion
configures the "enable" state to set the bit and "disable" to clear.
SIG_DESC_CLEAR() was introduced to provide a similar single-bit
abstraction for for descriptors to clear the bit of interest. However
its behaviour was defined as the literal inverse of SIG_DESC_SET() - the
impact is the bit of interest is set in the disable path. This behaviour
isn't intuitive and doesn't align with how we want to use the macro in
practice, so make it clear the bit for both the enable and disable
paths.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinmux-aspeed.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h
index a2c0d52e4f7b..d5202241f411 100644
--- a/drivers/pinctrl/aspeed/pinmux-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h
@@ -508,7 +508,7 @@ struct aspeed_pin_desc {
* @idx: The bit index in the register
*/
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
-#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0)
+#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jeffery <andrew@aj.id.au>
To: linux-gpio@vger.kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
johnny_huang@aspeedtech.com, linux-aspeed@lists.ozlabs.org,
linus.walleij@linaro.org, ryanchen.aspeed@gmail.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, joel@jms.id.au,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
Date: Tue, 8 Oct 2019 15:11:51 +1030 [thread overview]
Message-ID: <20191008044153.12734-6-andrew@aj.id.au> (raw)
In-Reply-To: <20191008044153.12734-1-andrew@aj.id.au>
Signal descriptors can represent multi-bit bitfields and so have
explicit "enable" and "disable" states. However many descriptor
instances only describe a single bit, and so the SIG_DESC_SET() macro is
provides an abstraction for the single-bit cases: Its expansion
configures the "enable" state to set the bit and "disable" to clear.
SIG_DESC_CLEAR() was introduced to provide a similar single-bit
abstraction for for descriptors to clear the bit of interest. However
its behaviour was defined as the literal inverse of SIG_DESC_SET() - the
impact is the bit of interest is set in the disable path. This behaviour
isn't intuitive and doesn't align with how we want to use the macro in
practice, so make it clear the bit for both the enable and disable
paths.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinmux-aspeed.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h
index a2c0d52e4f7b..d5202241f411 100644
--- a/drivers/pinctrl/aspeed/pinmux-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h
@@ -508,7 +508,7 @@ struct aspeed_pin_desc {
* @idx: The bit index in the register
*/
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
-#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0)
+#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \
--
2.20.1
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next prev parent reply other threads:[~2019-10-08 4:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 4:41 [PATCH 0/7] pinctrl: Fixes for AST2600 support Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` [PATCH 1/7] dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-15 22:24 ` Rob Herring
2019-10-15 22:24 ` Rob Herring
2019-10-08 4:41 ` [PATCH 2/7] pinctrl: aspeed-g6: Sort pins for sanity Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` [PATCH 3/7] pinctrl: aspeed-g6: Fix I2C14 SDA description Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` [PATCH 4/7] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery [this message]
2019-10-08 4:41 ` [PATCH 5/7] pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` [PATCH 6/7] pinctrl: aspeed-g6: Fix UART13 group pinmux Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` [PATCH 7/7] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:41 ` Andrew Jeffery
2019-10-08 4:54 ` [PATCH 0/7] pinctrl: Fixes for AST2600 support Joel Stanley
2019-10-08 4:54 ` Joel Stanley
2019-10-16 11:19 ` Linus Walleij
2019-10-16 11:19 ` Linus Walleij
2019-10-16 11:41 ` Andrew Jeffery
2019-10-16 11:41 ` Andrew Jeffery
2019-10-16 14:00 ` Linus Walleij
2019-10-16 14:00 ` Linus Walleij
2019-10-16 23:26 ` Andrew Jeffery
2019-10-16 23:26 ` Andrew Jeffery
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