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From: Daniel Drake <drake@endlessm.com>
To: bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, rafael.j.wysocki@intel.com,
	linux@endlessm.com, linux-pm@vger.kernel.org,
	linux-usb@vger.kernel.org
Subject: [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers
Date: Mon, 14 Oct 2019 14:13:55 +0800	[thread overview]
Message-ID: <20191014061355.29072-1-drake@endlessm.com> (raw)

On Asus laptops with AMD Ryzen7 3700U and AMD Ryzen5 3500U,
the XHCI controller fails to resume from runtime suspend or s2idle,
and USB becomes unusable from that point.

xhci_hcd 0000:03:00.4: Refused to change power state, currently in D3
xhci_hcd 0000:03:00.4: enabling device (0000 -> 0002)
xhci_hcd 0000:03:00.4: WARN: xHC restore state timeout
xhci_hcd 0000:03:00.4: PCI post-resume error -110!
xhci_hcd 0000:03:00.4: HC died; cleaning up

The D3-to-D0 transition is successful if the D3 delay is increased
to 20ms. Add an appropriate quirk for the affected hardware.

Link: http://lkml.kernel.org/r/CAD8Lp47Vh69gQjROYG69=waJgL7hs1PwnLonL9+27S_TcRhixA@mail.gmail.com
Signed-off-by: Daniel Drake <drake@endlessm.com>
---
 drivers/pci/quirks.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 320255e5e8f8..4570439a6a6c 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1871,19 +1871,35 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);
 
+static void quirk_d3_delay(struct pci_dev *dev, unsigned int delay)
+{
+	if (dev->d3_delay >= delay)
+		return;
+
+	dev->d3_delay = delay;
+	pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
+		 dev->d3_delay);
+}
+
 static void quirk_radeon_pm(struct pci_dev *dev)
 {
 	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
-	    dev->subsystem_device == 0x00e2) {
-		if (dev->d3_delay < 20) {
-			dev->d3_delay = 20;
-			pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
-				 dev->d3_delay);
-		}
-	}
+	    dev->subsystem_device == 0x00e2)
+		quirk_d3_delay(dev, 20);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
 
+/*
+ * Ryzen7 XHCI controllers fail upon resume from runtime suspend or s2idle
+ * unless an extended D3 delay is used.
+ */
+static void quirk_ryzen_xhci_d3(struct pci_dev *dev)
+{
+	quirk_d3_delay(dev, 20);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3);
+
 #ifdef CONFIG_X86_IO_APIC
 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
 {
-- 
2.20.1


             reply	other threads:[~2019-10-14  6:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-14  6:13 Daniel Drake [this message]
2019-10-14 15:43 ` [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers Bjorn Helgaas
2019-10-15  5:31   ` Daniel Drake
2019-10-15 17:52     ` Rafael J. Wysocki
2019-10-16  6:14       ` Daniel Drake
2019-10-21 11:33     ` Mika Westerberg
2019-10-22  2:40       ` Daniel Drake
2019-10-22  9:33         ` Mika Westerberg
2019-10-23 22:40           ` Bjorn Helgaas
2019-10-24  3:28             ` Daniel Drake
2019-10-24 17:00               ` Bjorn Helgaas
2019-10-25  7:11                 ` Daniel Drake
2019-10-25 16:28                   ` Bjorn Helgaas
2019-10-28  6:32                     ` Daniel Drake
2019-11-18  8:52                       ` Daniel Drake
2019-11-20  0:28 ` Bjorn Helgaas
2019-11-21 18:15   ` Bjorn Helgaas
2019-11-22  3:00     ` Daniel Drake
2019-11-22 11:15       ` Rafael J. Wysocki
2019-11-25  3:45         ` Daniel Drake
2019-11-25 13:37           ` Rafael J. Wysocki

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