* [PATCH v4 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 02/10] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
` (16 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2376d36ea573..52107533994c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 02/10] drm/i915: Use intel_tile_height() instead of re-implementing
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
` (15 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3cf39fc153b3..626046e97b40 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1955,7 +1955,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
unsigned int cpp = fb->format->cpp[color_plane];
*tile_width = tile_width_bytes / cpp;
- *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+ *tile_height = intel_tile_height(fb, color_plane);
}
unsigned int
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 02/10] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 04/10] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
` (14 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 626046e97b40..0a2f68dd7620 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2546,7 +2546,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
else
return 64;
} else {
- return intel_tile_width_bytes(fb, color_plane);
+ u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+ /*
+ * Display WA #0531: skl,bxt,kbl,glk
+ *
+ * Render decompression and plane width > 3840
+ * combined with horizontal panning requires the
+ * plane stride to be a multiple of 4. We'll just
+ * require the entire fb to accommodate that to avoid
+ * potential runtime errors at plane configuration time.
+ */
+ if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+ color_plane == 0 && fb->width > 3840)
+ tile_width *= 4;
+
+ return tile_width;
}
}
@@ -15694,20 +15709,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
stride_alignment = intel_fb_stride_alignment(fb, i);
-
- /*
- * Display WA #0531: skl,bxt,kbl,glk
- *
- * Render decompression and plane width > 3840
- * combined with horizontal panning requires the
- * plane stride to be a multiple of 4. We'll just
- * require the entire fb to accommodate that to avoid
- * potential runtime errors at plane configuration time.
- */
- if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
- is_ccs_modifier(fb->modifier))
- stride_alignment *= 4;
-
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
i, fb->pitches[i], stride_alignment);
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 04/10] drm/i915/tgl: Gen-12 render decompression
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (2 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 05/10] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
` (13 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.
v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 84 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0a2f68dd7620..a1dccca6a03d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1909,6 +1909,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -1942,8 +1946,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 1;
+ /* fall through */
+ default:
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
+ }
}
/* Return the tile dimensions in pixel units */
@@ -2042,6 +2053,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2238,7 +2251,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2425,6 +2439,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2445,7 +2460,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2456,6 +2471,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2476,8 +2509,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+ cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
default:
return NULL;
@@ -2486,7 +2523,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2531,8 +2569,9 @@ static u32
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ u32 tile_width;
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ if (is_surface_linear(fb->modifier, color_plane)) {
u32 max_stride = intel_plane_fb_max_stride(dev_priv,
fb->format->format,
fb->modifier);
@@ -2541,13 +2580,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* To make remapping with linear generally feasible
* we need the stride to be page aligned.
*/
- if (fb->pitches[color_plane] > max_stride)
+ if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
return intel_tile_size(dev_priv);
else
return 64;
- } else {
- u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+ }
+ tile_width = intel_tile_width_bytes(fb, color_plane);
+ if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2557,12 +2597,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
- color_plane == 0 && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ tile_width *= 4;
+ /*
+ * The main surface pitch must be padded to a multiple of four
+ * tile widths.
+ */
+ else if (INTEL_GEN(dev_priv) >= 12)
tile_width *= 4;
-
- return tile_width;
}
+ return tile_width;
}
bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2671,6 +2715,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ccs_x, ccs_y;
intel_tile_dims(fb, i, &tile_width, &tile_height);
+
tile_width *= hsub;
tile_height *= vsub;
@@ -3963,7 +4008,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
*/
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ if (is_surface_linear(fb->modifier, color_plane))
return 64;
else if (drm_rotation_90_or_270(rotation))
return intel_tile_height(fb, color_plane);
@@ -4089,6 +4134,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return PLANE_CTL_TILED_Y |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9850,7 +9899,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+ fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 633fa8069348..20df64336669 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -535,6 +535,7 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
+ u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
@@ -576,8 +577,10 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ aux_dist |= aux_stride;
+ I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
@@ -1734,7 +1737,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2146,7 +2150,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2308,6 +2313,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
break;
default:
return false;
@@ -2318,6 +2324,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
+ if (is_ccs_modifier(modifier))
+ return true;
+ /* fall through */
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -2526,13 +2535,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: Implement support for gen-12 CCS modifiers */
- plane->has_ccs = false;
- modifiers = gen12_plane_format_modifiers_noccs;
+ modifiers = gen12_plane_format_modifiers_ccs;
plane_funcs = &gen12_plane_funcs;
} else {
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (plane->has_ccs)
modifiers = skl_plane_format_modifiers_ccs;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e24991e54897..c1583f5c413b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6702,6 +6702,7 @@ enum {
#define PLANE_CTL_YUV422_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
#define PLANE_CTL_TILED_MASK (0x7 << 10)
#define PLANE_CTL_TILED_LINEAR (0 << 10)
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 05/10] drm/i915: Extract framebufer CCS offset checks into a function
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (3 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 04/10] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
` (12 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1dccca6a03d..be61dfdebb34 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2677,6 +2677,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ int hsub = fb->format->hsub;
+ int vsub = fb->format->vsub;
+ int tile_width, tile_height;
+ int ccs_x, ccs_y;
+ int main_x, main_y;
+
+ intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+ tile_width *= hsub;
+ tile_height *= vsub;
+
+ ccs_x = (x * hsub) % tile_width;
+ ccs_y = (y * vsub) % tile_height;
+ main_x = intel_fb->normal[0].x % tile_width;
+ main_y = intel_fb->normal[0].y % tile_height;
+
+ /*
+ * CCS doesn't have its own x/y offset register, so the intra CCS tile
+ * x/y offsets must match between CCS and the main surface.
+ */
+ if (main_x != ccs_x || main_y != ccs_y) {
+ DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+ main_x, main_y,
+ ccs_x, ccs_y,
+ intel_fb->normal[0].x,
+ intel_fb->normal[0].y,
+ x, y);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2708,35 +2745,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
}
if (is_ccs_modifier(fb->modifier) && i == 1) {
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int tile_width, tile_height;
- int main_x, main_y;
- int ccs_x, ccs_y;
-
- intel_tile_dims(fb, i, &tile_width, &tile_height);
-
- tile_width *= hsub;
- tile_height *= vsub;
-
- ccs_x = (x * hsub) % tile_width;
- ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
-
- /*
- * CCS doesn't have its own x/y offset register, so the intra CCS tile
- * x/y offsets must match between CCS and the main surface.
- */
- if (main_x != ccs_x || main_y != ccs_y) {
- DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
- main_x, main_y,
- ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
- x, y);
- return -EINVAL;
- }
+ ret = intel_fb_check_ccs_xy(fb, x, y);
+ if (ret)
+ return ret;
}
/*
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (4 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 05/10] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 07/10] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
` (11 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 52107533994c..dd9c85111e77 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 07/10] drm/fb: Extend format_info member arrays to handle four planes
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (5 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 08/10] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
` (10 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
include/drm/drm_fourcc.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.20.1
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2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (6 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 07/10] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
` (9 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 237 +++++++++++++-----
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 220 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index be61dfdebb34..448168a4d780 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1909,6 +1909,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (color_plane == 3)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
if (color_plane == 1)
return 64;
@@ -2251,8 +2255,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1 || color_plane == 3;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2440,6 +2452,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2487,6 +2500,10 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
static const struct drm_format_info *
@@ -2524,6 +2541,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2587,7 +2605,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+ if (is_ccs_modifier(fb->modifier)) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2597,7 +2615,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -2677,25 +2695,71 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+ static const struct {
+ int cpp[4];
+ int vsub[4];
+ int hsub[4];
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
+
+ *hsub = mc_ccs_subsampling.hsub[color_plane];
+ *vsub = mc_ccs_subsampling.vsub[color_plane];
+ } else {
+ *hsub = fb->format->hsub;
+ *vsub = fb->format->vsub;
+ }
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+ int hsub, vsub;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ *w = fb->width / hsub;
+ *h = fb->height / vsub;
+}
+
+static bool is_ccs_plane(u64 modifier, int color_plane)
+{
+ if (!is_ccs_modifier(modifier))
+ return false;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return color_plane == 3 || color_plane == 1;
+ else
+ return color_plane == 1;
+}
+
static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int color_plane, int x, int y)
{
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
+ int hsub, vsub;
+ int hsub_main, vsub_main;
int tile_width, tile_height;
int ccs_x, ccs_y;
int main_x, main_y;
- intel_tile_dims(fb, 1, &tile_width, &tile_height);
+ if (!is_ccs_plane(fb->modifier, color_plane))
+ return 0;
+
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb, color_plane - 1);
+
+ hsub /= hsub_main;
+ vsub /= vsub_main;
tile_width *= hsub;
tile_height *= vsub;
ccs_x = (x * hsub) % tile_width;
ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
+ main_x = intel_fb->normal[color_plane - 1].x % tile_width;
+ main_y = intel_fb->normal[color_plane - 1].y % tile_height;
/*
* CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2705,8 +2769,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
main_x, main_y,
ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
+ intel_fb->normal[color_plane - 1].x,
+ intel_fb->normal[color_plane - 1].y,
x, y);
return -EINVAL;
}
@@ -2734,8 +2798,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ret;
cpp = fb->format->cpp[i];
- width = drm_framebuffer_plane_width(fb->width, fb, i);
- height = drm_framebuffer_plane_height(fb->height, fb, i);
+ intel_fb_plane_dims(&width, &height, fb, i);
ret = intel_fb_offset_to_xy(&x, &y, fb, i);
if (ret) {
@@ -2744,11 +2807,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return ret;
}
- if (is_ccs_modifier(fb->modifier) && i == 1) {
- ret = intel_fb_check_ccs_xy(fb, x, y);
- if (ret)
- return ret;
- }
+ ret = intel_fb_check_ccs_xy(fb, i, x, y);
+ if (ret)
+ return ret;
/*
* The fence (if used) is aligned to the start of the object
@@ -3360,6 +3421,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
return 5120;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
/* FIXME AUX plane? */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
@@ -3419,16 +3481,18 @@ static int icl_max_plane_height(void)
}
static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
- int main_x, int main_y, u32 main_offset)
+ int main_x, int main_y, u32 main_offset,
+ int aux_plane)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int aux_x = plane_state->color_plane[1].x;
- int aux_y = plane_state->color_plane[1].y;
- u32 aux_offset = plane_state->color_plane[1].offset;
- u32 alignment = intel_surf_alignment(fb, 1);
-
+ int hsub;
+ int vsub;
+ int aux_x = plane_state->color_plane[aux_plane].x;
+ int aux_y = plane_state->color_plane[aux_plane].y;
+ u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
while (aux_offset >= main_offset && aux_y <= main_y) {
int x, y;
@@ -3440,7 +3504,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
x = aux_x / hsub;
y = aux_y / vsub;
- aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+ aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
aux_offset, aux_offset - alignment);
aux_x = x * hsub + aux_x % hsub;
aux_y = y * vsub + aux_y % vsub;
@@ -3449,9 +3513,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
if (aux_x != main_x || aux_y != main_y)
return false;
- plane_state->color_plane[1].offset = aux_offset;
- plane_state->color_plane[1].x = aux_x;
- plane_state->color_plane[1].y = aux_y;
+ plane_state->color_plane[aux_plane].offset = aux_offset;
+ plane_state->color_plane[aux_plane].x = aux_x;
+ plane_state->color_plane[aux_plane].y = aux_y;
return true;
}
@@ -3525,7 +3589,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* they match with the main surface x/y offsets.
*/
if (is_ccs_modifier(fb->modifier)) {
- while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 1)) {
if (offset == 0)
break;
@@ -3558,7 +3622,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
- int max_width = skl_max_plane_width(fb, 1, rotation);
+ int uv = is_ccs_modifier(fb->modifier) ? 2 : 1;
+ int max_width = skl_max_plane_width(fb, uv, rotation);
int max_height = 4096;
int x = plane_state->base.src.x1 >> 17;
int y = plane_state->base.src.y1 >> 17;
@@ -3566,8 +3631,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int h = drm_rect_height(&plane_state->base.src) >> 17;
u32 offset;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+ intel_add_fb_offsets(&x, &y, plane_state, uv);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv);
/* FIXME not quite sure how/if these apply to the chroma plane */
if (w > max_width || h > max_height) {
@@ -3576,9 +3641,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x;
- plane_state->color_plane[1].y = y;
+ if (is_ccs_modifier(fb->modifier)) {
+ int aux_offset = plane_state->color_plane[3].offset;
+ int alignment = intel_surf_alignment(fb, uv);
+
+ if (offset > aux_offset) {
+ int hsub, vsub;
+ int main_x = x, main_y = y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, uv);
+ x = main_x / hsub;
+ y = main_y / vsub;
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset,
+ aux_offset & ~(alignment - 1));
+ x = x * hsub + main_x % hsub;
+ y = y * vsub + main_y % vsub;
+ }
+
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+ if (offset == 0)
+ break;
+
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset, offset - alignment);
+ }
+
+ if (x != plane_state->color_plane[3].x || y != plane_state->color_plane[3].y) {
+ DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+ return -EINVAL;
+ }
+ }
+
+ plane_state->color_plane[uv].offset = offset;
+ plane_state->color_plane[uv].x = x;
+ plane_state->color_plane[uv].y = y;
return 0;
}
@@ -3588,19 +3685,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
const struct drm_framebuffer *fb = plane_state->base.fb;
int src_x = plane_state->base.src.x1 >> 16;
int src_y = plane_state->base.src.y1 >> 16;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int x = src_x / hsub;
- int y = src_y / vsub;
u32 offset;
+ int ccs;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x * hsub + src_x % hsub;
- plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+ for (ccs = 1; ccs < fb->format->num_planes; ccs += 2) {
+ int hsub, vsub;
+ int main_hsub, main_vsub;
+ int x, y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, ccs - 1);
+ hsub /= main_hsub;
+ vsub /= main_vsub;
+ x = src_x / hsub;
+ y = src_y / vsub;
+
+ intel_add_fb_offsets(&x, &y, plane_state, ccs);
+ offset = intel_plane_compute_aligned_offset(&x, &y,
+ plane_state, ccs);
+ plane_state->color_plane[ccs].offset = offset;
+ plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+ plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+ }
return 0;
}
@@ -3608,6 +3716,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
+ bool needs_aux = false;
ret = intel_plane_compute_gtt(plane_state);
if (ret)
@@ -3617,21 +3726,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
return 0;
/*
- * Handle the AUX surface first since
- * the main surface setup depends on it.
+ * Handle the AUX surface first since the main surface setup depends on
+ * it.
*/
- if (drm_format_info_is_yuv_semiplanar(fb->format)) {
- ret = skl_check_nv12_aux_surface(plane_state);
+ if (is_ccs_modifier(fb->modifier)) {
+ needs_aux = true;
+ ret = skl_check_ccs_aux_surface(plane_state);
if (ret)
return ret;
- } else if (is_ccs_modifier(fb->modifier)) {
- ret = skl_check_ccs_aux_surface(plane_state);
+ }
+
+ if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+ needs_aux = true;
+ ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
- } else {
- plane_state->color_plane[1].offset = ~0xfff;
- plane_state->color_plane[1].x = 0;
- plane_state->color_plane[1].y = 0;
+ }
+
+ if (!needs_aux) {
+ int i;
+
+ for (i = 1; i < fb->format->num_planes; i++) {
+ plane_state->color_plane[i].offset = ~0xfff;
+ plane_state->color_plane[i].x = 0;
+ plane_state->color_plane[i].y = 0;
+ }
}
ret = skl_check_main_surface(plane_state);
@@ -4149,6 +4268,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9913,6 +10034,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..91241f2bc575 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -530,7 +530,7 @@ struct intel_plane_state {
*/
u32 stride;
int x, y;
- } color_plane[2];
+ } color_plane[4];
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 20df64336669..fdb9dcc4060c 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1738,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2150,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
@@ -2306,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+ return plane_id < PLANE_SPRITE4;
+}
+
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (!gen12_plane_supports_mc_ccs(plane->id))
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2327,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2471,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+ if (gen12_plane_supports_mc_ccs(plane_id))
+ return gen12_plane_format_modifiers_mc_ccs;
+ else
+ return gen12_plane_format_modifiers_rc_ccs;
+}
+
static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2537,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- modifiers = gen12_plane_format_modifiers_ccs;
+ modifiers = gen12_get_plane_modifiers(plane_id);
plane_funcs = &gen12_plane_funcs;
} else {
if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1583f5c413b..5fad9cb35979 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6710,6 +6710,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (7 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 08/10] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-15 0:47 ` Radhakrishna Sripada
2019-10-15 0:05 ` [PATCH v4 " Radhakrishna Sripada
` (8 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, dhinakaran.pandiyan, Kalyan Kondapally, ville.syrjala
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index dd9c85111e77..a20f2ea8ddc6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,17 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The size of clear color should be 64 bits. A CCS_CC cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
2019-10-15 0:05 ` [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
@ 2019-10-15 0:47 ` Radhakrishna Sripada
2019-10-23 0:09 ` [PATCH v5 " Radhakrishna Sripada
0 siblings, 1 reply; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley Chery, Dhinakaran Pandiyan, Kalyan Kondapally
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index dd9c85111e77..8979fdd5a414 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,17 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The size of clear color should be 64 bits. A CCS_CC cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
2019-10-15 0:47 ` Radhakrishna Sripada
@ 2019-10-23 0:09 ` Radhakrishna Sripada
2019-10-24 0:00 ` [Intel-gfx] " Chery, Nanley G
2019-10-28 18:58 ` [Intel-gfx] " Radhakrishna Sripada
0 siblings, 2 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-23 0:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley Chery, Dhinakaran Pandiyan, Kalyan Kondapally
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1aa6d468c048..6b4d36e0ccd0 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,24 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits represents
+ * Raw Clear Color Red, Green, Blue and Alpha color each represented by 32 bits.
+ * The raw clear color is consumed by the 3d engine and generates the converted
+ * clear color of size 64 bits. The first 32 bits store the Lower Converted Clear
+ * Color value and the next 32 bits store the Higher Converted Clear Color value
+ * when applicable. The Converted Clear Color values are consumed by the DE. The
+ * last 64 bits are used to store Color Discard Enable and Depth Clear Value Valid
+ * which are ignored by the DE. A CCS_CC cache line corresponds to an area of 4x1
+ * tiles in the main surface. The main surface pitch is required to be a multiple
+ * of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-24 0:00 ` Chery, Nanley G
0 siblings, 0 replies; 29+ messages in thread
From: Chery, Nanley G @ 2019-10-24 0:00 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx; +Cc: Ekstrand, Jason, Pandiyan, Dhinakaran
Hi RK,
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Tuesday, October 22, 2019 5:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Kondapally, Kalyan <kalyan.kondapally@intel.com>; Antognolli, Rafael <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> Subject: [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
> a new modifier as the driver needs to know the surface was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1aa6d468c048..6b4d36e0ccd0 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,24 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
A couple nit-picks here:
- It's not clear to me why "clear color" is capitalized but "color control surfaces" is not.
- It also isn't clear why "surfaces" is plural here but singular in the Y_TILED_CCS comment.
- A space is missing between "Color" and "(CCS_CC)".
- Perhaps insert a "with" between "color control surface" and "clear color"?
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
I thought "CCS_CC" would be referring to the CCS with clear color, not the CCS
by itself. I can't find this term in the BSpec. Perhaps we shouldn't create a
new one here to avoid confusion?
-Nanley
> + * be ignored. The clear color structure is 256 bits. The first 128 bits represents
> + * Raw Clear Color Red, Green, Blue and Alpha color each represented by 32 bits.
> + * The raw clear color is consumed by the 3d engine and generates the converted
> + * clear color of size 64 bits. The first 32 bits store the Lower Converted Clear
> + * Color value and the next 32 bits store the Higher Converted Clear Color value
> + * when applicable. The Converted Clear Color values are consumed by the DE. The
> + * last 64 bits are used to store Color Discard Enable and Depth Clear Value Valid
> + * which are ignored by the DE. A CCS_CC cache line corresponds to an area of 4x1
> + * tiles in the main surface. The main surface pitch is required to be a multiple
> + * of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.20.1
>
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-24 0:00 ` Chery, Nanley G
0 siblings, 0 replies; 29+ messages in thread
From: Chery, Nanley G @ 2019-10-24 0:00 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx; +Cc: Ekstrand, Jason, Pandiyan, Dhinakaran
Hi RK,
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Tuesday, October 22, 2019 5:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Kondapally, Kalyan <kalyan.kondapally@intel.com>; Antognolli, Rafael <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> Subject: [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
> a new modifier as the driver needs to know the surface was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1aa6d468c048..6b4d36e0ccd0 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,24 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
A couple nit-picks here:
- It's not clear to me why "clear color" is capitalized but "color control surfaces" is not.
- It also isn't clear why "surfaces" is plural here but singular in the Y_TILED_CCS comment.
- A space is missing between "Color" and "(CCS_CC)".
- Perhaps insert a "with" between "color control surface" and "clear color"?
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
I thought "CCS_CC" would be referring to the CCS with clear color, not the CCS
by itself. I can't find this term in the BSpec. Perhaps we shouldn't create a
new one here to avoid confusion?
-Nanley
> + * be ignored. The clear color structure is 256 bits. The first 128 bits represents
> + * Raw Clear Color Red, Green, Blue and Alpha color each represented by 32 bits.
> + * The raw clear color is consumed by the 3d engine and generates the converted
> + * clear color of size 64 bits. The first 32 bits store the Lower Converted Clear
> + * Color value and the next 32 bits store the Higher Converted Clear Color value
> + * when applicable. The Converted Clear Color values are consumed by the DE. The
> + * last 64 bits are used to store Color Discard Enable and Depth Clear Value Valid
> + * which are ignored by the DE. A CCS_CC cache line corresponds to an area of 4x1
> + * tiles in the main surface. The main surface pitch is required to be a multiple
> + * of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.20.1
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v6 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
@ 2019-10-28 18:58 ` Radhakrishna Sripada
0 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 18:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley G Chery, Dhinakaran Pandiyan, Ville Syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2756,6 +2784,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2824,6 +2854,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4341,6 +4383,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15212,6 +15255,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e98f212682f6..9e147bba092e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -587,6 +587,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a5018fffa8f2..f8d2985e6c01 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -596,6 +596,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -656,6 +657,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -2115,7 +2120,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2554,6 +2560,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2562,6 +2569,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2737,6 +2745,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75cccd498b42..8a24707ea697 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6753,6 +6753,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6792,6 +6794,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v6 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
@ 2019-10-28 18:58 ` Radhakrishna Sripada
0 siblings, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 18:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley G Chery, Dhinakaran Pandiyan, Ville Syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2756,6 +2784,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2824,6 +2854,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4341,6 +4383,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15212,6 +15255,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e98f212682f6..9e147bba092e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -587,6 +587,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a5018fffa8f2..f8d2985e6c01 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -596,6 +596,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -656,6 +657,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -2115,7 +2120,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2554,6 +2560,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2562,6 +2569,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2737,6 +2745,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75cccd498b42..8a24707ea697 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6753,6 +6753,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6792,6 +6794,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (8 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
@ 2019-10-15 0:05 ` Radhakrishna Sripada
2019-10-22 18:15 ` Matt Roper
2019-10-23 0:09 ` [PATCH v5 " Radhakrishna Sripada
2019-10-15 0:09 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev4) Patchwork
` (7 subsequent siblings)
17 siblings, 2 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-15 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 448168a4d780..8835920cb005 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1917,6 +1917,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2058,6 +2062,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2260,6 +2265,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2453,6 +2460,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2506,6 +2514,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * top pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2533,6 +2556,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2542,6 +2569,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2729,6 +2757,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2797,6 +2827,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier is consumed
+ * by the driver and not passed to DE. Skip the arithmetic related to
+ * alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4263,6 +4305,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -14586,6 +14629,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 91241f2bc575..213899e202a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -579,6 +579,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index fdb9dcc4060c..baf1351910ca 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -1739,7 +1744,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2154,6 +2160,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2162,6 +2169,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2335,6 +2343,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fad9cb35979..d8883ad99a67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6743,6 +6743,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6782,6 +6784,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v4 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-10-15 0:05 ` [PATCH v4 " Radhakrishna Sripada
@ 2019-10-22 18:15 ` Matt Roper
2019-10-22 18:37 ` Sripada, Radhakrishna
2019-10-23 0:09 ` [PATCH v5 " Radhakrishna Sripada
1 sibling, 1 reply; 29+ messages in thread
From: Matt Roper @ 2019-10-22 18:15 UTC (permalink / raw)
To: Radhakrishna Sripada
Cc: nanley.g.chery, intel-gfx, dhinakaran.pandiyan, ville.syrjala
On Mon, Oct 14, 2019 at 05:05:33PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
> v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
One minor typo and one documentation suggestion, but aside from fixing
those this patch looks good to me:
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
The previous patch that adds the modifier looks fine to me too, but I
figure we should leave it to whoever is working on the corresponding
userspace code to ack/rb that one.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 3 ++
> drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> drivers/gpu/drm/i915/i915_reg.h | 12 +++++
> 4 files changed, 77 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 448168a4d780..8835920cb005 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1917,6 +1917,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> if (color_plane == 1)
> return 64;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + if (color_plane == 1 || color_plane == 2)
> + return 64;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2058,6 +2062,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> return 256 * 1024;
> return 0;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2260,6 +2265,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
> return true;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return color_plane == 1;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return color_plane == 1 || color_plane == 2;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return color_plane == 1 || color_plane == 3;
> default:
> @@ -2453,6 +2460,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2506,6 +2514,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> };
>
> +/*
> + * Same as gen12_ccs_formats[] above, but with additional surface used
> + * top pass Clear Color information in plane 2 with 64 bits of data.
s/top/to
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2533,6 +2556,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return lookup_format_info(gen12_ccs_cc_formats,
> + ARRAY_SIZE(gen12_ccs_cc_formats),
> + cmd->pixel_format);
> default:
> return NULL;
> }
> @@ -2542,6 +2569,7 @@ bool is_ccs_modifier(u64 modifier)
> {
> return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
> @@ -2729,6 +2757,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
> return false;
> else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> return color_plane == 3 || color_plane == 1;
> + else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> + return color_plane == 1 || color_plane == 2;
> else
> return color_plane == 1;
> }
> @@ -2797,6 +2827,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> int x, y;
> int ret;
>
> + /*
> + * Plane 2 of Render Compression with Clear Color fb modifier is consumed
> + * by the driver and not passed to DE. Skip the arithmetic related to
These comment lines are >80 characters and should be re-wrapped.
> + * alignment and offset calculation.
> + */
> + if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> + if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
> + continue;
> + else
> + return -EINVAL;
> + }
> +
> cpp = fb->format->cpp[i];
> intel_fb_plane_dims(&width, &height, fb, i);
>
> @@ -4263,6 +4305,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return PLANE_CTL_TILED_Y |
> @@ -14586,6 +14629,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>
> plane_state->vma = vma;
>
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> + fb->offsets[2] >> PAGE_SHIFT));
> +
> + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> + | *(ccaddr + CC_VAL_LOWER_OFFSET);
I think it would be good to document what the expected format is, either
through comments and/or through a structure definition that describes
the exact layout. As you mentioned before, some of the bytes provided
by the render engine aren't used by the display engine, so a more formal
description of the layout would make this easier to understand.
> + kunmap_atomic(ccaddr);
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 91241f2bc575..213899e202a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -579,6 +579,9 @@ struct intel_plane_state {
> u32 planar_slave;
>
> struct drm_intel_sprite_colorkey ckey;
> +
> + /* Clear Color Value */
> + u64 ccval;
> };
>
> struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index fdb9dcc4060c..baf1351910ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> u32 plane_color_ctl = 0;
> unsigned long irqflags;
> u32 keymsk, keymax;
> + u64 ccval = plane_state->ccval;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> + intel_uncore_write64_fw(&dev_priv->uncore,
> + PLANE_CC_VAL(pipe, plane_id), ccval);
> +
> skl_write_plane_wm(plane, crtc_state);
>
> I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@ -1739,7 +1744,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> return -EINVAL;
> }
> @@ -2154,6 +2160,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -2162,6 +2169,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
>
> static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -2335,6 +2343,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> break;
> default:
> return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5fad9cb35979..d8883ad99a67 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6743,6 +6743,8 @@ enum {
> #define _PLANE_KEYMAX_1_A 0x701a0
> #define _PLANE_KEYMAX_2_A 0x702a0
> #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> +#define _PLANE_CC_VAL_1_A 0x701b4
> +#define _PLANE_CC_VAL_2_A 0x702b4
> #define _PLANE_AUX_DIST_1_A 0x701c0
> #define _PLANE_AUX_DIST_2_A 0x702c0
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> @@ -6782,6 +6784,16 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> +#define PLANE_CC_VAL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +
> +#define CC_VAL_LOWER_OFFSET 4
> +#define CC_VAL_HIGHER_OFFSET 5
> +
> /* Input CSC Register Definitions */
> #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v4 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-10-22 18:15 ` Matt Roper
@ 2019-10-22 18:37 ` Sripada, Radhakrishna
0 siblings, 0 replies; 29+ messages in thread
From: Sripada, Radhakrishna @ 2019-10-22 18:37 UTC (permalink / raw)
To: Roper, Matthew D
Cc: Chery, Nanley G, intel-gfx, Pandiyan, Dhinakaran, Syrjala, Ville
Hi Matt,
> -----Original Message-----
> From: Roper, Matthew D
> Sent: Tuesday, October 22, 2019 11:15 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Sharma, Shashank <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> Subject: Re: [PATCH v4 10/10] drm/i915/tgl: Add Clear Color supoort for TGL
> Render Decompression
>
> On Mon, Oct 14, 2019 at 05:05:33PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS
> > is linear and has 4 bits of data for each main surface cache line
> > pair, a ratio of 1:256. Additional Clear Color information is passed
> > from the user-space through an offset in the GEM BO. Add a new
> > modifier to identify and parse new Clear Color information and extend
> > Gen12 render decompression functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> > v4: Add alignment check and reuse the comments for
> > ge12_ccs_formats(Matt)
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> One minor typo and one documentation suggestion, but aside from fixing
> those this patch looks good to me:
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
Thanks for the review.
> The previous patch that adds the modifier looks fine to me too, but I figure
> we should leave it to whoever is working on the corresponding userspace
> code to ack/rb that one.
>
>
> Matt
>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
> > .../drm/i915/display/intel_display_types.h | 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 12 +++++
> > 4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 448168a4d780..8835920cb005 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1917,6 +1917,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> > if (color_plane == 1)
> > return 64;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + if (color_plane == 1 || color_plane == 2)
> > + return 64;
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > @@ -2058,6 +2062,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> > return 256 * 1024;
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2260,6 +2265,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return color_plane == 1;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return color_plane == 1 || color_plane == 2;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return color_plane == 1 || color_plane == 3;
> > default:
> > @@ -2453,6 +2460,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2506,6 +2514,21 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, };
> >
> > +/*
> > + * Same as gen12_ccs_formats[] above, but with additional surface
> > +used
> > + * top pass Clear Color information in plane 2 with 64 bits of data.
>
> s/top/to
Oops will fix it.
>
> > + */
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +};
> > +
> > static const struct drm_format_info * lookup_format_info(const
> > struct drm_format_info formats[],
> > int num_formats, u32 format)
> > @@ -2533,6 +2556,10 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
> > return lookup_format_info(gen12_ccs_formats,
> > ARRAY_SIZE(gen12_ccs_formats),
> > cmd->pixel_format);
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return lookup_format_info(gen12_ccs_cc_formats,
> > + ARRAY_SIZE(gen12_ccs_cc_formats),
> > + cmd->pixel_format);
> > default:
> > return NULL;
> > }
> > @@ -2542,6 +2569,7 @@ bool is_ccs_modifier(u64 modifier) {
> > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -2729,6
> > +2757,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
> > return false;
> > else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> > return color_plane == 3 || color_plane == 1;
> > + else if (modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > + return color_plane == 1 || color_plane == 2;
> > else
> > return color_plane == 1;
> > }
> > @@ -2797,6 +2827,18 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
> > int x, y;
> > int ret;
> >
> > + /*
> > + * Plane 2 of Render Compression with Clear Color fb
> modifier is consumed
> > + * by the driver and not passed to DE. Skip the arithmetic
> related
> > +to
>
> These comment lines are >80 characters and should be re-wrapped.
>
> > + * alignment and offset calculation.
> > + */
> > + if (i == 2 && fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > + if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
> > + continue;
> > + else
> > + return -EINVAL;
> > + }
> > +
> > cpp = fb->format->cpp[i];
> > intel_fb_plane_dims(&width, &height, fb, i);
> >
> > @@ -4263,6 +4305,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return PLANE_CTL_TILED_Y |
> > @@ -14586,6 +14629,15 @@ static int intel_plane_pin_fb(struct
> > intel_plane_state *plane_state)
> >
> > plane_state->vma = vma;
> >
> > + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > + u32 *ccaddr =
> kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > + fb-
> >offsets[2] >> PAGE_SHIFT));
> > +
> > + plane_state->ccval = ((u64)*(ccaddr +
> CC_VAL_HIGHER_OFFSET) << 32)
> > + | *(ccaddr + CC_VAL_LOWER_OFFSET);
>
> I think it would be good to document what the expected format is, either
> through comments and/or through a structure definition that describes the
> exact layout. As you mentioned before, some of the bytes provided by the
> render engine aren't used by the display engine, so a more formal
> description of the layout would make this easier to understand.
Documenting this in the previous patch would be the right place. So that
The description of the Color format is available at the modifier declaration.
Thanks,
Radhakrishna(RK) Sripada
>
> > + kunmap_atomic(ccaddr);
> > + }
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 91241f2bc575..213899e202a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -579,6 +579,9 @@ struct intel_plane_state {
> > u32 planar_slave;
> >
> > struct drm_intel_sprite_colorkey ckey;
> > +
> > + /* Clear Color Value */
> > + u64 ccval;
> > };
> >
> > struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index fdb9dcc4060c..baf1351910ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane,
> > u32 plane_color_ctl = 0;
> > unsigned long irqflags;
> > u32 keymsk, keymax;
> > + u64 ccval = plane_state->ccval;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >
> > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane,
> > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > icl_program_input_csc(plane, crtc_state, plane_state);
> >
> > + if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > + intel_uncore_write64_fw(&dev_priv->uncore,
> > + PLANE_CC_VAL(pipe, plane_id),
> ccval);
> > +
> > skl_write_plane_wm(plane, crtc_state);
> >
> > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@
> > -1739,7 +1744,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > + fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
> > return -EINVAL;
> > }
> > @@ -2154,6 +2160,7 @@ static const u64
> > skl_plane_format_modifiers_ccs[] = { static const u64
> gen12_plane_format_modifiers_mc_ccs[] = {
> > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > I915_FORMAT_MOD_Y_TILED,
> > I915_FORMAT_MOD_X_TILED,
> > DRM_FORMAT_MOD_LINEAR,
> > @@ -2162,6 +2169,7 @@ static const u64
> > gen12_plane_format_modifiers_mc_ccs[] = {
> >
> > static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > I915_FORMAT_MOD_Y_TILED,
> > I915_FORMAT_MOD_X_TILED,
> > DRM_FORMAT_MOD_LINEAR,
> > @@ -2335,6 +2343,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > break;
> > default:
> > return false;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 5fad9cb35979..d8883ad99a67
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6743,6 +6743,8 @@ enum {
> > #define _PLANE_KEYMAX_1_A 0x701a0
> > #define _PLANE_KEYMAX_2_A 0x702a0
> > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
> > +#define _PLANE_CC_VAL_1_A 0x701b4
> > +#define _PLANE_CC_VAL_2_A 0x702b4
> > #define _PLANE_AUX_DIST_1_A 0x701c0
> > #define _PLANE_AUX_DIST_2_A 0x702c0
> > #define _PLANE_AUX_OFFSET_1_A 0x701c4
> > @@ -6782,6 +6784,16 @@ enum {
> > #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> > #define _PLANE_NV12_BUF_CFG_2_A 0x70378
> >
> > +#define _PLANE_CC_VAL_1_B 0x711b4
> > +#define _PLANE_CC_VAL_2_B 0x712b4
> > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B)
> > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B)
> > +#define PLANE_CC_VAL(pipe, plane) \
> > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe),
> _PLANE_CC_VAL_2(pipe))
> > +
> > +#define CC_VAL_LOWER_OFFSET 4
> > +#define CC_VAL_HIGHER_OFFSET 5
> > +
> > /* Input CSC Register Definitions */
> > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> > --
> > 2.20.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v5 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
2019-10-15 0:05 ` [PATCH v4 " Radhakrishna Sripada
2019-10-22 18:15 ` Matt Roper
@ 2019-10-23 0:09 ` Radhakrishna Sripada
1 sibling, 0 replies; 29+ messages in thread
From: Radhakrishna Sripada @ 2019-10-23 0:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Nanley G Chery, Dhinakaran Pandiyan, Ville Syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 177fc0e1d8bf..4b08383ce65b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1931,6 +1931,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2072,6 +2076,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2274,6 +2279,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2467,6 +2474,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2520,6 +2528,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2547,6 +2570,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2556,6 +2583,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2743,6 +2771,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2811,6 +2841,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4269,6 +4311,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15048,6 +15091,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 599b32ef518f..6fa3594e9dea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -579,6 +579,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 67e4224a31a3..bdc412d98101 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -607,6 +608,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -1737,7 +1742,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2152,6 +2158,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2160,6 +2167,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2333,6 +2341,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 306a8c63080d..ed4107147fef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6750,6 +6750,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6789,6 +6791,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev4)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (9 preceding siblings ...)
2019-10-15 0:05 ` [PATCH v4 " Radhakrishna Sripada
@ 2019-10-15 0:09 ` Patchwork
2019-10-15 0:34 ` ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-15 0:09 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev4)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5b2a67fc7d74 drm/framebuffer: Format modifier for Intel Gen-12 render compression
7ae892f52e6b drm/i915: Use intel_tile_height() instead of re-implementing
6e151153d384 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
fe009ce2a753 drm/i915/tgl: Gen-12 render decompression
922c0f17cfcb drm/i915: Extract framebufer CCS offset checks into a function
3e0c8644766c drm/framebuffer: Format modifier for Intel Gen-12 media compression
e81ef5974cd9 drm/fb: Extend format_info member arrays to handle four planes
6af18a7bd390 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2699:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2706:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
0a4f1ab7678c drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7:
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
-:33: ERROR:TRAILING_WHITESPACE: trailing whitespace
#33: FILE: include/uapi/drm/drm_fourcc.h:442:
+ * be ignored. The size of clear color should be 64 bits. A CCS_CC cache line $
-:34: ERROR:TRAILING_WHITESPACE: trailing whitespace
#34: FILE: include/uapi/drm/drm_fourcc.h:443:
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface $
total: 2 errors, 1 warnings, 0 checks, 17 lines checked
cb25ebee96c9 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#252: FILE: drivers/gpu/drm/i915/i915_reg.h:6791:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.BAT: success for Clear Color Support for TGL Render Decompression (rev4)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (10 preceding siblings ...)
2019-10-15 0:09 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev4) Patchwork
@ 2019-10-15 0:34 ` Patchwork
2019-10-15 1:08 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev5) Patchwork
` (5 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-15 0:34 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev4)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14802
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/index.html
Known issues
------------
Here are the changes found in Patchwork_14802 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-apl-guc/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/fi-apl-guc/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (52 -> 45)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7091 -> Patchwork_14802
CI-20190529: 20190529
CI_DRM_7091: d88a66d195bcf71e6e05db07ba79c9fab5651f22 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5225: 991ce4eede1c52f76378aebf162a13c20d6f6293 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14802: cb25ebee96c966a74afdf8e23a4004a82757e32d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cb25ebee96c9 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
0a4f1ab7678c drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
6af18a7bd390 Gen-12 display can decompress surfaces compressed by the media engine.
e81ef5974cd9 drm/fb: Extend format_info member arrays to handle four planes
3e0c8644766c drm/framebuffer: Format modifier for Intel Gen-12 media compression
922c0f17cfcb drm/i915: Extract framebufer CCS offset checks into a function
fe009ce2a753 drm/i915/tgl: Gen-12 render decompression
6e151153d384 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
7ae892f52e6b drm/i915: Use intel_tile_height() instead of re-implementing
5b2a67fc7d74 drm/framebuffer: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14802/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev5)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (11 preceding siblings ...)
2019-10-15 0:34 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-15 1:08 ` Patchwork
2019-10-15 1:56 ` ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-15 1:08 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev5)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e84d0c20bec1 drm/framebuffer: Format modifier for Intel Gen-12 render compression
46a58f5e2541 drm/i915: Use intel_tile_height() instead of re-implementing
43b42e53f492 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
150111127386 drm/i915/tgl: Gen-12 render decompression
8be18fc5f18e drm/i915: Extract framebufer CCS offset checks into a function
e9aab6479891 drm/framebuffer: Format modifier for Intel Gen-12 media compression
b4947111fb56 drm/fb: Extend format_info member arrays to handle four planes
0f52b8eef612 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2699:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2706:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
71d0a02d234b drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7:
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
4f8d40fcc90f drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#252: FILE: drivers/gpu/drm/i915/i915_reg.h:6791:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.BAT: success for Clear Color Support for TGL Render Decompression (rev5)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (12 preceding siblings ...)
2019-10-15 1:08 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev5) Patchwork
@ 2019-10-15 1:56 ` Patchwork
2019-10-15 12:12 ` ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-15 1:56 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev5)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091 -> Patchwork_14803
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14803:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload-with-fault-injection:
- {fi-tgl-u}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-tgl-u/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/fi-tgl-u/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_14803 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-icl-u3/igt@gem_render_linear_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/fi-icl-u3/igt@gem_render_linear_blits@basic.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [PASS][5] -> [DMESG-FAIL][6] ([fdo# 111537])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111537]: https://bugs.freedesktop.org/show_bug.cgi?id= 111537
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7091 -> Patchwork_14803
CI-20190529: 20190529
CI_DRM_7091: d88a66d195bcf71e6e05db07ba79c9fab5651f22 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5225: 991ce4eede1c52f76378aebf162a13c20d6f6293 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14803: 4f8d40fcc90f255c3f838505ca7a2316ae8ab367 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4f8d40fcc90f drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
71d0a02d234b drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
0f52b8eef612 Gen-12 display can decompress surfaces compressed by the media engine.
b4947111fb56 drm/fb: Extend format_info member arrays to handle four planes
e9aab6479891 drm/framebuffer: Format modifier for Intel Gen-12 media compression
8be18fc5f18e drm/i915: Extract framebufer CCS offset checks into a function
150111127386 drm/i915/tgl: Gen-12 render decompression
43b42e53f492 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
46a58f5e2541 drm/i915: Use intel_tile_height() instead of re-implementing
e84d0c20bec1 drm/framebuffer: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.IGT: success for Clear Color Support for TGL Render Decompression (rev5)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (13 preceding siblings ...)
2019-10-15 1:56 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-15 12:12 ` Patchwork
2019-10-23 1:52 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev7) Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-15 12:12 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev5)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7091_full -> Patchwork_14803_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14803_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f:
- {shard-tglb}: NOTRUN -> [SKIP][1] +7 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-tglb2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f.html
* igt@kms_plane@pixel-format-pipe-c-planes:
- {shard-tglb}: NOTRUN -> [FAIL][2] +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-tglb7/igt@kms_plane@pixel-format-pipe-c-planes.html
Known issues
------------
Here are the changes found in Patchwork_14803_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-suspend:
- shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([fdo#111764])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb4/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb3/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#109661])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-snb1/igt@gem_eio@unwedge-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-snb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-snb4/igt@gem_userptr_blits@dmabuf-unsync.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@i915_pm_rpm@gem-mmap-gtt:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#108840])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb5/igt@i915_pm_rpm@gem-mmap-gtt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb1/igt@i915_pm_rpm@gem-mmap-gtt.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#103355])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-apl5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103166])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-glk: [PASS][29] -> [FAIL][30] ([fdo#109016]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-glk4/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-glk2/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: [PASS][31] -> [FAIL][32] ([fdo#109016]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-kbl7/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-kbl1/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
- shard-iclb: [PASS][33] -> [FAIL][34] ([fdo#109016]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb1/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb2/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][35] -> [FAIL][36] ([fdo#99912])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-skl2/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-skl5/igt@kms_setmode@basic.html
* igt@perf_pmu@rc6-runtime-pm:
- shard-iclb: [PASS][37] -> [INCOMPLETE][38] ([fdo#107713])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb5/igt@perf_pmu@rc6-runtime-pm.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb1/igt@perf_pmu@rc6-runtime-pm.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109276]) +21 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb1/igt@prime_busy@hang-bsd2.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb3/igt@prime_busy@hang-bsd2.html
* igt@prime_mmap_coherency@read:
- shard-snb: [PASS][41] -> [INCOMPLETE][42] ([fdo#105411])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-snb2/igt@prime_mmap_coherency@read.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-snb7/igt@prime_mmap_coherency@read.html
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-snb: [FAIL][43] ([fdo#109661]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-snb2/igt@gem_eio@reset-stress.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-snb1/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [SKIP][45] ([fdo#111325]) -> [PASS][46] +5 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [PASS][48] +12 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb6/igt@gem_exec_schedule@promotion-bsd1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [INCOMPLETE][49] ([fdo#103359] / [fdo#108686] / [k.org#198133]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-glk4/igt@gem_tiled_swapping@non-threaded.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-glk5/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [DMESG-WARN][53] ([fdo#111870]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-hsw8/igt@gem_userptr_blits@sync-unmap-cycles.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-hsw7/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [DMESG-FAIL][55] ([fdo#111991]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-hsw8/igt@i915_selftest@live_hangcheck.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-hsw7/igt@i915_selftest@live_hangcheck.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-skl: [DMESG-WARN][57] ([fdo#106107]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-skl2/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-skl5/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][59] ([fdo#103167]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-iclb: [INCOMPLETE][61] ([fdo#106978] / [fdo#107713]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][63] ([fdo#108566]) -> [PASS][64] +4 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][67] ([fdo#99912]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-apl6/igt@kms_setmode@basic.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-apl5/igt@kms_setmode@basic.html
* igt@prime_busy@wait-hang-blt:
- shard-apl: [INCOMPLETE][69] ([fdo#103927]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-apl2/igt@prime_busy@wait-hang-blt.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-apl6/igt@prime_busy@wait-hang-blt.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [SKIP][71] ([fdo#109276]) -> [FAIL][72] ([fdo#111330])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb1/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][73] ([fdo#107724]) -> [SKIP][74] ([fdo#109349])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-suspend:
- shard-apl: [INCOMPLETE][75] ([fdo#103927]) -> [DMESG-WARN][76] ([fdo#108566])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7091/shard-apl6/igt@kms_flip@flip-vs-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/shard-apl4/igt@kms_flip@flip-vs-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7091 -> Patchwork_14803
CI-20190529: 20190529
CI_DRM_7091: d88a66d195bcf71e6e05db07ba79c9fab5651f22 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5225: 991ce4eede1c52f76378aebf162a13c20d6f6293 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14803: 4f8d40fcc90f255c3f838505ca7a2316ae8ab367 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14803/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev7)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (14 preceding siblings ...)
2019-10-15 12:12 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-10-23 1:52 ` Patchwork
2019-10-23 2:35 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-23 17:20 ` [Intel-gfx] " Patchwork
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-23 1:52 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad3f8ef792a4 drm/framebuffer: Format modifier for Intel Gen-12 render compression
8130c8f3c633 drm/i915: Use intel_tile_height() instead of re-implementing
0513f8dd0e4f drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
aa26ffc536ed drm/i915/tgl: Gen-12 render decompression
3a4093bd96ef drm/i915: Extract framebufer CCS offset checks into a function
130bad161a5f drm/framebuffer: Format modifier for Intel Gen-12 media compression
5f5914ce2a12 drm/fb: Extend format_info member arrays to handle four planes
791ce575f45a Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2713:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2720:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
471c649e8d20 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7:
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
total: 0 errors, 1 warnings, 0 checks, 24 lines checked
4530a97a79f2 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:6798:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.BAT: success for Clear Color Support for TGL Render Decompression (rev7)
2019-10-15 0:05 [PATCH v4 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
` (15 preceding siblings ...)
2019-10-23 1:52 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev7) Patchwork
@ 2019-10-23 2:35 ` Patchwork
2019-10-23 17:20 ` [Intel-gfx] " Patchwork
17 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-23 2:35 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14937
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14937:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/fi-tgl-u/igt@i915_selftest@live_gem.html
Known issues
------------
Here are the changes found in Patchwork_14937 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-write-read:
- fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html
#### Possible fixes ####
* igt@gem_flink_basic@basic:
- fi-icl-u3: [DMESG-WARN][4] ([fdo#107724] / [fdo#112052 ]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@gem_flink_basic@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/fi-icl-u3/igt@gem_flink_basic@basic.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][6] ([fdo#111880]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u/igt@gem_sync@basic-many-each.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/fi-tgl-u/igt@gem_sync@basic-many-each.html
* igt@vgem_basic@setversion:
- fi-icl-u3: [DMESG-WARN][8] ([fdo#107724]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@vgem_basic@setversion.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/fi-icl-u3/igt@vgem_basic@setversion.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 43)
------------------------------
Additional (1): fi-bxt-dsi
Missing (10): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus fi-cml-u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7155 -> Patchwork_14937
CI-20190529: 20190529
CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14937: 4530a97a79f21b2d24a9c0a8750524d8f6b9d34b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4530a97a79f2 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
471c649e8d20 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
791ce575f45a Gen-12 display can decompress surfaces compressed by the media engine.
5f5914ce2a12 drm/fb: Extend format_info member arrays to handle four planes
130bad161a5f drm/framebuffer: Format modifier for Intel Gen-12 media compression
3a4093bd96ef drm/i915: Extract framebufer CCS offset checks into a function
aa26ffc536ed drm/i915/tgl: Gen-12 render decompression
0513f8dd0e4f drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
8130c8f3c633 drm/i915: Use intel_tile_height() instead of re-implementing
ad3f8ef792a4 drm/framebuffer: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.IGT: success for Clear Color Support for TGL Render Decompression (rev7)
@ 2019-10-23 17:20 ` Patchwork
0 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-10-23 17:20 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14937_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14937_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- {shard-tglb}: [PASS][1] -> [FAIL][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb2/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane@pixel-format-pipe-d-planes:
- {shard-tglb}: NOTRUN -> [FAIL][3] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb3/igt@kms_plane@pixel-format-pipe-d-planes.html
Known issues
------------
Here are the changes found in Patchwork_14937_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb7/igt@gem_ctx_isolation@vcs1-clean.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +16 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb3/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-snb: [PASS][10] -> [FAIL][11] ([fdo#112037])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [PASS][16] -> [DMESG-WARN][17] ([fdo#105763] / [fdo#106538])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@i915_pm_rpm@modeset-stress-extra-wait.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
* igt@kms_busy@basic-flip-c:
- shard-skl: [PASS][18] -> [DMESG-WARN][19] ([fdo#106107])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_busy@basic-flip-c.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-skl8/igt@kms_busy@basic-flip-c.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-a:
- shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([fdo#107713])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@kms_busy@extended-pageflip-hang-oldfb-render-a.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb7/igt@kms_busy@extended-pageflip-hang-oldfb-render-a.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([fdo#103665])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-apl: [PASS][24] -> [INCOMPLETE][25] ([fdo#103927])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-apl4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][26] -> [INCOMPLETE][27] ([fdo#103540])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][28] -> [FAIL][29] ([fdo#103167]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][30] -> [DMESG-WARN][31] ([fdo#103313])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][32] -> [FAIL][33] ([fdo#108145])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109441])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-glk: [PASS][36] -> [FAIL][37] ([fdo#109016]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk8/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk6/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: [PASS][38] -> [FAIL][39] ([fdo#109016]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl1/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-kbl7/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
- shard-iclb: [PASS][40] -> [FAIL][41] ([fdo#109016]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb8/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][42] -> [DMESG-WARN][43] ([fdo#108566]) +6 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][44] -> [SKIP][45] ([fdo#112080]) +7 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb3/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-switch:
- shard-iclb: [SKIP][46] ([fdo#109276] / [fdo#112080]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-switch.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-switch.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: [INCOMPLETE][48] ([fdo#103665]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_ctx_isolation@vecs0-s3.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-kbl2/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][50] ([fdo#110841]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@vcs1-heavy-queue:
- shard-iclb: [SKIP][52] ([fdo#112080]) -> [PASS][53] +11 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_ctx_switch@vcs1-heavy-queue.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy-queue.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][54] ([fdo#111325]) -> [PASS][55] +5 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][56] ([fdo#111870]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][58] ([fdo#111870]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-apl: [INCOMPLETE][60] ([fdo#103927]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl3/igt@gem_userptr_blits@unsync-unmap-cycles.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-apl3/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][62] ([fdo#108566]) -> [PASS][63] +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
- {shard-tglb}: [INCOMPLETE][64] ([fdo#111832] / [fdo#111850]) -> [PASS][65] +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb6/igt@gem_workarounds@suspend-resume-context.html
* {igt@i915_pm_dc@dc6-dpms}:
- shard-iclb: [FAIL][66] ([fdo#110548]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-snb: [SKIP][68] ([fdo#109271]) -> [PASS][69] +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb4/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-iclb: [INCOMPLETE][70] ([fdo#107713]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: [FAIL][72] ([fdo#111609]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@kms_flip@dpms-vs-vblank-race.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk8/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][74] ([fdo#105363]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-skl: [FAIL][76] ([fdo#107931] / [fdo#108303]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-skl1/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt:
- shard-iclb: [FAIL][78] ([fdo#103167]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- {shard-tglb}: [INCOMPLETE][80] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- {shard-tglb}: [FAIL][82] ([fdo#103167]) -> [PASS][83] +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][84] ([fdo#109441]) -> [PASS][85] +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][86] ([fdo#99912]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk4/igt@kms_setmode@basic.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk2/igt@kms_setmode@basic.html
* igt@perf@short-reads:
- shard-glk: [TIMEOUT][88] ([fdo#103183]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk9/igt@perf@short-reads.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk1/igt@perf@short-reads.html
* igt@perf_pmu@busy-start-vecs0:
- {shard-tglb}: [INCOMPLETE][90] ([fdo#111747]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@perf_pmu@busy-start-vecs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb7/igt@perf_pmu@busy-start-vecs0.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][92] ([fdo#109276]) -> [PASS][93] +15 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@prime_busy@hang-bsd2.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb2/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][94] ([fdo#109276]) -> [FAIL][95] ([fdo#111330])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][96] ([fdo#111330]) -> [SKIP][97] ([fdo#109276])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/index.html
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