* [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-29 10:01 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV Ville Syrjala
` (12 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..1cdcd0ea0564 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+};
+
static const u64 i9xx_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
switch (format) {
case DISPPLANE_8BPP:
return DRM_FORMAT_C8;
+ case DISPPLANE_BGRA555:
+ return DRM_FORMAT_ARGB1555;
case DISPPLANE_BGRX555:
return DRM_FORMAT_XRGB1555;
case DISPPLANE_BGRX565:
@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
return DRM_FORMAT_XRGB8888;
case DISPPLANE_RGBX888:
return DRM_FORMAT_XBGR8888;
+ case DISPPLANE_BGRA888:
+ return DRM_FORMAT_ARGB8888;
+ case DISPPLANE_RGBA888:
+ return DRM_FORMAT_ABGR8888;
case DISPPLANE_BGRX101010:
return DRM_FORMAT_XRGB2101010;
case DISPPLANE_RGBX101010:
return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_BGRA101010:
+ return DRM_FORMAT_ARGB2101010;
+ case DISPPLANE_RGBA101010:
+ return DRM_FORMAT_ABGR2101010;
}
}
@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
case DRM_FORMAT_XRGB1555:
dspcntr |= DISPPLANE_BGRX555;
break;
+ case DRM_FORMAT_ARGB1555:
+ dspcntr |= DISPPLANE_BGRA555;
+ break;
case DRM_FORMAT_RGB565:
dspcntr |= DISPPLANE_BGRX565;
break;
@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
case DRM_FORMAT_XBGR8888:
dspcntr |= DISPPLANE_RGBX888;
break;
+ case DRM_FORMAT_ARGB8888:
+ dspcntr |= DISPPLANE_BGRA888;
+ break;
+ case DRM_FORMAT_ABGR8888:
+ dspcntr |= DISPPLANE_RGBA888;
+ break;
case DRM_FORMAT_XRGB2101010:
dspcntr |= DISPPLANE_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
dspcntr |= DISPPLANE_RGBX101010;
break;
+ case DRM_FORMAT_ARGB2101010:
+ dspcntr |= DISPPLANE_BGRA101010;
+ break;
+ case DRM_FORMAT_ABGR2101010:
+ dspcntr |= DISPPLANE_RGBA101010;
+ break;
default:
MISSING_CASE(fb->format->format);
return 0;
@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
return modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED;
default:
@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ formats = vlv_primary_formats;
+ num_formats = ARRAY_SIZE(vlv_primary_formats);
+ modifiers = i9xx_format_modifiers;
+
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+ plane->get_hw_state = i9xx_plane_get_hw_state;
+ plane->check_plane = i9xx_plane_check;
+
+ plane_funcs = &i965_plane_funcs;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
modifiers = i9xx_format_modifiers;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..8bd75eff1266 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6270,6 +6270,7 @@ enum {
#define DISPPLANE_RGBX101010 (0x8 << 26)
#define DISPPLANE_RGBA101010 (0x9 << 26)
#define DISPPLANE_BGRX101010 (0xa << 26)
+#define DISPPLANE_BGRA101010 (0xb << 26)
#define DISPPLANE_RGBX161616 (0xc << 26)
#define DISPPLANE_RGBX888 (0xe << 26)
#define DISPPLANE_RGBA888 (0xf << 26)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
@ 2019-10-29 10:01 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 10:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary
>planes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we expose VLV/CHV alpha blending only on the sprite planes, but the
>primary planes can do it as well. Let's flip it on.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 57 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1a533ccdb54f..1cdcd0ea0564 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
> DRM_FORMAT_XBGR2101010,
> };
>
>+/* Primary plane formats for vlv/chv */ static const u32
>+vlv_primary_formats[] = {
>+ DRM_FORMAT_C8,
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
>+};
>+
> static const u64 i9xx_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
>@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
> switch (format) {
> case DISPPLANE_8BPP:
> return DRM_FORMAT_C8;
>+ case DISPPLANE_BGRA555:
>+ return DRM_FORMAT_ARGB1555;
> case DISPPLANE_BGRX555:
> return DRM_FORMAT_XRGB1555;
> case DISPPLANE_BGRX565:
>@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
> return DRM_FORMAT_XRGB8888;
> case DISPPLANE_RGBX888:
> return DRM_FORMAT_XBGR8888;
>+ case DISPPLANE_BGRA888:
>+ return DRM_FORMAT_ARGB8888;
>+ case DISPPLANE_RGBA888:
>+ return DRM_FORMAT_ABGR8888;
> case DISPPLANE_BGRX101010:
> return DRM_FORMAT_XRGB2101010;
> case DISPPLANE_RGBX101010:
> return DRM_FORMAT_XBGR2101010;
>+ case DISPPLANE_BGRA101010:
>+ return DRM_FORMAT_ARGB2101010;
>+ case DISPPLANE_RGBA101010:
>+ return DRM_FORMAT_ABGR2101010;
> }
> }
>
>@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB1555:
> dspcntr |= DISPPLANE_BGRX555;
> break;
>+ case DRM_FORMAT_ARGB1555:
>+ dspcntr |= DISPPLANE_BGRA555;
>+ break;
> case DRM_FORMAT_RGB565:
> dspcntr |= DISPPLANE_BGRX565;
> break;
>@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XBGR8888:
> dspcntr |= DISPPLANE_RGBX888;
> break;
>+ case DRM_FORMAT_ARGB8888:
>+ dspcntr |= DISPPLANE_BGRA888;
>+ break;
>+ case DRM_FORMAT_ABGR8888:
>+ dspcntr |= DISPPLANE_RGBA888;
>+ break;
> case DRM_FORMAT_XRGB2101010:
> dspcntr |= DISPPLANE_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> dspcntr |= DISPPLANE_RGBX101010;
> break;
>+ case DRM_FORMAT_ARGB2101010:
>+ dspcntr |= DISPPLANE_BGRA101010;
>+ break;
>+ case DRM_FORMAT_ABGR2101010:
>+ dspcntr |= DISPPLANE_RGBA101010;
>+ break;
> default:
> MISSING_CASE(fb->format->format);
> return 0;
>@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
>+ case DRM_FORMAT_ARGB8888:
>+ case DRM_FORMAT_ABGR8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return modifier == DRM_FORMAT_MOD_LINEAR ||
> modifier == I915_FORMAT_MOD_X_TILED;
> default:
>@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> }
>
>- if (INTEL_GEN(dev_priv) >= 4) {
>+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>+ formats = vlv_primary_formats;
>+ num_formats = ARRAY_SIZE(vlv_primary_formats);
>+ modifiers = i9xx_format_modifiers;
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disable_plane = i9xx_disable_plane;
>+ plane->get_hw_state = i9xx_plane_get_hw_state;
>+ plane->check_plane = i9xx_plane_check;
>+
>+ plane_funcs = &i965_plane_funcs;
These seems to be duplicated, but since this is already refactored in later patch so
should be ok.
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>+ } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
> modifiers = i9xx_format_modifiers;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>1dc067fc57ab..8bd75eff1266 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6270,6 +6270,7 @@ enum {
> #define DISPPLANE_RGBX101010 (0x8 << 26)
> #define DISPPLANE_RGBA101010 (0x9 << 26)
> #define DISPPLANE_BGRX101010 (0xa << 26)
>+#define DISPPLANE_BGRA101010 (0xb << 26)
> #define DISPPLANE_RGBX161616 (0xc << 26)
> #define DISPPLANE_RGBX888 (0xe << 26)
> #define DISPPLANE_RGBA888 (0xf << 26)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
@ 2019-10-29 10:01 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 10:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary
>planes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we expose VLV/CHV alpha blending only on the sprite planes, but the
>primary planes can do it as well. Let's flip it on.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 57 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1a533ccdb54f..1cdcd0ea0564 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
> DRM_FORMAT_XBGR2101010,
> };
>
>+/* Primary plane formats for vlv/chv */ static const u32
>+vlv_primary_formats[] = {
>+ DRM_FORMAT_C8,
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
>+};
>+
> static const u64 i9xx_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
>@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
> switch (format) {
> case DISPPLANE_8BPP:
> return DRM_FORMAT_C8;
>+ case DISPPLANE_BGRA555:
>+ return DRM_FORMAT_ARGB1555;
> case DISPPLANE_BGRX555:
> return DRM_FORMAT_XRGB1555;
> case DISPPLANE_BGRX565:
>@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
> return DRM_FORMAT_XRGB8888;
> case DISPPLANE_RGBX888:
> return DRM_FORMAT_XBGR8888;
>+ case DISPPLANE_BGRA888:
>+ return DRM_FORMAT_ARGB8888;
>+ case DISPPLANE_RGBA888:
>+ return DRM_FORMAT_ABGR8888;
> case DISPPLANE_BGRX101010:
> return DRM_FORMAT_XRGB2101010;
> case DISPPLANE_RGBX101010:
> return DRM_FORMAT_XBGR2101010;
>+ case DISPPLANE_BGRA101010:
>+ return DRM_FORMAT_ARGB2101010;
>+ case DISPPLANE_RGBA101010:
>+ return DRM_FORMAT_ABGR2101010;
> }
> }
>
>@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB1555:
> dspcntr |= DISPPLANE_BGRX555;
> break;
>+ case DRM_FORMAT_ARGB1555:
>+ dspcntr |= DISPPLANE_BGRA555;
>+ break;
> case DRM_FORMAT_RGB565:
> dspcntr |= DISPPLANE_BGRX565;
> break;
>@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XBGR8888:
> dspcntr |= DISPPLANE_RGBX888;
> break;
>+ case DRM_FORMAT_ARGB8888:
>+ dspcntr |= DISPPLANE_BGRA888;
>+ break;
>+ case DRM_FORMAT_ABGR8888:
>+ dspcntr |= DISPPLANE_RGBA888;
>+ break;
> case DRM_FORMAT_XRGB2101010:
> dspcntr |= DISPPLANE_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> dspcntr |= DISPPLANE_RGBX101010;
> break;
>+ case DRM_FORMAT_ARGB2101010:
>+ dspcntr |= DISPPLANE_BGRA101010;
>+ break;
>+ case DRM_FORMAT_ABGR2101010:
>+ dspcntr |= DISPPLANE_RGBA101010;
>+ break;
> default:
> MISSING_CASE(fb->format->format);
> return 0;
>@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
>+ case DRM_FORMAT_ARGB8888:
>+ case DRM_FORMAT_ABGR8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return modifier == DRM_FORMAT_MOD_LINEAR ||
> modifier == I915_FORMAT_MOD_X_TILED;
> default:
>@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> }
>
>- if (INTEL_GEN(dev_priv) >= 4) {
>+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>+ formats = vlv_primary_formats;
>+ num_formats = ARRAY_SIZE(vlv_primary_formats);
>+ modifiers = i9xx_format_modifiers;
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disable_plane = i9xx_disable_plane;
>+ plane->get_hw_state = i9xx_plane_get_hw_state;
>+ plane->check_plane = i9xx_plane_check;
>+
>+ plane_funcs = &i965_plane_funcs;
These seems to be duplicated, but since this is already refactored in later patch so
should be ok.
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>+ } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
> modifiers = i9xx_format_modifiers;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>1dc067fc57ab..8bd75eff1266 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6270,6 +6270,7 @@ enum {
> #define DISPPLANE_RGBX101010 (0x8 << 26)
> #define DISPPLANE_RGBA101010 (0x9 << 26)
> #define DISPPLANE_BGRX101010 (0xa << 26)
>+#define DISPPLANE_BGRA101010 (0xb << 26)
> #define DISPPLANE_RGBX161616 (0xc << 26)
> #define DISPPLANE_RGBX888 (0xe << 26)
> #define DISPPLANE_RGBA888 (0xf << 26)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
2019-10-08 16:14 ` [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-29 11:53 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes Ville Syrjala
` (11 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the the primary
plane. Add the require bits to expose the new formats.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 14 +++++----
2 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 90b0e65420a5..fb36da58390a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
case DRM_FORMAT_ABGR2101010:
sprctl |= SP_FORMAT_RGBA1010102;
break;
+ case DRM_FORMAT_XRGB2101010:
+ sprctl |= SP_FORMAT_BGRX1010102;
+ break;
+ case DRM_FORMAT_ARGB2101010:
+ sprctl |= SP_FORMAT_BGRA1010102;
+ break;
case DRM_FORMAT_XBGR8888:
sprctl |= SP_FORMAT_RGBX8888;
break;
@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = vlv_plane_get_hw_state;
plane->check_plane = vlv_sprite_check;
- formats = vlv_plane_formats;
- num_formats = ARRAY_SIZE(vlv_plane_formats);
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+ formats = chv_pipe_b_sprite_formats;
+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+ } else {
+ formats = vlv_plane_formats;
+ num_formats = ARRAY_SIZE(vlv_plane_formats);
+ }
modifiers = i9xx_plane_format_modifiers;
plane_funcs = &vlv_sprite_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd75eff1266..74bb5a6cbe4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6545,12 +6545,14 @@ enum {
#define SP_ENABLE (1 << 31)
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK (0xf << 26)
-#define SP_FORMAT_YUV422 (0 << 26)
-#define SP_FORMAT_BGR565 (5 << 26)
-#define SP_FORMAT_BGRX8888 (6 << 26)
-#define SP_FORMAT_BGRA8888 (7 << 26)
-#define SP_FORMAT_RGBX1010102 (8 << 26)
-#define SP_FORMAT_RGBA1010102 (9 << 26)
+#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_BGR565 (0x5 << 26)
+#define SP_FORMAT_BGRX8888 (0x6 << 26)
+#define SP_FORMAT_BGRA8888 (0x7 << 26)
+#define SP_FORMAT_RGBX1010102 (0x8 << 26)
+#define SP_FORMAT_RGBA1010102 (0x9 << 26)
+#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
#define SP_FORMAT_RGBX8888 (0xe << 26)
#define SP_FORMAT_RGBA8888 (0xf << 26)
#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
@ 2019-10-29 11:53 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 11:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B
>sprites on CHV
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
>On VLV and CHV pipe A/C these are only supported by the the primary plane. Add the
Drop the redundant "the".
CHV indeed has this additional capability on pipe B (MPO pipe) sprites.
Overall changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>require bits to expose the new formats.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++----
> 2 files changed, 39 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 90b0e65420a5..fb36da58390a 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ABGR2101010:
> sprctl |= SP_FORMAT_RGBA1010102;
> break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SP_FORMAT_BGRX1010102;
>+ break;
>+ case DRM_FORMAT_ARGB2101010:
>+ sprctl |= SP_FORMAT_BGRA1010102;
>+ break;
> case DRM_FORMAT_XBGR8888:
> sprctl |= SP_FORMAT_RGBX8888;
> break;
>@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
>+static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_ABGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_YUYV,
>+ DRM_FORMAT_YVYU,
>+ DRM_FORMAT_UYVY,
>+ DRM_FORMAT_VYUY,
>+};
>+
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_ABGR2101010:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private
>*dev_priv,
> plane->get_hw_state = vlv_plane_get_hw_state;
> plane->check_plane = vlv_sprite_check;
>
>- formats = vlv_plane_formats;
>- num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>+ formats = chv_pipe_b_sprite_formats;
>+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
>+ } else {
>+ formats = vlv_plane_formats;
>+ num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ }
> modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &vlv_sprite_funcs;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>8bd75eff1266..74bb5a6cbe4f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6545,12 +6545,14 @@ enum {
> #define SP_ENABLE (1 << 31)
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
>-#define SP_FORMAT_YUV422 (0 << 26)
>-#define SP_FORMAT_BGR565 (5 << 26)
>-#define SP_FORMAT_BGRX8888 (6 << 26)
>-#define SP_FORMAT_BGRA8888 (7 << 26)
>-#define SP_FORMAT_RGBX1010102 (8 << 26)
>-#define SP_FORMAT_RGBA1010102 (9 << 26)
>+#define SP_FORMAT_YUV422 (0x0 << 26)
>+#define SP_FORMAT_BGR565 (0x5 << 26)
>+#define SP_FORMAT_BGRX8888 (0x6 << 26)
>+#define SP_FORMAT_BGRA8888 (0x7 << 26)
>+#define SP_FORMAT_RGBX1010102 (0x8 << 26)
>+#define SP_FORMAT_RGBA1010102 (0x9 << 26)
>+#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
>+#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
> #define SP_FORMAT_RGBX8888 (0xe << 26)
> #define SP_FORMAT_RGBA8888 (0xf << 26)
> #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
@ 2019-10-29 11:53 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 11:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B
>sprites on CHV
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
>On VLV and CHV pipe A/C these are only supported by the the primary plane. Add the
Drop the redundant "the".
CHV indeed has this additional capability on pipe B (MPO pipe) sprites.
Overall changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>require bits to expose the new formats.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++----
> 2 files changed, 39 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 90b0e65420a5..fb36da58390a 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ABGR2101010:
> sprctl |= SP_FORMAT_RGBA1010102;
> break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SP_FORMAT_BGRX1010102;
>+ break;
>+ case DRM_FORMAT_ARGB2101010:
>+ sprctl |= SP_FORMAT_BGRA1010102;
>+ break;
> case DRM_FORMAT_XBGR8888:
> sprctl |= SP_FORMAT_RGBX8888;
> break;
>@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
>+static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_ABGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_YUYV,
>+ DRM_FORMAT_YVYU,
>+ DRM_FORMAT_UYVY,
>+ DRM_FORMAT_VYUY,
>+};
>+
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_ABGR2101010:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private
>*dev_priv,
> plane->get_hw_state = vlv_plane_get_hw_state;
> plane->check_plane = vlv_sprite_check;
>
>- formats = vlv_plane_formats;
>- num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>+ formats = chv_pipe_b_sprite_formats;
>+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
>+ } else {
>+ formats = vlv_plane_formats;
>+ num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ }
> modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &vlv_sprite_funcs;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>8bd75eff1266..74bb5a6cbe4f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6545,12 +6545,14 @@ enum {
> #define SP_ENABLE (1 << 31)
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
>-#define SP_FORMAT_YUV422 (0 << 26)
>-#define SP_FORMAT_BGR565 (5 << 26)
>-#define SP_FORMAT_BGRX8888 (6 << 26)
>-#define SP_FORMAT_BGRA8888 (7 << 26)
>-#define SP_FORMAT_RGBX1010102 (8 << 26)
>-#define SP_FORMAT_RGBA1010102 (9 << 26)
>+#define SP_FORMAT_YUV422 (0x0 << 26)
>+#define SP_FORMAT_BGR565 (0x5 << 26)
>+#define SP_FORMAT_BGRX8888 (0x6 << 26)
>+#define SP_FORMAT_BGRA8888 (0x7 << 26)
>+#define SP_FORMAT_RGBX1010102 (0x8 << 26)
>+#define SP_FORMAT_RGBA1010102 (0x9 << 26)
>+#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
>+#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
> #define SP_FORMAT_RGBX8888 (0xe << 26)
> #define SP_FORMAT_RGBA8888 (0xf << 26)
> #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
2019-10-08 16:14 ` [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes Ville Syrjala
2019-10-08 16:14 ` [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-29 10:29 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
` (10 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index fb36da58390a..4cd0982dc8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
case DRM_FORMAT_VYUY:
sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
break;
+ case DRM_FORMAT_C8:
+ sprctl |= SP_FORMAT_8BPP;
+ break;
case DRM_FORMAT_RGB565:
sprctl |= SP_FORMAT_BGR565;
break;
@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = {
};
static const u32 vlv_plane_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = {
};
static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
}
switch (format) {
+ case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_ARGB8888:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74bb5a6cbe4f..577468928ffa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,7 @@ enum {
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK (0xf << 26)
#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_8BPP (0x2 << 26)
#define SP_FORMAT_BGR565 (0x5 << 26)
#define SP_FORMAT_BGRX8888 (0x6 << 26)
#define SP_FORMAT_BGRA8888 (0x7 << 26)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
@ 2019-10-29 10:29 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 10:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>VLV/CHV sprite planes also support the C8 format. Let's expose that.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index fb36da58390a..4cd0982dc8a2 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_VYUY:
> sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> break;
>+ case DRM_FORMAT_C8:
>+ sprctl |= SP_FORMAT_8BPP;
>+ break;
> case DRM_FORMAT_RGB565:
> sprctl |= SP_FORMAT_BGR565;
> break;
>@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = { };
>
> static const u32 vlv_plane_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_ARGB8888,
>@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = { };
>
> static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_ARGB8888,
>@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> }
>
> switch (format) {
>+ case DRM_FORMAT_C8:
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_ABGR8888:
> case DRM_FORMAT_ARGB8888:
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>74bb5a6cbe4f..577468928ffa 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6546,6 +6546,7 @@ enum {
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
> #define SP_FORMAT_YUV422 (0x0 << 26)
>+#define SP_FORMAT_8BPP (0x2 << 26)
> #define SP_FORMAT_BGR565 (0x5 << 26)
> #define SP_FORMAT_BGRX8888 (0x6 << 26)
> #define SP_FORMAT_BGRA8888 (0x7 << 26)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
@ 2019-10-29 10:29 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 10:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>VLV/CHV sprite planes also support the C8 format. Let's expose that.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index fb36da58390a..4cd0982dc8a2 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_VYUY:
> sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> break;
>+ case DRM_FORMAT_C8:
>+ sprctl |= SP_FORMAT_8BPP;
>+ break;
> case DRM_FORMAT_RGB565:
> sprctl |= SP_FORMAT_BGR565;
> break;
>@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = { };
>
> static const u32 vlv_plane_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_ARGB8888,
>@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = { };
>
> static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_ARGB8888,
>@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> }
>
> switch (format) {
>+ case DRM_FORMAT_C8:
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_ABGR8888:
> case DRM_FORMAT_ARGB8888:
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>74bb5a6cbe4f..577468928ffa 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6546,6 +6546,7 @@ enum {
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
> #define SP_FORMAT_YUV422 (0x0 << 26)
>+#define SP_FORMAT_8BPP (0x2 << 26)
> #define SP_FORMAT_BGR565 (0x5 << 26)
> #define SP_FORMAT_BGRX8888 (0x6 << 26)
> #define SP_FORMAT_BGRA8888 (0x7 << 26)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (2 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-09 10:43 ` [PATCH v2 " Ville Syrjala
2019-10-29 20:07 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-08 16:14 ` [PATCH 6/9] drm/i915: Sort format arrays consistently Ville Syrjala
` (9 subsequent siblings)
13 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 4cd0982dc8a2..aaabeaf11ae9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XRGB16161616F,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ARGB16161616F,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
@ 2019-10-09 10:43 ` Ville Syrjala
2019-10-29 12:08 ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:07 ` [Intel-gfx] " Juha-Pekka Heikkila
1 sibling, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-09 10:43 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
v2: Add all the stuff I missed earlier!
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++++++++++
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1cdcd0ea0564..19a0c8cfb151 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3031,10 +3031,17 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_XRGB8888;
}
case PLANE_CTL_FORMAT_XRGB_2101010:
- if (rgb_order)
- return DRM_FORMAT_XBGR2101010;
- else
- return DRM_FORMAT_XRGB2101010;
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR2101010;
+ else
+ return DRM_FORMAT_XBGR2101010;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB2101010;
+ else
+ return DRM_FORMAT_XRGB2101010;
+ }
case PLANE_CTL_FORMAT_XRGB_16161616F:
if (rgb_order) {
if (alpha)
@@ -4024,8 +4031,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_ARGB8888:
return PLANE_CTL_FORMAT_XRGB_8888;
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ABGR2101010:
return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
@@ -5617,6 +5626,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
case DRM_FORMAT_XRGB16161616F:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 4cd0982dc8a2..df3ca75580d7 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XRGB16161616F,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ARGB16161616F,
@@ -2315,6 +2321,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -2367,6 +2375,8 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
@ 2019-10-29 12:08 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 12:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Wednesday, October 9, 2019 4:14 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>ICL+ again supports alpha blending with 10bpc pixel formats.
>Expose them.
>
>v2: Add all the stuff I missed earlier!
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++----
>drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++++++++++
> 2 files changed, 25 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..19a0c8cfb151 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -3031,10 +3031,17 @@ int skl_format_to_fourcc(int format, bool rgb_order,
>bool alpha)
> return DRM_FORMAT_XRGB8888;
> }
> case PLANE_CTL_FORMAT_XRGB_2101010:
>- if (rgb_order)
>- return DRM_FORMAT_XBGR2101010;
>- else
>- return DRM_FORMAT_XRGB2101010;
>+ if (rgb_order) {
>+ if (alpha)
>+ return DRM_FORMAT_ABGR2101010;
>+ else
>+ return DRM_FORMAT_XBGR2101010;
>+ } else {
>+ if (alpha)
>+ return DRM_FORMAT_ARGB2101010;
>+ else
>+ return DRM_FORMAT_XRGB2101010;
>+ }
> case PLANE_CTL_FORMAT_XRGB_16161616F:
> if (rgb_order) {
> if (alpha)
>@@ -4024,8 +4031,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_ARGB8888:
> return PLANE_CTL_FORMAT_XRGB_8888;
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010 |
>PLANE_CTL_ORDER_RGBX;
> case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
>@@ -5617,6 +5626,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ARGB8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
> case DRM_FORMAT_XRGB16161616F:
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 4cd0982dc8a2..df3ca75580d7 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>@@ -2315,6 +2321,8 @@ static bool skl_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2367,6 +2375,8 @@ static bool gen12_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
@ 2019-10-29 12:08 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 12:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Wednesday, October 9, 2019 4:14 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>ICL+ again supports alpha blending with 10bpc pixel formats.
>Expose them.
>
>v2: Add all the stuff I missed earlier!
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++----
>drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++++++++++
> 2 files changed, 25 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..19a0c8cfb151 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -3031,10 +3031,17 @@ int skl_format_to_fourcc(int format, bool rgb_order,
>bool alpha)
> return DRM_FORMAT_XRGB8888;
> }
> case PLANE_CTL_FORMAT_XRGB_2101010:
>- if (rgb_order)
>- return DRM_FORMAT_XBGR2101010;
>- else
>- return DRM_FORMAT_XRGB2101010;
>+ if (rgb_order) {
>+ if (alpha)
>+ return DRM_FORMAT_ABGR2101010;
>+ else
>+ return DRM_FORMAT_XBGR2101010;
>+ } else {
>+ if (alpha)
>+ return DRM_FORMAT_ARGB2101010;
>+ else
>+ return DRM_FORMAT_XRGB2101010;
>+ }
> case PLANE_CTL_FORMAT_XRGB_16161616F:
> if (rgb_order) {
> if (alpha)
>@@ -4024,8 +4031,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_ARGB8888:
> return PLANE_CTL_FORMAT_XRGB_8888;
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010 |
>PLANE_CTL_ORDER_RGBX;
> case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
>@@ -5617,6 +5626,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ARGB8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
> case DRM_FORMAT_XRGB16161616F:
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 4cd0982dc8a2..df3ca75580d7 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>@@ -2315,6 +2321,8 @@ static bool skl_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2367,6 +2375,8 @@ static bool gen12_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+
@ 2019-10-29 20:07 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-29 20:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL+ again supports alpha blending with 10bpc pixel formats.
> Expose them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 4cd0982dc8a2..aaabeaf11ae9 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+
@ 2019-10-29 20:07 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-29 20:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL+ again supports alpha blending with 10bpc pixel formats.
> Expose them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 4cd0982dc8a2..aaabeaf11ae9 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 6/9] drm/i915: Sort format arrays consistently
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (3 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 5/9] drm/i915: Add 10bpc formats with alpha for icl+ Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-27 20:53 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 12:10 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+ Ville Syrjala
` (8 subsequent siblings)
13 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1cdcd0ea0564..a8124f01bdb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -83,8 +83,8 @@
/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_C8,
- DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
};
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index aaabeaf11ae9..cc9e5c9668b1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
};
static const u32 snb_plane_formats[] = {
- DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
- DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR8888,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = {
static const u32 vlv_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
@@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = {
static const u32 chv_pipe_b_sprite_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
- DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 6/9] drm/i915: Sort format arrays consistently
@ 2019-10-27 20:53 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-27 20:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's try to keep the pixel format arrays somewhat sorted:
> 1. RGB before YUV
> 2. smaller bpp before larger bpp
> 3. X before A
> 4. RGB before BGR
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++++++++++----------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1cdcd0ea0564..a8124f01bdb2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -83,8 +83,8 @@
> /* Primary plane formats for gen <= 3 */
> static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
> - DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
> + DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index aaabeaf11ae9..cc9e5c9668b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
> };
>
> static const u32 snb_plane_formats[] = {
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = {
> static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> - DRM_FORMAT_ABGR8888,
> - DRM_FORMAT_ARGB8888,
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> @@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = {
> static const u32 chv_pipe_b_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> - DRM_FORMAT_ABGR8888,
> - DRM_FORMAT_ARGB8888,
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_XBGR2101010,
> - DRM_FORMAT_ABGR2101010,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
@ 2019-10-27 20:53 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-27 20:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's try to keep the pixel format arrays somewhat sorted:
> 1. RGB before YUV
> 2. smaller bpp before larger bpp
> 3. X before A
> 4. RGB before BGR
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++++++++++----------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1cdcd0ea0564..a8124f01bdb2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -83,8 +83,8 @@
> /* Primary plane formats for gen <= 3 */
> static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
> - DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
> + DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index aaabeaf11ae9..cc9e5c9668b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
> };
>
> static const u32 snb_plane_formats[] = {
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = {
> static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> - DRM_FORMAT_ABGR8888,
> - DRM_FORMAT_ARGB8888,
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> @@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = {
> static const u32 chv_pipe_b_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> - DRM_FORMAT_ABGR8888,
> - DRM_FORMAT_ARGB8888,
> - DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_XBGR2101010,
> - DRM_FORMAT_ABGR2101010,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ARGB2101010,
> + DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/9] drm/i915: Sort format arrays consistently
@ 2019-10-29 12:10 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 12:10 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's try to keep the pixel format arrays somewhat sorted:
>1. RGB before YUV
>2. smaller bpp before larger bpp
>3. X before A
>4. RGB before BGR
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++++++++++----------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..a8124f01bdb2 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -83,8 +83,8 @@
> /* Primary plane formats for gen <= 3 */ static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
>- DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
>+ DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> };
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index aaabeaf11ae9..cc9e5c9668b1 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = { };
>
> static const u32 snb_plane_formats[] = {
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>- DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = { static const
>u32 vlv_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR8888,
>- DRM_FORMAT_ARGB8888,
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
>@@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = { static const u32
>chv_pipe_b_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR8888,
>- DRM_FORMAT_ARGB8888,
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>- DRM_FORMAT_XBGR2101010,
>- DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
@ 2019-10-29 12:10 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 12:10 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's try to keep the pixel format arrays somewhat sorted:
>1. RGB before YUV
>2. smaller bpp before larger bpp
>3. X before A
>4. RGB before BGR
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++++++++++----------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..a8124f01bdb2 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -83,8 +83,8 @@
> /* Primary plane formats for gen <= 3 */ static const u32 i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
>- DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
>+ DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> };
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index aaabeaf11ae9..cc9e5c9668b1 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = { };
>
> static const u32 snb_plane_formats[] = {
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>- DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = { static const
>u32 vlv_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR8888,
>- DRM_FORMAT_ARGB8888,
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
>@@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = { static const u32
>chv_pipe_b_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR8888,
>- DRM_FORMAT_ARGB8888,
>- DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>- DRM_FORMAT_XBGR2101010,
>- DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XBGR8888,
>+ DRM_FORMAT_ARGB8888,
>+ DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (4 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 6/9] drm/i915: Sort format arrays consistently Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-29 13:07 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active Ville Syrjala
` (7 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
According to the spec color keying is not supported with
fp16 pixel formats on skl+. Reject that combo.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cc9e5c9668b1..d6cd46e3f738 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+static bool format_is_fp16(u32 format)
+{
+ switch (format) {
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
+ DRM_DEBUG_KMS("Color keying not supported with fp16 formats\n");
+ return -EINVAL;
+ }
+
return 0;
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 13:07 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>According to the spec color keying is not supported with
>fp16 pixel formats on skl+. Reject that combo.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index cc9e5c9668b1..d6cd46e3f738 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
>+static bool format_is_fp16(u32 format)
>+{
>+ switch (format) {
>+ case DRM_FORMAT_XRGB16161616F:
>+ case DRM_FORMAT_XBGR16161616F:
>+ case DRM_FORMAT_ARGB16161616F:
>+ case DRM_FORMAT_ABGR16161616F:
>+ return true;
>+ default:
>+ return false;
>+ }
>+}
>+
> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state) { @@ -
>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct intel_crtc_state
>*crtc_state,
> return -EINVAL;
> }
>
>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>formats\n");
It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you can extend it to
even C8.
>+ return -EINVAL;
>+ }
>+
> return 0;
> }
>
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 13:07 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>According to the spec color keying is not supported with
>fp16 pixel formats on skl+. Reject that combo.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index cc9e5c9668b1..d6cd46e3f738 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
>+static bool format_is_fp16(u32 format)
>+{
>+ switch (format) {
>+ case DRM_FORMAT_XRGB16161616F:
>+ case DRM_FORMAT_XBGR16161616F:
>+ case DRM_FORMAT_ARGB16161616F:
>+ case DRM_FORMAT_ABGR16161616F:
>+ return true;
>+ default:
>+ return false;
>+ }
>+}
>+
> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state) { @@ -
>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct intel_crtc_state
>*crtc_state,
> return -EINVAL;
> }
>
>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>formats\n");
It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you can extend it to
even C8.
>+ return -EINVAL;
>+ }
>+
> return 0;
> }
>
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 13:35 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:35 UTC (permalink / raw)
To: 'Ville Syrjala', 'intel-gfx@lists.freedesktop.org'
>-----Original Message-----
>From: Shankar, Uma
>Sent: Tuesday, October 29, 2019 6:38 PM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>
>
>>-----Original Message-----
>>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
>>Ville Syrjala
>>Sent: Tuesday, October 8, 2019 9:45 PM
>>To: intel-gfx@lists.freedesktop.org
>>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>>
>>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>According to the spec color keying is not supported with
>>fp16 pixel formats on skl+. Reject that combo.
>>
>>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>>b/drivers/gpu/drm/i915/display/intel_sprite.c
>>index cc9e5c9668b1..d6cd46e3f738 100644
>>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>> return 0;
>> }
>>
>>+static bool format_is_fp16(u32 format) {
>>+ switch (format) {
>>+ case DRM_FORMAT_XRGB16161616F:
>>+ case DRM_FORMAT_XBGR16161616F:
>>+ case DRM_FORMAT_ARGB16161616F:
>>+ case DRM_FORMAT_ABGR16161616F:
>>+ return true;
>>+ default:
>>+ return false;
>>+ }
>>+}
>>+
>> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state) { @@ -
>>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
>>intel_crtc_state *crtc_state,
>> return -EINVAL;
>> }
>>
>>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>>formats\n");
>
>It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you
>can extend it to even C8.
wrt C8, at the bit definition of color keying on PLANE_CTL the description says
"Plane color keying is not compatible with the Indexed 8-bit pixel format.",
but on capability it do list C8. So not sure what is correct.
>
>>+ return -EINVAL;
>>+ }
>>+
>> return 0;
>> }
>>
>>--
>>2.21.0
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 13:35 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:35 UTC (permalink / raw)
To: 'Ville Syrjala', 'intel-gfx@lists.freedesktop.org'
>-----Original Message-----
>From: Shankar, Uma
>Sent: Tuesday, October 29, 2019 6:38 PM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>
>
>>-----Original Message-----
>>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
>>Ville Syrjala
>>Sent: Tuesday, October 8, 2019 9:45 PM
>>To: intel-gfx@lists.freedesktop.org
>>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>>
>>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>According to the spec color keying is not supported with
>>fp16 pixel formats on skl+. Reject that combo.
>>
>>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>>b/drivers/gpu/drm/i915/display/intel_sprite.c
>>index cc9e5c9668b1..d6cd46e3f738 100644
>>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>> return 0;
>> }
>>
>>+static bool format_is_fp16(u32 format) {
>>+ switch (format) {
>>+ case DRM_FORMAT_XRGB16161616F:
>>+ case DRM_FORMAT_XBGR16161616F:
>>+ case DRM_FORMAT_ARGB16161616F:
>>+ case DRM_FORMAT_ABGR16161616F:
>>+ return true;
>>+ default:
>>+ return false;
>>+ }
>>+}
>>+
>> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state) { @@ -
>>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
>>intel_crtc_state *crtc_state,
>> return -EINVAL;
>> }
>>
>>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>>formats\n");
>
>It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you
>can extend it to even C8.
wrt C8, at the bit definition of color keying on PLANE_CTL the description says
"Plane color keying is not compatible with the Indexed 8-bit pixel format.",
but on capability it do list C8. So not sure what is correct.
>
>>+ return -EINVAL;
>>+ }
>>+
>> return 0;
>> }
>>
>>--
>>2.21.0
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 15:22 ` Ville Syrjälä
0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-10-29 15:22 UTC (permalink / raw)
To: Shankar, Uma; +Cc: 'intel-gfx@lists.freedesktop.org'
On Tue, Oct 29, 2019 at 01:35:57PM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Shankar, Uma
> >Sent: Tuesday, October 29, 2019 6:38 PM
> >To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
> >Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
> >
> >
> >
> >>-----Original Message-----
> >>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> >>Ville Syrjala
> >>Sent: Tuesday, October 8, 2019 9:45 PM
> >>To: intel-gfx@lists.freedesktop.org
> >>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
> >>
> >>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >>According to the spec color keying is not supported with
> >>fp16 pixel formats on skl+. Reject that combo.
> >>
> >>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>---
> >> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
> >> 1 file changed, 18 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> >>b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>index cc9e5c9668b1..d6cd46e3f738 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> >> return 0;
> >> }
> >>
> >>+static bool format_is_fp16(u32 format) {
> >>+ switch (format) {
> >>+ case DRM_FORMAT_XRGB16161616F:
> >>+ case DRM_FORMAT_XBGR16161616F:
> >>+ case DRM_FORMAT_ARGB16161616F:
> >>+ case DRM_FORMAT_ABGR16161616F:
> >>+ return true;
> >>+ default:
> >>+ return false;
> >>+ }
> >>+}
> >>+
> >> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >> const struct intel_plane_state *plane_state) { @@ -
> >>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
> >>intel_crtc_state *crtc_state,
> >> return -EINVAL;
> >> }
> >>
> >>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
> >>+ DRM_DEBUG_KMS("Color keying not supported with fp16
> >>formats\n");
> >
> >It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you
> >can extend it to even C8.
>
> wrt C8, at the bit definition of color keying on PLANE_CTL the description says
> "Plane color keying is not compatible with the Indexed 8-bit pixel format.",
> but on capability it do list C8. So not sure what is correct.
It works just fine, or at least it did on older platforms.
So unless they broke it recently we should be good.
Regarding fp16 vs. colorkey, not sure what the deal really is.
I should probably test it across the board now that we have
fp16 for all gen4+.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-29 15:22 ` Ville Syrjälä
0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-10-29 15:22 UTC (permalink / raw)
To: Shankar, Uma; +Cc: 'intel-gfx@lists.freedesktop.org'
On Tue, Oct 29, 2019 at 01:35:57PM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Shankar, Uma
> >Sent: Tuesday, October 29, 2019 6:38 PM
> >To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
> >Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
> >
> >
> >
> >>-----Original Message-----
> >>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> >>Ville Syrjala
> >>Sent: Tuesday, October 8, 2019 9:45 PM
> >>To: intel-gfx@lists.freedesktop.org
> >>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
> >>
> >>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >>According to the spec color keying is not supported with
> >>fp16 pixel formats on skl+. Reject that combo.
> >>
> >>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>---
> >> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
> >> 1 file changed, 18 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> >>b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>index cc9e5c9668b1..d6cd46e3f738 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> >>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> >> return 0;
> >> }
> >>
> >>+static bool format_is_fp16(u32 format) {
> >>+ switch (format) {
> >>+ case DRM_FORMAT_XRGB16161616F:
> >>+ case DRM_FORMAT_XBGR16161616F:
> >>+ case DRM_FORMAT_ARGB16161616F:
> >>+ case DRM_FORMAT_ABGR16161616F:
> >>+ return true;
> >>+ default:
> >>+ return false;
> >>+ }
> >>+}
> >>+
> >> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >> const struct intel_plane_state *plane_state) { @@ -
> >>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
> >>intel_crtc_state *crtc_state,
> >> return -EINVAL;
> >> }
> >>
> >>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
> >>+ DRM_DEBUG_KMS("Color keying not supported with fp16
> >>formats\n");
> >
> >It seems even "Indexed 8 bit formats" also don't support Color Keying. May be you
> >can extend it to even C8.
>
> wrt C8, at the bit definition of color keying on PLANE_CTL the description says
> "Plane color keying is not compatible with the Indexed 8-bit pixel format.",
> but on capability it do list C8. So not sure what is correct.
It works just fine, or at least it did on older platforms.
So unless they broke it recently we should be good.
Regarding fp16 vs. colorkey, not sure what the deal really is.
I should probably test it across the board now that we have
fp16 for all gen4+.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-30 15:26 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-30 15:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: 'intel-gfx@lists.freedesktop.org'
>> >>-----Original Message-----
>> >>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
>> >>Of Ville Syrjala
>> >>Sent: Tuesday, October 8, 2019 9:45 PM
>> >>To: intel-gfx@lists.freedesktop.org
>> >>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>> >>
>> >>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>
>> >>According to the spec color keying is not supported with
>> >>fp16 pixel formats on skl+. Reject that combo.
>> >>
>> >>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>---
>> >> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
>> >> 1 file changed, 18 insertions(+)
>> >>
>> >>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>index cc9e5c9668b1..d6cd46e3f738 100644
>> >>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>> >> return 0;
>> >> }
>> >>
>> >>+static bool format_is_fp16(u32 format) {
>> >>+ switch (format) {
>> >>+ case DRM_FORMAT_XRGB16161616F:
>> >>+ case DRM_FORMAT_XBGR16161616F:
>> >>+ case DRM_FORMAT_ARGB16161616F:
>> >>+ case DRM_FORMAT_ABGR16161616F:
>> >>+ return true;
>> >>+ default:
>> >>+ return false;
>> >>+ }
>> >>+}
>> >>+
>> >> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> >> const struct intel_plane_state *plane_state) { @@ -
>> >>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
>> >>intel_crtc_state *crtc_state,
>> >> return -EINVAL;
>> >> }
>> >>
>> >>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>> >>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>> >>formats\n");
>> >
>> >It seems even "Indexed 8 bit formats" also don't support Color
>> >Keying. May be you can extend it to even C8.
>>
>> wrt C8, at the bit definition of color keying on PLANE_CTL the
>> description says "Plane color keying is not compatible with the
>> Indexed 8-bit pixel format.", but on capability it do list C8. So not sure what is
>correct.
>
>It works just fine, or at least it did on older platforms.
>So unless they broke it recently we should be good.
Ok, yeah that description was misleading. Will try to get some clarification from
hardware folks as well.
>Regarding fp16 vs. colorkey, not sure what the deal really is.
>I should probably test it across the board now that we have
>fp16 for all gen4+.
That would be great and will confirm the behaviour.
Regards,
Uma Shankar
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
@ 2019-10-30 15:26 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-30 15:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: 'intel-gfx@lists.freedesktop.org'
>> >>-----Original Message-----
>> >>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
>> >>Of Ville Syrjala
>> >>Sent: Tuesday, October 8, 2019 9:45 PM
>> >>To: intel-gfx@lists.freedesktop.org
>> >>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>> >>
>> >>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>
>> >>According to the spec color keying is not supported with
>> >>fp16 pixel formats on skl+. Reject that combo.
>> >>
>> >>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>---
>> >> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++++++++++++++++++
>> >> 1 file changed, 18 insertions(+)
>> >>
>> >>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>index cc9e5c9668b1..d6cd46e3f738 100644
>> >>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> >>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>> >> return 0;
>> >> }
>> >>
>> >>+static bool format_is_fp16(u32 format) {
>> >>+ switch (format) {
>> >>+ case DRM_FORMAT_XRGB16161616F:
>> >>+ case DRM_FORMAT_XBGR16161616F:
>> >>+ case DRM_FORMAT_ARGB16161616F:
>> >>+ case DRM_FORMAT_ABGR16161616F:
>> >>+ return true;
>> >>+ default:
>> >>+ return false;
>> >>+ }
>> >>+}
>> >>+
>> >> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> >> const struct intel_plane_state *plane_state) { @@ -
>> >>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
>> >>intel_crtc_state *crtc_state,
>> >> return -EINVAL;
>> >> }
>> >>
>> >>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>> >>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>> >>formats\n");
>> >
>> >It seems even "Indexed 8 bit formats" also don't support Color
>> >Keying. May be you can extend it to even C8.
>>
>> wrt C8, at the bit definition of color keying on PLANE_CTL the
>> description says "Plane color keying is not compatible with the
>> Indexed 8-bit pixel format.", but on capability it do list C8. So not sure what is
>correct.
>
>It works just fine, or at least it did on older platforms.
>So unless they broke it recently we should be good.
Ok, yeah that description was misleading. Will try to get some clarification from
hardware folks as well.
>Regarding fp16 vs. colorkey, not sure what the deal really is.
>I should probably test it across the board now that we have
>fp16 for all gen4+.
That would be great and will confirm the behaviour.
Regards,
Uma Shankar
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (5 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+ Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-29 13:22 ` [Intel-gfx] " Shankar, Uma
2019-10-08 16:14 ` [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create() Ville Syrjala
` (6 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The spec says that color keying and HDR mode are mutually exclusive.
So let's not enable HDR mode when color keying is active.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++++
drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 98b7766eaa7a..f64204f6f37f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
+ new_crtc_state->ckey_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
new_plane_state->base.visible = false;
@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
+ if (new_plane_state->base.visible &&
+ new_plane_state->ckey.flags)
+ new_crtc_state->ckey_planes |= BIT(plane->id);
+
if (new_plane_state->base.visible || old_plane_state->base.visible)
new_crtc_state->update_planes |= BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8124f01bdb2..c553a3417891 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
POSTING_READ(PIPECONF(cpu_transcoder));
}
+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
+{
+ u8 ckey_planes = crtc_state->ckey_planes;
+ u8 sdr_planes = crtc_state->active_planes &
+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
+
+ return !ckey_planes && !sdr_planes;
+}
+
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
val |= PIPEMISC_YUV420_ENABLE |
PIPEMISC_YUV420_MODE_FULL_BLEND;
- if (INTEL_GEN(dev_priv) >= 11 &&
- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
- BIT(PLANE_CURSOR))) == 0)
+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
val |= PIPEMISC_HDR_MODE_PRECISION;
I915_WRITE(PIPEMISC(crtc->pipe), val);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..4935ea41d3e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -949,6 +949,7 @@ struct intel_crtc_state {
u8 active_planes;
u8 nv12_planes;
u8 c8_planes;
+ u8 ckey_planes;
/* bitmask of planes that will be updated during the commit */
u8 update_planes;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
@ 2019-10-29 13:22 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color
>keying is active
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The spec says that color keying and HDR mode are mutually exclusive.
>So let's not enable HDR mode when color keying is active.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> 3 files changed, 16 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>index 98b7766eaa7a..f64204f6f37f 100644
>--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> new_crtc_state->c8_planes &= ~BIT(plane->id);
>+ new_crtc_state->ckey_planes &= ~BIT(plane->id);
> new_crtc_state->data_rate[plane->id] = 0;
> new_plane_state->base.visible = false;
>
>@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> fb->format->format == DRM_FORMAT_C8)
> new_crtc_state->c8_planes |= BIT(plane->id);
>
>+ if (new_plane_state->base.visible &&
>+ new_plane_state->ckey.flags)
>+ new_crtc_state->ckey_planes |= BIT(plane->id);
>+
> if (new_plane_state->base.visible || old_plane_state->base.visible)
> new_crtc_state->update_planes |= BIT(plane->id);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index a8124f01bdb2..c553a3417891 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct
>intel_crtc_state *crtc_state)
> POSTING_READ(PIPECONF(cpu_transcoder));
> }
>
>+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
>+{
>+ u8 ckey_planes = crtc_state->ckey_planes;
>+ u8 sdr_planes = crtc_state->active_planes &
>+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
>+
>+ return !ckey_planes && !sdr_planes;
>+}
>+
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state
>*crtc_state)
> val |= PIPEMISC_YUV420_ENABLE |
> PIPEMISC_YUV420_MODE_FULL_BLEND;
>
>- if (INTEL_GEN(dev_priv) >= 11 &&
>- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
>- BIT(PLANE_CURSOR))) == 0)
>+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
> val |= PIPEMISC_HDR_MODE_PRECISION;
>
> I915_WRITE(PIPEMISC(crtc->pipe), val); diff --git
>a/drivers/gpu/drm/i915/display/intel_display_types.h
>b/drivers/gpu/drm/i915/display/intel_display_types.h
>index 40390d855815..4935ea41d3e1 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_types.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>@@ -949,6 +949,7 @@ struct intel_crtc_state {
> u8 active_planes;
> u8 nv12_planes;
> u8 c8_planes;
>+ u8 ckey_planes;
>
> /* bitmask of planes that will be updated during the commit */
> u8 update_planes;
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
@ 2019-10-29 13:22 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color
>keying is active
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The spec says that color keying and HDR mode are mutually exclusive.
>So let's not enable HDR mode when color keying is active.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> 3 files changed, 16 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>index 98b7766eaa7a..f64204f6f37f 100644
>--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> new_crtc_state->c8_planes &= ~BIT(plane->id);
>+ new_crtc_state->ckey_planes &= ~BIT(plane->id);
> new_crtc_state->data_rate[plane->id] = 0;
> new_plane_state->base.visible = false;
>
>@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> fb->format->format == DRM_FORMAT_C8)
> new_crtc_state->c8_planes |= BIT(plane->id);
>
>+ if (new_plane_state->base.visible &&
>+ new_plane_state->ckey.flags)
>+ new_crtc_state->ckey_planes |= BIT(plane->id);
>+
> if (new_plane_state->base.visible || old_plane_state->base.visible)
> new_crtc_state->update_planes |= BIT(plane->id);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index a8124f01bdb2..c553a3417891 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct
>intel_crtc_state *crtc_state)
> POSTING_READ(PIPECONF(cpu_transcoder));
> }
>
>+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
>+{
>+ u8 ckey_planes = crtc_state->ckey_planes;
>+ u8 sdr_planes = crtc_state->active_planes &
>+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
>+
>+ return !ckey_planes && !sdr_planes;
>+}
>+
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state
>*crtc_state)
> val |= PIPEMISC_YUV420_ENABLE |
> PIPEMISC_YUV420_MODE_FULL_BLEND;
>
>- if (INTEL_GEN(dev_priv) >= 11 &&
>- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
>- BIT(PLANE_CURSOR))) == 0)
>+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
> val |= PIPEMISC_HDR_MODE_PRECISION;
>
> I915_WRITE(PIPEMISC(crtc->pipe), val); diff --git
>a/drivers/gpu/drm/i915/display/intel_display_types.h
>b/drivers/gpu/drm/i915/display/intel_display_types.h
>index 40390d855815..4935ea41d3e1 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_types.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>@@ -949,6 +949,7 @@ struct intel_crtc_state {
> u8 active_planes;
> u8 nv12_planes;
> u8 c8_planes;
>+ u8 ckey_planes;
>
> /* bitmask of planes that will be updated during the commit */
> u8 update_planes;
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (6 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active Ville Syrjala
@ 2019-10-08 16:14 ` Ville Syrjala
2019-10-27 20:53 ` [Intel-gfx] " Juha-Pekka Heikkila
2019-10-29 13:24 ` [Intel-gfx] " Shankar, Uma
2019-10-08 18:24 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Patchwork
` (5 subsequent siblings)
13 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-10-08 16:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 43 +++++++-------------
1 file changed, 14 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c553a3417891..2acec838fb8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
unsigned int possible_crtcs;
- const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
formats = vlv_primary_formats;
num_formats = ARRAY_SIZE(vlv_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
-
- plane_funcs = &i965_plane_funcs;
} else if (INTEL_GEN(dev_priv) >= 4) {
formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
-
- plane_funcs = &i965_plane_funcs;
} else {
formats = i8xx_primary_formats;
num_formats = ARRAY_SIZE(i8xx_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
+ }
+ if (INTEL_GEN(dev_priv) >= 4)
+ plane_funcs = &i965_plane_funcs;
+ else
plane_funcs = &i8xx_plane_funcs;
- }
+
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+ plane->get_hw_state = i9xx_plane_get_hw_state;
+ plane->check_plane = i9xx_plane_check;
possible_crtcs = BIT(pipe);
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+ formats, num_formats,
+ i9xx_format_modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+ formats, num_formats,
+ i9xx_format_modifiers,
DRM_PLANE_TYPE_PRIMARY,
"plane %c",
plane_name(plane->i9xx_plane));
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
@ 2019-10-27 20:53 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-27 20:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Lots of redundant assignments inside intel_primary_plane_create().
> Get rid of them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 43 +++++++-------------
> 1 file changed, 14 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c553a3417891..2acec838fb8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> unsigned int possible_crtcs;
> - const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
> @@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> num_formats = ARRAY_SIZE(vlv_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> -
> - plane_funcs = &i965_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> -
> - plane_funcs = &i965_plane_funcs;
> } else {
> formats = i8xx_primary_formats;
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> + }
>
> + if (INTEL_GEN(dev_priv) >= 4)
> + plane_funcs = &i965_plane_funcs;
> + else
> plane_funcs = &i8xx_plane_funcs;
> - }
> +
> + plane->max_stride = i9xx_plane_max_stride;
> + plane->update_plane = i9xx_update_plane;
> + plane->disable_plane = i9xx_disable_plane;
> + plane->get_hw_state = i9xx_plane_get_hw_state;
> + plane->check_plane = i9xx_plane_check;
>
> possible_crtcs = BIT(pipe);
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
> - formats, num_formats, modifiers,
> + formats, num_formats,
> + i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
> - formats, num_formats, modifiers,
> + formats, num_formats,
> + i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
@ 2019-10-27 20:53 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-27 20:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Lots of redundant assignments inside intel_primary_plane_create().
> Get rid of them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 43 +++++++-------------
> 1 file changed, 14 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c553a3417891..2acec838fb8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> unsigned int possible_crtcs;
> - const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
> @@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> num_formats = ARRAY_SIZE(vlv_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> -
> - plane_funcs = &i965_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> -
> - plane_funcs = &i965_plane_funcs;
> } else {
> formats = i8xx_primary_formats;
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
> - modifiers = i9xx_format_modifiers;
> -
> - plane->max_stride = i9xx_plane_max_stride;
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> - plane->get_hw_state = i9xx_plane_get_hw_state;
> - plane->check_plane = i9xx_plane_check;
> + }
>
> + if (INTEL_GEN(dev_priv) >= 4)
> + plane_funcs = &i965_plane_funcs;
> + else
> plane_funcs = &i8xx_plane_funcs;
> - }
> +
> + plane->max_stride = i9xx_plane_max_stride;
> + plane->update_plane = i9xx_update_plane;
> + plane->disable_plane = i9xx_disable_plane;
> + plane->get_hw_state = i9xx_plane_get_hw_state;
> + plane->check_plane = i9xx_plane_check;
>
> possible_crtcs = BIT(pipe);
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
> - formats, num_formats, modifiers,
> + formats, num_formats,
> + i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
> - formats, num_formats, modifiers,
> + formats, num_formats,
> + i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
@ 2019-10-29 13:24 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:24 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in
>intel_primary_plane_create()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Lots of redundant assignments inside intel_primary_plane_create().
>Get rid of them.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 43 +++++++-------------
> 1 file changed, 14 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index c553a3417891..2acec838fb8e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> unsigned int possible_crtcs;
>- const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
>@@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> num_formats = ARRAY_SIZE(vlv_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else {
> formats = i8xx_primary_formats;
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>+ }
>
>+ if (INTEL_GEN(dev_priv) >= 4)
>+ plane_funcs = &i965_plane_funcs;
>+ else
> plane_funcs = &i8xx_plane_funcs;
>- }
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disable_plane = i9xx_disable_plane;
>+ plane->get_hw_state = i9xx_plane_get_hw_state;
>+ plane->check_plane = i9xx_plane_check;
>
> possible_crtcs = BIT(pipe);
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
@ 2019-10-29 13:24 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 13:24 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in
>intel_primary_plane_create()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Lots of redundant assignments inside intel_primary_plane_create().
>Get rid of them.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 43 +++++++-------------
> 1 file changed, 14 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index c553a3417891..2acec838fb8e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> unsigned int possible_crtcs;
>- const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
>@@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> num_formats = ARRAY_SIZE(vlv_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else {
> formats = i8xx_primary_formats;
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>+ }
>
>+ if (INTEL_GEN(dev_priv) >= 4)
>+ plane_funcs = &i965_plane_funcs;
>+ else
> plane_funcs = &i8xx_plane_funcs;
>- }
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disable_plane = i9xx_disable_plane;
>+ plane->get_hw_state = i9xx_plane_get_hw_state;
>+ plane->check_plane = i9xx_plane_check;
>
> possible_crtcs = BIT(pipe);
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (7 preceding siblings ...)
2019-10-08 16:14 ` [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create() Ville Syrjala
@ 2019-10-08 18:24 ` Patchwork
2019-10-09 0:55 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-10-08 18:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
URL : https://patchwork.freedesktop.org/series/67741/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7035 -> Patchwork_14705
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/index.html
Known issues
------------
Here are the changes found in Patchwork_14705 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-cml-u2/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-cml-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111747]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (51 -> 45)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7035 -> Patchwork_14705
CI-20190529: 20190529
CI_DRM_7035: 6256c298ba41f295206104fb6eaa067dde46a4d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5218: 869ed1ee0b71ce17f0a864512488f8b1a6cb8545 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14705: cca2b959c9a9dd108b59504b3cceed096c61d162 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cca2b959c9a9 drm/i915: Eliminate redundancy in intel_primary_plane_create()
709d12b04c69 drm/i915: Do not enable HDR mode when color keying is active
ce206c719838 drm/i915: Reject ckey+fp16 on skl+
5c3dbeb08683 drm/i915: Sort format arrays consistently
13c5f2cb6cb3 drm/i915: Add 10bpc formats with alpha for icl+
966514314aea drm/i915: Expose C8 on VLV/CHV sprite planes
5030b840ef0b drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
0e88079e0ae0 drm/i915: Expose alpha formats on VLV/CHV primary planes
c4acf9d20614 drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (8 preceding siblings ...)
2019-10-08 18:24 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Patchwork
@ 2019-10-09 0:55 ` Patchwork
2019-10-09 15:45 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2) Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-10-09 0:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
URL : https://patchwork.freedesktop.org/series/67741/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7035_full -> Patchwork_14705_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14705_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14705_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14705_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb6/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-iclb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb7/igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- {shard-tglb}: [PASS][4] -> [INCOMPLETE][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- {shard-tglb}: NOTRUN -> [FAIL][6] +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb7/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- {shard-tglb}: NOTRUN -> [SKIP][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
Known issues
------------
Here are the changes found in Patchwork_14705_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_balancer@smoke.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-apl: [PASS][12] -> [INCOMPLETE][13] ([fdo#103927])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@gem_exec_flush@basic-wb-pro-default.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([fdo#103558] / [fdo#105602]) +30 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#103558] / [fdo#105602] / [fdo#108566])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103167]) +6 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109441]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][26] -> [FAIL][27] ([fdo#99912])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl3/igt@kms_setmode@basic.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-iclb: [PASS][28] -> [INCOMPLETE][29] ([fdo#107713])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb3/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb1/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109276]) +25 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@prime_busy@hang-bsd2.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb5/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][32] ([fdo#110841]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [FAIL][34] ([fdo#111925]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb5/igt@gem_eio@in-flight-contexts-immediate.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-snb1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [FAIL][36] ([fdo#109661]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb2/igt@gem_eio@unwedge-stress.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][38] ([fdo#111325]) -> [PASS][39] +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][40] ([fdo#109276]) -> [PASS][41] +16 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [DMESG-WARN][42] ([fdo#111870]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html
- shard-hsw: [DMESG-WARN][44] ([fdo#111870]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-hsw1/igt@gem_userptr_blits@dmabuf-sync.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-hsw4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [INCOMPLETE][46] ([fdo#104108] / [fdo#107807]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl10/igt@i915_pm_rpm@system-suspend-execbuf.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live_coherency:
- shard-skl: [TIMEOUT][48] -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl2/igt@i915_selftest@live_coherency.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl3/igt@i915_selftest@live_coherency.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [FAIL][50] ([fdo#102670]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-glk: [FAIL][52] ([fdo#100368]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][54] ([fdo#105363]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][56] ([fdo#103540]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [FAIL][58] ([fdo#100368]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_flip_tiling@flip-to-y-tiled:
- shard-skl: [FAIL][60] ([fdo#107931] / [fdo#108134]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl9/igt@kms_flip_tiling@flip-to-y-tiled.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl8/igt@kms_flip_tiling@flip-to-y-tiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][62] ([fdo#103167]) -> [PASS][63] +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-tglb}: [FAIL][64] ([fdo#103167]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
- shard-skl: [FAIL][66] ([fdo#103191]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl9/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [INCOMPLETE][68] ([fdo#104108]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][70] ([fdo#108145]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][72] ([fdo#108145] / [fdo#110403]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][74] ([fdo#109441]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][76] ([fdo#99912]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-kbl6/igt@kms_setmode@basic.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-kbl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- {shard-tglb}: [INCOMPLETE][78] -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb6/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-tglb5/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][80] ([fdo#108566]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [FAIL][82] ([fdo#110728]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-skl5/igt@perf@polling.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-skl2/igt@perf@polling.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][84] ([fdo#109276]) -> [FAIL][85] ([fdo#111329])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][86] ([fdo#111330]) -> [SKIP][87] ([fdo#109276])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb5/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][88] ([fdo#109276]) -> [FAIL][89] ([fdo#111330])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-apl: [SKIP][90] ([fdo#109271]) -> [SKIP][91] ([fdo#105602] / [fdo#109271]) +23 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_busy@extended-modeset-hang-newfb-render-e:
- shard-apl: [SKIP][92] ([fdo#109271] / [fdo#109278]) -> [SKIP][93] ([fdo#105602] / [fdo#109271] / [fdo#109278]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-apl6/igt@kms_busy@extended-modeset-hang-newfb-render-e.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/shard-apl4/igt@kms_busy@extended-modeset-hang-newfb-render-e.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14705/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (9 preceding siblings ...)
2019-10-09 0:55 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-10-09 15:45 ` Patchwork
2019-10-09 21:12 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-10-09 15:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
URL : https://patchwork.freedesktop.org/series/67741/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7042 -> Patchwork_14725
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/index.html
Known issues
------------
Here are the changes found in Patchwork_14725 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- {fi-icl-u4}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-icl-u4/igt@gem_close_race@basic-process.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-icl-u4/igt@gem_close_race@basic-process.html
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-icl-guc/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-icl-guc/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-glk-dsi: [INCOMPLETE][7] ([fdo#103359] / [k.org#198133]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-glk-dsi/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-glk-dsi/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-icl-u3/igt@gem_mmap_gtt@basic-short.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-icl-u3/igt@gem_mmap_gtt@basic-short.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u2}: [INCOMPLETE][11] ([fdo#111831]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-tgl-u2/igt@i915_selftest@live_gt_timelines.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-tgl-u2/igt@i915_selftest@live_gt_timelines.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}: [DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][15] ([fdo#109483]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (54 -> 47)
------------------------------
Additional (1): fi-apl-guc
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7042 -> Patchwork_14725
CI-20190529: 20190529
CI_DRM_7042: 22c41b8242975f09144e6f9eebc58ad357fbb8bc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14725: 6023eea6b2c5424980f249126425f393ad2d040a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6023eea6b2c5 drm/i915: Eliminate redundancy in intel_primary_plane_create()
ecc3b59e2f68 drm/i915: Do not enable HDR mode when color keying is active
9491d345e9c6 drm/i915: Reject ckey+fp16 on skl+
7aaaa59bef45 drm/i915: Sort format arrays consistently
0769f7cbfca3 drm/i915: Add 10bpc formats with alpha for icl+
e345ec744411 drm/i915: Expose C8 on VLV/CHV sprite planes
5f6fe134ea69 drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
e19e32456928 drm/i915: Expose alpha formats on VLV/CHV primary planes
a9ac7e6feb83 drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/index.html
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^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-08 16:14 [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites Ville Syrjala
` (10 preceding siblings ...)
2019-10-09 15:45 ` ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2) Patchwork
@ 2019-10-09 21:12 ` Patchwork
2019-10-14 19:23 ` Ville Syrjälä
2019-10-29 9:08 ` [Intel-gfx] " Shankar, Uma
2019-10-29 20:15 ` [Intel-gfx] " Juha-Pekka Heikkila
13 siblings, 1 reply; 52+ messages in thread
From: Patchwork @ 2019-10-09 21:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
URL : https://patchwork.freedesktop.org/series/67741/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14725_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14725_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14725_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-1us:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-pipe-a-planes:
- {shard-tglb}: [PASS][5] -> [FAIL][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-tglb7/igt@kms_plane@pixel-format-pipe-a-planes.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb6/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-c-planes:
- {shard-tglb}: NOTRUN -> [FAIL][7] +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb1/igt@kms_plane@pixel-format-pipe-c-planes.html
Known issues
------------
Here are the changes found in Patchwork_14725_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][8] -> [FAIL][9] ([fdo#111925])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb1/igt@gem_eio@in-flight-contexts-immediate.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb2/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +11 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][14] -> [INCOMPLETE][15] ([fdo#103359] / [fdo#108686] / [k.org#198133])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-glk8/igt@gem_tiled_swapping@non-threaded.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-glk8/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-hsw8/igt@gem_userptr_blits@sync-unmap-after-close.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][22] -> [DMESG-FAIL][23] ([fdo#111872])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-hsw1/igt@i915_selftest@live_hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-hsw5/igt@i915_selftest@live_hangcheck.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-iclb: [PASS][24] -> [INCOMPLETE][25] ([fdo#107713])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb6/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb7/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][26] -> [INCOMPLETE][27] ([fdo#109507]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-skl9/igt@kms_flip@flip-vs-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-skl8/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [PASS][28] -> [FAIL][29] ([fdo#100368])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][30] -> [FAIL][31] ([fdo#103167]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
#### Possible fixes ####
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][34] ([fdo#111325]) -> [PASS][35] +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb1/igt@gem_exec_schedule@pi-ringfull-bsd.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb6/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd1:
- shard-iclb: [SKIP][36] ([fdo#109276]) -> [PASS][37] +7 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb2/igt@gem_exec_schedule@preempt-queue-contexts-bsd1.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][38] ([fdo#111870]) -> [PASS][39] +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_userptr_blits@sync-unmap.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
- shard-hsw: [DMESG-WARN][40] ([fdo#111870]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-hsw6/igt@gem_userptr_blits@sync-unmap.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html
* igt@kms_atomic_interruptible@legacy-pageflip:
- shard-apl: [INCOMPLETE][42] ([fdo#103927]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-apl2/igt@kms_atomic_interruptible@legacy-pageflip.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-apl6/igt@kms_atomic_interruptible@legacy-pageflip.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][44] ([fdo#110741]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@pipe-b-torture-move:
- shard-iclb: [INCOMPLETE][46] ([fdo#107713]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb1/igt@kms_cursor_legacy@pipe-b-torture-move.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb4/igt@kms_cursor_legacy@pipe-b-torture-move.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][48] ([fdo#105363]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- {shard-tglb}: [INCOMPLETE][50] ([fdo#111714]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-tglb1/igt@kms_flip@flip-vs-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: [FAIL][52] ([fdo#103167]) -> [PASS][53] +4 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- {shard-tglb}: [FAIL][54] ([fdo#103167]) -> [PASS][55] +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][56] ([fdo#108145]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][58] ([fdo#103166]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][60] ([fdo#109441]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][62] ([fdo#99912]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-apl8/igt@kms_setmode@basic.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-apl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][64] ([fdo#108566]) -> [PASS][65] +3 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- {shard-tglb}: [INCOMPLETE][66] ([fdo#111832]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-tglb6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][68] ([fdo#109276]) -> [FAIL][69] ([fdo#111330])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb3/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][70] ([fdo#109441]) -> [DMESG-WARN][71] ([fdo#107724])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb8/igt@kms_psr@psr2_suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb2/igt@kms_psr@psr2_suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111714]: https://bugs.freedesktop.org/show_bug.cgi?id=111714
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111872]: https://bugs.freedesktop.org/show_bug.cgi?id=111872
[fdo#111925]: https://bugs.freedesktop.org/show_bug.cgi?id=111925
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7042 -> Patchwork_14725
CI-20190529: 20190529
CI_DRM_7042: 22c41b8242975f09144e6f9eebc58ad357fbb8bc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14725: 6023eea6b2c5424980f249126425f393ad2d040a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/index.html
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^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-09 21:12 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-10-14 19:23 ` Ville Syrjälä
2019-10-14 20:23 ` Chris Wilson
2019-10-15 6:41 ` Arkadiusz Hiler
0 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-10-14 19:23 UTC (permalink / raw)
To: intel-gfx
On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> URL : https://patchwork.freedesktop.org/series/67741/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14725_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_14725_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_eio@in-flight-1us:
> - shard-snb: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
>
> * igt@kms_plane@pixel-format-pipe-a-planes:
> - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
IGT-Version: 1.24-ge501741f
...
Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
(kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
DRM_FORMAT_ARGB2101010 = 0x30335241
IGT_FORMAT_FLOAT = 0x78464749
{ .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
.pixman_id = PIXMAN_a2r10g10b10,
{ .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
.pixman_id = PIXMAN_rgba_float,
if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
(drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
cnvert_pixman(cvt);
return;
...
igt_assert_f(false, "Conversion not implemented ...);
So wtf?
Are we somehow compiling igt with an old pixman causing
#if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
#define PIXMAN_rgba_float PIXMAN_invalid
#endif
to happen?
But the reference run shows it testing all the fancy YUV formats so
I don't think that can be the case.
And my CHV can run this test with ARGB2101010 just fine so
the code can't be totally broken.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-14 19:23 ` Ville Syrjälä
@ 2019-10-14 20:23 ` Chris Wilson
2019-10-15 6:41 ` Arkadiusz Hiler
1 sibling, 0 replies; 52+ messages in thread
From: Chris Wilson @ 2019-10-14 20:23 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
Quoting Ville Syrjälä (2019-10-14 20:23:42)
> On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> > URL : https://patchwork.freedesktop.org/series/67741/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_14725_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> >
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in Patchwork_14725_full:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@gem_eio@in-flight-1us:
> > - shard-snb: [PASS][1] -> [FAIL][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
> >
> > * igt@kms_plane@pixel-format-pipe-a-planes:
> > - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
>
> IGT-Version: 1.24-ge501741f
> ...
> Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
> (kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
>
> DRM_FORMAT_ARGB2101010 = 0x30335241
> IGT_FORMAT_FLOAT = 0x78464749
>
> { .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
> .pixman_id = PIXMAN_a2r10g10b10,
>
> { .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
> .pixman_id = PIXMAN_rgba_float,
>
> if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
> (drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
> cnvert_pixman(cvt);
> return;
> ...
> igt_assert_f(false, "Conversion not implemented ...);
>
> So wtf?
>
> Are we somehow compiling igt with an old pixman causing
> #if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
> #define PIXMAN_rgba_float PIXMAN_invalid
> #endif
> to happen?
That's the only way I can see, perhaps stick a #warn in there.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-14 19:23 ` Ville Syrjälä
2019-10-14 20:23 ` Chris Wilson
@ 2019-10-15 6:41 ` Arkadiusz Hiler
2019-10-15 9:25 ` Petri Latvala
1 sibling, 1 reply; 52+ messages in thread
From: Arkadiusz Hiler @ 2019-10-15 6:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Tomi Sarvela, intel-gfx
On Mon, Oct 14, 2019 at 10:23:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> > URL : https://patchwork.freedesktop.org/series/67741/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_14725_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> >
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in Patchwork_14725_full:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@gem_eio@in-flight-1us:
> > - shard-snb: [PASS][1] -> [FAIL][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
> >
> > * igt@kms_plane@pixel-format-pipe-a-planes:
> > - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
>
> IGT-Version: 1.24-ge501741f
> ...
> Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
> (kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
>
> DRM_FORMAT_ARGB2101010 = 0x30335241
> IGT_FORMAT_FLOAT = 0x78464749
>
> { .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
> .pixman_id = PIXMAN_a2r10g10b10,
>
> { .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
> .pixman_id = PIXMAN_rgba_float,
>
> if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
> (drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
> cnvert_pixman(cvt);
> return;
> ...
> igt_assert_f(false, "Conversion not implemented ...);
>
> So wtf?
>
> Are we somehow compiling igt with an old pixman causing
> #if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
> #define PIXMAN_rgba_float PIXMAN_invalid
> #endif
> to happen?
oof, seems like the building machine got downgraded somehow
ci-worker1:~$ dpkg -l '*pixman*'
Desired=Unknown/Install/Remove/Purge/Hold
| Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-inst/trig-aWait/Trig-pend
|/ Err?=(none)/Reinst-required (Status,Err: uppercase=bad)
||/ Name Version Architecture Description
+++-===============================================-============================-============================-===================================================================================================
ii libpixman-1-0:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo
ii libpixman-1-dev:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo (development files)
that's bad...
> But the reference run shows it testing all the fancy YUV formats so
> I don't think that can be the case.
That's the weird bit...
Anyway the building machine needs updating and apt-mark hold.
This can cause fallout and we need to file bugs to limit the noise.
There is quite some queue right now, but hopefully by tomorrow it will
be drained. I'll do the necessary updates and force IGT run to see what
is going to happen in the morning. Then I'll rerun this series.
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-15 6:41 ` Arkadiusz Hiler
@ 2019-10-15 9:25 ` Petri Latvala
2019-10-15 11:51 ` Ville Syrjälä
2019-10-15 12:08 ` Arkadiusz Hiler
0 siblings, 2 replies; 52+ messages in thread
From: Petri Latvala @ 2019-10-15 9:25 UTC (permalink / raw)
To: Arkadiusz Hiler; +Cc: Tomi Sarvela, intel-gfx
On Tue, Oct 15, 2019 at 09:41:20AM +0300, Arkadiusz Hiler wrote:
> On Mon, Oct 14, 2019 at 10:23:42PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> > > URL : https://patchwork.freedesktop.org/series/67741/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> > > ====================================================
> > >
> > > Summary
> > > -------
> > >
> > > **FAILURE**
> > >
> > > Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> > > verified manually.
> > >
> > > If you think the reported changes have nothing to do with the changes
> > > introduced in Patchwork_14725_full, please notify your bug team to allow them
> > > to document this new failure mode, which will reduce false positives in CI.
> > >
> > >
> > >
> > > Possible new issues
> > > -------------------
> > >
> > > Here are the unknown changes that may have been introduced in Patchwork_14725_full:
> > >
> > > ### IGT changes ###
> > >
> > > #### Possible regressions ####
> > >
> > > * igt@gem_eio@in-flight-1us:
> > > - shard-snb: [PASS][1] -> [FAIL][2]
> > > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> > > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
> > >
> > > * igt@kms_plane@pixel-format-pipe-a-planes:
> > > - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> > > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> > > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
> >
> > IGT-Version: 1.24-ge501741f
> > ...
> > Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
> > (kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
> >
> > DRM_FORMAT_ARGB2101010 = 0x30335241
> > IGT_FORMAT_FLOAT = 0x78464749
> >
> > { .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
> > .pixman_id = PIXMAN_a2r10g10b10,
> >
> > { .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
> > .pixman_id = PIXMAN_rgba_float,
> >
> > if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
> > (drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
> > cnvert_pixman(cvt);
> > return;
> > ...
> > igt_assert_f(false, "Conversion not implemented ...);
> >
> > So wtf?
> >
> > Are we somehow compiling igt with an old pixman causing
> > #if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
> > #define PIXMAN_rgba_float PIXMAN_invalid
> > #endif
> > to happen?
>
> oof, seems like the building machine got downgraded somehow
>
> ci-worker1:~$ dpkg -l '*pixman*'
> Desired=Unknown/Install/Remove/Purge/Hold
> | Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-inst/trig-aWait/Trig-pend
> |/ Err?=(none)/Reinst-required (Status,Err: uppercase=bad)
> ||/ Name Version Architecture Description
> +++-===============================================-============================-============================-===================================================================================================
> ii libpixman-1-0:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo
> ii libpixman-1-dev:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo (development files)
>
> that's bad...
>
> > But the reference run shows it testing all the fancy YUV formats so
> > I don't think that can be the case.
>
> That's the weird bit...
>
> Anyway the building machine needs updating and apt-mark hold.
> This can cause fallout and we need to file bugs to limit the noise.
>
> There is quite some queue right now, but hopefully by tomorrow it will
> be drained. I'll do the necessary updates and force IGT run to see what
> is going to happen in the morning. Then I'll rerun this series.
>
I don't think the builder ever had a higher version.
The fancy YUV formats work because the runtime lib is new enough, and
the build-time checks for those are as such:
#if CAIRO_VERSION < CAIRO_VERSION_ENCODE(1, 17, 2)
/*
* We need cairo 1.17.2 to use HDR formats, but the only thing added is a value
* to cairo_format_t.
*
* To prevent going outside the enum, make cairo_format_t an int and define
* ourselves.
*/
#define CAIRO_FORMAT_RGB96F (6)
#define CAIRO_FORMAT_RGBA128F (7)
#define cairo_format_t int
#endif
and
igt_skip_on_f(status == CAIRO_STATUS_INVALID_FORMAT &&
cairo_version() < CAIRO_VERSION_ENCODE(1, 17, 2),
"Cairo version too old, need 1.17.2, have %s\n",
cairo_version_string());
igt_skip_on_f(status == CAIRO_STATUS_NO_MEMORY &&
pixman_version() < PIXMAN_VERSION_ENCODE(0, 36, 0),
"Pixman version too old, need 0.36.0, have %s\n",
pixman_version_string());
In other words, the backwards compatibility for the fancy YUV formats
at build-time was easy to sneak in by defining some values, is that
possible to do with the 10bpc stuff? PIXMAN_rgba_float seems to be
just PIXMAN_FORMAT_BYTE(128, PIXMAN_TYPE_RGBA_FLOAT,32,32,32,32),
where PIXMAN_TYPE_RGBA_FLOAT is 11.
--
Petri Latvala
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-15 9:25 ` Petri Latvala
@ 2019-10-15 11:51 ` Ville Syrjälä
2019-10-15 12:08 ` Arkadiusz Hiler
1 sibling, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-10-15 11:51 UTC (permalink / raw)
To: Arkadiusz Hiler, Tomi Sarvela, intel-gfx
On Tue, Oct 15, 2019 at 12:25:59PM +0300, Petri Latvala wrote:
> On Tue, Oct 15, 2019 at 09:41:20AM +0300, Arkadiusz Hiler wrote:
> > On Mon, Oct 14, 2019 at 10:23:42PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> > > > == Series Details ==
> > > >
> > > > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> > > > URL : https://patchwork.freedesktop.org/series/67741/
> > > > State : failure
> > > >
> > > > == Summary ==
> > > >
> > > > CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> > > > ====================================================
> > > >
> > > > Summary
> > > > -------
> > > >
> > > > **FAILURE**
> > > >
> > > > Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> > > > verified manually.
> > > >
> > > > If you think the reported changes have nothing to do with the changes
> > > > introduced in Patchwork_14725_full, please notify your bug team to allow them
> > > > to document this new failure mode, which will reduce false positives in CI.
> > > >
> > > >
> > > >
> > > > Possible new issues
> > > > -------------------
> > > >
> > > > Here are the unknown changes that may have been introduced in Patchwork_14725_full:
> > > >
> > > > ### IGT changes ###
> > > >
> > > > #### Possible regressions ####
> > > >
> > > > * igt@gem_eio@in-flight-1us:
> > > > - shard-snb: [PASS][1] -> [FAIL][2]
> > > > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> > > > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
> > > >
> > > > * igt@kms_plane@pixel-format-pipe-a-planes:
> > > > - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> > > > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> > > > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
> > >
> > > IGT-Version: 1.24-ge501741f
> > > ...
> > > Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
> > > (kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
> > >
> > > DRM_FORMAT_ARGB2101010 = 0x30335241
> > > IGT_FORMAT_FLOAT = 0x78464749
> > >
> > > { .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
> > > .pixman_id = PIXMAN_a2r10g10b10,
> > >
> > > { .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
> > > .pixman_id = PIXMAN_rgba_float,
> > >
> > > if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
> > > (drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
> > > cnvert_pixman(cvt);
> > > return;
> > > ...
> > > igt_assert_f(false, "Conversion not implemented ...);
> > >
> > > So wtf?
> > >
> > > Are we somehow compiling igt with an old pixman causing
> > > #if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
> > > #define PIXMAN_rgba_float PIXMAN_invalid
> > > #endif
> > > to happen?
> >
> > oof, seems like the building machine got downgraded somehow
> >
> > ci-worker1:~$ dpkg -l '*pixman*'
> > Desired=Unknown/Install/Remove/Purge/Hold
> > | Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-inst/trig-aWait/Trig-pend
> > |/ Err?=(none)/Reinst-required (Status,Err: uppercase=bad)
> > ||/ Name Version Architecture Description
> > +++-===============================================-============================-============================-===================================================================================================
> > ii libpixman-1-0:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo
> > ii libpixman-1-dev:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo (development files)
> >
> > that's bad...
> >
> > > But the reference run shows it testing all the fancy YUV formats so
> > > I don't think that can be the case.
> >
> > That's the weird bit...
> >
> > Anyway the building machine needs updating and apt-mark hold.
> > This can cause fallout and we need to file bugs to limit the noise.
> >
> > There is quite some queue right now, but hopefully by tomorrow it will
> > be drained. I'll do the necessary updates and force IGT run to see what
> > is going to happen in the morning. Then I'll rerun this series.
> >
>
>
> I don't think the builder ever had a higher version.
>
> The fancy YUV formats work because the runtime lib is new enough, and
> the build-time checks for those are as such:
>
> #if CAIRO_VERSION < CAIRO_VERSION_ENCODE(1, 17, 2)
> /*
> * We need cairo 1.17.2 to use HDR formats, but the only thing added is a value
> * to cairo_format_t.
> *
> * To prevent going outside the enum, make cairo_format_t an int and define
> * ourselves.
> */
>
> #define CAIRO_FORMAT_RGB96F (6)
> #define CAIRO_FORMAT_RGBA128F (7)
> #define cairo_format_t int
> #endif
>
>
> and
>
>
> igt_skip_on_f(status == CAIRO_STATUS_INVALID_FORMAT &&
> cairo_version() < CAIRO_VERSION_ENCODE(1, 17, 2),
> "Cairo version too old, need 1.17.2, have %s\n",
> cairo_version_string());
>
> igt_skip_on_f(status == CAIRO_STATUS_NO_MEMORY &&
> pixman_version() < PIXMAN_VERSION_ENCODE(0, 36, 0),
> "Pixman version too old, need 0.36.0, have %s\n",
> pixman_version_string());
>
>
>
>
> In other words, the backwards compatibility for the fancy YUV formats
> at build-time was easy to sneak in by defining some values, is that
> possible to do with the 10bpc stuff? PIXMAN_rgba_float seems to be
> just PIXMAN_FORMAT_BYTE(128, PIXMAN_TYPE_RGBA_FLOAT,32,32,32,32),
> where PIXMAN_TYPE_RGBA_FLOAT is 11.
Hmm, yeah I suppose I can try to go that route instead.
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
2019-10-15 9:25 ` Petri Latvala
2019-10-15 11:51 ` Ville Syrjälä
@ 2019-10-15 12:08 ` Arkadiusz Hiler
1 sibling, 0 replies; 52+ messages in thread
From: Arkadiusz Hiler @ 2019-10-15 12:08 UTC (permalink / raw)
To: Ville Syrjälä, Tomi Sarvela, intel-gfx
On Tue, Oct 15, 2019 at 12:25:59PM +0300, Petri Latvala wrote:
> On Tue, Oct 15, 2019 at 09:41:20AM +0300, Arkadiusz Hiler wrote:
> > On Mon, Oct 14, 2019 at 10:23:42PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 09, 2019 at 09:12:23PM -0000, Patchwork wrote:
> > > > == Series Details ==
> > > >
> > > > Series: series starting with [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites (rev2)
> > > > URL : https://patchwork.freedesktop.org/series/67741/
> > > > State : failure
> > > >
> > > > == Summary ==
> > > >
> > > > CI Bug Log - changes from CI_DRM_7042_full -> Patchwork_14725_full
> > > > ====================================================
> > > >
> > > > Summary
> > > > -------
> > > >
> > > > **FAILURE**
> > > >
> > > > Serious unknown changes coming with Patchwork_14725_full absolutely need to be
> > > > verified manually.
> > > >
> > > > If you think the reported changes have nothing to do with the changes
> > > > introduced in Patchwork_14725_full, please notify your bug team to allow them
> > > > to document this new failure mode, which will reduce false positives in CI.
> > > >
> > > >
> > > >
> > > > Possible new issues
> > > > -------------------
> > > >
> > > > Here are the unknown changes that may have been introduced in Patchwork_14725_full:
> > > >
> > > > ### IGT changes ###
> > > >
> > > > #### Possible regressions ####
> > > >
> > > > * igt@gem_eio@in-flight-1us:
> > > > - shard-snb: [PASS][1] -> [FAIL][2]
> > > > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-snb7/igt@gem_eio@in-flight-1us.html
> > > > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-snb7/igt@gem_eio@in-flight-1us.html
> > > >
> > > > * igt@kms_plane@pixel-format-pipe-a-planes:
> > > > - shard-iclb: [PASS][3] -> [FAIL][4] +13 similar issues
> > > > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7042/shard-iclb7/igt@kms_plane@pixel-format-pipe-a-planes.html
> > > > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14725/shard-iclb8/igt@kms_plane@pixel-format-pipe-a-planes.html
> > >
> > > IGT-Version: 1.24-ge501741f
> > > ...
> > > Testing format AR30(0x30335241) / modifier 0x100000000000003 on A.0
> > > (kms_plane:1411) igt_fb-CRITICAL: Conversion not implemented (from format 0x30335241 to 0x78464749)
> > >
> > > DRM_FORMAT_ARGB2101010 = 0x30335241
> > > IGT_FORMAT_FLOAT = 0x78464749
> > >
> > > { .name = "ARGB2101010", .depth = 30, .drm_id = DRM_FORMAT_ARGB2101010,
> > > .pixman_id = PIXMAN_a2r10g10b10,
> > >
> > > { .name = "IGT-FLOAT", .depth = -1, .drm_id = IGT_FORMAT_FLOAT,
> > > .pixman_id = PIXMAN_rgba_float,
> > >
> > > if ((drm_format_to_pixman(cvt->src.fb->drm_format) != PIXMAN_invalid) &&
> > > (drm_format_to_pixman(cvt->dst.fb->drm_format) != PIXMAN_invalid)) {
> > > cnvert_pixman(cvt);
> > > return;
> > > ...
> > > igt_assert_f(false, "Conversion not implemented ...);
> > >
> > > So wtf?
> > >
> > > Are we somehow compiling igt with an old pixman causing
> > > #if PIXMAN_VERSION < PIXMAN_VERSION_ENCODE(0, 36, 0)
> > > #define PIXMAN_rgba_float PIXMAN_invalid
> > > #endif
> > > to happen?
> >
> > oof, seems like the building machine got downgraded somehow
> >
> > ci-worker1:~$ dpkg -l '*pixman*'
> > Desired=Unknown/Install/Remove/Purge/Hold
> > | Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-inst/trig-aWait/Trig-pend
> > |/ Err?=(none)/Reinst-required (Status,Err: uppercase=bad)
> > ||/ Name Version Architecture Description
> > +++-===============================================-============================-============================-===================================================================================================
> > ii libpixman-1-0:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo
> > ii libpixman-1-dev:amd64 0.34.0-2 amd64 pixel-manipulation library for X and cairo (development files)
> >
> > that's bad...
> >
> > > But the reference run shows it testing all the fancy YUV formats so
> > > I don't think that can be the case.
> >
> > That's the weird bit...
> >
> > Anyway the building machine needs updating and apt-mark hold.
> > This can cause fallout and we need to file bugs to limit the noise.
> >
> > There is quite some queue right now, but hopefully by tomorrow it will
> > be drained. I'll do the necessary updates and force IGT run to see what
> > is going to happen in the morning. Then I'll rerun this series.
> >
>
>
> I don't think the builder ever had a higher version.
>
> The fancy YUV formats work because the runtime lib is new enough, and
> the build-time checks for those are as such:
>
> #if CAIRO_VERSION < CAIRO_VERSION_ENCODE(1, 17, 2)
> /*
> * We need cairo 1.17.2 to use HDR formats, but the only thing added is a value
> * to cairo_format_t.
> *
> * To prevent going outside the enum, make cairo_format_t an int and define
> * ourselves.
> */
>
> #define CAIRO_FORMAT_RGB96F (6)
> #define CAIRO_FORMAT_RGBA128F (7)
> #define cairo_format_t int
> #endif
>
>
> and
>
>
> igt_skip_on_f(status == CAIRO_STATUS_INVALID_FORMAT &&
> cairo_version() < CAIRO_VERSION_ENCODE(1, 17, 2),
> "Cairo version too old, need 1.17.2, have %s\n",
> cairo_version_string());
>
> igt_skip_on_f(status == CAIRO_STATUS_NO_MEMORY &&
> pixman_version() < PIXMAN_VERSION_ENCODE(0, 36, 0),
> "Pixman version too old, need 0.36.0, have %s\n",
> pixman_version_string());
I am not a fan of this approach as we nest skips pretty deep within
functions that have neither 'require' nor 'skip' in the name. The
issuing longjmp() can cause surprise short-circuiting of tests iterating
through multiple formats...
Some of that would be solved by the "dynamic subsubtests", but the
semantics still feels off.
> In other words, the backwards compatibility for the fancy YUV formats
> at build-time was easy to sneak in by defining some values, is that
> possible to do with the 10bpc stuff? PIXMAN_rgba_float seems to be
> just PIXMAN_FORMAT_BYTE(128, PIXMAN_TYPE_RGBA_FLOAT,32,32,32,32),
> where PIXMAN_TYPE_RGBA_FLOAT is 11.
Yeah, let it be for now unless someone finds time to do the necessary
reworks :-P
--
Cheers,
Arek
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
@ 2019-10-29 9:08 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 9:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-
>BDW sprites
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose them.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 633fa8069348..90b0e65420a5 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB8888:
> sprctl |= SPRITE_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010 |
>SPRITE_RGB_ORDER_RGBX;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
> break;
>@@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB8888:
> dvscntr |= DVS_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
> break;
>@@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = { static
>const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
The order seems inconsistent with 8888 but I guess you have a patch fixing the
ordering, so should be ok.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct
>drm_plane *_plane,
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
@ 2019-10-29 9:08 ` Shankar, Uma
0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-10-29 9:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-
>BDW sprites
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose them.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 633fa8069348..90b0e65420a5 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB8888:
> sprctl |= SPRITE_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010 |
>SPRITE_RGB_ORDER_RGBX;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
> break;
>@@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB8888:
> dvscntr |= DVS_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
> break;
>@@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = { static
>const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
The order seems inconsistent with 8888 but I guess you have a patch fixing the
ordering, so should be ok.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct
>drm_plane *_plane,
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
@ 2019-10-29 20:15 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-29 20:15 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
> them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 633fa8069348..90b0e65420a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_XRGB8888:
> sprctl |= SPRITE_FORMAT_RGBX888;
> break;
> + case DRM_FORMAT_XBGR2101010:
> + sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX;
> + break;
> + case DRM_FORMAT_XRGB2101010:
> + sprctl |= SPRITE_FORMAT_RGBX101010;
> + break;
> case DRM_FORMAT_YUYV:
> sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
> break;
> @@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_XRGB8888:
> dvscntr |= DVS_FORMAT_RGBX888;
> break;
> + case DRM_FORMAT_XBGR2101010:
> + dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
> + break;
> + case DRM_FORMAT_XRGB2101010:
> + dvscntr |= DVS_FORMAT_RGBX101010;
> + break;
> case DRM_FORMAT_YUYV:
> dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
> break;
> @@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = {
> static const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
@ 2019-10-29 20:15 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 52+ messages in thread
From: Juha-Pekka Heikkila @ 2019-10-29 20:15 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 8.10.2019 19.14, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
> them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 633fa8069348..90b0e65420a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_XRGB8888:
> sprctl |= SPRITE_FORMAT_RGBX888;
> break;
> + case DRM_FORMAT_XBGR2101010:
> + sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX;
> + break;
> + case DRM_FORMAT_XRGB2101010:
> + sprctl |= SPRITE_FORMAT_RGBX101010;
> + break;
> case DRM_FORMAT_YUYV:
> sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
> break;
> @@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_XRGB8888:
> dvscntr |= DVS_FORMAT_RGBX888;
> break;
> + case DRM_FORMAT_XBGR2101010:
> + dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
> + break;
> + case DRM_FORMAT_XRGB2101010:
> + dvscntr |= DVS_FORMAT_RGBX101010;
> + break;
> case DRM_FORMAT_YUYV:
> dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
> break;
> @@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = {
> static const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> @@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>
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