* [PATCH 02/11] drm/i915/tgl: Include ro parts of l3 to invalidate
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 15:44 ` [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 8e63cffcabe0..4586a6a1fad4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -233,6 +233,7 @@
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
+#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
#define PIPE_CONTROL_NOTIFY (1<<8)
#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 21635db8d76c..2fe339228b82 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3231,6 +3231,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
2019-10-15 15:44 ` [PATCH 02/11] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 15:55 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 04/11] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
` (9 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
v2: Flush also in breadcrumbs (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 4586a6a1fad4..d6bf272d8c59 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -235,6 +235,7 @@
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
+#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
#define PIPE_CONTROL_NOTIFY (1<<8)
#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 2fe339228b82..27b5259f2f66 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3206,6 +3206,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
@@ -3416,7 +3417,9 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ PIPE_CONTROL_FLUSH_ENABLE |
+ PIPE_CONTROL_HDC_PIPELINE_FLUSH);
+
return gen12_emit_fini_breadcrumb_footer(request, cs);
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush
2019-10-15 15:44 ` [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
@ 2019-10-15 15:55 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 15:55 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:41)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> v2: Flush also in breadcrumbs (Chris)
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> @@ -3416,7 +3417,9 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> - PIPE_CONTROL_FLUSH_ENABLE);
> + PIPE_CONTROL_FLUSH_ENABLE |
> + PIPE_CONTROL_HDC_PIPELINE_FLUSH);
> +
Bonus!
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 04/11] drm/i915/tgl: Add extra hdc flush workaround
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
2019-10-15 15:44 ` [PATCH 02/11] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
2019-10-15 15:44 ` [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 15:57 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0 Mika Kuoppala
` (8 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
v2: use IS_TGL_REVID (Chris)
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 27b5259f2f66..5e98114a07a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3254,6 +3254,26 @@ static int gen12_emit_flush_render(struct i915_request *request,
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
+
+ /*
+ * Wa_1604544889:tgl
+ */
+ if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ flags = 0;
+ flags |= PIPE_CONTROL_CS_STALL;
+ flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
+
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ flags |= PIPE_CONTROL_QW_WRITE;
+
+ cs = intel_ring_begin(request, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen8_emit_pipe_control(cs, flags,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(request, cs);
+ }
}
return 0;
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (2 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 04/11] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:00 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 06/11] drm/i915/tgl: Wa_1409420604 Mika Kuoppala
` (7 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.
References: HSDES#1606700617
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba65e5018978..db7844daace9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,7 +567,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- /* Wa_1409142259 */
+ /* Wa_1409142259:tgl */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
@@ -1260,6 +1260,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+ GEN9_CS_DEBUG_MODE1,
+ FF_DOP_CLOCK_GATE_DISABLE);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dd126cc3ac3..781ca18cb45b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7671,6 +7671,7 @@ enum {
#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
+ #define FF_DOP_CLOCK_GATE_DISABLE BIT(1)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0
2019-10-15 15:44 ` [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0 Mika Kuoppala
@ 2019-10-15 16:00 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:00 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:43)
> To ensure correct state data for compute workloads, we
> need to keep the ff dop clock enabled.
>
> References: HSDES#1606700617
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ba65e5018978..db7844daace9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,7 +567,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> - /* Wa_1409142259 */
> + /* Wa_1409142259:tgl */
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> }
> @@ -1260,6 +1260,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> + /* Wa_1606700617:tgl */
> + wa_masked_en(wal,
> + GEN9_CS_DEBUG_MODE1,
> + FF_DOP_CLOCK_GATE_DISABLE);
> + }
Bah, and they wanted it dynamic!
> +
> if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dd126cc3ac3..781ca18cb45b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7671,6 +7671,7 @@ enum {
> #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
>
> #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> + #define FF_DOP_CLOCK_GATE_DISABLE BIT(1)
REG_BIT(1)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 06/11] drm/i915/tgl: Wa_1409420604
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (3 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:02 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 07/11] drm/i915/tgl: Wa_1409170338 Mika Kuoppala
` (6 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Avoid possible hang in CPSS unit.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index db7844daace9..b7d7fdc5ba90 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -897,6 +897,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
+ /* Wa_1409420604:tgl */
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 781ca18cb45b..51c3e7975d6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4054,6 +4054,9 @@ enum {
#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define GWUNIT_CLKGATE_DIS (1 << 16)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
+#define CPSSUNIT_CLKGATE_DIS (1 << 9)
+
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
#define VFUNIT_CLKGATE_DIS (1 << 20)
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 06/11] drm/i915/tgl: Wa_1409420604
2019-10-15 15:44 ` [PATCH 06/11] drm/i915/tgl: Wa_1409420604 Mika Kuoppala
@ 2019-10-15 16:02 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:02 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:44)
> Avoid possible hang in CPSS unit.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index db7844daace9..b7d7fdc5ba90 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -897,6 +897,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> + /* Wa_1409420604:tgl */
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + wa_write_or(wal,
> + SUBSLICE_UNIT_LEVEL_CLKGATE2,
> + CPSSUNIT_CLKGATE_DIS);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 781ca18cb45b..51c3e7975d6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4054,6 +4054,9 @@ enum {
> #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> #define GWUNIT_CLKGATE_DIS (1 << 16)
>
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
> +#define CPSSUNIT_CLKGATE_DIS (1 << 9)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 07/11] drm/i915/tgl: Wa_1409170338
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (4 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 06/11] drm/i915/tgl: Wa_1409420604 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:03 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 08/11] drm/i915/tgl: Wa_1409600907 Mika Kuoppala
` (5 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b7d7fdc5ba90..4b7740aaf3bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -902,6 +902,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
wa_write_or(wal,
SUBSLICE_UNIT_LEVEL_CLKGATE2,
CPSSUNIT_CLKGATE_DIS);
+
+ /* Wa_1409180338:tgl */
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
static void
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 07/11] drm/i915/tgl: Wa_1409170338
2019-10-15 15:44 ` [PATCH 07/11] drm/i915/tgl: Wa_1409170338 Mika Kuoppala
@ 2019-10-15 16:03 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:03 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:45)
> Avoid possible hang in tsg,vfe units by keeping
> l3 clocks runnings.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b7d7fdc5ba90..4b7740aaf3bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -902,6 +902,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> wa_write_or(wal,
> SUBSLICE_UNIT_LEVEL_CLKGATE2,
> CPSSUNIT_CLKGATE_DIS);
> +
> + /* Wa_1409180338:tgl */
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + wa_write_or(wal,
> + SLICE_UNIT_LEVEL_CLKGATE,
> + L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> }
I've seen this somewhere before... ;)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 08/11] drm/i915/tgl: Wa_1409600907
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (5 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 07/11] drm/i915/tgl: Wa_1409170338 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:05 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 09/11] drm/i915/tgl: Wa_1607138336 Mika Kuoppala
` (4 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
To avoid possible hang, we need to add depth stall if we flush the
depth cache.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5e98114a07a1..1ef23735c1f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3204,6 +3204,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ /* Wa_1409600907:tgl */
+ flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
@@ -3436,6 +3438,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ /* Wa_1409600907:tgl */
+ PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_HDC_PIPELINE_FLUSH);
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 08/11] drm/i915/tgl: Wa_1409600907
2019-10-15 15:44 ` [PATCH 08/11] drm/i915/tgl: Wa_1409600907 Mika Kuoppala
@ 2019-10-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:05 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:46)
> To avoid possible hang, we need to add depth stall if we flush the
> depth cache.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 5e98114a07a1..1ef23735c1f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3204,6 +3204,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + /* Wa_1409600907:tgl */
> + flags |= PIPE_CONTROL_DEPTH_STALL;
> flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
> @@ -3436,6 +3438,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> + /* Wa_1409600907:tgl */
> + PIPE_CONTROL_DEPTH_STALL |
The advice is indeed to ignore bspec and just set the bit regardless of
the programming notes.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 09/11] drm/i915/tgl: Wa_1607138336
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (6 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 08/11] drm/i915/tgl: Wa_1409600907 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:06 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627 Mika Kuoppala
` (3 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Avoid possible deadlock on context switch.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4b7740aaf3bf..3bacf3d9684e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1276,6 +1276,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_masked_en(wal,
GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE);
+
+ /* Wa_1607138336:tgl */
+ wa_write_or(wal,
+ GEN9_CTX_PREEMPT_REG,
+ GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 51c3e7975d6b..19ac01057528 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7676,6 +7676,8 @@ enum {
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
#define FF_DOP_CLOCK_GATE_DISABLE BIT(1)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
+ #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG (1 << 11)
+
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 09/11] drm/i915/tgl: Wa_1607138336
2019-10-15 15:44 ` [PATCH 09/11] drm/i915/tgl: Wa_1607138336 Mika Kuoppala
@ 2019-10-15 16:06 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:06 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:47)
> Avoid possible deadlock on context switch.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4b7740aaf3bf..3bacf3d9684e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1276,6 +1276,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_masked_en(wal,
> GEN9_CS_DEBUG_MODE1,
> FF_DOP_CLOCK_GATE_DISABLE);
> +
> + /* Wa_1607138336:tgl */
> + wa_write_or(wal,
> + GEN9_CTX_PREEMPT_REG,
> + GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 51c3e7975d6b..19ac01057528 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7676,6 +7676,8 @@ enum {
> #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> #define FF_DOP_CLOCK_GATE_DISABLE BIT(1)
> #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> + #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG (1 << 11)
REG_BIT(11)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (7 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 09/11] drm/i915/tgl: Wa_1607138336 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:08 ` Chris Wilson
2019-10-15 15:44 ` [PATCH 11/11] drm/i915/tgl: Wa_1607138340 Mika Kuoppala
` (2 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Disable semaphore idle messages and wait for event
power downs.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3bacf3d9684e..73fc168d7f60 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1281,6 +1281,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+
+ /* Wa_1607030317:tgl */
+ /* Wa_1607186500:tgl */
+ /* Wa_1607297627:tgl */
+ wa_masked_en(wal,
+ GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19ac01057528..b50ec878a0b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2885,6 +2885,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE (1 << 7)
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627
2019-10-15 15:44 ` [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627 Mika Kuoppala
@ 2019-10-15 16:08 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:08 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:48)
> Disable semaphore idle messages and wait for event
> power downs.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3bacf3d9684e..73fc168d7f60 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1281,6 +1281,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_write_or(wal,
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> +
> + /* Wa_1607030317:tgl */
> + /* Wa_1607186500:tgl */
> + /* Wa_1607297627:tgl */
> + wa_masked_en(wal,
> + GEN6_RC_SLEEP_PSMI_CONTROL,
> + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> + GEN8_RC_SEMA_IDLE_MSG_DISABLE);
rcs only, ack.
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19ac01057528..b50ec878a0b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2885,6 +2885,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> +#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE (1 << 7)
REG_BIT(7)
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 11/11] drm/i915/tgl: Wa_1607138340
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (8 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 10/11] drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627 Mika Kuoppala
@ 2019-10-15 15:44 ` Mika Kuoppala
2019-10-15 16:10 ` Chris Wilson
2019-10-15 16:11 ` [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Chris Wilson
2019-10-15 18:21 ` ✗ Fi.CI.BUILD: failure for series starting with [01/11] " Patchwork
11 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2019-10-15 15:44 UTC (permalink / raw)
To: intel-gfx
Avoid possible cs hang with semaphores by disabling
lite restore.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1ef23735c1f6..580d99d18e71 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1048,6 +1048,10 @@ static u64 execlists_update_context(const struct i915_request *rq)
desc = ce->lrc_desc;
ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
+ /* Wa_1607138340:tgl */
+ if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_A0))
+ desc |= CTX_DESC_FORCE_RESTORE;
+
return desc;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 11/11] drm/i915/tgl: Wa_1607138340
2019-10-15 15:44 ` [PATCH 11/11] drm/i915/tgl: Wa_1607138340 Mika Kuoppala
@ 2019-10-15 16:10 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:10 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:49)
> Avoid possible cs hang with semaphores by disabling
> lite restore.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 1ef23735c1f6..580d99d18e71 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1048,6 +1048,10 @@ static u64 execlists_update_context(const struct i915_request *rq)
> desc = ce->lrc_desc;
> ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
>
> + /* Wa_1607138340:tgl */
> + if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_A0))
> + desc |= CTX_DESC_FORCE_RESTORE;
This looks much more heavy handed than suggested, but for a0, I'm not
fused.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (9 preceding siblings ...)
2019-10-15 15:44 ` [PATCH 11/11] drm/i915/tgl: Wa_1607138340 Mika Kuoppala
@ 2019-10-15 16:11 ` Chris Wilson
2019-10-15 18:21 ` ✗ Fi.CI.BUILD: failure for series starting with [01/11] " Patchwork
11 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-10-15 16:11 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-15 16:44:39)
> We are going to need this macro on limiting
> the workaround scope.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c46b339064c0..f6aee1e01a7f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1686,6 +1686,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ICL_REVID(p, since, until) \
> (IS_ICELAKE(p) && IS_REVID(p, since, until))
>
> +#define TGL_REVID_A0 0x0
> +
> +#define IS_TGL_REVID(p, since, until) \
> + (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915/tgl: Add IS_TGL_REVID
2019-10-15 15:44 [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
` (10 preceding siblings ...)
2019-10-15 16:11 ` [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Chris Wilson
@ 2019-10-15 18:21 ` Patchwork
11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-10-15 18:21 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/11] drm/i915/tgl: Add IS_TGL_REVID
URL : https://patchwork.freedesktop.org/series/68037/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
drivers/gpu/drm/i915/gt/intel_workarounds.c: In function ‘tgl_gt_workarounds_init’:
drivers/gpu/drm/i915/gt/intel_workarounds.c:910:8: error: ‘L3_CLKGATE_DIS’ undeclared (first use in this function); did you mean ‘CGPSF_CLKGATE_DIS’?
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
^~~~~~~~~~~~~~
CGPSF_CLKGATE_DIS
drivers/gpu/drm/i915/gt/intel_workarounds.c:910:8: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gt/intel_workarounds.c:910:25: error: ‘L3_CR2X_CLKGATE_DIS’ undeclared (first use in this function); did you mean ‘L3_CLKGATE_DIS’?
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
^~~~~~~~~~~~~~~~~~~
L3_CLKGATE_DIS
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/gt/intel_workarounds.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_workarounds.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1650: recipe for target 'drivers' failed
make: *** [drivers] Error 2
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^ permalink raw reply [flat|nested] 22+ messages in thread