[PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[Philippe Mathieu-Daudé]

Hi,

This series is a rework of "piix4: cleanup and improvements" [1]
from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].

Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.

This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.

The overall design cleanup is not yet perfect, but enough to post
as a series.

Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.

Next step is probably:

1/ Extract i8259 from "pc.h" and sort all the places where we call
   pic_*() using global variables
2/ Refactor common PIIX code from hw/i386/pc_*.c to piix*.c

Please review,

Phil.

Series available here:
branch pc_split_i440fx_piix-v1 on https://gitlab.com/philmd/qemu.git

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html

Hervé Poussineau (9):
  mc146818rtc: move structure to header file
  mc146818rtc: always register rtc to rtc list
  piix4: rename some variables in realize function
  piix4: add Reset Control Register
  piix4: add a i8259 interrupt controller as specified in datasheet
  piix4: rename PIIX4 object to piix4-isa
  piix4: convert reset function to QOM
  piix4: add a i8257 dma controller as specified in datasheet
  piix4: add a i8254 pit controller as specified in datasheet

Philippe Mathieu-Daudé (23):
  hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
  hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
  mc146818rtc: Move RTC_ISA_IRQ definition
  mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
  MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
  Revert "irq: introduce qemu_irq_proxy()"
  piix4: add a mc146818rtc controller as specified in datasheet
  hw/mips/mips_malta: Create IDE hard drive array dynamically
  hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
  hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
  hw/i386/pc: Extract pc_gsi_create()
  hw/i386/pc: Reduce gsi_handler scope
  hw/i386/pc: Move gsi_state creation code
  hw/i386/pc: Extract pc_i8259_create()
  hw/i386/pc: Remove kvm_i386.h include
  hw/pci-host/piix: Extract piix3_create()
  hw/pci-host/piix: Move RCR_IOPORT register definition
  hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
  hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
  hw/pci-host/piix: Fix code style issues
  hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
  hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
  hw/pci-host/i440fx: Remove the last PIIX3 traces

 MAINTAINERS                         |  14 +-
 hw/acpi/pcihp.c                     |   2 +-
 hw/acpi/piix4.c                     |  42 +--
 hw/core/irq.c                       |  14 -
 hw/i386/Kconfig                     |   3 +-
 hw/i386/acpi-build.c                |   3 +-
 hw/i386/pc.c                        |  36 ++-
 hw/i386/pc_piix.c                   |  33 +--
 hw/i386/pc_q35.c                    |  28 +-
 hw/i386/xen/xen-hvm.c               |   5 +-
 hw/intc/apic_common.c               |  49 ----
 hw/isa/Kconfig                      |   4 +
 hw/isa/Makefile.objs                |   1 +
 hw/isa/piix3.c                      | 399 ++++++++++++++++++++++++++
 hw/isa/piix4.c                      | 155 ++++++++--
 hw/mips/gt64xxx_pci.c               |   5 +-
 hw/mips/mips_malta.c                |  46 +--
 hw/pci-host/Kconfig                 |   3 +-
 hw/pci-host/Makefile.objs           |   2 +-
 hw/pci-host/{piix.c => i440fx.c}    | 424 +---------------------------
 hw/timer/i8254_common.c             |  40 ---
 hw/timer/mc146818rtc.c              |  39 +--
 include/hw/acpi/piix4.h             |   6 -
 include/hw/i386/pc.h                |  41 +--
 include/hw/irq.h                    |   5 -
 include/hw/isa/isa.h                |   2 +
 include/hw/pci-host/i440fx.h        |  36 +++
 include/hw/southbridge/piix.h       |  74 +++++
 include/hw/timer/mc146818rtc.h      |  36 ++-
 include/hw/timer/mc146818rtc_regs.h |   2 -
 include/sysemu/kvm.h                |   1 +
 stubs/pci-host-piix.c               |   3 +-
 tests/rtc-test.c                    |   1 +
 33 files changed, 781 insertions(+), 773 deletions(-)
 create mode 100644 hw/isa/piix3.c
 rename hw/pci-host/{piix.c => i440fx.c} (58%)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/pci-host/i440fx.h
 create mode 100644 include/hw/southbridge/piix.h

-- 
2.21.0

[PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[Philippe Mathieu-Daudé]

Hi,

This series is a rework of "piix4: cleanup and improvements" [1]
from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].

Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.

This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.

The overall design cleanup is not yet perfect, but enough to post
as a series.

Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.

Next step is probably:

1/ Extract i8259 from "pc.h" and sort all the places where we call
   pic_*() using global variables
2/ Refactor common PIIX code from hw/i386/pc_*.c to piix*.c

Please review,

Phil.

Series available here:
branch pc_split_i440fx_piix-v1 on https://gitlab.com/philmd/qemu.git

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html

Hervé Poussineau (9):
  mc146818rtc: move structure to header file
  mc146818rtc: always register rtc to rtc list
  piix4: rename some variables in realize function
  piix4: add Reset Control Register
  piix4: add a i8259 interrupt controller as specified in datasheet
  piix4: rename PIIX4 object to piix4-isa
  piix4: convert reset function to QOM
  piix4: add a i8257 dma controller as specified in datasheet
  piix4: add a i8254 pit controller as specified in datasheet

Philippe Mathieu-Daudé (23):
  hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
  hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
  mc146818rtc: Move RTC_ISA_IRQ definition
  mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
  MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
  Revert "irq: introduce qemu_irq_proxy()"
  piix4: add a mc146818rtc controller as specified in datasheet
  hw/mips/mips_malta: Create IDE hard drive array dynamically
  hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
  hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
  hw/i386/pc: Extract pc_gsi_create()
  hw/i386/pc: Reduce gsi_handler scope
  hw/i386/pc: Move gsi_state creation code
  hw/i386/pc: Extract pc_i8259_create()
  hw/i386/pc: Remove kvm_i386.h include
  hw/pci-host/piix: Extract piix3_create()
  hw/pci-host/piix: Move RCR_IOPORT register definition
  hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
  hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
  hw/pci-host/piix: Fix code style issues
  hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
  hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
  hw/pci-host/i440fx: Remove the last PIIX3 traces

 MAINTAINERS                         |  14 +-
 hw/acpi/pcihp.c                     |   2 +-
 hw/acpi/piix4.c                     |  42 +--
 hw/core/irq.c                       |  14 -
 hw/i386/Kconfig                     |   3 +-
 hw/i386/acpi-build.c                |   3 +-
 hw/i386/pc.c                        |  36 ++-
 hw/i386/pc_piix.c                   |  33 +--
 hw/i386/pc_q35.c                    |  28 +-
 hw/i386/xen/xen-hvm.c               |   5 +-
 hw/intc/apic_common.c               |  49 ----
 hw/isa/Kconfig                      |   4 +
 hw/isa/Makefile.objs                |   1 +
 hw/isa/piix3.c                      | 399 ++++++++++++++++++++++++++
 hw/isa/piix4.c                      | 155 ++++++++--
 hw/mips/gt64xxx_pci.c               |   5 +-
 hw/mips/mips_malta.c                |  46 +--
 hw/pci-host/Kconfig                 |   3 +-
 hw/pci-host/Makefile.objs           |   2 +-
 hw/pci-host/{piix.c => i440fx.c}    | 424 +---------------------------
 hw/timer/i8254_common.c             |  40 ---
 hw/timer/mc146818rtc.c              |  39 +--
 include/hw/acpi/piix4.h             |   6 -
 include/hw/i386/pc.h                |  41 +--
 include/hw/irq.h                    |   5 -
 include/hw/isa/isa.h                |   2 +
 include/hw/pci-host/i440fx.h        |  36 +++
 include/hw/southbridge/piix.h       |  74 +++++
 include/hw/timer/mc146818rtc.h      |  36 ++-
 include/hw/timer/mc146818rtc_regs.h |   2 -
 include/sysemu/kvm.h                |   1 +
 stubs/pci-host-piix.c               |   3 +-
 tests/rtc-test.c                    |   1 +
 33 files changed, 781 insertions(+), 773 deletions(-)
 create mode 100644 hw/isa/piix3.c
 rename hw/pci-host/{piix.c => i440fx.c} (58%)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/pci-host/i440fx.h
 create mode 100644 include/hw/southbridge/piix.h

-- 
2.21.0

[Xen-devel] [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[Philippe Mathieu-Daudé]

Hi,

This series is a rework of "piix4: cleanup and improvements" [1]
from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].

Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.

This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.

The overall design cleanup is not yet perfect, but enough to post
as a series.

Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.

Next step is probably:

1/ Extract i8259 from "pc.h" and sort all the places where we call
   pic_*() using global variables
2/ Refactor common PIIX code from hw/i386/pc_*.c to piix*.c

Please review,

Phil.

Series available here:
branch pc_split_i440fx_piix-v1 on https://gitlab.com/philmd/qemu.git

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html

Hervé Poussineau (9):
  mc146818rtc: move structure to header file
  mc146818rtc: always register rtc to rtc list
  piix4: rename some variables in realize function
  piix4: add Reset Control Register
  piix4: add a i8259 interrupt controller as specified in datasheet
  piix4: rename PIIX4 object to piix4-isa
  piix4: convert reset function to QOM
  piix4: add a i8257 dma controller as specified in datasheet
  piix4: add a i8254 pit controller as specified in datasheet

Philippe Mathieu-Daudé (23):
  hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
  hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
  mc146818rtc: Move RTC_ISA_IRQ definition
  mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
  MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
  Revert "irq: introduce qemu_irq_proxy()"
  piix4: add a mc146818rtc controller as specified in datasheet
  hw/mips/mips_malta: Create IDE hard drive array dynamically
  hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
  hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
  hw/i386/pc: Extract pc_gsi_create()
  hw/i386/pc: Reduce gsi_handler scope
  hw/i386/pc: Move gsi_state creation code
  hw/i386/pc: Extract pc_i8259_create()
  hw/i386/pc: Remove kvm_i386.h include
  hw/pci-host/piix: Extract piix3_create()
  hw/pci-host/piix: Move RCR_IOPORT register definition
  hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
  hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
  hw/pci-host/piix: Fix code style issues
  hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
  hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
  hw/pci-host/i440fx: Remove the last PIIX3 traces

 MAINTAINERS                         |  14 +-
 hw/acpi/pcihp.c                     |   2 +-
 hw/acpi/piix4.c                     |  42 +--
 hw/core/irq.c                       |  14 -
 hw/i386/Kconfig                     |   3 +-
 hw/i386/acpi-build.c                |   3 +-
 hw/i386/pc.c                        |  36 ++-
 hw/i386/pc_piix.c                   |  33 +--
 hw/i386/pc_q35.c                    |  28 +-
 hw/i386/xen/xen-hvm.c               |   5 +-
 hw/intc/apic_common.c               |  49 ----
 hw/isa/Kconfig                      |   4 +
 hw/isa/Makefile.objs                |   1 +
 hw/isa/piix3.c                      | 399 ++++++++++++++++++++++++++
 hw/isa/piix4.c                      | 155 ++++++++--
 hw/mips/gt64xxx_pci.c               |   5 +-
 hw/mips/mips_malta.c                |  46 +--
 hw/pci-host/Kconfig                 |   3 +-
 hw/pci-host/Makefile.objs           |   2 +-
 hw/pci-host/{piix.c => i440fx.c}    | 424 +---------------------------
 hw/timer/i8254_common.c             |  40 ---
 hw/timer/mc146818rtc.c              |  39 +--
 include/hw/acpi/piix4.h             |   6 -
 include/hw/i386/pc.h                |  41 +--
 include/hw/irq.h                    |   5 -
 include/hw/isa/isa.h                |   2 +
 include/hw/pci-host/i440fx.h        |  36 +++
 include/hw/southbridge/piix.h       |  74 +++++
 include/hw/timer/mc146818rtc.h      |  36 ++-
 include/hw/timer/mc146818rtc_regs.h |   2 -
 include/sysemu/kvm.h                |   1 +
 stubs/pci-host-piix.c               |   3 +-
 tests/rtc-test.c                    |   1 +
 33 files changed, 781 insertions(+), 773 deletions(-)
 create mode 100644 hw/isa/piix3.c
 rename hw/pci-host/{piix.c => i440fx.c} (58%)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/pci-host/i440fx.h
 create mode 100644 include/hw/southbridge/piix.h

-- 
2.21.0


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[PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

These devices implemented their load_state_old() handler 10 years
ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
we can drop this code.

Note: the mips_r4k machine started to use the i8254 device just
after QEMU v0.5.0, but the MIPS machine types are not versioned,
so there is no migration compatibility issue removing this handler.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/acpi/piix4.c         | 40 ---------------------------------
 hw/intc/apic_common.c   | 49 -----------------------------------------
 hw/pci-host/piix.c      | 25 ---------------------
 hw/timer/i8254_common.c | 40 ---------------------------------
 4 files changed, 154 deletions(-)

diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 5742c3df87..1d29d438c7 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -42,7 +42,6 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/core/cpu.h"
 #include "trace.h"
@@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
     }
 };
 
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PIIX4PMState *s = opaque;
-    int ret, i;
-    uint16_t temp;
-
-    ret = pci_device_load(PCI_DEVICE(s), f);
-    if (ret < 0) {
-        return ret;
-    }
-    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
-    qemu_get_be16s(f, &s->ar.pm1.evt.en);
-    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
-    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
-    if (ret) {
-        return ret;
-    }
-
-    timer_get(f, s->ar.tmr.timer);
-    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    ret = vmstate_load_state(f, &vmstate_pci_status,
-        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
-    return ret;
-}
-
 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 {
     PIIX4PMState *s = opaque;
@@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
     .name = "piix4_pm",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = acpi_load_old,
     .post_load = vmstate_acpi_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index aafd8e0e33..375cb6abe9 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,7 +31,6 @@
 #include "sysemu/kvm.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 static int apic_irq_delivered;
@@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
     apic_init_reset(dev);
 }
 
-/* This function is only used for old state version 1 and 2 */
-static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    APICCommonState *s = opaque;
-    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
-    int i;
-
-    if (version_id > 2) {
-        return -EINVAL;
-    }
-
-    /* XXX: what if the base changes? (registered memory regions) */
-    qemu_get_be32s(f, &s->apicbase);
-    qemu_get_8s(f, &s->id);
-    qemu_get_8s(f, &s->arb_id);
-    qemu_get_8s(f, &s->tpr);
-    qemu_get_be32s(f, &s->spurious_vec);
-    qemu_get_8s(f, &s->log_dest);
-    qemu_get_8s(f, &s->dest_mode);
-    for (i = 0; i < 8; i++) {
-        qemu_get_be32s(f, &s->isr[i]);
-        qemu_get_be32s(f, &s->tmr[i]);
-        qemu_get_be32s(f, &s->irr[i]);
-    }
-    for (i = 0; i < APIC_LVT_NB; i++) {
-        qemu_get_be32s(f, &s->lvt[i]);
-    }
-    qemu_get_be32s(f, &s->esr);
-    qemu_get_be32s(f, &s->icr[0]);
-    qemu_get_be32s(f, &s->icr[1]);
-    qemu_get_be32s(f, &s->divide_conf);
-    s->count_shift = qemu_get_be32(f);
-    qemu_get_be32s(f, &s->initial_count);
-    s->initial_count_load_time = qemu_get_be64(f);
-    s->next_time = qemu_get_be64(f);
-
-    if (version_id >= 2) {
-        s->timer_expiry = qemu_get_be64(f);
-    }
-
-    if (info->post_load) {
-        info->post_load(s);
-    }
-    return 0;
-}
-
 static const VMStateDescription vmstate_apic_common;
 
 static void apic_common_realize(DeviceState *dev, Error **errp)
@@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
     .name = "apic",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = apic_load_old,
     .pre_load = apic_pre_load,
     .pre_save = apic_dispatch_pre_save,
     .post_load = apic_dispatch_post_load,
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 135c645535..2f4cbcbfe9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -33,7 +33,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
 #include "sysemu/reset.h"
@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
     }
 }
 
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
-    PCII440FXState *d = opaque;
-    PCIDevice *pd = PCI_DEVICE(d);
-    int ret, i;
-    uint8_t smm_enabled;
-
-    ret = pci_device_load(pd, f);
-    if (ret < 0)
-        return ret;
-    i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &smm_enabled);
-
-    if (version_id == 2) {
-        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
-            qemu_get_be32(f); /* dummy load for compatibility */
-        }
-    }
-
-    return 0;
-}
-
 static int i440fx_post_load(void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;
@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
     .name = "I440FX",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = i440fx_load_old,
     .post_load = i440fx_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 57bf10cc94..050875b497 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -29,7 +29,6 @@
 #include "qemu/timer.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 /* val must be 0 or 1 */
@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
     }
 };
 
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PITCommonState *pit = opaque;
-    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
-    PITChannelState *s;
-    int i;
-
-    if (version_id != 1) {
-        return -EINVAL;
-    }
-
-    for (i = 0; i < 3; i++) {
-        s = &pit->channels[i];
-        s->count = qemu_get_be32(f);
-        qemu_get_be16s(f, &s->latched_count);
-        qemu_get_8s(f, &s->count_latched);
-        qemu_get_8s(f, &s->status_latched);
-        qemu_get_8s(f, &s->status);
-        qemu_get_8s(f, &s->read_state);
-        qemu_get_8s(f, &s->write_state);
-        qemu_get_8s(f, &s->write_latch);
-        qemu_get_8s(f, &s->rw_mode);
-        qemu_get_8s(f, &s->mode);
-        qemu_get_8s(f, &s->bcd);
-        qemu_get_8s(f, &s->gate);
-        s->count_load_time = qemu_get_be64(f);
-        s->irq_disabled = 0;
-        if (i == 0) {
-            s->next_transition_time = qemu_get_be64(f);
-        }
-    }
-    if (c->post_load) {
-        c->post_load(pit);
-    }
-    return 0;
-}
-
 static int pit_dispatch_pre_save(void *opaque)
 {
     PITCommonState *s = opaque;
@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
     .name = "i8254",
     .version_id = 3,
     .minimum_version_id = 2,
-    .minimum_version_id_old = 1,
-    .load_state_old = pit_load_old,
     .pre_save = pit_dispatch_pre_save,
     .post_load = pit_dispatch_post_load,
     .fields = (VMStateField[]) {
-- 
2.21.0

[PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

These devices implemented their load_state_old() handler 10 years
ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
we can drop this code.

Note: the mips_r4k machine started to use the i8254 device just
after QEMU v0.5.0, but the MIPS machine types are not versioned,
so there is no migration compatibility issue removing this handler.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/acpi/piix4.c         | 40 ---------------------------------
 hw/intc/apic_common.c   | 49 -----------------------------------------
 hw/pci-host/piix.c      | 25 ---------------------
 hw/timer/i8254_common.c | 40 ---------------------------------
 4 files changed, 154 deletions(-)

diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 5742c3df87..1d29d438c7 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -42,7 +42,6 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/core/cpu.h"
 #include "trace.h"
@@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
     }
 };
 
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PIIX4PMState *s = opaque;
-    int ret, i;
-    uint16_t temp;
-
-    ret = pci_device_load(PCI_DEVICE(s), f);
-    if (ret < 0) {
-        return ret;
-    }
-    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
-    qemu_get_be16s(f, &s->ar.pm1.evt.en);
-    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
-    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
-    if (ret) {
-        return ret;
-    }
-
-    timer_get(f, s->ar.tmr.timer);
-    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    ret = vmstate_load_state(f, &vmstate_pci_status,
-        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
-    return ret;
-}
-
 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 {
     PIIX4PMState *s = opaque;
@@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
     .name = "piix4_pm",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = acpi_load_old,
     .post_load = vmstate_acpi_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index aafd8e0e33..375cb6abe9 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,7 +31,6 @@
 #include "sysemu/kvm.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 static int apic_irq_delivered;
@@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
     apic_init_reset(dev);
 }
 
-/* This function is only used for old state version 1 and 2 */
-static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    APICCommonState *s = opaque;
-    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
-    int i;
-
-    if (version_id > 2) {
-        return -EINVAL;
-    }
-
-    /* XXX: what if the base changes? (registered memory regions) */
-    qemu_get_be32s(f, &s->apicbase);
-    qemu_get_8s(f, &s->id);
-    qemu_get_8s(f, &s->arb_id);
-    qemu_get_8s(f, &s->tpr);
-    qemu_get_be32s(f, &s->spurious_vec);
-    qemu_get_8s(f, &s->log_dest);
-    qemu_get_8s(f, &s->dest_mode);
-    for (i = 0; i < 8; i++) {
-        qemu_get_be32s(f, &s->isr[i]);
-        qemu_get_be32s(f, &s->tmr[i]);
-        qemu_get_be32s(f, &s->irr[i]);
-    }
-    for (i = 0; i < APIC_LVT_NB; i++) {
-        qemu_get_be32s(f, &s->lvt[i]);
-    }
-    qemu_get_be32s(f, &s->esr);
-    qemu_get_be32s(f, &s->icr[0]);
-    qemu_get_be32s(f, &s->icr[1]);
-    qemu_get_be32s(f, &s->divide_conf);
-    s->count_shift = qemu_get_be32(f);
-    qemu_get_be32s(f, &s->initial_count);
-    s->initial_count_load_time = qemu_get_be64(f);
-    s->next_time = qemu_get_be64(f);
-
-    if (version_id >= 2) {
-        s->timer_expiry = qemu_get_be64(f);
-    }
-
-    if (info->post_load) {
-        info->post_load(s);
-    }
-    return 0;
-}
-
 static const VMStateDescription vmstate_apic_common;
 
 static void apic_common_realize(DeviceState *dev, Error **errp)
@@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
     .name = "apic",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = apic_load_old,
     .pre_load = apic_pre_load,
     .pre_save = apic_dispatch_pre_save,
     .post_load = apic_dispatch_post_load,
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 135c645535..2f4cbcbfe9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -33,7 +33,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
 #include "sysemu/reset.h"
@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
     }
 }
 
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
-    PCII440FXState *d = opaque;
-    PCIDevice *pd = PCI_DEVICE(d);
-    int ret, i;
-    uint8_t smm_enabled;
-
-    ret = pci_device_load(pd, f);
-    if (ret < 0)
-        return ret;
-    i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &smm_enabled);
-
-    if (version_id == 2) {
-        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
-            qemu_get_be32(f); /* dummy load for compatibility */
-        }
-    }
-
-    return 0;
-}
-
 static int i440fx_post_load(void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;
@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
     .name = "I440FX",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = i440fx_load_old,
     .post_load = i440fx_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 57bf10cc94..050875b497 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -29,7 +29,6 @@
 #include "qemu/timer.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 /* val must be 0 or 1 */
@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
     }
 };
 
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PITCommonState *pit = opaque;
-    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
-    PITChannelState *s;
-    int i;
-
-    if (version_id != 1) {
-        return -EINVAL;
-    }
-
-    for (i = 0; i < 3; i++) {
-        s = &pit->channels[i];
-        s->count = qemu_get_be32(f);
-        qemu_get_be16s(f, &s->latched_count);
-        qemu_get_8s(f, &s->count_latched);
-        qemu_get_8s(f, &s->status_latched);
-        qemu_get_8s(f, &s->status);
-        qemu_get_8s(f, &s->read_state);
-        qemu_get_8s(f, &s->write_state);
-        qemu_get_8s(f, &s->write_latch);
-        qemu_get_8s(f, &s->rw_mode);
-        qemu_get_8s(f, &s->mode);
-        qemu_get_8s(f, &s->bcd);
-        qemu_get_8s(f, &s->gate);
-        s->count_load_time = qemu_get_be64(f);
-        s->irq_disabled = 0;
-        if (i == 0) {
-            s->next_transition_time = qemu_get_be64(f);
-        }
-    }
-    if (c->post_load) {
-        c->post_load(pit);
-    }
-    return 0;
-}
-
 static int pit_dispatch_pre_save(void *opaque)
 {
     PITCommonState *s = opaque;
@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
     .name = "i8254",
     .version_id = 3,
     .minimum_version_id = 2,
-    .minimum_version_id_old = 1,
-    .load_state_old = pit_load_old,
     .pre_save = pit_dispatch_pre_save,
     .post_load = pit_dispatch_post_load,
     .fields = (VMStateField[]) {
-- 
2.21.0

[Xen-devel] [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

These devices implemented their load_state_old() handler 10 years
ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
we can drop this code.

Note: the mips_r4k machine started to use the i8254 device just
after QEMU v0.5.0, but the MIPS machine types are not versioned,
so there is no migration compatibility issue removing this handler.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/acpi/piix4.c         | 40 ---------------------------------
 hw/intc/apic_common.c   | 49 -----------------------------------------
 hw/pci-host/piix.c      | 25 ---------------------
 hw/timer/i8254_common.c | 40 ---------------------------------
 4 files changed, 154 deletions(-)

diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 5742c3df87..1d29d438c7 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -42,7 +42,6 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/core/cpu.h"
 #include "trace.h"
@@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
     }
 };
 
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PIIX4PMState *s = opaque;
-    int ret, i;
-    uint16_t temp;
-
-    ret = pci_device_load(PCI_DEVICE(s), f);
-    if (ret < 0) {
-        return ret;
-    }
-    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
-    qemu_get_be16s(f, &s->ar.pm1.evt.en);
-    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
-    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
-    if (ret) {
-        return ret;
-    }
-
-    timer_get(f, s->ar.tmr.timer);
-    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    ret = vmstate_load_state(f, &vmstate_pci_status,
-        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
-    return ret;
-}
-
 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 {
     PIIX4PMState *s = opaque;
@@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
     .name = "piix4_pm",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = acpi_load_old,
     .post_load = vmstate_acpi_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index aafd8e0e33..375cb6abe9 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,7 +31,6 @@
 #include "sysemu/kvm.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 static int apic_irq_delivered;
@@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
     apic_init_reset(dev);
 }
 
-/* This function is only used for old state version 1 and 2 */
-static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    APICCommonState *s = opaque;
-    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
-    int i;
-
-    if (version_id > 2) {
-        return -EINVAL;
-    }
-
-    /* XXX: what if the base changes? (registered memory regions) */
-    qemu_get_be32s(f, &s->apicbase);
-    qemu_get_8s(f, &s->id);
-    qemu_get_8s(f, &s->arb_id);
-    qemu_get_8s(f, &s->tpr);
-    qemu_get_be32s(f, &s->spurious_vec);
-    qemu_get_8s(f, &s->log_dest);
-    qemu_get_8s(f, &s->dest_mode);
-    for (i = 0; i < 8; i++) {
-        qemu_get_be32s(f, &s->isr[i]);
-        qemu_get_be32s(f, &s->tmr[i]);
-        qemu_get_be32s(f, &s->irr[i]);
-    }
-    for (i = 0; i < APIC_LVT_NB; i++) {
-        qemu_get_be32s(f, &s->lvt[i]);
-    }
-    qemu_get_be32s(f, &s->esr);
-    qemu_get_be32s(f, &s->icr[0]);
-    qemu_get_be32s(f, &s->icr[1]);
-    qemu_get_be32s(f, &s->divide_conf);
-    s->count_shift = qemu_get_be32(f);
-    qemu_get_be32s(f, &s->initial_count);
-    s->initial_count_load_time = qemu_get_be64(f);
-    s->next_time = qemu_get_be64(f);
-
-    if (version_id >= 2) {
-        s->timer_expiry = qemu_get_be64(f);
-    }
-
-    if (info->post_load) {
-        info->post_load(s);
-    }
-    return 0;
-}
-
 static const VMStateDescription vmstate_apic_common;
 
 static void apic_common_realize(DeviceState *dev, Error **errp)
@@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
     .name = "apic",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = apic_load_old,
     .pre_load = apic_pre_load,
     .pre_save = apic_dispatch_pre_save,
     .post_load = apic_dispatch_post_load,
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 135c645535..2f4cbcbfe9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -33,7 +33,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
 #include "sysemu/reset.h"
@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
     }
 }
 
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
-    PCII440FXState *d = opaque;
-    PCIDevice *pd = PCI_DEVICE(d);
-    int ret, i;
-    uint8_t smm_enabled;
-
-    ret = pci_device_load(pd, f);
-    if (ret < 0)
-        return ret;
-    i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &smm_enabled);
-
-    if (version_id == 2) {
-        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
-            qemu_get_be32(f); /* dummy load for compatibility */
-        }
-    }
-
-    return 0;
-}
-
 static int i440fx_post_load(void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;
@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
     .name = "I440FX",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = i440fx_load_old,
     .post_load = i440fx_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 57bf10cc94..050875b497 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -29,7 +29,6 @@
 #include "qemu/timer.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 /* val must be 0 or 1 */
@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
     }
 };
 
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PITCommonState *pit = opaque;
-    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
-    PITChannelState *s;
-    int i;
-
-    if (version_id != 1) {
-        return -EINVAL;
-    }
-
-    for (i = 0; i < 3; i++) {
-        s = &pit->channels[i];
-        s->count = qemu_get_be32(f);
-        qemu_get_be16s(f, &s->latched_count);
-        qemu_get_8s(f, &s->count_latched);
-        qemu_get_8s(f, &s->status_latched);
-        qemu_get_8s(f, &s->status);
-        qemu_get_8s(f, &s->read_state);
-        qemu_get_8s(f, &s->write_state);
-        qemu_get_8s(f, &s->write_latch);
-        qemu_get_8s(f, &s->rw_mode);
-        qemu_get_8s(f, &s->mode);
-        qemu_get_8s(f, &s->bcd);
-        qemu_get_8s(f, &s->gate);
-        s->count_load_time = qemu_get_be64(f);
-        s->irq_disabled = 0;
-        if (i == 0) {
-            s->next_transition_time = qemu_get_be64(f);
-        }
-    }
-    if (c->post_load) {
-        c->post_load(pit);
-    }
-    return 0;
-}
-
 static int pit_dispatch_pre_save(void *opaque)
 {
     PITCommonState *s = opaque;
@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
     .name = "i8254",
     .version_id = 3,
     .minimum_version_id = 2,
-    .minimum_version_id_old = 1,
-    .load_state_old = pit_load_old,
     .pre_save = pit_dispatch_pre_save,
     .post_load = pit_dispatch_post_load,
     .fields = (VMStateField[]) {
-- 
2.21.0


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[PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

Move the KVM-related call to "sysemu/kvm.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/i386/pc.h | 1 -
 include/sysemu/kvm.h | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 6df4f4b6fb..09e74e7764 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -158,7 +158,6 @@ typedef struct PCMachineClass {
 
 extern DeviceState *isa_pic;
 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
-qemu_irq *kvm_i8259_init(ISABus *bus);
 int pic_read_irq(DeviceState *d);
 int pic_get_output(DeviceState *d);
 
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 9d143282bc..da8aa9f5a8 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
 void kvm_pc_gsi_handler(void *opaque, int n, int level);
 void kvm_pc_setup_irq_routing(bool pci_enabled);
 void kvm_init_irq_routing(KVMState *s);
+qemu_irq *kvm_i8259_init(ISABus *bus);
 
 /**
  * kvm_arch_irqchip_create:
-- 
2.21.0

[PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

Move the KVM-related call to "sysemu/kvm.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/i386/pc.h | 1 -
 include/sysemu/kvm.h | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 6df4f4b6fb..09e74e7764 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -158,7 +158,6 @@ typedef struct PCMachineClass {
 
 extern DeviceState *isa_pic;
 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
-qemu_irq *kvm_i8259_init(ISABus *bus);
 int pic_read_irq(DeviceState *d);
 int pic_get_output(DeviceState *d);
 
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 9d143282bc..da8aa9f5a8 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
 void kvm_pc_gsi_handler(void *opaque, int n, int level);
 void kvm_pc_setup_irq_routing(bool pci_enabled);
 void kvm_init_irq_routing(KVMState *s);
+qemu_irq *kvm_i8259_init(ISABus *bus);
 
 /**
  * kvm_arch_irqchip_create:
-- 
2.21.0

[Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

Move the KVM-related call to "sysemu/kvm.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/i386/pc.h | 1 -
 include/sysemu/kvm.h | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 6df4f4b6fb..09e74e7764 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -158,7 +158,6 @@ typedef struct PCMachineClass {
 
 extern DeviceState *isa_pic;
 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
-qemu_irq *kvm_i8259_init(ISABus *bus);
 int pic_read_irq(DeviceState *d);
 int pic_get_output(DeviceState *d);
 
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 9d143282bc..da8aa9f5a8 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
 void kvm_pc_gsi_handler(void *opaque, int n, int level);
 void kvm_pc_setup_irq_routing(bool pci_enabled);
 void kvm_init_irq_routing(KVMState *s);
+qemu_irq *kvm_i8259_init(ISABus *bus);
 
 /**
  * kvm_arch_irqchip_create:
-- 
2.21.0


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[PATCH 03/32] mc146818rtc: move structure to header file

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are now able to embed a timer in another object.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 30 ------------------------------
 include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 6cb378751b..e40b54e743 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -71,36 +71,6 @@
 #define RTC_CLOCK_RATE            32768
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
 
-#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-
-typedef struct RTCState {
-    ISADevice parent_obj;
-
-    MemoryRegion io;
-    MemoryRegion coalesced_io;
-    uint8_t cmos_data[128];
-    uint8_t cmos_index;
-    int32_t base_year;
-    uint64_t base_rtc;
-    uint64_t last_update;
-    int64_t offset;
-    qemu_irq irq;
-    int it_shift;
-    /* periodic timer */
-    QEMUTimer *periodic_timer;
-    int64_t next_periodic_time;
-    /* update-ended timer */
-    QEMUTimer *update_timer;
-    uint64_t next_alarm_time;
-    uint16_t irq_reinject_on_ack_count;
-    uint32_t irq_coalesced;
-    uint32_t period;
-    QEMUTimer *coalesced_timer;
-    LostTickPolicy lost_tick_policy;
-    Notifier suspend_notifier;
-    QLIST_ENTRY(RTCState) link;
-} RTCState;
-
 static void rtc_set_time(RTCState *s);
 static void rtc_update_time(RTCState *s);
 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index fe6ed63f71..0f1c886e5b 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -1,10 +1,43 @@
 #ifndef MC146818RTC_H
 #define MC146818RTC_H
 
+#include "qapi/qapi-types-misc.h"
+#include "qemu/queue.h"
+#include "qemu/timer.h"
 #include "hw/isa/isa.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
+#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
+
+typedef struct RTCState {
+    ISADevice parent_obj;
+
+    MemoryRegion io;
+    MemoryRegion coalesced_io;
+    uint8_t cmos_data[128];
+    uint8_t cmos_index;
+    int32_t base_year;
+    uint64_t base_rtc;
+    uint64_t last_update;
+    int64_t offset;
+    qemu_irq irq;
+    int it_shift;
+    /* periodic timer */
+    QEMUTimer *periodic_timer;
+    int64_t next_periodic_time;
+    /* update-ended timer */
+    QEMUTimer *update_timer;
+    uint64_t next_alarm_time;
+    uint16_t irq_reinject_on_ack_count;
+    uint32_t irq_coalesced;
+    uint32_t period;
+    QEMUTimer *coalesced_timer;
+    Notifier clock_reset_notifier;
+    LostTickPolicy lost_tick_policy;
+    Notifier suspend_notifier;
+    QLIST_ENTRY(RTCState) link;
+} RTCState;
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
-- 
2.21.0

[PATCH 03/32] mc146818rtc: move structure to header file

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are now able to embed a timer in another object.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 30 ------------------------------
 include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 6cb378751b..e40b54e743 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -71,36 +71,6 @@
 #define RTC_CLOCK_RATE            32768
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
 
-#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-
-typedef struct RTCState {
-    ISADevice parent_obj;
-
-    MemoryRegion io;
-    MemoryRegion coalesced_io;
-    uint8_t cmos_data[128];
-    uint8_t cmos_index;
-    int32_t base_year;
-    uint64_t base_rtc;
-    uint64_t last_update;
-    int64_t offset;
-    qemu_irq irq;
-    int it_shift;
-    /* periodic timer */
-    QEMUTimer *periodic_timer;
-    int64_t next_periodic_time;
-    /* update-ended timer */
-    QEMUTimer *update_timer;
-    uint64_t next_alarm_time;
-    uint16_t irq_reinject_on_ack_count;
-    uint32_t irq_coalesced;
-    uint32_t period;
-    QEMUTimer *coalesced_timer;
-    LostTickPolicy lost_tick_policy;
-    Notifier suspend_notifier;
-    QLIST_ENTRY(RTCState) link;
-} RTCState;
-
 static void rtc_set_time(RTCState *s);
 static void rtc_update_time(RTCState *s);
 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index fe6ed63f71..0f1c886e5b 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -1,10 +1,43 @@
 #ifndef MC146818RTC_H
 #define MC146818RTC_H
 
+#include "qapi/qapi-types-misc.h"
+#include "qemu/queue.h"
+#include "qemu/timer.h"
 #include "hw/isa/isa.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
+#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
+
+typedef struct RTCState {
+    ISADevice parent_obj;
+
+    MemoryRegion io;
+    MemoryRegion coalesced_io;
+    uint8_t cmos_data[128];
+    uint8_t cmos_index;
+    int32_t base_year;
+    uint64_t base_rtc;
+    uint64_t last_update;
+    int64_t offset;
+    qemu_irq irq;
+    int it_shift;
+    /* periodic timer */
+    QEMUTimer *periodic_timer;
+    int64_t next_periodic_time;
+    /* update-ended timer */
+    QEMUTimer *update_timer;
+    uint64_t next_alarm_time;
+    uint16_t irq_reinject_on_ack_count;
+    uint32_t irq_coalesced;
+    uint32_t period;
+    QEMUTimer *coalesced_timer;
+    Notifier clock_reset_notifier;
+    LostTickPolicy lost_tick_policy;
+    Notifier suspend_notifier;
+    QLIST_ENTRY(RTCState) link;
+} RTCState;
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
-- 
2.21.0

[Xen-devel] [PATCH 03/32] mc146818rtc: move structure to header file

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are now able to embed a timer in another object.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 30 ------------------------------
 include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 6cb378751b..e40b54e743 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -71,36 +71,6 @@
 #define RTC_CLOCK_RATE            32768
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
 
-#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-
-typedef struct RTCState {
-    ISADevice parent_obj;
-
-    MemoryRegion io;
-    MemoryRegion coalesced_io;
-    uint8_t cmos_data[128];
-    uint8_t cmos_index;
-    int32_t base_year;
-    uint64_t base_rtc;
-    uint64_t last_update;
-    int64_t offset;
-    qemu_irq irq;
-    int it_shift;
-    /* periodic timer */
-    QEMUTimer *periodic_timer;
-    int64_t next_periodic_time;
-    /* update-ended timer */
-    QEMUTimer *update_timer;
-    uint64_t next_alarm_time;
-    uint16_t irq_reinject_on_ack_count;
-    uint32_t irq_coalesced;
-    uint32_t period;
-    QEMUTimer *coalesced_timer;
-    LostTickPolicy lost_tick_policy;
-    Notifier suspend_notifier;
-    QLIST_ENTRY(RTCState) link;
-} RTCState;
-
 static void rtc_set_time(RTCState *s);
 static void rtc_update_time(RTCState *s);
 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index fe6ed63f71..0f1c886e5b 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -1,10 +1,43 @@
 #ifndef MC146818RTC_H
 #define MC146818RTC_H
 
+#include "qapi/qapi-types-misc.h"
+#include "qemu/queue.h"
+#include "qemu/timer.h"
 #include "hw/isa/isa.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
+#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
+
+typedef struct RTCState {
+    ISADevice parent_obj;
+
+    MemoryRegion io;
+    MemoryRegion coalesced_io;
+    uint8_t cmos_data[128];
+    uint8_t cmos_index;
+    int32_t base_year;
+    uint64_t base_rtc;
+    uint64_t last_update;
+    int64_t offset;
+    qemu_irq irq;
+    int it_shift;
+    /* periodic timer */
+    QEMUTimer *periodic_timer;
+    int64_t next_periodic_time;
+    /* update-ended timer */
+    QEMUTimer *update_timer;
+    uint64_t next_alarm_time;
+    uint16_t irq_reinject_on_ack_count;
+    uint32_t irq_coalesced;
+    uint32_t period;
+    QEMUTimer *coalesced_timer;
+    Notifier clock_reset_notifier;
+    LostTickPolicy lost_tick_policy;
+    Notifier suspend_notifier;
+    QLIST_ENTRY(RTCState) link;
+} RTCState;
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
-- 
2.21.0


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[PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The ISA default number for the RTC devices is not related to its
registers neither. Move this definition to "hw/timer/mc146818rtc.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/timer/mc146818rtc.h      | 2 ++
 include/hw/timer/mc146818rtc_regs.h | 2 --
 tests/rtc-test.c                    | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 0f1c886e5b..17761cf6d9 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -39,6 +39,8 @@ typedef struct RTCState {
     QLIST_ENTRY(RTCState) link;
 } RTCState;
 
+#define RTC_ISA_IRQ 8
+
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
 void rtc_set_memory(ISADevice *dev, int addr, int val);
diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/mc146818rtc_regs.h
index bfbb57e570..631f71cfd9 100644
--- a/include/hw/timer/mc146818rtc_regs.h
+++ b/include/hw/timer/mc146818rtc_regs.h
@@ -27,8 +27,6 @@
 
 #include "qemu/timer.h"
 
-#define RTC_ISA_IRQ 8
-
 #define RTC_SECONDS             0
 #define RTC_SECONDS_ALARM       1
 #define RTC_MINUTES             2
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 6309b0ef6c..18f895690f 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -15,6 +15,7 @@
 
 #include "libqtest-single.h"
 #include "qemu/timer.h"
+#include "hw/timer/mc146818rtc.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
-- 
2.21.0

[PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The ISA default number for the RTC devices is not related to its
registers neither. Move this definition to "hw/timer/mc146818rtc.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/timer/mc146818rtc.h      | 2 ++
 include/hw/timer/mc146818rtc_regs.h | 2 --
 tests/rtc-test.c                    | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 0f1c886e5b..17761cf6d9 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -39,6 +39,8 @@ typedef struct RTCState {
     QLIST_ENTRY(RTCState) link;
 } RTCState;
 
+#define RTC_ISA_IRQ 8
+
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
 void rtc_set_memory(ISADevice *dev, int addr, int val);
diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/mc146818rtc_regs.h
index bfbb57e570..631f71cfd9 100644
--- a/include/hw/timer/mc146818rtc_regs.h
+++ b/include/hw/timer/mc146818rtc_regs.h
@@ -27,8 +27,6 @@
 
 #include "qemu/timer.h"
 
-#define RTC_ISA_IRQ 8
-
 #define RTC_SECONDS             0
 #define RTC_SECONDS_ALARM       1
 #define RTC_MINUTES             2
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 6309b0ef6c..18f895690f 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -15,6 +15,7 @@
 
 #include "libqtest-single.h"
 #include "qemu/timer.h"
+#include "hw/timer/mc146818rtc.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
-- 
2.21.0

[Xen-devel] [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The ISA default number for the RTC devices is not related to its
registers neither. Move this definition to "hw/timer/mc146818rtc.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/hw/timer/mc146818rtc.h      | 2 ++
 include/hw/timer/mc146818rtc_regs.h | 2 --
 tests/rtc-test.c                    | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 0f1c886e5b..17761cf6d9 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -39,6 +39,8 @@ typedef struct RTCState {
     QLIST_ENTRY(RTCState) link;
 } RTCState;
 
+#define RTC_ISA_IRQ 8
+
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
                              qemu_irq intercept_irq);
 void rtc_set_memory(ISADevice *dev, int addr, int val);
diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/mc146818rtc_regs.h
index bfbb57e570..631f71cfd9 100644
--- a/include/hw/timer/mc146818rtc_regs.h
+++ b/include/hw/timer/mc146818rtc_regs.h
@@ -27,8 +27,6 @@
 
 #include "qemu/timer.h"
 
-#define RTC_ISA_IRQ 8
-
 #define RTC_SECONDS             0
 #define RTC_SECONDS_ALARM       1
 #define RTC_MINUTES             2
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 6309b0ef6c..18f895690f 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -15,6 +15,7 @@
 
 #include "libqtest-single.h"
 #include "qemu/timer.h"
+#include "hw/timer/mc146818rtc.h"
 #include "hw/timer/mc146818rtc_regs.h"
 
 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
-- 
2.21.0


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[PATCH 05/32] mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Devices/boards wanting to use the MC146818 RTC don't need
the knowledge its internal registers. Move the "mc146818rtc_regs.h"
inclusion to mc146818rtc.c where it is required.

We can not move this file from include/hw/timer/ to hw/timer/ for
local inclusion because the ACPI FADT table use the RTC_CENTURY
register address.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 1 +
 include/hw/timer/mc146818rtc.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index e40b54e743..0c04b74c2e 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -41,6 +41,7 @@
 #include "qapi/qapi-events-misc-target.h"
 #include "qapi/visitor.h"
 #include "exec/address-spaces.h"
+#include "hw/timer/mc146818rtc_regs.h"
 
 #ifdef TARGET_I386
 #include "hw/i386/apic.h"
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 17761cf6d9..a857dcdc69 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -5,7 +5,6 @@
 #include "qemu/queue.h"
 #include "qemu/timer.h"
 #include "hw/isa/isa.h"
-#include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-- 
2.21.0

[PATCH 05/32] mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Devices/boards wanting to use the MC146818 RTC don't need
the knowledge its internal registers. Move the "mc146818rtc_regs.h"
inclusion to mc146818rtc.c where it is required.

We can not move this file from include/hw/timer/ to hw/timer/ for
local inclusion because the ACPI FADT table use the RTC_CENTURY
register address.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 1 +
 include/hw/timer/mc146818rtc.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index e40b54e743..0c04b74c2e 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -41,6 +41,7 @@
 #include "qapi/qapi-events-misc-target.h"
 #include "qapi/visitor.h"
 #include "exec/address-spaces.h"
+#include "hw/timer/mc146818rtc_regs.h"
 
 #ifdef TARGET_I386
 #include "hw/i386/apic.h"
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 17761cf6d9..a857dcdc69 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -5,7 +5,6 @@
 #include "qemu/queue.h"
 #include "qemu/timer.h"
 #include "hw/isa/isa.h"
-#include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-- 
2.21.0

[Xen-devel] [PATCH 05/32] mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Devices/boards wanting to use the MC146818 RTC don't need
the knowledge its internal registers. Move the "mc146818rtc_regs.h"
inclusion to mc146818rtc.c where it is required.

We can not move this file from include/hw/timer/ to hw/timer/ for
local inclusion because the ACPI FADT table use the RTC_CENTURY
register address.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c         | 1 +
 include/hw/timer/mc146818rtc.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index e40b54e743..0c04b74c2e 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -41,6 +41,7 @@
 #include "qapi/qapi-events-misc-target.h"
 #include "qapi/visitor.h"
 #include "exec/address-spaces.h"
+#include "hw/timer/mc146818rtc_regs.h"
 
 #ifdef TARGET_I386
 #include "hw/i386/apic.h"
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 17761cf6d9..a857dcdc69 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -5,7 +5,6 @@
 #include "qemu/queue.h"
 #include "qemu/timer.h"
 #include "hw/isa/isa.h"
-#include "hw/timer/mc146818rtc_regs.h"
 
 #define TYPE_MC146818_RTC "mc146818rtc"
 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-- 
2.21.0


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[PATCH 06/32] mc146818rtc: always register rtc to rtc list

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are not required anymore to use rtc_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-5-hpoussin@reactos.org>
[PMD: rebased, fix OBJECT() value]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 0c04b74c2e..8f7d3a9cdf 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -963,17 +963,16 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 
     qdev_init_gpio_out(dev, &s->irq, 1);
+    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 }
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 {
     DeviceState *dev;
     ISADevice *isadev;
-    RTCState *s;
 
     isadev = isa_create(bus, TYPE_MC146818_RTC);
     dev = DEVICE(isadev);
-    s = MC146818_RTC(isadev);
     qdev_prop_set_int32(dev, "base_year", base_year);
     qdev_init_nofail(dev);
     if (intercept_irq) {
@@ -981,9 +980,8 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
     } else {
         isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
     }
-    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 
-    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s),
+    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
                               "date", NULL);
 
     return isadev;
@@ -1015,8 +1013,6 @@ static void rtc_class_initfn(ObjectClass *klass, void *data)
     dc->reset = rtc_resetdev;
     dc->vmsd = &vmstate_rtc;
     dc->props = mc146818rtc_properties;
-    /* Reason: needs to be wired up by rtc_init() */
-    dc->user_creatable = false;
 }
 
 static const TypeInfo mc146818rtc_info = {
-- 
2.21.0

[PATCH 06/32] mc146818rtc: always register rtc to rtc list

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are not required anymore to use rtc_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-5-hpoussin@reactos.org>
[PMD: rebased, fix OBJECT() value]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 0c04b74c2e..8f7d3a9cdf 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -963,17 +963,16 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 
     qdev_init_gpio_out(dev, &s->irq, 1);
+    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 }
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 {
     DeviceState *dev;
     ISADevice *isadev;
-    RTCState *s;
 
     isadev = isa_create(bus, TYPE_MC146818_RTC);
     dev = DEVICE(isadev);
-    s = MC146818_RTC(isadev);
     qdev_prop_set_int32(dev, "base_year", base_year);
     qdev_init_nofail(dev);
     if (intercept_irq) {
@@ -981,9 +980,8 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
     } else {
         isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
     }
-    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 
-    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s),
+    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
                               "date", NULL);
 
     return isadev;
@@ -1015,8 +1013,6 @@ static void rtc_class_initfn(ObjectClass *klass, void *data)
     dc->reset = rtc_resetdev;
     dc->vmsd = &vmstate_rtc;
     dc->props = mc146818rtc_properties;
-    /* Reason: needs to be wired up by rtc_init() */
-    dc->user_creatable = false;
 }
 
 static const TypeInfo mc146818rtc_info = {
-- 
2.21.0

[Xen-devel] [PATCH 06/32] mc146818rtc: always register rtc to rtc list

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

We are not required anymore to use rtc_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-5-hpoussin@reactos.org>
[PMD: rebased, fix OBJECT() value]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/timer/mc146818rtc.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 0c04b74c2e..8f7d3a9cdf 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -963,17 +963,16 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 
     qdev_init_gpio_out(dev, &s->irq, 1);
+    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 }
 
 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 {
     DeviceState *dev;
     ISADevice *isadev;
-    RTCState *s;
 
     isadev = isa_create(bus, TYPE_MC146818_RTC);
     dev = DEVICE(isadev);
-    s = MC146818_RTC(isadev);
     qdev_prop_set_int32(dev, "base_year", base_year);
     qdev_init_nofail(dev);
     if (intercept_irq) {
@@ -981,9 +980,8 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
     } else {
         isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
     }
-    QLIST_INSERT_HEAD(&rtc_devices, s, link);
 
-    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s),
+    object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
                               "date", NULL);
 
     return isadev;
@@ -1015,8 +1013,6 @@ static void rtc_class_initfn(ObjectClass *klass, void *data)
     dc->reset = rtc_resetdev;
     dc->vmsd = &vmstate_rtc;
     dc->props = mc146818rtc_properties;
-    /* Reason: needs to be wired up by rtc_init() */
-    dc->user_creatable = false;
 }
 
 static const TypeInfo mc146818rtc_info = {
-- 
2.21.0


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[PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The PIIX4 Southbridge is not used by the PC machine,
but by the Malta board (MIPS). Add a new section to
keep it covered.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 MAINTAINERS | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fe4dc51b08..c9f625fc2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
@@ -1716,6 +1715,12 @@ F: hw/display/edid*
 F: include/hw/display/edid.h
 F: qemu-edid.c
 
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <hpoussin@reactos.org>
+M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+S: Maintained
+F: hw/isa/piix4.c
+
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
 R: Laszlo Ersek <lersek@redhat.com>
-- 
2.21.0

[PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The PIIX4 Southbridge is not used by the PC machine,
but by the Malta board (MIPS). Add a new section to
keep it covered.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 MAINTAINERS | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fe4dc51b08..c9f625fc2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
@@ -1716,6 +1715,12 @@ F: hw/display/edid*
 F: include/hw/display/edid.h
 F: qemu-edid.c
 
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <hpoussin@reactos.org>
+M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+S: Maintained
+F: hw/isa/piix4.c
+
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
 R: Laszlo Ersek <lersek@redhat.com>
-- 
2.21.0

[Xen-devel] [PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The PIIX4 Southbridge is not used by the PC machine,
but by the Malta board (MIPS). Add a new section to
keep it covered.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 MAINTAINERS | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fe4dc51b08..c9f625fc2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
@@ -1716,6 +1715,12 @@ F: hw/display/edid*
 F: include/hw/display/edid.h
 F: qemu-edid.c
 
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <hpoussin@reactos.org>
+M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+S: Maintained
+F: hw/isa/piix4.c
+
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
 R: Laszlo Ersek <lersek@redhat.com>
-- 
2.21.0


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[PATCH 08/32] piix4: rename some variables in realize function

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

PIIX4 structure is now 's'
PCI device is now 'pci_dev'
DeviceState is now 'dev'

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 3294056cd5..4202243e41 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
-static void piix4_realize(PCIDevice *dev, Error **errp)
+static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
-    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+    DeviceState *dev = DEVICE(pci_dev);
+    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
 
-    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
-                     pci_address_space_io(dev), errp)) {
+    if (!isa_bus_new(dev, pci_address_space(pci_dev),
+                     pci_address_space_io(pci_dev), errp)) {
         return;
     }
-    piix4_dev = &d->dev;
-    qemu_register_reset(piix4_reset, d);
+    piix4_dev = pci_dev;
+    qemu_register_reset(piix4_reset, s);
 }
 
 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-- 
2.21.0

[PATCH 08/32] piix4: rename some variables in realize function

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

PIIX4 structure is now 's'
PCI device is now 'pci_dev'
DeviceState is now 'dev'

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 3294056cd5..4202243e41 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
-static void piix4_realize(PCIDevice *dev, Error **errp)
+static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
-    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+    DeviceState *dev = DEVICE(pci_dev);
+    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
 
-    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
-                     pci_address_space_io(dev), errp)) {
+    if (!isa_bus_new(dev, pci_address_space(pci_dev),
+                     pci_address_space_io(pci_dev), errp)) {
         return;
     }
-    piix4_dev = &d->dev;
-    qemu_register_reset(piix4_reset, d);
+    piix4_dev = pci_dev;
+    qemu_register_reset(piix4_reset, s);
 }
 
 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-- 
2.21.0

[Xen-devel] [PATCH 08/32] piix4: rename some variables in realize function

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

PIIX4 structure is now 's'
PCI device is now 'pci_dev'
DeviceState is now 'dev'

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 3294056cd5..4202243e41 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
-static void piix4_realize(PCIDevice *dev, Error **errp)
+static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
-    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+    DeviceState *dev = DEVICE(pci_dev);
+    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
 
-    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
-                     pci_address_space_io(dev), errp)) {
+    if (!isa_bus_new(dev, pci_address_space(pci_dev),
+                     pci_address_space_io(pci_dev), errp)) {
         return;
     }
-    piix4_dev = &d->dev;
-    qemu_register_reset(piix4_reset, d);
+    piix4_dev = pci_dev;
+    qemu_register_reset(piix4_reset, s);
 }
 
 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-- 
2.21.0


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[PATCH 09/32] piix4: add Reset Control Register

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
[PMD: rebased, updated includes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 4202243e41..6e2d9b9774 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -2,6 +2,7 @@
  * QEMU PIIX4 PCI Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,11 +30,16 @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
+#include "sysemu/runstate.h"
 
 PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+
+    /* Reset Control Register */
+    MemoryRegion rcr_mem;
+    uint8_t rcr;
 } PIIX4State;
 
 #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
@@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+                            unsigned int len)
+{
+    PIIX4State *s = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+    PIIX4State *s = opaque;
+    return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+    .read = piix4_rcr_read,
+    .write = piix4_rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 1,
+    },
+};
+
 static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
@@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
                      pci_address_space_io(pci_dev), errp)) {
         return;
     }
+
+    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+                          "reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
+                                        &s->rcr_mem, 1);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
-- 
2.21.0

[PATCH 09/32] piix4: add Reset Control Register

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
[PMD: rebased, updated includes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 4202243e41..6e2d9b9774 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -2,6 +2,7 @@
  * QEMU PIIX4 PCI Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,11 +30,16 @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
+#include "sysemu/runstate.h"
 
 PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+
+    /* Reset Control Register */
+    MemoryRegion rcr_mem;
+    uint8_t rcr;
 } PIIX4State;
 
 #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
@@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+                            unsigned int len)
+{
+    PIIX4State *s = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+    PIIX4State *s = opaque;
+    return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+    .read = piix4_rcr_read,
+    .write = piix4_rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 1,
+    },
+};
+
 static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
@@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
                      pci_address_space_io(pci_dev), errp)) {
         return;
     }
+
+    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+                          "reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
+                                        &s->rcr_mem, 1);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
-- 
2.21.0

[Xen-devel] [PATCH 09/32] piix4: add Reset Control Register

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
[PMD: rebased, updated includes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 4202243e41..6e2d9b9774 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -2,6 +2,7 @@
  * QEMU PIIX4 PCI Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,11 +30,16 @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
+#include "sysemu/runstate.h"
 
 PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+
+    /* Reset Control Register */
+    MemoryRegion rcr_mem;
+    uint8_t rcr;
 } PIIX4State;
 
 #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
@@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+                            unsigned int len)
+{
+    PIIX4State *s = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+    PIIX4State *s = opaque;
+    return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+    .read = piix4_rcr_read,
+    .write = piix4_rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 1,
+    },
+};
+
 static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
@@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
                      pci_address_space_io(pci_dev), errp)) {
         return;
     }
+
+    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+                          "reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
+                                        &s->rcr_mem, 1);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
-- 
2.21.0


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[PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
Remove i8259 instanciated in malta board, to not have it twice.

We can also remove the now unused piix4_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 41 ++++++++++++++++++++++++++++++-----------
 hw/mips/mips_malta.c | 32 +++++++++++++-------------------
 include/hw/i386/pc.h |  1 -
 3 files changed, 43 insertions(+), 31 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 6e2d9b9774..1cfc51335a 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+    qemu_irq cpu_intr;
+    qemu_irq *isa;
 
     /* Reset Control Register */
     MemoryRegion rcr_mem;
@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->isa[irq], level);
+}
+
 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
                             unsigned int len)
 {
@@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
+    ISABus *isa_bus;
+    qemu_irq *i8259_out_irq;
 
-    if (!isa_bus_new(dev, pci_address_space(pci_dev),
-                     pci_address_space_io(pci_dev), errp)) {
+    isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
+                          pci_address_space_io(pci_dev), errp);
+    if (!isa_bus) {
         return;
     }
 
+    qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa", ISA_NUM_IRQS);
+    qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
+
     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
                           "reset-control", 1);
     memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
                                         &s->rcr_mem, 1);
 
+    /* initialize i8259 pic */
+    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+    s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+    /* initialize ISA irqs */
+    isa_bus_irqs(isa_bus, s->isa);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
 
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
-    PCIDevice *d;
-
-    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
-    return d->devfn;
-}
-
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..7d25ab6c23 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -97,7 +97,7 @@ typedef struct {
     SysBusDevice parent_obj;
 
     MIPSCPSState cps;
-    qemu_irq *i8259;
+    qemu_irq i8259[16];
 } MaltaState;
 
 static ISADevice *pit;
@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int64_t kernel_entry, bootloader_run_addr;
     PCIBus *pci_bus;
     ISABus *isa_bus;
-    qemu_irq *isa_irq;
     qemu_irq cbus_irq, i8259_irq;
+    PCIDevice *pci;
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
     /* Board ID = 0x420 (Malta Board with CoreLV) */
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
-    /*
-     * We have a circular dependency problem: pci_bus depends on isa_irq,
-     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
-     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
-     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
-     * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
-     */
-    isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
     /* Northbridge */
-    pci_bus = gt64120_register(isa_irq);
+    pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
-    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, "PIIX4");
+    dev = DEVICE(pci);
+    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    piix4_devfn = pci->devfn;
 
-    /*
-     * Interrupt controller
-     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
-     */
-    s->i8259 = i8259_init(isa_bus, i8259_irq);
+    /* Interrupt controller */
+    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+    for (int i = 0; i < ISA_NUM_IRQS; i++) {
+        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+    }
 
-    isa_bus_irqs(isa_bus, s->i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09e74e7764..a95eab0d8a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 PCIBus *find_i440fx(void);
 /* piix4.c */
 extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
-- 
2.21.0

[PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
Remove i8259 instanciated in malta board, to not have it twice.

We can also remove the now unused piix4_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 41 ++++++++++++++++++++++++++++++-----------
 hw/mips/mips_malta.c | 32 +++++++++++++-------------------
 include/hw/i386/pc.h |  1 -
 3 files changed, 43 insertions(+), 31 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 6e2d9b9774..1cfc51335a 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+    qemu_irq cpu_intr;
+    qemu_irq *isa;
 
     /* Reset Control Register */
     MemoryRegion rcr_mem;
@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->isa[irq], level);
+}
+
 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
                             unsigned int len)
 {
@@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
+    ISABus *isa_bus;
+    qemu_irq *i8259_out_irq;
 
-    if (!isa_bus_new(dev, pci_address_space(pci_dev),
-                     pci_address_space_io(pci_dev), errp)) {
+    isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
+                          pci_address_space_io(pci_dev), errp);
+    if (!isa_bus) {
         return;
     }
 
+    qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa", ISA_NUM_IRQS);
+    qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
+
     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
                           "reset-control", 1);
     memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
                                         &s->rcr_mem, 1);
 
+    /* initialize i8259 pic */
+    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+    s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+    /* initialize ISA irqs */
+    isa_bus_irqs(isa_bus, s->isa);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
 
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
-    PCIDevice *d;
-
-    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
-    return d->devfn;
-}
-
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..7d25ab6c23 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -97,7 +97,7 @@ typedef struct {
     SysBusDevice parent_obj;
 
     MIPSCPSState cps;
-    qemu_irq *i8259;
+    qemu_irq i8259[16];
 } MaltaState;
 
 static ISADevice *pit;
@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int64_t kernel_entry, bootloader_run_addr;
     PCIBus *pci_bus;
     ISABus *isa_bus;
-    qemu_irq *isa_irq;
     qemu_irq cbus_irq, i8259_irq;
+    PCIDevice *pci;
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
     /* Board ID = 0x420 (Malta Board with CoreLV) */
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
-    /*
-     * We have a circular dependency problem: pci_bus depends on isa_irq,
-     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
-     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
-     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
-     * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
-     */
-    isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
     /* Northbridge */
-    pci_bus = gt64120_register(isa_irq);
+    pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
-    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, "PIIX4");
+    dev = DEVICE(pci);
+    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    piix4_devfn = pci->devfn;
 
-    /*
-     * Interrupt controller
-     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
-     */
-    s->i8259 = i8259_init(isa_bus, i8259_irq);
+    /* Interrupt controller */
+    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+    for (int i = 0; i < ISA_NUM_IRQS; i++) {
+        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+    }
 
-    isa_bus_irqs(isa_bus, s->i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09e74e7764..a95eab0d8a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 PCIBus *find_i440fx(void);
 /* piix4.c */
 extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
-- 
2.21.0

[Xen-devel] [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
Remove i8259 instanciated in malta board, to not have it twice.

We can also remove the now unused piix4_init() function.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 41 ++++++++++++++++++++++++++++++-----------
 hw/mips/mips_malta.c | 32 +++++++++++++-------------------
 include/hw/i386/pc.h |  1 -
 3 files changed, 43 insertions(+), 31 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 6e2d9b9774..1cfc51335a 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+    qemu_irq cpu_intr;
+    qemu_irq *isa;
 
     /* Reset Control Register */
     MemoryRegion rcr_mem;
@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->isa[irq], level);
+}
+
 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
                             unsigned int len)
 {
@@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
 {
     DeviceState *dev = DEVICE(pci_dev);
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
+    ISABus *isa_bus;
+    qemu_irq *i8259_out_irq;
 
-    if (!isa_bus_new(dev, pci_address_space(pci_dev),
-                     pci_address_space_io(pci_dev), errp)) {
+    isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
+                          pci_address_space_io(pci_dev), errp);
+    if (!isa_bus) {
         return;
     }
 
+    qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa", ISA_NUM_IRQS);
+    qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
+
     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
                           "reset-control", 1);
     memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,
                                         &s->rcr_mem, 1);
 
+    /* initialize i8259 pic */
+    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+    s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+    /* initialize ISA irqs */
+    isa_bus_irqs(isa_bus, s->isa);
+
     piix4_dev = pci_dev;
     qemu_register_reset(piix4_reset, s);
 }
 
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
-    PCIDevice *d;
-
-    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
-    return d->devfn;
-}
-
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..7d25ab6c23 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -97,7 +97,7 @@ typedef struct {
     SysBusDevice parent_obj;
 
     MIPSCPSState cps;
-    qemu_irq *i8259;
+    qemu_irq i8259[16];
 } MaltaState;
 
 static ISADevice *pit;
@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int64_t kernel_entry, bootloader_run_addr;
     PCIBus *pci_bus;
     ISABus *isa_bus;
-    qemu_irq *isa_irq;
     qemu_irq cbus_irq, i8259_irq;
+    PCIDevice *pci;
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
     /* Board ID = 0x420 (Malta Board with CoreLV) */
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
-    /*
-     * We have a circular dependency problem: pci_bus depends on isa_irq,
-     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
-     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
-     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
-     * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
-     */
-    isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
     /* Northbridge */
-    pci_bus = gt64120_register(isa_irq);
+    pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
-    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, "PIIX4");
+    dev = DEVICE(pci);
+    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    piix4_devfn = pci->devfn;
 
-    /*
-     * Interrupt controller
-     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
-     */
-    s->i8259 = i8259_init(isa_bus, i8259_irq);
+    /* Interrupt controller */
+    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+    for (int i = 0; i < ISA_NUM_IRQS; i++) {
+        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+    }
 
-    isa_bus_irqs(isa_bus, s->i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09e74e7764..a95eab0d8a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 PCIBus *find_i440fx(void);
 /* piix4.c */
 extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
-- 
2.21.0


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[PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

This function isn't used anymore.

This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/core/irq.c    | 14 --------------
 include/hw/irq.h |  5 -----
 2 files changed, 19 deletions(-)

diff --git a/hw/core/irq.c b/hw/core/irq.c
index 7cc0295d0e..fb3045b912 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
     return qemu_allocate_irq(qemu_splitirq, s, 0);
 }
 
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
-    qemu_irq **target = opaque;
-
-    if (*target) {
-        qemu_set_irq((*target)[n], level);
-    }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
-    return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index fe527f6f51..24ba0ece11 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
  */
 qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
 
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
-- 
2.21.0

[PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

This function isn't used anymore.

This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/core/irq.c    | 14 --------------
 include/hw/irq.h |  5 -----
 2 files changed, 19 deletions(-)

diff --git a/hw/core/irq.c b/hw/core/irq.c
index 7cc0295d0e..fb3045b912 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
     return qemu_allocate_irq(qemu_splitirq, s, 0);
 }
 
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
-    qemu_irq **target = opaque;
-
-    if (*target) {
-        qemu_set_irq((*target)[n], level);
-    }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
-    return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index fe527f6f51..24ba0ece11 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
  */
 qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
 
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
-- 
2.21.0

[Xen-devel] [PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

This function isn't used anymore.

This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/core/irq.c    | 14 --------------
 include/hw/irq.h |  5 -----
 2 files changed, 19 deletions(-)

diff --git a/hw/core/irq.c b/hw/core/irq.c
index 7cc0295d0e..fb3045b912 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
     return qemu_allocate_irq(qemu_splitirq, s, 0);
 }
 
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
-    qemu_irq **target = opaque;
-
-    if (*target) {
-        qemu_set_irq((*target)[n], level);
-    }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
-    return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index fe527f6f51..24ba0ece11 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
  */
 qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
 
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
-- 
2.21.0


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[PATCH 12/32] piix4: rename PIIX4 object to piix4-isa

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Other piix4 parts are already named piix4-ide and piix4-usb-uhci.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 1 -
 hw/mips/mips_malta.c | 2 +-
 include/hw/isa/isa.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1cfc51335a..c3a2bd0d70 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
     uint8_t rcr;
 } PIIX4State;
 
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 7d25ab6c23..e499b7a6bb 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, "PIIX4");
+                                          true, TYPE_PIIX4_PCI_DEVICE);
     dev = DEVICE(pci);
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
     piix4_devfn = pci->devfn;
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 018ada4f6f..79f703fd6c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
     return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
 }
 
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
 #endif
-- 
2.21.0

[PATCH 12/32] piix4: rename PIIX4 object to piix4-isa

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Other piix4 parts are already named piix4-ide and piix4-usb-uhci.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 1 -
 hw/mips/mips_malta.c | 2 +-
 include/hw/isa/isa.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1cfc51335a..c3a2bd0d70 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
     uint8_t rcr;
 } PIIX4State;
 
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 7d25ab6c23..e499b7a6bb 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, "PIIX4");
+                                          true, TYPE_PIIX4_PCI_DEVICE);
     dev = DEVICE(pci);
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
     piix4_devfn = pci->devfn;
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 018ada4f6f..79f703fd6c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
     return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
 }
 
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
 #endif
-- 
2.21.0

[Xen-devel] [PATCH 12/32] piix4: rename PIIX4 object to piix4-isa

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Other piix4 parts are already named piix4-ide and piix4-usb-uhci.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 1 -
 hw/mips/mips_malta.c | 2 +-
 include/hw/isa/isa.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1cfc51335a..c3a2bd0d70 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
     uint8_t rcr;
 } PIIX4State;
 
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 7d25ab6c23..e499b7a6bb 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, "PIIX4");
+                                          true, TYPE_PIIX4_PCI_DEVICE);
     dev = DEVICE(pci);
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
     piix4_devfn = pci->devfn;
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 018ada4f6f..79f703fd6c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
     return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
 }
 
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
 #endif
-- 
2.21.0


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[PATCH 13/32] piix4: convert reset function to QOM

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20180106153730.30313-15-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index c3a2bd0d70..8998b0ca47 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -48,10 +48,10 @@ typedef struct PIIX4State {
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
-static void piix4_reset(void *opaque)
+static void piix4_reset(DeviceState *dev)
 {
-    PIIX4State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
+    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+    uint8_t *pci_conf = s->dev.config;
 
     pci_conf[0x04] = 0x07; // master, memory and I/O
     pci_conf[0x05] = 0x00;
@@ -165,7 +165,6 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     isa_bus_irqs(isa_bus, s->isa);
 
     piix4_dev = pci_dev;
-    qemu_register_reset(piix4_reset, s);
 }
 
 static void piix4_class_init(ObjectClass *klass, void *data)
@@ -177,6 +176,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
     k->class_id = PCI_CLASS_BRIDGE_ISA;
+    dc->reset = piix4_reset;
     dc->desc = "ISA bridge";
     dc->vmsd = &vmstate_piix4;
     /*
-- 
2.21.0

[PATCH 13/32] piix4: convert reset function to QOM

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20180106153730.30313-15-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index c3a2bd0d70..8998b0ca47 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -48,10 +48,10 @@ typedef struct PIIX4State {
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
-static void piix4_reset(void *opaque)
+static void piix4_reset(DeviceState *dev)
 {
-    PIIX4State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
+    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+    uint8_t *pci_conf = s->dev.config;
 
     pci_conf[0x04] = 0x07; // master, memory and I/O
     pci_conf[0x05] = 0x00;
@@ -165,7 +165,6 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     isa_bus_irqs(isa_bus, s->isa);
 
     piix4_dev = pci_dev;
-    qemu_register_reset(piix4_reset, s);
 }
 
 static void piix4_class_init(ObjectClass *klass, void *data)
@@ -177,6 +176,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
     k->class_id = PCI_CLASS_BRIDGE_ISA;
+    dc->reset = piix4_reset;
     dc->desc = "ISA bridge";
     dc->vmsd = &vmstate_piix4;
     /*
-- 
2.21.0

[Xen-devel] [PATCH 13/32] piix4: convert reset function to QOM

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20180106153730.30313-15-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index c3a2bd0d70..8998b0ca47 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -48,10 +48,10 @@ typedef struct PIIX4State {
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
 
-static void piix4_reset(void *opaque)
+static void piix4_reset(DeviceState *dev)
 {
-    PIIX4State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
+    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+    uint8_t *pci_conf = s->dev.config;
 
     pci_conf[0x04] = 0x07; // master, memory and I/O
     pci_conf[0x05] = 0x00;
@@ -165,7 +165,6 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     isa_bus_irqs(isa_bus, s->isa);
 
     piix4_dev = pci_dev;
-    qemu_register_reset(piix4_reset, s);
 }
 
 static void piix4_class_init(ObjectClass *klass, void *data)
@@ -177,6 +176,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
     k->vendor_id = PCI_VENDOR_ID_INTEL;
     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
     k->class_id = PCI_CLASS_BRIDGE_ISA;
+    dc->reset = piix4_reset;
     dc->desc = "ISA bridge";
     dc->vmsd = &vmstate_piix4;
     /*
-- 
2.21.0


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[PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8257 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8998b0ca47..1bc91b590c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -29,6 +29,7 @@
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -164,6 +165,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* DMA */
+    i8257_dma_init(isa_bus, 0);
+
     piix4_dev = pci_dev;
 }
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e499b7a6bb..df247177ca 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,7 +28,6 @@
 #include "cpu.h"
 #include "hw/i386/pc.h"
 #include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
 #include "hw/boards.h"
@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
-    i8257_dma_init(isa_bus, 0);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0

[PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8257 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8998b0ca47..1bc91b590c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -29,6 +29,7 @@
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -164,6 +165,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* DMA */
+    i8257_dma_init(isa_bus, 0);
+
     piix4_dev = pci_dev;
 }
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e499b7a6bb..df247177ca 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,7 +28,6 @@
 #include "cpu.h"
 #include "hw/i386/pc.h"
 #include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
 #include "hw/boards.h"
@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
-    i8257_dma_init(isa_bus, 0);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0

[Xen-devel] [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8257 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8998b0ca47..1bc91b590c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -29,6 +29,7 @@
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -164,6 +165,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* DMA */
+    i8257_dma_init(isa_bus, 0);
+
     piix4_dev = pci_dev;
 }
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e499b7a6bb..df247177ca 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,7 +28,6 @@
 #include "cpu.h"
 #include "hw/i386/pc.h"
 #include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
 #include "hw/boards.h"
@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
-    i8257_dma_init(isa_bus, 0);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0


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[PATCH 15/32] piix4: add a i8254 pit controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8254 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1bc91b590c..0b0a0ecab1 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,6 +30,7 @@
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -165,6 +166,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* initialize pit */
+    i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index df247177ca..16d7a0e785 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -45,7 +45,6 @@
 #include "hw/loader.h"
 #include "elf.h"
 #include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -99,8 +98,6 @@ typedef struct {
     qemu_irq i8259[16];
 } MaltaState;
 
-static ISADevice *pit;
-
 static struct _loaderparams {
     int ram_size, ram_low_size;
     const char *kernel_filename;
@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0

[PATCH 15/32] piix4: add a i8254 pit controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8254 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1bc91b590c..0b0a0ecab1 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,6 +30,7 @@
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -165,6 +166,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* initialize pit */
+    i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index df247177ca..16d7a0e785 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -45,7 +45,6 @@
 #include "hw/loader.h"
 #include "elf.h"
 #include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -99,8 +98,6 @@ typedef struct {
     qemu_irq i8259[16];
 } MaltaState;
 
-static ISADevice *pit;
-
 static struct _loaderparams {
     int ram_size, ram_low_size;
     const char *kernel_filename;
@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0

[Xen-devel] [PATCH 15/32] piix4: add a i8254 pit controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Hervé Poussineau <hpoussin@reactos.org>

Remove i8254 instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 1bc91b590c..0b0a0ecab1 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,6 +30,7 @@
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -165,6 +166,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* initialize pit */
+    i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index df247177ca..16d7a0e785 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -45,7 +45,6 @@
 #include "hw/loader.h"
 #include "elf.h"
 #include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -99,8 +98,6 @@ typedef struct {
     qemu_irq i8259[16];
 } MaltaState;
 
-static ISADevice *pit;
-
 static struct _loaderparams {
     int ram_size, ram_low_size;
     const char *kernel_filename;
@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
-- 
2.21.0


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

[PATCH 16/32] piix4: add a mc146818rtc controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Remove mc146818rtc instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
[PMD: rebased, set RTC base_year to 2000]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                   |  3 ++-
 hw/acpi/piix4.c               |  2 +-
 hw/i386/acpi-build.c          |  3 +--
 hw/i386/pc_piix.c             |  1 +
 hw/isa/piix4.c                | 22 ++++++++++++++++++++++
 hw/mips/mips_malta.c          |  4 +---
 include/hw/acpi/piix4.h       |  6 ------
 include/hw/i386/pc.h          |  6 ------
 include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
 9 files changed, 48 insertions(+), 19 deletions(-)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/southbridge/piix.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c9f625fc2e..556f58bd8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
 F: hw/acpi/ich9.c
 F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
 F: hw/misc/sga.c
 F: hw/isa/apm.c
 F: include/hw/isa/apm.h
@@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
 M: Philippe Mathieu-Daudé <f4bug@amsat.org>
 S: Maintained
 F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
 
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 1d29d438c7..27270621ab 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -21,6 +21,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/isa/apm.h"
 #include "hw/i2c/pm_smbus.h"
@@ -33,7 +34,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/acpi/cpu_hotplug.h"
 #include "hw/acpi/cpu.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4e0f9f425a..aa6fe61191 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -34,7 +34,6 @@
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"
@@ -52,7 +51,7 @@
 #include "sysemu/reset.h"
 
 /* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/i386/ich9.h"
 #include "hw/pci/pci_bus.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72124..431965d921 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
 #include "hw/pci/pci.h"
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0b0a0ecab1..9f554747af 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
@@ -31,6 +32,7 @@
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -42,6 +44,7 @@ typedef struct PIIX4State {
     qemu_irq cpu_intr;
     qemu_irq *isa;
 
+    RTCState rtc;
     /* Reset Control Register */
     MemoryRegion rcr_mem;
     uint8_t rcr;
@@ -144,6 +147,7 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
     ISABus *isa_bus;
     qemu_irq *i8259_out_irq;
+    Error *err = NULL;
 
     isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
                           pci_address_space_io(pci_dev), errp);
@@ -172,9 +176,26 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
+    /* RTC */
+    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
     piix4_dev = pci_dev;
 }
 
+static void piix4_init(Object *obj)
+{
+    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -199,6 +220,7 @@ static const TypeInfo piix4_info = {
     .name          = TYPE_PIIX4_PCI_DEVICE,
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
+    .instance_init = piix4_init,
     .class_init    = piix4_class_init,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 16d7a0e785..528c34a1c3 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -26,7 +26,7 @@
 #include "qemu/units.h"
 #include "qemu-common.h"
 #include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/isa/superio.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
@@ -44,7 +44,6 @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "elf.h"
-#include "hw/timer/mc146818rtc.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
deleted file mode 100644
index 028bb53e3d..0000000000
--- a/include/hw/acpi/piix4.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index a95eab0d8a..c671c9fd2a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -244,12 +244,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 
 #define PORT92_A20_LINE "a20"
 
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm);
-
 /* hpet.c */
 extern int no_hpet;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
new file mode 100644
index 0000000000..b8ce26fec4
--- /dev/null
+++ b/include/hw/southbridge/piix.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                      qemu_irq sci_irq, qemu_irq smi_irq,
+                      int smm_enabled, DeviceState **piix4_pm);
+
+#endif
-- 
2.21.0

[PATCH 16/32] piix4: add a mc146818rtc controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Remove mc146818rtc instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
[PMD: rebased, set RTC base_year to 2000]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                   |  3 ++-
 hw/acpi/piix4.c               |  2 +-
 hw/i386/acpi-build.c          |  3 +--
 hw/i386/pc_piix.c             |  1 +
 hw/isa/piix4.c                | 22 ++++++++++++++++++++++
 hw/mips/mips_malta.c          |  4 +---
 include/hw/acpi/piix4.h       |  6 ------
 include/hw/i386/pc.h          |  6 ------
 include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
 9 files changed, 48 insertions(+), 19 deletions(-)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/southbridge/piix.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c9f625fc2e..556f58bd8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
 F: hw/acpi/ich9.c
 F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
 F: hw/misc/sga.c
 F: hw/isa/apm.c
 F: include/hw/isa/apm.h
@@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
 M: Philippe Mathieu-Daudé <f4bug@amsat.org>
 S: Maintained
 F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
 
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 1d29d438c7..27270621ab 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -21,6 +21,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/isa/apm.h"
 #include "hw/i2c/pm_smbus.h"
@@ -33,7 +34,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/acpi/cpu_hotplug.h"
 #include "hw/acpi/cpu.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4e0f9f425a..aa6fe61191 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -34,7 +34,6 @@
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"
@@ -52,7 +51,7 @@
 #include "sysemu/reset.h"
 
 /* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/i386/ich9.h"
 #include "hw/pci/pci_bus.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72124..431965d921 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
 #include "hw/pci/pci.h"
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0b0a0ecab1..9f554747af 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
@@ -31,6 +32,7 @@
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -42,6 +44,7 @@ typedef struct PIIX4State {
     qemu_irq cpu_intr;
     qemu_irq *isa;
 
+    RTCState rtc;
     /* Reset Control Register */
     MemoryRegion rcr_mem;
     uint8_t rcr;
@@ -144,6 +147,7 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
     ISABus *isa_bus;
     qemu_irq *i8259_out_irq;
+    Error *err = NULL;
 
     isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
                           pci_address_space_io(pci_dev), errp);
@@ -172,9 +176,26 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
+    /* RTC */
+    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
     piix4_dev = pci_dev;
 }
 
+static void piix4_init(Object *obj)
+{
+    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -199,6 +220,7 @@ static const TypeInfo piix4_info = {
     .name          = TYPE_PIIX4_PCI_DEVICE,
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
+    .instance_init = piix4_init,
     .class_init    = piix4_class_init,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 16d7a0e785..528c34a1c3 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -26,7 +26,7 @@
 #include "qemu/units.h"
 #include "qemu-common.h"
 #include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/isa/superio.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
@@ -44,7 +44,6 @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "elf.h"
-#include "hw/timer/mc146818rtc.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
deleted file mode 100644
index 028bb53e3d..0000000000
--- a/include/hw/acpi/piix4.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index a95eab0d8a..c671c9fd2a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -244,12 +244,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 
 #define PORT92_A20_LINE "a20"
 
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm);
-
 /* hpet.c */
 extern int no_hpet;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
new file mode 100644
index 0000000000..b8ce26fec4
--- /dev/null
+++ b/include/hw/southbridge/piix.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                      qemu_irq sci_irq, qemu_irq smi_irq,
+                      int smm_enabled, DeviceState **piix4_pm);
+
+#endif
-- 
2.21.0

[Xen-devel] [PATCH 16/32] piix4: add a mc146818rtc controller as specified in datasheet

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Remove mc146818rtc instanciated in malta board, to not have it twice.

Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
[PMD: rebased, set RTC base_year to 2000]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                   |  3 ++-
 hw/acpi/piix4.c               |  2 +-
 hw/i386/acpi-build.c          |  3 +--
 hw/i386/pc_piix.c             |  1 +
 hw/isa/piix4.c                | 22 ++++++++++++++++++++++
 hw/mips/mips_malta.c          |  4 +---
 include/hw/acpi/piix4.h       |  6 ------
 include/hw/i386/pc.h          |  6 ------
 include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
 9 files changed, 48 insertions(+), 19 deletions(-)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/southbridge/piix.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c9f625fc2e..556f58bd8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
 F: hw/acpi/ich9.c
 F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
 F: hw/misc/sga.c
 F: hw/isa/apm.c
 F: include/hw/isa/apm.h
@@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
 M: Philippe Mathieu-Daudé <f4bug@amsat.org>
 S: Maintained
 F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
 
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 1d29d438c7..27270621ab 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -21,6 +21,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/isa/apm.h"
 #include "hw/i2c/pm_smbus.h"
@@ -33,7 +34,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/acpi/cpu_hotplug.h"
 #include "hw/acpi/cpu.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4e0f9f425a..aa6fe61191 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -34,7 +34,6 @@
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"
@@ -52,7 +51,7 @@
 #include "sysemu/reset.h"
 
 /* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/i386/ich9.h"
 #include "hw/pci/pci_bus.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72124..431965d921 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
 #include "hw/pci/pci.h"
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0b0a0ecab1..9f554747af 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
@@ -31,6 +32,7 @@
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -42,6 +44,7 @@ typedef struct PIIX4State {
     qemu_irq cpu_intr;
     qemu_irq *isa;
 
+    RTCState rtc;
     /* Reset Control Register */
     MemoryRegion rcr_mem;
     uint8_t rcr;
@@ -144,6 +147,7 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
     ISABus *isa_bus;
     qemu_irq *i8259_out_irq;
+    Error *err = NULL;
 
     isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
                           pci_address_space_io(pci_dev), errp);
@@ -172,9 +176,26 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
+    /* RTC */
+    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
     piix4_dev = pci_dev;
 }
 
+static void piix4_init(Object *obj)
+{
+    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -199,6 +220,7 @@ static const TypeInfo piix4_info = {
     .name          = TYPE_PIIX4_PCI_DEVICE,
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
+    .instance_init = piix4_init,
     .class_init    = piix4_class_init,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 16d7a0e785..528c34a1c3 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -26,7 +26,7 @@
 #include "qemu/units.h"
 #include "qemu-common.h"
 #include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/isa/superio.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
@@ -44,7 +44,6 @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "elf.h"
-#include "hw/timer/mc146818rtc.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"
@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
deleted file mode 100644
index 028bb53e3d..0000000000
--- a/include/hw/acpi/piix4.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index a95eab0d8a..c671c9fd2a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -244,12 +244,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 
 #define PORT92_A20_LINE "a20"
 
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm);
-
 /* hpet.c */
 extern int no_hpet;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
new file mode 100644
index 0000000000..b8ce26fec4
--- /dev/null
+++ b/include/hw/southbridge/piix.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                      qemu_irq sci_irq, qemu_irq smi_irq,
+                      int smm_enabled, DeviceState **piix4_pm);
+
+#endif
-- 
2.21.0


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https://lists.xenproject.org/mailman/listinfo/xen-devel

[PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically

[Philippe Mathieu-Daudé]

In the next commit we'll refactor the PIIX4 code out of
mips_malta_init(). As a preliminary step, add the 'ide_drives'
variable and create the drive array dynamically.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 528c34a1c3..774bb810f6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    ide_drive_get(hd, ARRAY_SIZE(hd));
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
                                           true, TYPE_PIIX4_PCI_DEVICE);
@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
     }
 
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+    g_free(hd);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-- 
2.21.0

[PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically

[Philippe Mathieu-Daudé]

In the next commit we'll refactor the PIIX4 code out of
mips_malta_init(). As a preliminary step, add the 'ide_drives'
variable and create the drive array dynamically.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 528c34a1c3..774bb810f6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    ide_drive_get(hd, ARRAY_SIZE(hd));
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
                                           true, TYPE_PIIX4_PCI_DEVICE);
@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
     }
 
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+    g_free(hd);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-- 
2.21.0

[Xen-devel] [PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically

[Philippe Mathieu-Daudé]

In the next commit we'll refactor the PIIX4 code out of
mips_malta_init(). As a preliminary step, add the 'ide_drives'
variable and create the drive array dynamically.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 528c34a1c3..774bb810f6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    ide_drive_get(hd, ARRAY_SIZE(hd));
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
                                           true, TYPE_PIIX4_PCI_DEVICE);
@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
     }
 
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+    g_free(hd);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-- 
2.21.0


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https://lists.xenproject.org/mailman/listinfo/xen-devel

[PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

[Philippe Mathieu-Daudé]

The Malta board instantiate a PIIX4 chipset doing various
calls. Refactor all those related calls into a single
function: piix4_create().

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 774bb810f6..0d4312840b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                                 I2CBus **smbus, size_t ide_buses)
+{
+    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {
@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq cbus_irq, i8259_irq;
-    PCIDevice *pci;
-    int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
-    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    piix4_devfn = pci->devfn;
+    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
 
     /* Interrupt controller */
     qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
         s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
     }
 
-    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
-    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
-                          isa_get_irq(NULL, 9), NULL, 0, NULL);
-
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
     generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
-- 
2.21.0

[PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

[Philippe Mathieu-Daudé]

The Malta board instantiate a PIIX4 chipset doing various
calls. Refactor all those related calls into a single
function: piix4_create().

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 774bb810f6..0d4312840b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                                 I2CBus **smbus, size_t ide_buses)
+{
+    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {
@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq cbus_irq, i8259_irq;
-    PCIDevice *pci;
-    int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
-    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    piix4_devfn = pci->devfn;
+    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
 
     /* Interrupt controller */
     qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
         s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
     }
 
-    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
-    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
-                          isa_get_irq(NULL, 9), NULL, 0, NULL);
-
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
     generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
-- 
2.21.0

[Xen-devel] [PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

[Philippe Mathieu-Daudé]

The Malta board instantiate a PIIX4 chipset doing various
calls. Refactor all those related calls into a single
function: piix4_create().

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 774bb810f6..0d4312840b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                                 I2CBus **smbus, size_t ide_buses)
+{
+    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {
@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq cbus_irq, i8259_irq;
-    PCIDevice *pci;
-    int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
-    DriveInfo **hd;
     int fl_idx = 0;
     int be;
 
@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    piix4_devfn = pci->devfn;
+    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
 
     /* Interrupt controller */
     qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
         s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
     }
 
-    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
-    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
-                          isa_get_irq(NULL, 9), NULL, 0, NULL);
-
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
     generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
-- 
2.21.0


_______________________________________________
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Xen-devel@lists.xenproject.org
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[PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Now that we properly refactored the piix4_create() function, let's
move it to hw/isa/piix4.c where it belongs, so it can be reused
on other places.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
 hw/mips/gt64xxx_pci.c         |  1 +
 hw/mips/mips_malta.c          | 28 ----------------------------
 include/hw/i386/pc.h          |  2 --
 include/hw/southbridge/piix.h |  6 ++++++
 5 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9f554747af..d90899e122 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -27,12 +27,14 @@
 #include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/mc146818rtc.h"
+#include "hw/ide.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -234,3 +236,31 @@ static void piix4_register_types(void)
 }
 
 type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses)
+{
+    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f325bd6c1c..c277398c0d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -28,6 +28,7 @@
 #include "hw/mips/mips.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "migration/vmstate.h"
 #include "hw/i386/pc.h"
 #include "hw/irq.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 0d4312840b..477a4725c0 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-                                 I2CBus **smbus, size_t ide_buses)
-{
-    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
-    DriveInfo **hd;
-    PCIDevice *pci;
-    DeviceState *dev;
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    if (isa_bus) {
-        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    }
-
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
-    if (smbus) {
-        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
-                               isa_get_irq(NULL, 9), NULL, 0, NULL);
-   }
-
-    return dev;
-}
-
 static
 void mips_malta_init(MachineState *machine)
 {
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c671c9fd2a..b63fc7631e 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -274,8 +274,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     MemoryRegion *ram_memory);
 
 PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b8ce26fec4..add352456b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -2,6 +2,7 @@
  * QEMU PIIX South Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses);
+
 #endif
-- 
2.21.0

[PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Now that we properly refactored the piix4_create() function, let's
move it to hw/isa/piix4.c where it belongs, so it can be reused
on other places.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
 hw/mips/gt64xxx_pci.c         |  1 +
 hw/mips/mips_malta.c          | 28 ----------------------------
 include/hw/i386/pc.h          |  2 --
 include/hw/southbridge/piix.h |  6 ++++++
 5 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9f554747af..d90899e122 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -27,12 +27,14 @@
 #include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/mc146818rtc.h"
+#include "hw/ide.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -234,3 +236,31 @@ static void piix4_register_types(void)
 }
 
 type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses)
+{
+    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f325bd6c1c..c277398c0d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -28,6 +28,7 @@
 #include "hw/mips/mips.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "migration/vmstate.h"
 #include "hw/i386/pc.h"
 #include "hw/irq.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 0d4312840b..477a4725c0 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-                                 I2CBus **smbus, size_t ide_buses)
-{
-    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
-    DriveInfo **hd;
-    PCIDevice *pci;
-    DeviceState *dev;
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    if (isa_bus) {
-        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    }
-
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
-    if (smbus) {
-        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
-                               isa_get_irq(NULL, 9), NULL, 0, NULL);
-   }
-
-    return dev;
-}
-
 static
 void mips_malta_init(MachineState *machine)
 {
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c671c9fd2a..b63fc7631e 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -274,8 +274,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     MemoryRegion *ram_memory);
 
 PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b8ce26fec4..add352456b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -2,6 +2,7 @@
  * QEMU PIIX South Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses);
+
 #endif
-- 
2.21.0

[Xen-devel] [PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Now that we properly refactored the piix4_create() function, let's
move it to hw/isa/piix4.c where it belongs, so it can be reused
on other places.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
 hw/mips/gt64xxx_pci.c         |  1 +
 hw/mips/mips_malta.c          | 28 ----------------------------
 include/hw/i386/pc.h          |  2 --
 include/hw/southbridge/piix.h |  6 ++++++
 5 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9f554747af..d90899e122 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -27,12 +27,14 @@
 #include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/mc146818rtc.h"
+#include "hw/ide.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
@@ -234,3 +236,31 @@ static void piix4_register_types(void)
 }
 
 type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses)
+{
+    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f325bd6c1c..c277398c0d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -28,6 +28,7 @@
 #include "hw/mips/mips.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "migration/vmstate.h"
 #include "hw/i386/pc.h"
 #include "hw/irq.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 0d4312840b..477a4725c0 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-                                 I2CBus **smbus, size_t ide_buses)
-{
-    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
-    DriveInfo **hd;
-    PCIDevice *pci;
-    DeviceState *dev;
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    if (isa_bus) {
-        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    }
-
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
-    if (smbus) {
-        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
-                               isa_get_irq(NULL, 9), NULL, 0, NULL);
-   }
-
-    return dev;
-}
-
 static
 void mips_malta_init(MachineState *machine)
 {
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c671c9fd2a..b63fc7631e 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -274,8 +274,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     MemoryRegion *ram_memory);
 
 PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b8ce26fec4..add352456b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -2,6 +2,7 @@
  * QEMU PIIX South Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses);
+
 #endif
-- 
2.21.0


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[PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Philippe Mathieu-Daudé]

The GSI creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 15 +++++++++++++++
 hw/i386/pc_piix.c    |  9 +--------
 hw/i386/pc_q35.c     |  9 +--------
 include/hw/i386/pc.h |  2 ++
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bcda50efcc..a7597c6c44 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -357,6 +357,21 @@ void gsi_handler(void *opaque, int n, int level)
     qemu_set_irq(s->ioapic_irq[n], level);
 }
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
+{
+    GSIState *s;
+
+    s = g_new0(GSIState, 1);
+    if (kvm_ioapic_in_kernel()) {
+        kvm_pc_setup_irq_routing(pci_enabled);
+        *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
+    } else {
+        *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+    }
+
+    return s;
+}
+
 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
                            unsigned size)
 {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 431965d921..452b107e1b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -188,14 +188,7 @@ static void pc_init1(MachineState *machine,
         xen_load_linux(pcms);
     }
 
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
         pci_bus = i440fx_init(host_type,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8fad20f314..52261962b8 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -210,14 +210,7 @@ static void pc_q35_init(MachineState *machine)
     }
 
     /* irq lines */
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index b63fc7631e..d0c6b9d469 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -174,6 +174,8 @@ typedef struct GSIState {
 
 void gsi_handler(void *opaque, int n, int level);
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
+
 /* vmport.c */
 #define TYPE_VMPORT "vmport"
 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
-- 
2.21.0

[PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Philippe Mathieu-Daudé]

The GSI creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 15 +++++++++++++++
 hw/i386/pc_piix.c    |  9 +--------
 hw/i386/pc_q35.c     |  9 +--------
 include/hw/i386/pc.h |  2 ++
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bcda50efcc..a7597c6c44 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -357,6 +357,21 @@ void gsi_handler(void *opaque, int n, int level)
     qemu_set_irq(s->ioapic_irq[n], level);
 }
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
+{
+    GSIState *s;
+
+    s = g_new0(GSIState, 1);
+    if (kvm_ioapic_in_kernel()) {
+        kvm_pc_setup_irq_routing(pci_enabled);
+        *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
+    } else {
+        *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+    }
+
+    return s;
+}
+
 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
                            unsigned size)
 {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 431965d921..452b107e1b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -188,14 +188,7 @@ static void pc_init1(MachineState *machine,
         xen_load_linux(pcms);
     }
 
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
         pci_bus = i440fx_init(host_type,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8fad20f314..52261962b8 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -210,14 +210,7 @@ static void pc_q35_init(MachineState *machine)
     }
 
     /* irq lines */
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index b63fc7631e..d0c6b9d469 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -174,6 +174,8 @@ typedef struct GSIState {
 
 void gsi_handler(void *opaque, int n, int level);
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
+
 /* vmport.c */
 #define TYPE_VMPORT "vmport"
 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
-- 
2.21.0

[Xen-devel] [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Philippe Mathieu-Daudé]

The GSI creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 15 +++++++++++++++
 hw/i386/pc_piix.c    |  9 +--------
 hw/i386/pc_q35.c     |  9 +--------
 include/hw/i386/pc.h |  2 ++
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bcda50efcc..a7597c6c44 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -357,6 +357,21 @@ void gsi_handler(void *opaque, int n, int level)
     qemu_set_irq(s->ioapic_irq[n], level);
 }
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
+{
+    GSIState *s;
+
+    s = g_new0(GSIState, 1);
+    if (kvm_ioapic_in_kernel()) {
+        kvm_pc_setup_irq_routing(pci_enabled);
+        *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
+    } else {
+        *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+    }
+
+    return s;
+}
+
 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
                            unsigned size)
 {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 431965d921..452b107e1b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -188,14 +188,7 @@ static void pc_init1(MachineState *machine,
         xen_load_linux(pcms);
     }
 
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
         pci_bus = i440fx_init(host_type,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8fad20f314..52261962b8 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -210,14 +210,7 @@ static void pc_q35_init(MachineState *machine)
     }
 
     /* irq lines */
-    gsi_state = g_malloc0(sizeof(*gsi_state));
-    if (kvm_ioapic_in_kernel()) {
-        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
-        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
-                                       GSI_NUM_PINS);
-    } else {
-        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
-    }
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index b63fc7631e..d0c6b9d469 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -174,6 +174,8 @@ typedef struct GSIState {
 
 void gsi_handler(void *opaque, int n, int level);
 
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
+
 /* vmport.c */
 #define TYPE_VMPORT "vmport"
 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
-- 
2.21.0


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[PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

pc_gsi_create() is the single function that uses gsi_handler.
Make it a static variable.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 2 +-
 include/hw/i386/pc.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a7597c6c44..59de0c8a1f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
 };
 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
 
-void gsi_handler(void *opaque, int n, int level)
+static void gsi_handler(void *opaque, int n, int level)
 {
     GSIState *s = opaque;
 
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index d0c6b9d469..75b44e156c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -172,8 +172,6 @@ typedef struct GSIState {
     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 } GSIState;
 
-void gsi_handler(void *opaque, int n, int level);
-
 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
 
 /* vmport.c */
-- 
2.21.0

[PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

pc_gsi_create() is the single function that uses gsi_handler.
Make it a static variable.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 2 +-
 include/hw/i386/pc.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a7597c6c44..59de0c8a1f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
 };
 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
 
-void gsi_handler(void *opaque, int n, int level)
+static void gsi_handler(void *opaque, int n, int level)
 {
     GSIState *s = opaque;
 
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index d0c6b9d469..75b44e156c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -172,8 +172,6 @@ typedef struct GSIState {
     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 } GSIState;
 
-void gsi_handler(void *opaque, int n, int level);
-
 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
 
 /* vmport.c */
-- 
2.21.0

[Xen-devel] [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

pc_gsi_create() is the single function that uses gsi_handler.
Make it a static variable.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 2 +-
 include/hw/i386/pc.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a7597c6c44..59de0c8a1f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
 };
 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
 
-void gsi_handler(void *opaque, int n, int level)
+static void gsi_handler(void *opaque, int n, int level)
 {
     GSIState *s = opaque;
 
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index d0c6b9d469..75b44e156c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -172,8 +172,6 @@ typedef struct GSIState {
     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 } GSIState;
 
-void gsi_handler(void *opaque, int n, int level);
-
 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
 
 /* vmport.c */
-- 
2.21.0


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[PATCH 22/32] hw/i386/pc: Move gsi_state creation code

[Philippe Mathieu-Daudé]

The block code related to IRQ start few lines later. Move
the comment and the pc_gsi_create() call where we start
to use the IRQs.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_q35.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 52261962b8..6d096eff28 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -209,9 +209,6 @@ static void pc_q35_init(MachineState *machine)
                        rom_memory, &ram_memory);
     }
 
-    /* irq lines */
-    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
-
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 
@@ -245,6 +242,9 @@ static void pc_q35_init(MachineState *machine)
     object_property_set_link(OBJECT(machine), OBJECT(lpc),
                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 
+    /* irq lines */
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
+
     ich9_lpc = ICH9_LPC_DEVICE(lpc);
     lpc_dev = DEVICE(lpc);
     for (i = 0; i < GSI_NUM_PINS; i++) {
-- 
2.21.0

[PATCH 22/32] hw/i386/pc: Move gsi_state creation code

[Philippe Mathieu-Daudé]

The block code related to IRQ start few lines later. Move
the comment and the pc_gsi_create() call where we start
to use the IRQs.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_q35.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 52261962b8..6d096eff28 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -209,9 +209,6 @@ static void pc_q35_init(MachineState *machine)
                        rom_memory, &ram_memory);
     }
 
-    /* irq lines */
-    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
-
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 
@@ -245,6 +242,9 @@ static void pc_q35_init(MachineState *machine)
     object_property_set_link(OBJECT(machine), OBJECT(lpc),
                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 
+    /* irq lines */
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
+
     ich9_lpc = ICH9_LPC_DEVICE(lpc);
     lpc_dev = DEVICE(lpc);
     for (i = 0; i < GSI_NUM_PINS; i++) {
-- 
2.21.0

[Xen-devel] [PATCH 22/32] hw/i386/pc: Move gsi_state creation code

[Philippe Mathieu-Daudé]

The block code related to IRQ start few lines later. Move
the comment and the pc_gsi_create() call where we start
to use the IRQs.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_q35.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 52261962b8..6d096eff28 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -209,9 +209,6 @@ static void pc_q35_init(MachineState *machine)
                        rom_memory, &ram_memory);
     }
 
-    /* irq lines */
-    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
-
     /* create pci host bus */
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 
@@ -245,6 +242,9 @@ static void pc_q35_init(MachineState *machine)
     object_property_set_link(OBJECT(machine), OBJECT(lpc),
                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 
+    /* irq lines */
+    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
+
     ich9_lpc = ICH9_LPC_DEVICE(lpc);
     lpc_dev = DEVICE(lpc);
     for (i = 0; i < GSI_NUM_PINS; i++) {
-- 
2.21.0


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[PATCH 23/32] hw/i386/pc: Extract pc_i8259_create()

[Philippe Mathieu-Daudé]

The i8259 creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 19 +++++++++++++++++++
 hw/i386/pc_piix.c    | 13 +------------
 hw/i386/pc_q35.c     | 14 +-------------
 include/hw/i386/pc.h |  1 +
 4 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 59de0c8a1f..2b6a52f23b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1978,6 +1978,25 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
     rom_reset_order_override();
 }
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
+{
+    qemu_irq *i8259;
+
+    if (kvm_pic_in_kernel()) {
+        i8259 = kvm_i8259_init(isa_bus);
+    } else if (xen_enabled()) {
+        i8259 = xen_interrupt_controller_init();
+    } else {
+        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
+    }
+
+    for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
+        i8259_irqs[i] = i8259[i];
+    }
+
+    g_free(i8259);
+}
+
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
 {
     DeviceState *dev;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 452b107e1b..0a7193a3cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -81,7 +81,6 @@ static void pc_init1(MachineState *machine,
     ISABus *isa_bus;
     PCII440FXState *i440fx_state;
     int piix3_devfn = -1;
-    qemu_irq *i8259;
     qemu_irq smi_irq;
     GSIState *gsi_state;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -208,18 +207,8 @@ static void pc_init1(MachineState *machine,
     }
     isa_bus_irqs(isa_bus, pcms->gsi);
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "i440fx");
     }
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6d096eff28..f4fb9a02ba 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -128,7 +128,6 @@ static void pc_q35_init(MachineState *machine)
     MemoryRegion *ram_memory;
     GSIState *gsi_state;
     ISABus *isa_bus;
-    qemu_irq *i8259;
     int i;
     ICH9LPCState *ich9_lpc;
     PCIDevice *ahci;
@@ -255,18 +254,7 @@ static void pc_q35_init(MachineState *machine)
     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
     isa_bus = ich9_lpc->isa_bus;
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
-
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "q35");
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 75b44e156c..183326d9fe 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 
 ISADevice *pc_find_fdc0(void);
-- 
2.21.0

[PATCH 23/32] hw/i386/pc: Extract pc_i8259_create()

[Philippe Mathieu-Daudé]

The i8259 creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 19 +++++++++++++++++++
 hw/i386/pc_piix.c    | 13 +------------
 hw/i386/pc_q35.c     | 14 +-------------
 include/hw/i386/pc.h |  1 +
 4 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 59de0c8a1f..2b6a52f23b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1978,6 +1978,25 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
     rom_reset_order_override();
 }
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
+{
+    qemu_irq *i8259;
+
+    if (kvm_pic_in_kernel()) {
+        i8259 = kvm_i8259_init(isa_bus);
+    } else if (xen_enabled()) {
+        i8259 = xen_interrupt_controller_init();
+    } else {
+        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
+    }
+
+    for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
+        i8259_irqs[i] = i8259[i];
+    }
+
+    g_free(i8259);
+}
+
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
 {
     DeviceState *dev;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 452b107e1b..0a7193a3cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -81,7 +81,6 @@ static void pc_init1(MachineState *machine,
     ISABus *isa_bus;
     PCII440FXState *i440fx_state;
     int piix3_devfn = -1;
-    qemu_irq *i8259;
     qemu_irq smi_irq;
     GSIState *gsi_state;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -208,18 +207,8 @@ static void pc_init1(MachineState *machine,
     }
     isa_bus_irqs(isa_bus, pcms->gsi);
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "i440fx");
     }
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6d096eff28..f4fb9a02ba 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -128,7 +128,6 @@ static void pc_q35_init(MachineState *machine)
     MemoryRegion *ram_memory;
     GSIState *gsi_state;
     ISABus *isa_bus;
-    qemu_irq *i8259;
     int i;
     ICH9LPCState *ich9_lpc;
     PCIDevice *ahci;
@@ -255,18 +254,7 @@ static void pc_q35_init(MachineState *machine)
     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
     isa_bus = ich9_lpc->isa_bus;
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
-
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "q35");
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 75b44e156c..183326d9fe 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 
 ISADevice *pc_find_fdc0(void);
-- 
2.21.0

[Xen-devel] [PATCH 23/32] hw/i386/pc: Extract pc_i8259_create()

[Philippe Mathieu-Daudé]

The i8259 creation code is common to all PC machines, extract the
common code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc.c         | 19 +++++++++++++++++++
 hw/i386/pc_piix.c    | 13 +------------
 hw/i386/pc_q35.c     | 14 +-------------
 include/hw/i386/pc.h |  1 +
 4 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 59de0c8a1f..2b6a52f23b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1978,6 +1978,25 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
     rom_reset_order_override();
 }
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
+{
+    qemu_irq *i8259;
+
+    if (kvm_pic_in_kernel()) {
+        i8259 = kvm_i8259_init(isa_bus);
+    } else if (xen_enabled()) {
+        i8259 = xen_interrupt_controller_init();
+    } else {
+        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
+    }
+
+    for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
+        i8259_irqs[i] = i8259[i];
+    }
+
+    g_free(i8259);
+}
+
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
 {
     DeviceState *dev;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 452b107e1b..0a7193a3cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -81,7 +81,6 @@ static void pc_init1(MachineState *machine,
     ISABus *isa_bus;
     PCII440FXState *i440fx_state;
     int piix3_devfn = -1;
-    qemu_irq *i8259;
     qemu_irq smi_irq;
     GSIState *gsi_state;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -208,18 +207,8 @@ static void pc_init1(MachineState *machine,
     }
     isa_bus_irqs(isa_bus, pcms->gsi);
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "i440fx");
     }
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6d096eff28..f4fb9a02ba 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -128,7 +128,6 @@ static void pc_q35_init(MachineState *machine)
     MemoryRegion *ram_memory;
     GSIState *gsi_state;
     ISABus *isa_bus;
-    qemu_irq *i8259;
     int i;
     ICH9LPCState *ich9_lpc;
     PCIDevice *ahci;
@@ -255,18 +254,7 @@ static void pc_q35_init(MachineState *machine)
     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
     isa_bus = ich9_lpc->isa_bus;
 
-    if (kvm_pic_in_kernel()) {
-        i8259 = kvm_i8259_init(isa_bus);
-    } else if (xen_enabled()) {
-        i8259 = xen_interrupt_controller_init();
-    } else {
-        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
-    }
-
-    for (i = 0; i < ISA_NUM_IRQS; i++) {
-        gsi_state->i8259_irq[i] = i8259[i];
-    }
-    g_free(i8259);
+    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 
     if (pcmc->pci_enabled) {
         ioapic_init_gsi(gsi_state, "q35");
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 75b44e156c..183326d9fe 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 
 ISADevice *pc_find_fdc0(void);
-- 
2.21.0


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[PATCH 24/32] hw/i386/pc: Remove kvm_i386.h include

[Philippe Mathieu-Daudé]

By extracting pc_gsi_create() and pc_i8259_create() we removed
the access to "kvm_i386.h" from the machine code. We can now
remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c | 1 -
 hw/i386/pc_q35.c  | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0a7193a3cc..5b35ff04c7 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -57,7 +57,6 @@
 #endif
 #include "migration/global_state.h"
 #include "migration/misc.h"
-#include "kvm_i386.h"
 #include "sysemu/numa.h"
 
 #define MAX_IDE_BUS 2
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index f4fb9a02ba..2e5d6821fb 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -36,7 +36,6 @@
 #include "hw/timer/mc146818rtc.h"
 #include "hw/xen/xen.h"
 #include "sysemu/kvm.h"
-#include "kvm_i386.h"
 #include "hw/kvm/clock.h"
 #include "hw/pci-host/q35.h"
 #include "hw/qdev-properties.h"
-- 
2.21.0

[PATCH 24/32] hw/i386/pc: Remove kvm_i386.h include

[Philippe Mathieu-Daudé]

By extracting pc_gsi_create() and pc_i8259_create() we removed
the access to "kvm_i386.h" from the machine code. We can now
remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c | 1 -
 hw/i386/pc_q35.c  | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0a7193a3cc..5b35ff04c7 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -57,7 +57,6 @@
 #endif
 #include "migration/global_state.h"
 #include "migration/misc.h"
-#include "kvm_i386.h"
 #include "sysemu/numa.h"
 
 #define MAX_IDE_BUS 2
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index f4fb9a02ba..2e5d6821fb 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -36,7 +36,6 @@
 #include "hw/timer/mc146818rtc.h"
 #include "hw/xen/xen.h"
 #include "sysemu/kvm.h"
-#include "kvm_i386.h"
 #include "hw/kvm/clock.h"
 #include "hw/pci-host/q35.h"
 #include "hw/qdev-properties.h"
-- 
2.21.0

[Xen-devel] [PATCH 24/32] hw/i386/pc: Remove kvm_i386.h include

[Philippe Mathieu-Daudé]

By extracting pc_gsi_create() and pc_i8259_create() we removed
the access to "kvm_i386.h" from the machine code. We can now
remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c | 1 -
 hw/i386/pc_q35.c  | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0a7193a3cc..5b35ff04c7 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -57,7 +57,6 @@
 #endif
 #include "migration/global_state.h"
 #include "migration/misc.h"
-#include "kvm_i386.h"
 #include "sysemu/numa.h"
 
 #define MAX_IDE_BUS 2
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index f4fb9a02ba..2e5d6821fb 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -36,7 +36,6 @@
 #include "hw/timer/mc146818rtc.h"
 #include "hw/xen/xen.h"
 #include "sysemu/kvm.h"
-#include "kvm_i386.h"
 #include "hw/kvm/clock.h"
 #include "hw/pci-host/q35.h"
 #include "hw/qdev-properties.h"
-- 
2.21.0


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[PATCH 25/32] hw/pci-host/piix: Extract piix3_create()

[Philippe Mathieu-Daudé]

Extract the PIIX3 creation code from the i440fx_init() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 2f4cbcbfe9..3292703de7 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
+
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    /* Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI. */
-    if (xen_enabled()) {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
-                PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
-    }
+    piix3 = piix3_create(b, isa_bus);
     piix3->pic = pic;
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
     *piix3_devfn = piix3->dev.devfn;
 
     ram_size = ram_size / 8 / 1024 / 1024;
-- 
2.21.0

[PATCH 25/32] hw/pci-host/piix: Extract piix3_create()

[Philippe Mathieu-Daudé]

Extract the PIIX3 creation code from the i440fx_init() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 2f4cbcbfe9..3292703de7 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
+
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    /* Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI. */
-    if (xen_enabled()) {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
-                PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
-    }
+    piix3 = piix3_create(b, isa_bus);
     piix3->pic = pic;
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
     *piix3_devfn = piix3->dev.devfn;
 
     ram_size = ram_size / 8 / 1024 / 1024;
-- 
2.21.0

[Xen-devel] [PATCH 25/32] hw/pci-host/piix: Extract piix3_create()

[Philippe Mathieu-Daudé]

Extract the PIIX3 creation code from the i440fx_init() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 2f4cbcbfe9..3292703de7 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
+
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    /* Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI. */
-    if (xen_enabled()) {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
-                PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
-    }
+    piix3 = piix3_create(b, isa_bus);
     piix3->pic = pic;
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
     *piix3_devfn = piix3->dev.devfn;
 
     ram_size = ram_size / 8 / 1024 / 1024;
-- 
2.21.0


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[PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c            | 1 +
 include/hw/i386/pc.h          | 6 ------
 include/hw/southbridge/piix.h | 6 ++++++
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3292703de7..3770575c1a 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 183326d9fe..1c20b96571 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
 
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state, int *piix_devfn,
                     ISABus **isa_bus, qemu_irq *pic,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index add352456b..79ebe0089b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define RCR_IOPORT 0xcf9
+
 extern PCIDevice *piix4_dev;
 
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-- 
2.21.0

[PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c            | 1 +
 include/hw/i386/pc.h          | 6 ------
 include/hw/southbridge/piix.h | 6 ++++++
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3292703de7..3770575c1a 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 183326d9fe..1c20b96571 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
 
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state, int *piix_devfn,
                     ISABus **isa_bus, qemu_irq *pic,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index add352456b..79ebe0089b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define RCR_IOPORT 0xcf9
+
 extern PCIDevice *piix4_dev;
 
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-- 
2.21.0

[Xen-devel] [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c            | 1 +
 include/hw/i386/pc.h          | 6 ------
 include/hw/southbridge/piix.h | 6 ++++++
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3292703de7..3770575c1a 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 183326d9fe..1c20b96571 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
 
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state, int *piix_devfn,
                     ISABus **isa_bus, qemu_irq *pic,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index add352456b..79ebe0089b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define RCR_IOPORT 0xcf9
+
 extern PCIDevice *piix4_dev;
 
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-- 
2.21.0


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[PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Philippe Mathieu-Daudé]

The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/xen/xen-hvm.c         | 5 +++--
 hw/mips/gt64xxx_pci.c         | 4 ++--
 hw/pci-host/piix.c            | 9 ++++-----
 include/hw/southbridge/piix.h | 6 ++++++
 4 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/hw.h"
 #include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
             v = 0;
         }
         v &= 0xf;
-        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
-            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
         }
     }
 }
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix4_dev->config[0x60 + irq_num];
+    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix4_dev->config[0x60 + i]) {
+            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
                 pic_level |= pci_irq_levels[i];
             }
         }
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3770575c1a..a450fc726e 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
 #define XEN_PIIX_NUM_PIRQS      128ULL
-#define PIIX_PIRQC              0x60
 
 typedef struct PIIX3State {
     PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
     int pic_irq;
     uint64_t mask;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 {
     int pic_irq;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 {
     PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQC + pin];
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
     PCIINTxRoute route;
 
     if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
 {
     pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
         int pic_irq;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 79ebe0089b..9c92c37a4d 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
 /*
  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
-- 
2.21.0

[PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Philippe Mathieu-Daudé]

The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/xen/xen-hvm.c         | 5 +++--
 hw/mips/gt64xxx_pci.c         | 4 ++--
 hw/pci-host/piix.c            | 9 ++++-----
 include/hw/southbridge/piix.h | 6 ++++++
 4 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/hw.h"
 #include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
             v = 0;
         }
         v &= 0xf;
-        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
-            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
         }
     }
 }
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix4_dev->config[0x60 + irq_num];
+    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix4_dev->config[0x60 + i]) {
+            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
                 pic_level |= pci_irq_levels[i];
             }
         }
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3770575c1a..a450fc726e 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
 #define XEN_PIIX_NUM_PIRQS      128ULL
-#define PIIX_PIRQC              0x60
 
 typedef struct PIIX3State {
     PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
     int pic_irq;
     uint64_t mask;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 {
     int pic_irq;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 {
     PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQC + pin];
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
     PCIINTxRoute route;
 
     if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
 {
     pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
         int pic_irq;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 79ebe0089b..9c92c37a4d 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
 /*
  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
-- 
2.21.0

[Xen-devel] [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Philippe Mathieu-Daudé]

The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/xen/xen-hvm.c         | 5 +++--
 hw/mips/gt64xxx_pci.c         | 4 ++--
 hw/pci-host/piix.c            | 9 ++++-----
 include/hw/southbridge/piix.h | 6 ++++++
 4 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/hw.h"
 #include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
             v = 0;
         }
         v &= 0xf;
-        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
-            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
         }
     }
 }
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix4_dev->config[0x60 + irq_num];
+    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix4_dev->config[0x60 + i]) {
+            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
                 pic_level |= pci_irq_levels[i];
             }
         }
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3770575c1a..a450fc726e 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
 #define XEN_PIIX_NUM_PIRQS      128ULL
-#define PIIX_PIRQC              0x60
 
 typedef struct PIIX3State {
     PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
     int pic_irq;
     uint64_t mask;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 {
     int pic_irq;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 {
     PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQC + pin];
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
     PCIINTxRoute route;
 
     if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
 {
     pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
         int pic_irq;
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 79ebe0089b..9c92c37a4d 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
 /*
  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
-- 
2.21.0


_______________________________________________
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Xen-devel@lists.xenproject.org
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[PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
functions. To be able to split it, we need to export some
declarations first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                  |  1 +
 hw/acpi/pcihp.c              |  2 +-
 hw/i386/pc_piix.c            |  1 +
 hw/pci-host/piix.c           |  1 +
 include/hw/i386/pc.h         | 22 ---------------------
 include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
 stubs/pci-host-piix.c        |  3 ++-
 7 files changed, 43 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/pci-host/i440fx.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 556f58bd8c..adf059a164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/i386/
 F: hw/pci-host/piix.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
 F: hw/isa/lpc_ich9.c
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 82d295b6e8..8413348a33 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,7 +27,7 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/pcihp.h"
 
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bridge.h"
 #include "hw/acpi/acpi.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5b35ff04c7..8ac4bf12ca 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index a450fc726e..0b5da5bc94 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 1c20b96571..cead2828de 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -248,28 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 /* hpet.c */
 extern int no_hpet;
 
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
-                    MemoryRegion *address_space_mem,
-                    MemoryRegion *address_space_io,
-                    ram_addr_t ram_size,
-                    ram_addr_t below_4g_mem_size,
-                    ram_addr_t above_4g_mem_size,
-                    MemoryRegion *pci_memory,
-                    MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
new file mode 100644
index 0000000000..e327f9bf87
--- /dev/null
+++ b/include/hw/pci-host/i440fx.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+                    PCII440FXState **pi440fx_state, int *piix_devfn,
+                    ISABus **isa_bus, qemu_irq *pic,
+                    MemoryRegion *address_space_mem,
+                    MemoryRegion *address_space_io,
+                    ram_addr_t ram_size,
+                    ram_addr_t below_4g_mem_size,
+                    ram_addr_t above_4g_mem_size,
+                    MemoryRegion *pci_memory,
+                    MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif
diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
index 6ed81b1f21..93975adbfe 100644
--- a/stubs/pci-host-piix.c
+++ b/stubs/pci-host-piix.c
@@ -1,5 +1,6 @@
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
 PCIBus *find_i440fx(void)
 {
     return NULL;
-- 
2.21.0

[PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
functions. To be able to split it, we need to export some
declarations first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                  |  1 +
 hw/acpi/pcihp.c              |  2 +-
 hw/i386/pc_piix.c            |  1 +
 hw/pci-host/piix.c           |  1 +
 include/hw/i386/pc.h         | 22 ---------------------
 include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
 stubs/pci-host-piix.c        |  3 ++-
 7 files changed, 43 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/pci-host/i440fx.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 556f58bd8c..adf059a164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/i386/
 F: hw/pci-host/piix.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
 F: hw/isa/lpc_ich9.c
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 82d295b6e8..8413348a33 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,7 +27,7 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/pcihp.h"
 
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bridge.h"
 #include "hw/acpi/acpi.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5b35ff04c7..8ac4bf12ca 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index a450fc726e..0b5da5bc94 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 1c20b96571..cead2828de 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -248,28 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 /* hpet.c */
 extern int no_hpet;
 
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
-                    MemoryRegion *address_space_mem,
-                    MemoryRegion *address_space_io,
-                    ram_addr_t ram_size,
-                    ram_addr_t below_4g_mem_size,
-                    ram_addr_t above_4g_mem_size,
-                    MemoryRegion *pci_memory,
-                    MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
new file mode 100644
index 0000000000..e327f9bf87
--- /dev/null
+++ b/include/hw/pci-host/i440fx.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+                    PCII440FXState **pi440fx_state, int *piix_devfn,
+                    ISABus **isa_bus, qemu_irq *pic,
+                    MemoryRegion *address_space_mem,
+                    MemoryRegion *address_space_io,
+                    ram_addr_t ram_size,
+                    ram_addr_t below_4g_mem_size,
+                    ram_addr_t above_4g_mem_size,
+                    MemoryRegion *pci_memory,
+                    MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif
diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
index 6ed81b1f21..93975adbfe 100644
--- a/stubs/pci-host-piix.c
+++ b/stubs/pci-host-piix.c
@@ -1,5 +1,6 @@
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
 PCIBus *find_i440fx(void)
 {
     return NULL;
-- 
2.21.0

[Xen-devel] [PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
functions. To be able to split it, we need to export some
declarations first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                  |  1 +
 hw/acpi/pcihp.c              |  2 +-
 hw/i386/pc_piix.c            |  1 +
 hw/pci-host/piix.c           |  1 +
 include/hw/i386/pc.h         | 22 ---------------------
 include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
 stubs/pci-host-piix.c        |  3 ++-
 7 files changed, 43 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/pci-host/i440fx.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 556f58bd8c..adf059a164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/i386/
 F: hw/pci-host/piix.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
 F: hw/isa/lpc_ich9.c
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 82d295b6e8..8413348a33 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,7 +27,7 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/pcihp.h"
 
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bridge.h"
 #include "hw/acpi/acpi.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5b35ff04c7..8ac4bf12ca 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
 #include "hw/loader.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index a450fc726e..0b5da5bc94 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 1c20b96571..cead2828de 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -248,28 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 /* hpet.c */
 extern int no_hpet;
 
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
-                    MemoryRegion *address_space_mem,
-                    MemoryRegion *address_space_io,
-                    ram_addr_t ram_size,
-                    ram_addr_t below_4g_mem_size,
-                    ram_addr_t above_4g_mem_size,
-                    MemoryRegion *pci_memory,
-                    MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
new file mode 100644
index 0000000000..e327f9bf87
--- /dev/null
+++ b/include/hw/pci-host/i440fx.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+                    PCII440FXState **pi440fx_state, int *piix_devfn,
+                    ISABus **isa_bus, qemu_irq *pic,
+                    MemoryRegion *address_space_mem,
+                    MemoryRegion *address_space_io,
+                    ram_addr_t ram_size,
+                    ram_addr_t below_4g_mem_size,
+                    ram_addr_t above_4g_mem_size,
+                    MemoryRegion *pci_memory,
+                    MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif
diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
index 6ed81b1f21..93975adbfe 100644
--- a/stubs/pci-host-piix.c
+++ b/stubs/pci-host-piix.c
@@ -1,5 +1,6 @@
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
 PCIBus *find_i440fx(void)
 {
     return NULL;
-- 
2.21.0


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[PATCH 29/32] hw/pci-host/piix: Fix code style issues

[Philippe Mathieu-Daudé]

We will move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0b5da5bc94..61f91ff561 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 static void piix3_write_config_xen(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len);
 
-/* return the global irq number corresponding to a given device irq
-   pin. We could also use the bus number to have a more precise
-   mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 {
     int slot_addend;
-- 
2.21.0

[PATCH 29/32] hw/pci-host/piix: Fix code style issues

[Philippe Mathieu-Daudé]

We will move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0b5da5bc94..61f91ff561 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 static void piix3_write_config_xen(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len);
 
-/* return the global irq number corresponding to a given device irq
-   pin. We could also use the bus number to have a more precise
-   mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 {
     int slot_addend;
-- 
2.21.0

[Xen-devel] [PATCH 29/32] hw/pci-host/piix: Fix code style issues

[Philippe Mathieu-Daudé]

We will move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/pci-host/piix.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0b5da5bc94..61f91ff561 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 static void piix3_write_config_xen(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len);
 
-/* return the global irq number corresponding to a given device irq
-   pin. We could also use the bus number to have a more precise
-   mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 {
     int slot_addend;
-- 
2.21.0


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[PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Move all the PIIX3 functions to a new file: hw/isa/piix3.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Checkpatch warning:

 ERROR: spaces required around that '*' (ctx:VxV)
 #312: FILE: hw/isa/piix3.c:248:
 +    .subsections = (const VMStateDescription*[]) {
                                              ^
---
 MAINTAINERS                   |   1 +
 hw/i386/Kconfig               |   1 +
 hw/isa/Kconfig                |   4 +
 hw/isa/Makefile.objs          |   1 +
 hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
 hw/pci-host/Kconfig           |   1 -
 hw/pci-host/piix.c            | 402 ----------------------------------
 include/hw/southbridge/piix.h |  36 +++
 8 files changed, 442 insertions(+), 403 deletions(-)
 create mode 100644 hw/isa/piix3.c

diff --git a/MAINTAINERS b/MAINTAINERS
index adf059a164..4845f47d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..589d75e26a 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -61,6 +61,7 @@ config I440FX
     select PC_ACPI
     select ACPI_SMBUS
     select PCI_PIIX
+    select PIIX3
     select IDE_PIIX
     select DIMM
     select SMBIOS
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 98a289957e..8a38813cc1 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -29,6 +29,10 @@ config PC87312
     select FDC
     select IDE_ISA
 
+config PIIX3
+    bool
+    select ISA_BUS
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index ff97485504..8e73960a75 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
 common-obj-$(CONFIG_APM) += apm.o
 common-obj-$(CONFIG_I82378) += i82378.o
 common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
 common-obj-$(CONFIG_PIIX4) += piix4.o
 common-obj-$(CONFIG_VT82C686) += vt82c686.o
 common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
new file mode 100644
index 0000000000..05146447ef
--- /dev/null
+++ b/hw/isa/piix3.c
@@ -0,0 +1,399 @@
+/*
+ * QEMU PIIX PCI ISA Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "hw/southbridge/piix.h"
+#include "hw/irq.h"
+#include "hw/isa/isa.h"
+#include "hw/xen/xen.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
+
+#define XEN_PIIX_NUM_PIRQS      128ULL
+
+#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
+#define PIIX3_PCI_DEVICE(obj) \
+    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
+
+#define TYPE_PIIX3_DEVICE "PIIX3"
+#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
+
+static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+{
+    qemu_set_irq(piix3->pic[pic_irq],
+                 !!(piix3->pic_levels &
+                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
+                     (pic_irq * PIIX_NUM_PIRQS))));
+}
+
+static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+    uint64_t mask;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
+    piix3->pic_levels &= ~mask;
+    piix3->pic_levels |= mask * !!level;
+}
+
+static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    piix3_set_irq_level_internal(piix3, pirq, level);
+
+    piix3_set_irq_pic(piix3, pic_irq);
+}
+
+static void piix3_set_irq(void *opaque, int pirq, int level)
+{
+    PIIX3State *piix3 = opaque;
+    piix3_set_irq_level(piix3, pirq, level);
+}
+
+static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+{
+    PIIX3State *piix3 = opaque;
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+    PCIINTxRoute route;
+
+    if (irq < PIIX_NUM_PIC_IRQS) {
+        route.mode = PCI_INTX_ENABLED;
+        route.irq = irq;
+    } else {
+        route.mode = PCI_INTX_DISABLED;
+        route.irq = -1;
+    }
+    return route;
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+    PCIBus *bus = pci_get_bus(&piix3->dev);
+    int pirq;
+
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+    }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+                               uint32_t address, uint32_t val, int len)
+{
+    pci_default_write_config(dev, address, val, len);
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
+        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+        int pic_irq;
+
+        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
+        piix3_update_irq_levels(piix3);
+        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+            piix3_set_irq_pic(piix3, pic_irq);
+        }
+    }
+}
+
+static void piix3_write_config_xen(PCIDevice *dev,
+                                   uint32_t address, uint32_t val, int len)
+{
+    xen_piix_pci_write_config_client(address, val, len);
+    piix3_write_config(dev, address, val, len);
+}
+
+static void piix3_reset(void *opaque)
+{
+    PIIX3State *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
+
+    pci_conf[0x04] = 0x07; /* master, memory and I/O */
+    pci_conf[0x05] = 0x00;
+    pci_conf[0x06] = 0x00;
+    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
+    pci_conf[0x4c] = 0x4d;
+    pci_conf[0x4e] = 0x03;
+    pci_conf[0x4f] = 0x00;
+    pci_conf[0x60] = 0x80;
+    pci_conf[0x61] = 0x80;
+    pci_conf[0x62] = 0x80;
+    pci_conf[0x63] = 0x80;
+    pci_conf[0x69] = 0x02;
+    pci_conf[0x70] = 0x80;
+    pci_conf[0x76] = 0x0c;
+    pci_conf[0x77] = 0x0c;
+    pci_conf[0x78] = 0x02;
+    pci_conf[0x79] = 0x00;
+    pci_conf[0x80] = 0x00;
+    pci_conf[0x82] = 0x00;
+    pci_conf[0xa0] = 0x08;
+    pci_conf[0xa2] = 0x00;
+    pci_conf[0xa3] = 0x00;
+    pci_conf[0xa4] = 0x00;
+    pci_conf[0xa5] = 0x00;
+    pci_conf[0xa6] = 0x00;
+    pci_conf[0xa7] = 0x00;
+    pci_conf[0xa8] = 0x0f;
+    pci_conf[0xaa] = 0x00;
+    pci_conf[0xab] = 0x00;
+    pci_conf[0xac] = 0x00;
+    pci_conf[0xae] = 0x00;
+
+    d->pic_levels = 0;
+    d->rcr = 0;
+}
+
+static int piix3_post_load(void *opaque, int version_id)
+{
+    PIIX3State *piix3 = opaque;
+    int pirq;
+
+    /*
+     * Because the i8259 has not been deserialized yet, qemu_irq_raise
+     * might bring the system to a different state than the saved one;
+     * for example, the interrupt could be masked but the i8259 would
+     * not know that yet and would trigger an interrupt in the CPU.
+     *
+     * Here, we update irq levels without raising the interrupt.
+     * Interrupt state will be deserialized separately through the i8259.
+     */
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level_internal(piix3, pirq,
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+    }
+    return 0;
+}
+
+static int piix3_pre_save(void *opaque)
+{
+    int i;
+    PIIX3State *piix3 = opaque;
+
+    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
+        piix3->pci_irq_levels_vmstate[i] =
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
+    }
+
+    return 0;
+}
+
+static bool piix3_rcr_needed(void *opaque)
+{
+    PIIX3State *piix3 = opaque;
+
+    return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+    .name = "PIIX3/rcr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = piix3_rcr_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(rcr, PIIX3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_piix3 = {
+    .name = "PIIX3",
+    .version_id = 3,
+    .minimum_version_id = 2,
+    .post_load = piix3_post_load,
+    .pre_save = piix3_pre_save,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, PIIX3State),
+        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+                              PIIX_NUM_PIRQS, 3),
+        VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_piix3_rcr,
+        NULL
+    }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+    .read = rcr_read,
+    .write = rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static void piix3_realize(PCIDevice *dev, Error **errp)
+{
+    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+
+    if (!isa_bus_new(DEVICE(d), get_system_memory(),
+                     pci_address_space_io(dev), errp)) {
+        return;
+    }
+
+    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
+                          "piix3-reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
+                                        &d->rcr_mem, 1);
+
+    qemu_register_reset(piix3_reset, d);
+}
+
+static void pci_piix3_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    dc->desc        = "ISA bridge";
+    dc->vmsd        = &vmstate_piix3;
+    dc->hotpluggable   = false;
+    k->realize      = piix3_realize;
+    k->vendor_id    = PCI_VENDOR_ID_INTEL;
+    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
+    k->class_id     = PCI_CLASS_BRIDGE_ISA;
+    /*
+     * Reason: part of PIIX3 southbridge, needs to be wired up by
+     * pc_piix.c's pc_init1()
+     */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo piix3_pci_type_info = {
+    .name = TYPE_PIIX3_PCI_DEVICE,
+    .parent = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PIIX3State),
+    .abstract = true,
+    .class_init = pci_piix3_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+        { },
+    },
+};
+
+static void piix3_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config;
+}
+
+static const TypeInfo piix3_info = {
+    .name          = TYPE_PIIX3_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_class_init,
+};
+
+static void piix3_xen_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config_xen;
+};
+
+static const TypeInfo piix3_xen_info = {
+    .name          = TYPE_PIIX3_XEN_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_xen_class_init,
+};
+
+static void piix3_register_types(void)
+{
+    type_register_static(&piix3_pci_type_info);
+    type_register_static(&piix3_info);
+    type_register_static(&piix3_xen_info);
+}
+
+type_init(piix3_register_types)
+
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+{
+    int slot_addend;
+    slot_addend = (pci_dev->devfn >> 3) - 1;
+    return (pci_intx + slot_addend) & 3;
+}
+
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 1edc1a31d4..397043b289 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -32,7 +32,6 @@ config PCI_PIIX
     bool
     select PCI
     select PAM
-    select ISA_BUS
 
 config PCI_EXPRESS_Q35
     bool
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 61f91ff561..79ecd58a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -24,22 +24,15 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
-#include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
-#include "qemu/range.h"
-#include "hw/xen/xen.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "hw/i386/ioapic.h"
 #include "qapi/visitor.h"
 #include "qemu/error-report.h"
 
@@ -59,49 +52,9 @@ typedef struct I440FXState {
     uint32_t short_root_bus;
 } I440FXState;
 
-#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
-#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
-#define XEN_PIIX_NUM_PIRQS      128ULL
-
-typedef struct PIIX3State {
-    PCIDevice dev;
-
-    /*
-     * bitmap to track pic levels.
-     * The pic level is the logical OR of all the PCI irqs mapped to it
-     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
-     *
-     * PIRQ is mapped to PIC pins, we track it by
-     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
-     * pic_irq * PIIX_NUM_PIRQS + pirq
-     */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
-    uint64_t pic_levels;
-
-    qemu_irq *pic;
-
-    /* This member isn't used. Just for save/load compatibility */
-    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
-    /* Reset Control Register contents */
-    uint8_t rcr;
-
-    /* IO memory region for Reset Control Register (RCR_IOPORT) */
-    MemoryRegion rcr_mem;
-} PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-#define PIIX3_PCI_DEVICE(obj) \
-    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
-
 #define I440FX_PCI_DEVICE(obj) \
     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 
-#define TYPE_PIIX3_DEVICE "PIIX3"
-#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
-
 struct PCII440FXState {
     /*< private >*/
     PCIDevice parent_obj;
@@ -128,22 +81,6 @@ struct PCII440FXState {
  */
 #define I440FX_COREBOOT_RAM_SIZE 0x57
 
-static void piix3_set_irq(void *opaque, int pirq, int level);
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len);
-
-/*
- * Return the global irq number corresponding to a given device irq
- * pin. We could also use the bus number to have a more precise mapping.
- */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
-{
-    int slot_addend;
-    slot_addend = (pci_dev->devfn >> 3) - 1;
-    return (pci_intx + slot_addend) & 3;
-}
-
 static void i440fx_update_memory_mappings(PCII440FXState *d)
 {
     int i;
@@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
-static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
-{
-    PIIX3State *piix3;
-    PCIDevice *pci_dev;
-
-    /*
-     * Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI.
-     */
-    if (xen_enabled()) {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                     piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
-                     piix3, PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
-    }
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
-    return piix3;
-}
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
     return s ? s->bus : NULL;
 }
 
-/* PIIX3 PCI to ISA bridge */
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
-{
-    qemu_set_irq(piix3->pic[pic_irq],
-                 !!(piix3->pic_levels &
-                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
-                     (pic_irq * PIIX_NUM_PIRQS))));
-}
-
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-    uint64_t mask;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
-    piix3->pic_levels &= ~mask;
-    piix3->pic_levels |= mask * !!level;
-}
-
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    piix3_set_irq_level_internal(piix3, pirq, level);
-
-    piix3_set_irq_pic(piix3, pic_irq);
-}
-
-static void piix3_set_irq(void *opaque, int pirq, int level)
-{
-    PIIX3State *piix3 = opaque;
-    piix3_set_irq_level(piix3, pirq, level);
-}
-
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
-{
-    PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
-    PCIINTxRoute route;
-
-    if (irq < PIIX_NUM_PIC_IRQS) {
-        route.mode = PCI_INTX_ENABLED;
-        route.irq = irq;
-    } else {
-        route.mode = PCI_INTX_DISABLED;
-        route.irq = -1;
-    }
-    return route;
-}
-
-/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
-{
-    PCIBus *bus = pci_get_bus(&piix3->dev);
-    int pirq;
-
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
-    }
-}
-
-static void piix3_write_config(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
-        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
-        int pic_irq;
-
-        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
-        piix3_update_irq_levels(piix3);
-        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
-            piix3_set_irq_pic(piix3, pic_irq);
-        }
-    }
-}
-
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    xen_piix_pci_write_config_client(address, val, len);
-    piix3_write_config(dev, address, val, len);
-}
-
-static void piix3_reset(void *opaque)
-{
-    PIIX3State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
-
-    pci_conf[0x04] = 0x07; /* master, memory and I/O */
-    pci_conf[0x05] = 0x00;
-    pci_conf[0x06] = 0x00;
-    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
-    pci_conf[0x4c] = 0x4d;
-    pci_conf[0x4e] = 0x03;
-    pci_conf[0x4f] = 0x00;
-    pci_conf[0x60] = 0x80;
-    pci_conf[0x61] = 0x80;
-    pci_conf[0x62] = 0x80;
-    pci_conf[0x63] = 0x80;
-    pci_conf[0x69] = 0x02;
-    pci_conf[0x70] = 0x80;
-    pci_conf[0x76] = 0x0c;
-    pci_conf[0x77] = 0x0c;
-    pci_conf[0x78] = 0x02;
-    pci_conf[0x79] = 0x00;
-    pci_conf[0x80] = 0x00;
-    pci_conf[0x82] = 0x00;
-    pci_conf[0xa0] = 0x08;
-    pci_conf[0xa2] = 0x00;
-    pci_conf[0xa3] = 0x00;
-    pci_conf[0xa4] = 0x00;
-    pci_conf[0xa5] = 0x00;
-    pci_conf[0xa6] = 0x00;
-    pci_conf[0xa7] = 0x00;
-    pci_conf[0xa8] = 0x0f;
-    pci_conf[0xaa] = 0x00;
-    pci_conf[0xab] = 0x00;
-    pci_conf[0xac] = 0x00;
-    pci_conf[0xae] = 0x00;
-
-    d->pic_levels = 0;
-    d->rcr = 0;
-}
-
-static int piix3_post_load(void *opaque, int version_id)
-{
-    PIIX3State *piix3 = opaque;
-    int pirq;
-
-    /* Because the i8259 has not been deserialized yet, qemu_irq_raise
-     * might bring the system to a different state than the saved one;
-     * for example, the interrupt could be masked but the i8259 would
-     * not know that yet and would trigger an interrupt in the CPU.
-     *
-     * Here, we update irq levels without raising the interrupt.
-     * Interrupt state will be deserialized separately through the i8259.
-     */
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level_internal(piix3, pirq,
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
-    }
-    return 0;
-}
-
-static int piix3_pre_save(void *opaque)
-{
-    int i;
-    PIIX3State *piix3 = opaque;
-
-    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
-        piix3->pci_irq_levels_vmstate[i] =
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
-    }
-
-    return 0;
-}
-
-static bool piix3_rcr_needed(void *opaque)
-{
-    PIIX3State *piix3 = opaque;
-
-    return (piix3->rcr != 0);
-}
-
-static const VMStateDescription vmstate_piix3_rcr = {
-    .name = "PIIX3/rcr",
-    .version_id = 1,
-    .minimum_version_id = 1,
-    .needed = piix3_rcr_needed,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT8(rcr, PIIX3State),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-static const VMStateDescription vmstate_piix3 = {
-    .name = "PIIX3",
-    .version_id = 3,
-    .minimum_version_id = 2,
-    .post_load = piix3_post_load,
-    .pre_save = piix3_pre_save,
-    .fields = (VMStateField[]) {
-        VMSTATE_PCI_DEVICE(dev, PIIX3State),
-        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
-                              PIIX_NUM_PIRQS, 3),
-        VMSTATE_END_OF_LIST()
-    },
-    .subsections = (const VMStateDescription*[]) {
-        &vmstate_piix3_rcr,
-        NULL
-    }
-};
-
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    if (val & 4) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-        return;
-    }
-    d->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    return d->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
-    .read = rcr_read,
-    .write = rcr_write,
-    .endianness = DEVICE_LITTLE_ENDIAN
-};
-
-static void piix3_realize(PCIDevice *dev, Error **errp)
-{
-    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
-
-    if (!isa_bus_new(DEVICE(d), get_system_memory(),
-                     pci_address_space_io(dev), errp)) {
-        return;
-    }
-
-    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
-                          "piix3-reset-control", 1);
-    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
-                                        &d->rcr_mem, 1);
-
-    qemu_register_reset(piix3_reset, d);
-}
-
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    dc->desc        = "ISA bridge";
-    dc->vmsd        = &vmstate_piix3;
-    dc->hotpluggable   = false;
-    k->realize      = piix3_realize;
-    k->vendor_id    = PCI_VENDOR_ID_INTEL;
-    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
-    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
-    k->class_id     = PCI_CLASS_BRIDGE_ISA;
-    /*
-     * Reason: part of PIIX3 southbridge, needs to be wired up by
-     * pc_piix.c's pc_init1()
-     */
-    dc->user_creatable = false;
-}
-
-static const TypeInfo piix3_pci_type_info = {
-    .name = TYPE_PIIX3_PCI_DEVICE,
-    .parent = TYPE_PCI_DEVICE,
-    .instance_size = sizeof(PIIX3State),
-    .abstract = true,
-    .class_init = pci_piix3_class_init,
-    .interfaces = (InterfaceInfo[]) {
-        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
-        { },
-    },
-};
-
-static void piix3_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config;
-}
-
-static const TypeInfo piix3_info = {
-    .name          = TYPE_PIIX3_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_class_init,
-};
-
-static void piix3_xen_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config_xen;
-};
-
-static const TypeInfo piix3_xen_info = {
-    .name          = TYPE_PIIX3_XEN_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_xen_class_init,
-};
-
 static void i440fx_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -922,9 +523,6 @@ static void i440fx_register_types(void)
 {
     type_register_static(&i440fx_info);
     type_register_static(&igd_passthrough_i440fx_info);
-    type_register_static(&piix3_pci_type_info);
-    type_register_static(&piix3_info);
-    type_register_static(&piix3_xen_info);
     type_register_static(&i440fx_pcihost_info);
 }
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 9c92c37a4d..324a3a99fc 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -12,6 +12,8 @@
 #ifndef HW_SOUTHBRIDGE_PIIX_H
 #define HW_SOUTHBRIDGE_PIIX_H
 
+#include "hw/pci/pci.h"
+
 #define TYPE_PIIX4_PM "PIIX4_PM"
 
 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  */
 #define RCR_IOPORT 0xcf9
 
+#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
+#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+    PCIDevice dev;
+
+    /*
+     * bitmap to track pic levels.
+     * The pic level is the logical OR of all the PCI irqs mapped to it
+     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+     *
+     * PIRQ is mapped to PIC pins, we track it by
+     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+     * pic_irq * PIIX_NUM_PIRQS + pirq
+     */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+    uint64_t pic_levels;
+
+    qemu_irq *pic;
+
+    /* This member isn't used. Just for save/load compatibility */
+    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+    /* Reset Control Register contents */
+    uint8_t rcr;
+
+    /* IO memory region for Reset Control Register (RCR_IOPORT) */
+    MemoryRegion rcr_mem;
+} PIIX3State;
+
 extern PCIDevice *piix4_dev;
 
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
                           I2CBus **smbus, size_t ide_buses);
 
-- 
2.21.0

[PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Move all the PIIX3 functions to a new file: hw/isa/piix3.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Checkpatch warning:

 ERROR: spaces required around that '*' (ctx:VxV)
 #312: FILE: hw/isa/piix3.c:248:
 +    .subsections = (const VMStateDescription*[]) {
                                              ^
---
 MAINTAINERS                   |   1 +
 hw/i386/Kconfig               |   1 +
 hw/isa/Kconfig                |   4 +
 hw/isa/Makefile.objs          |   1 +
 hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
 hw/pci-host/Kconfig           |   1 -
 hw/pci-host/piix.c            | 402 ----------------------------------
 include/hw/southbridge/piix.h |  36 +++
 8 files changed, 442 insertions(+), 403 deletions(-)
 create mode 100644 hw/isa/piix3.c

diff --git a/MAINTAINERS b/MAINTAINERS
index adf059a164..4845f47d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..589d75e26a 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -61,6 +61,7 @@ config I440FX
     select PC_ACPI
     select ACPI_SMBUS
     select PCI_PIIX
+    select PIIX3
     select IDE_PIIX
     select DIMM
     select SMBIOS
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 98a289957e..8a38813cc1 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -29,6 +29,10 @@ config PC87312
     select FDC
     select IDE_ISA
 
+config PIIX3
+    bool
+    select ISA_BUS
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index ff97485504..8e73960a75 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
 common-obj-$(CONFIG_APM) += apm.o
 common-obj-$(CONFIG_I82378) += i82378.o
 common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
 common-obj-$(CONFIG_PIIX4) += piix4.o
 common-obj-$(CONFIG_VT82C686) += vt82c686.o
 common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
new file mode 100644
index 0000000000..05146447ef
--- /dev/null
+++ b/hw/isa/piix3.c
@@ -0,0 +1,399 @@
+/*
+ * QEMU PIIX PCI ISA Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "hw/southbridge/piix.h"
+#include "hw/irq.h"
+#include "hw/isa/isa.h"
+#include "hw/xen/xen.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
+
+#define XEN_PIIX_NUM_PIRQS      128ULL
+
+#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
+#define PIIX3_PCI_DEVICE(obj) \
+    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
+
+#define TYPE_PIIX3_DEVICE "PIIX3"
+#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
+
+static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+{
+    qemu_set_irq(piix3->pic[pic_irq],
+                 !!(piix3->pic_levels &
+                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
+                     (pic_irq * PIIX_NUM_PIRQS))));
+}
+
+static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+    uint64_t mask;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
+    piix3->pic_levels &= ~mask;
+    piix3->pic_levels |= mask * !!level;
+}
+
+static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    piix3_set_irq_level_internal(piix3, pirq, level);
+
+    piix3_set_irq_pic(piix3, pic_irq);
+}
+
+static void piix3_set_irq(void *opaque, int pirq, int level)
+{
+    PIIX3State *piix3 = opaque;
+    piix3_set_irq_level(piix3, pirq, level);
+}
+
+static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+{
+    PIIX3State *piix3 = opaque;
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+    PCIINTxRoute route;
+
+    if (irq < PIIX_NUM_PIC_IRQS) {
+        route.mode = PCI_INTX_ENABLED;
+        route.irq = irq;
+    } else {
+        route.mode = PCI_INTX_DISABLED;
+        route.irq = -1;
+    }
+    return route;
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+    PCIBus *bus = pci_get_bus(&piix3->dev);
+    int pirq;
+
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+    }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+                               uint32_t address, uint32_t val, int len)
+{
+    pci_default_write_config(dev, address, val, len);
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
+        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+        int pic_irq;
+
+        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
+        piix3_update_irq_levels(piix3);
+        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+            piix3_set_irq_pic(piix3, pic_irq);
+        }
+    }
+}
+
+static void piix3_write_config_xen(PCIDevice *dev,
+                                   uint32_t address, uint32_t val, int len)
+{
+    xen_piix_pci_write_config_client(address, val, len);
+    piix3_write_config(dev, address, val, len);
+}
+
+static void piix3_reset(void *opaque)
+{
+    PIIX3State *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
+
+    pci_conf[0x04] = 0x07; /* master, memory and I/O */
+    pci_conf[0x05] = 0x00;
+    pci_conf[0x06] = 0x00;
+    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
+    pci_conf[0x4c] = 0x4d;
+    pci_conf[0x4e] = 0x03;
+    pci_conf[0x4f] = 0x00;
+    pci_conf[0x60] = 0x80;
+    pci_conf[0x61] = 0x80;
+    pci_conf[0x62] = 0x80;
+    pci_conf[0x63] = 0x80;
+    pci_conf[0x69] = 0x02;
+    pci_conf[0x70] = 0x80;
+    pci_conf[0x76] = 0x0c;
+    pci_conf[0x77] = 0x0c;
+    pci_conf[0x78] = 0x02;
+    pci_conf[0x79] = 0x00;
+    pci_conf[0x80] = 0x00;
+    pci_conf[0x82] = 0x00;
+    pci_conf[0xa0] = 0x08;
+    pci_conf[0xa2] = 0x00;
+    pci_conf[0xa3] = 0x00;
+    pci_conf[0xa4] = 0x00;
+    pci_conf[0xa5] = 0x00;
+    pci_conf[0xa6] = 0x00;
+    pci_conf[0xa7] = 0x00;
+    pci_conf[0xa8] = 0x0f;
+    pci_conf[0xaa] = 0x00;
+    pci_conf[0xab] = 0x00;
+    pci_conf[0xac] = 0x00;
+    pci_conf[0xae] = 0x00;
+
+    d->pic_levels = 0;
+    d->rcr = 0;
+}
+
+static int piix3_post_load(void *opaque, int version_id)
+{
+    PIIX3State *piix3 = opaque;
+    int pirq;
+
+    /*
+     * Because the i8259 has not been deserialized yet, qemu_irq_raise
+     * might bring the system to a different state than the saved one;
+     * for example, the interrupt could be masked but the i8259 would
+     * not know that yet and would trigger an interrupt in the CPU.
+     *
+     * Here, we update irq levels without raising the interrupt.
+     * Interrupt state will be deserialized separately through the i8259.
+     */
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level_internal(piix3, pirq,
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+    }
+    return 0;
+}
+
+static int piix3_pre_save(void *opaque)
+{
+    int i;
+    PIIX3State *piix3 = opaque;
+
+    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
+        piix3->pci_irq_levels_vmstate[i] =
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
+    }
+
+    return 0;
+}
+
+static bool piix3_rcr_needed(void *opaque)
+{
+    PIIX3State *piix3 = opaque;
+
+    return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+    .name = "PIIX3/rcr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = piix3_rcr_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(rcr, PIIX3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_piix3 = {
+    .name = "PIIX3",
+    .version_id = 3,
+    .minimum_version_id = 2,
+    .post_load = piix3_post_load,
+    .pre_save = piix3_pre_save,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, PIIX3State),
+        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+                              PIIX_NUM_PIRQS, 3),
+        VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_piix3_rcr,
+        NULL
+    }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+    .read = rcr_read,
+    .write = rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static void piix3_realize(PCIDevice *dev, Error **errp)
+{
+    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+
+    if (!isa_bus_new(DEVICE(d), get_system_memory(),
+                     pci_address_space_io(dev), errp)) {
+        return;
+    }
+
+    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
+                          "piix3-reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
+                                        &d->rcr_mem, 1);
+
+    qemu_register_reset(piix3_reset, d);
+}
+
+static void pci_piix3_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    dc->desc        = "ISA bridge";
+    dc->vmsd        = &vmstate_piix3;
+    dc->hotpluggable   = false;
+    k->realize      = piix3_realize;
+    k->vendor_id    = PCI_VENDOR_ID_INTEL;
+    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
+    k->class_id     = PCI_CLASS_BRIDGE_ISA;
+    /*
+     * Reason: part of PIIX3 southbridge, needs to be wired up by
+     * pc_piix.c's pc_init1()
+     */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo piix3_pci_type_info = {
+    .name = TYPE_PIIX3_PCI_DEVICE,
+    .parent = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PIIX3State),
+    .abstract = true,
+    .class_init = pci_piix3_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+        { },
+    },
+};
+
+static void piix3_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config;
+}
+
+static const TypeInfo piix3_info = {
+    .name          = TYPE_PIIX3_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_class_init,
+};
+
+static void piix3_xen_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config_xen;
+};
+
+static const TypeInfo piix3_xen_info = {
+    .name          = TYPE_PIIX3_XEN_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_xen_class_init,
+};
+
+static void piix3_register_types(void)
+{
+    type_register_static(&piix3_pci_type_info);
+    type_register_static(&piix3_info);
+    type_register_static(&piix3_xen_info);
+}
+
+type_init(piix3_register_types)
+
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+{
+    int slot_addend;
+    slot_addend = (pci_dev->devfn >> 3) - 1;
+    return (pci_intx + slot_addend) & 3;
+}
+
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 1edc1a31d4..397043b289 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -32,7 +32,6 @@ config PCI_PIIX
     bool
     select PCI
     select PAM
-    select ISA_BUS
 
 config PCI_EXPRESS_Q35
     bool
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 61f91ff561..79ecd58a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -24,22 +24,15 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
-#include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
-#include "qemu/range.h"
-#include "hw/xen/xen.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "hw/i386/ioapic.h"
 #include "qapi/visitor.h"
 #include "qemu/error-report.h"
 
@@ -59,49 +52,9 @@ typedef struct I440FXState {
     uint32_t short_root_bus;
 } I440FXState;
 
-#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
-#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
-#define XEN_PIIX_NUM_PIRQS      128ULL
-
-typedef struct PIIX3State {
-    PCIDevice dev;
-
-    /*
-     * bitmap to track pic levels.
-     * The pic level is the logical OR of all the PCI irqs mapped to it
-     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
-     *
-     * PIRQ is mapped to PIC pins, we track it by
-     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
-     * pic_irq * PIIX_NUM_PIRQS + pirq
-     */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
-    uint64_t pic_levels;
-
-    qemu_irq *pic;
-
-    /* This member isn't used. Just for save/load compatibility */
-    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
-    /* Reset Control Register contents */
-    uint8_t rcr;
-
-    /* IO memory region for Reset Control Register (RCR_IOPORT) */
-    MemoryRegion rcr_mem;
-} PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-#define PIIX3_PCI_DEVICE(obj) \
-    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
-
 #define I440FX_PCI_DEVICE(obj) \
     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 
-#define TYPE_PIIX3_DEVICE "PIIX3"
-#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
-
 struct PCII440FXState {
     /*< private >*/
     PCIDevice parent_obj;
@@ -128,22 +81,6 @@ struct PCII440FXState {
  */
 #define I440FX_COREBOOT_RAM_SIZE 0x57
 
-static void piix3_set_irq(void *opaque, int pirq, int level);
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len);
-
-/*
- * Return the global irq number corresponding to a given device irq
- * pin. We could also use the bus number to have a more precise mapping.
- */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
-{
-    int slot_addend;
-    slot_addend = (pci_dev->devfn >> 3) - 1;
-    return (pci_intx + slot_addend) & 3;
-}
-
 static void i440fx_update_memory_mappings(PCII440FXState *d)
 {
     int i;
@@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
-static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
-{
-    PIIX3State *piix3;
-    PCIDevice *pci_dev;
-
-    /*
-     * Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI.
-     */
-    if (xen_enabled()) {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                     piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
-                     piix3, PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
-    }
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
-    return piix3;
-}
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
     return s ? s->bus : NULL;
 }
 
-/* PIIX3 PCI to ISA bridge */
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
-{
-    qemu_set_irq(piix3->pic[pic_irq],
-                 !!(piix3->pic_levels &
-                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
-                     (pic_irq * PIIX_NUM_PIRQS))));
-}
-
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-    uint64_t mask;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
-    piix3->pic_levels &= ~mask;
-    piix3->pic_levels |= mask * !!level;
-}
-
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    piix3_set_irq_level_internal(piix3, pirq, level);
-
-    piix3_set_irq_pic(piix3, pic_irq);
-}
-
-static void piix3_set_irq(void *opaque, int pirq, int level)
-{
-    PIIX3State *piix3 = opaque;
-    piix3_set_irq_level(piix3, pirq, level);
-}
-
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
-{
-    PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
-    PCIINTxRoute route;
-
-    if (irq < PIIX_NUM_PIC_IRQS) {
-        route.mode = PCI_INTX_ENABLED;
-        route.irq = irq;
-    } else {
-        route.mode = PCI_INTX_DISABLED;
-        route.irq = -1;
-    }
-    return route;
-}
-
-/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
-{
-    PCIBus *bus = pci_get_bus(&piix3->dev);
-    int pirq;
-
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
-    }
-}
-
-static void piix3_write_config(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
-        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
-        int pic_irq;
-
-        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
-        piix3_update_irq_levels(piix3);
-        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
-            piix3_set_irq_pic(piix3, pic_irq);
-        }
-    }
-}
-
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    xen_piix_pci_write_config_client(address, val, len);
-    piix3_write_config(dev, address, val, len);
-}
-
-static void piix3_reset(void *opaque)
-{
-    PIIX3State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
-
-    pci_conf[0x04] = 0x07; /* master, memory and I/O */
-    pci_conf[0x05] = 0x00;
-    pci_conf[0x06] = 0x00;
-    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
-    pci_conf[0x4c] = 0x4d;
-    pci_conf[0x4e] = 0x03;
-    pci_conf[0x4f] = 0x00;
-    pci_conf[0x60] = 0x80;
-    pci_conf[0x61] = 0x80;
-    pci_conf[0x62] = 0x80;
-    pci_conf[0x63] = 0x80;
-    pci_conf[0x69] = 0x02;
-    pci_conf[0x70] = 0x80;
-    pci_conf[0x76] = 0x0c;
-    pci_conf[0x77] = 0x0c;
-    pci_conf[0x78] = 0x02;
-    pci_conf[0x79] = 0x00;
-    pci_conf[0x80] = 0x00;
-    pci_conf[0x82] = 0x00;
-    pci_conf[0xa0] = 0x08;
-    pci_conf[0xa2] = 0x00;
-    pci_conf[0xa3] = 0x00;
-    pci_conf[0xa4] = 0x00;
-    pci_conf[0xa5] = 0x00;
-    pci_conf[0xa6] = 0x00;
-    pci_conf[0xa7] = 0x00;
-    pci_conf[0xa8] = 0x0f;
-    pci_conf[0xaa] = 0x00;
-    pci_conf[0xab] = 0x00;
-    pci_conf[0xac] = 0x00;
-    pci_conf[0xae] = 0x00;
-
-    d->pic_levels = 0;
-    d->rcr = 0;
-}
-
-static int piix3_post_load(void *opaque, int version_id)
-{
-    PIIX3State *piix3 = opaque;
-    int pirq;
-
-    /* Because the i8259 has not been deserialized yet, qemu_irq_raise
-     * might bring the system to a different state than the saved one;
-     * for example, the interrupt could be masked but the i8259 would
-     * not know that yet and would trigger an interrupt in the CPU.
-     *
-     * Here, we update irq levels without raising the interrupt.
-     * Interrupt state will be deserialized separately through the i8259.
-     */
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level_internal(piix3, pirq,
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
-    }
-    return 0;
-}
-
-static int piix3_pre_save(void *opaque)
-{
-    int i;
-    PIIX3State *piix3 = opaque;
-
-    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
-        piix3->pci_irq_levels_vmstate[i] =
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
-    }
-
-    return 0;
-}
-
-static bool piix3_rcr_needed(void *opaque)
-{
-    PIIX3State *piix3 = opaque;
-
-    return (piix3->rcr != 0);
-}
-
-static const VMStateDescription vmstate_piix3_rcr = {
-    .name = "PIIX3/rcr",
-    .version_id = 1,
-    .minimum_version_id = 1,
-    .needed = piix3_rcr_needed,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT8(rcr, PIIX3State),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-static const VMStateDescription vmstate_piix3 = {
-    .name = "PIIX3",
-    .version_id = 3,
-    .minimum_version_id = 2,
-    .post_load = piix3_post_load,
-    .pre_save = piix3_pre_save,
-    .fields = (VMStateField[]) {
-        VMSTATE_PCI_DEVICE(dev, PIIX3State),
-        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
-                              PIIX_NUM_PIRQS, 3),
-        VMSTATE_END_OF_LIST()
-    },
-    .subsections = (const VMStateDescription*[]) {
-        &vmstate_piix3_rcr,
-        NULL
-    }
-};
-
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    if (val & 4) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-        return;
-    }
-    d->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    return d->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
-    .read = rcr_read,
-    .write = rcr_write,
-    .endianness = DEVICE_LITTLE_ENDIAN
-};
-
-static void piix3_realize(PCIDevice *dev, Error **errp)
-{
-    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
-
-    if (!isa_bus_new(DEVICE(d), get_system_memory(),
-                     pci_address_space_io(dev), errp)) {
-        return;
-    }
-
-    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
-                          "piix3-reset-control", 1);
-    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
-                                        &d->rcr_mem, 1);
-
-    qemu_register_reset(piix3_reset, d);
-}
-
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    dc->desc        = "ISA bridge";
-    dc->vmsd        = &vmstate_piix3;
-    dc->hotpluggable   = false;
-    k->realize      = piix3_realize;
-    k->vendor_id    = PCI_VENDOR_ID_INTEL;
-    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
-    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
-    k->class_id     = PCI_CLASS_BRIDGE_ISA;
-    /*
-     * Reason: part of PIIX3 southbridge, needs to be wired up by
-     * pc_piix.c's pc_init1()
-     */
-    dc->user_creatable = false;
-}
-
-static const TypeInfo piix3_pci_type_info = {
-    .name = TYPE_PIIX3_PCI_DEVICE,
-    .parent = TYPE_PCI_DEVICE,
-    .instance_size = sizeof(PIIX3State),
-    .abstract = true,
-    .class_init = pci_piix3_class_init,
-    .interfaces = (InterfaceInfo[]) {
-        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
-        { },
-    },
-};
-
-static void piix3_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config;
-}
-
-static const TypeInfo piix3_info = {
-    .name          = TYPE_PIIX3_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_class_init,
-};
-
-static void piix3_xen_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config_xen;
-};
-
-static const TypeInfo piix3_xen_info = {
-    .name          = TYPE_PIIX3_XEN_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_xen_class_init,
-};
-
 static void i440fx_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -922,9 +523,6 @@ static void i440fx_register_types(void)
 {
     type_register_static(&i440fx_info);
     type_register_static(&igd_passthrough_i440fx_info);
-    type_register_static(&piix3_pci_type_info);
-    type_register_static(&piix3_info);
-    type_register_static(&piix3_xen_info);
     type_register_static(&i440fx_pcihost_info);
 }
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 9c92c37a4d..324a3a99fc 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -12,6 +12,8 @@
 #ifndef HW_SOUTHBRIDGE_PIIX_H
 #define HW_SOUTHBRIDGE_PIIX_H
 
+#include "hw/pci/pci.h"
+
 #define TYPE_PIIX4_PM "PIIX4_PM"
 
 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  */
 #define RCR_IOPORT 0xcf9
 
+#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
+#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+    PCIDevice dev;
+
+    /*
+     * bitmap to track pic levels.
+     * The pic level is the logical OR of all the PCI irqs mapped to it
+     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+     *
+     * PIRQ is mapped to PIC pins, we track it by
+     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+     * pic_irq * PIIX_NUM_PIRQS + pirq
+     */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+    uint64_t pic_levels;
+
+    qemu_irq *pic;
+
+    /* This member isn't used. Just for save/load compatibility */
+    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+    /* Reset Control Register contents */
+    uint8_t rcr;
+
+    /* IO memory region for Reset Control Register (RCR_IOPORT) */
+    MemoryRegion rcr_mem;
+} PIIX3State;
+
 extern PCIDevice *piix4_dev;
 
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
                           I2CBus **smbus, size_t ide_buses);
 
-- 
2.21.0

[Xen-devel] [PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Move all the PIIX3 functions to a new file: hw/isa/piix3.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Checkpatch warning:

 ERROR: spaces required around that '*' (ctx:VxV)
 #312: FILE: hw/isa/piix3.c:248:
 +    .subsections = (const VMStateDescription*[]) {
                                              ^
---
 MAINTAINERS                   |   1 +
 hw/i386/Kconfig               |   1 +
 hw/isa/Kconfig                |   4 +
 hw/isa/Makefile.objs          |   1 +
 hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
 hw/pci-host/Kconfig           |   1 -
 hw/pci-host/piix.c            | 402 ----------------------------------
 include/hw/southbridge/piix.h |  36 +++
 8 files changed, 442 insertions(+), 403 deletions(-)
 create mode 100644 hw/isa/piix3.c

diff --git a/MAINTAINERS b/MAINTAINERS
index adf059a164..4845f47d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..589d75e26a 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -61,6 +61,7 @@ config I440FX
     select PC_ACPI
     select ACPI_SMBUS
     select PCI_PIIX
+    select PIIX3
     select IDE_PIIX
     select DIMM
     select SMBIOS
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 98a289957e..8a38813cc1 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -29,6 +29,10 @@ config PC87312
     select FDC
     select IDE_ISA
 
+config PIIX3
+    bool
+    select ISA_BUS
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index ff97485504..8e73960a75 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
 common-obj-$(CONFIG_APM) += apm.o
 common-obj-$(CONFIG_I82378) += i82378.o
 common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
 common-obj-$(CONFIG_PIIX4) += piix4.o
 common-obj-$(CONFIG_VT82C686) += vt82c686.o
 common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
new file mode 100644
index 0000000000..05146447ef
--- /dev/null
+++ b/hw/isa/piix3.c
@@ -0,0 +1,399 @@
+/*
+ * QEMU PIIX PCI ISA Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "hw/southbridge/piix.h"
+#include "hw/irq.h"
+#include "hw/isa/isa.h"
+#include "hw/xen/xen.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
+
+#define XEN_PIIX_NUM_PIRQS      128ULL
+
+#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
+#define PIIX3_PCI_DEVICE(obj) \
+    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
+
+#define TYPE_PIIX3_DEVICE "PIIX3"
+#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
+
+static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+{
+    qemu_set_irq(piix3->pic[pic_irq],
+                 !!(piix3->pic_levels &
+                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
+                     (pic_irq * PIIX_NUM_PIRQS))));
+}
+
+static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+    uint64_t mask;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
+    piix3->pic_levels &= ~mask;
+    piix3->pic_levels |= mask * !!level;
+}
+
+static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+{
+    int pic_irq;
+
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+        return;
+    }
+
+    piix3_set_irq_level_internal(piix3, pirq, level);
+
+    piix3_set_irq_pic(piix3, pic_irq);
+}
+
+static void piix3_set_irq(void *opaque, int pirq, int level)
+{
+    PIIX3State *piix3 = opaque;
+    piix3_set_irq_level(piix3, pirq, level);
+}
+
+static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+{
+    PIIX3State *piix3 = opaque;
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+    PCIINTxRoute route;
+
+    if (irq < PIIX_NUM_PIC_IRQS) {
+        route.mode = PCI_INTX_ENABLED;
+        route.irq = irq;
+    } else {
+        route.mode = PCI_INTX_DISABLED;
+        route.irq = -1;
+    }
+    return route;
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+    PCIBus *bus = pci_get_bus(&piix3->dev);
+    int pirq;
+
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+    }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+                               uint32_t address, uint32_t val, int len)
+{
+    pci_default_write_config(dev, address, val, len);
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
+        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+        int pic_irq;
+
+        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
+        piix3_update_irq_levels(piix3);
+        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+            piix3_set_irq_pic(piix3, pic_irq);
+        }
+    }
+}
+
+static void piix3_write_config_xen(PCIDevice *dev,
+                                   uint32_t address, uint32_t val, int len)
+{
+    xen_piix_pci_write_config_client(address, val, len);
+    piix3_write_config(dev, address, val, len);
+}
+
+static void piix3_reset(void *opaque)
+{
+    PIIX3State *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
+
+    pci_conf[0x04] = 0x07; /* master, memory and I/O */
+    pci_conf[0x05] = 0x00;
+    pci_conf[0x06] = 0x00;
+    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
+    pci_conf[0x4c] = 0x4d;
+    pci_conf[0x4e] = 0x03;
+    pci_conf[0x4f] = 0x00;
+    pci_conf[0x60] = 0x80;
+    pci_conf[0x61] = 0x80;
+    pci_conf[0x62] = 0x80;
+    pci_conf[0x63] = 0x80;
+    pci_conf[0x69] = 0x02;
+    pci_conf[0x70] = 0x80;
+    pci_conf[0x76] = 0x0c;
+    pci_conf[0x77] = 0x0c;
+    pci_conf[0x78] = 0x02;
+    pci_conf[0x79] = 0x00;
+    pci_conf[0x80] = 0x00;
+    pci_conf[0x82] = 0x00;
+    pci_conf[0xa0] = 0x08;
+    pci_conf[0xa2] = 0x00;
+    pci_conf[0xa3] = 0x00;
+    pci_conf[0xa4] = 0x00;
+    pci_conf[0xa5] = 0x00;
+    pci_conf[0xa6] = 0x00;
+    pci_conf[0xa7] = 0x00;
+    pci_conf[0xa8] = 0x0f;
+    pci_conf[0xaa] = 0x00;
+    pci_conf[0xab] = 0x00;
+    pci_conf[0xac] = 0x00;
+    pci_conf[0xae] = 0x00;
+
+    d->pic_levels = 0;
+    d->rcr = 0;
+}
+
+static int piix3_post_load(void *opaque, int version_id)
+{
+    PIIX3State *piix3 = opaque;
+    int pirq;
+
+    /*
+     * Because the i8259 has not been deserialized yet, qemu_irq_raise
+     * might bring the system to a different state than the saved one;
+     * for example, the interrupt could be masked but the i8259 would
+     * not know that yet and would trigger an interrupt in the CPU.
+     *
+     * Here, we update irq levels without raising the interrupt.
+     * Interrupt state will be deserialized separately through the i8259.
+     */
+    piix3->pic_levels = 0;
+    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+        piix3_set_irq_level_internal(piix3, pirq,
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+    }
+    return 0;
+}
+
+static int piix3_pre_save(void *opaque)
+{
+    int i;
+    PIIX3State *piix3 = opaque;
+
+    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
+        piix3->pci_irq_levels_vmstate[i] =
+            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
+    }
+
+    return 0;
+}
+
+static bool piix3_rcr_needed(void *opaque)
+{
+    PIIX3State *piix3 = opaque;
+
+    return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+    .name = "PIIX3/rcr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = piix3_rcr_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(rcr, PIIX3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_piix3 = {
+    .name = "PIIX3",
+    .version_id = 3,
+    .minimum_version_id = 2,
+    .post_load = piix3_post_load,
+    .pre_save = piix3_pre_save,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, PIIX3State),
+        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+                              PIIX_NUM_PIRQS, 3),
+        VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_piix3_rcr,
+        NULL
+    }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+    d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+    PIIX3State *d = opaque;
+
+    return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+    .read = rcr_read,
+    .write = rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static void piix3_realize(PCIDevice *dev, Error **errp)
+{
+    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+
+    if (!isa_bus_new(DEVICE(d), get_system_memory(),
+                     pci_address_space_io(dev), errp)) {
+        return;
+    }
+
+    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
+                          "piix3-reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
+                                        &d->rcr_mem, 1);
+
+    qemu_register_reset(piix3_reset, d);
+}
+
+static void pci_piix3_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    dc->desc        = "ISA bridge";
+    dc->vmsd        = &vmstate_piix3;
+    dc->hotpluggable   = false;
+    k->realize      = piix3_realize;
+    k->vendor_id    = PCI_VENDOR_ID_INTEL;
+    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
+    k->class_id     = PCI_CLASS_BRIDGE_ISA;
+    /*
+     * Reason: part of PIIX3 southbridge, needs to be wired up by
+     * pc_piix.c's pc_init1()
+     */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo piix3_pci_type_info = {
+    .name = TYPE_PIIX3_PCI_DEVICE,
+    .parent = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PIIX3State),
+    .abstract = true,
+    .class_init = pci_piix3_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+        { },
+    },
+};
+
+static void piix3_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config;
+}
+
+static const TypeInfo piix3_info = {
+    .name          = TYPE_PIIX3_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_class_init,
+};
+
+static void piix3_xen_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_write = piix3_write_config_xen;
+};
+
+static const TypeInfo piix3_xen_info = {
+    .name          = TYPE_PIIX3_XEN_DEVICE,
+    .parent        = TYPE_PIIX3_PCI_DEVICE,
+    .class_init    = piix3_xen_class_init,
+};
+
+static void piix3_register_types(void)
+{
+    type_register_static(&piix3_pci_type_info);
+    type_register_static(&piix3_info);
+    type_register_static(&piix3_xen_info);
+}
+
+type_init(piix3_register_types)
+
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+{
+    int slot_addend;
+    slot_addend = (pci_dev->devfn >> 3) - 1;
+    return (pci_intx + slot_addend) & 3;
+}
+
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 1edc1a31d4..397043b289 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -32,7 +32,6 @@ config PCI_PIIX
     bool
     select PCI
     select PAM
-    select ISA_BUS
 
 config PCI_EXPRESS_Q35
     bool
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 61f91ff561..79ecd58a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -24,22 +24,15 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
-#include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
-#include "qemu/range.h"
-#include "hw/xen/xen.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "hw/i386/ioapic.h"
 #include "qapi/visitor.h"
 #include "qemu/error-report.h"
 
@@ -59,49 +52,9 @@ typedef struct I440FXState {
     uint32_t short_root_bus;
 } I440FXState;
 
-#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
-#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
-#define XEN_PIIX_NUM_PIRQS      128ULL
-
-typedef struct PIIX3State {
-    PCIDevice dev;
-
-    /*
-     * bitmap to track pic levels.
-     * The pic level is the logical OR of all the PCI irqs mapped to it
-     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
-     *
-     * PIRQ is mapped to PIC pins, we track it by
-     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
-     * pic_irq * PIIX_NUM_PIRQS + pirq
-     */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
-    uint64_t pic_levels;
-
-    qemu_irq *pic;
-
-    /* This member isn't used. Just for save/load compatibility */
-    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
-    /* Reset Control Register contents */
-    uint8_t rcr;
-
-    /* IO memory region for Reset Control Register (RCR_IOPORT) */
-    MemoryRegion rcr_mem;
-} PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-#define PIIX3_PCI_DEVICE(obj) \
-    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
-
 #define I440FX_PCI_DEVICE(obj) \
     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 
-#define TYPE_PIIX3_DEVICE "PIIX3"
-#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
-
 struct PCII440FXState {
     /*< private >*/
     PCIDevice parent_obj;
@@ -128,22 +81,6 @@ struct PCII440FXState {
  */
 #define I440FX_COREBOOT_RAM_SIZE 0x57
 
-static void piix3_set_irq(void *opaque, int pirq, int level);
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len);
-
-/*
- * Return the global irq number corresponding to a given device irq
- * pin. We could also use the bus number to have a more precise mapping.
- */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
-{
-    int slot_addend;
-    slot_addend = (pci_dev->devfn >> 3) - 1;
-    return (pci_intx + slot_addend) & 3;
-}
-
 static void i440fx_update_memory_mappings(PCII440FXState *d)
 {
     int i;
@@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
-static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
-{
-    PIIX3State *piix3;
-    PCIDevice *pci_dev;
-
-    /*
-     * Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI.
-     */
-    if (xen_enabled()) {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                     piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
-                                                  TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
-                     piix3, PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
-    }
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
-    return piix3;
-}
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
@@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
     return s ? s->bus : NULL;
 }
 
-/* PIIX3 PCI to ISA bridge */
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
-{
-    qemu_set_irq(piix3->pic[pic_irq],
-                 !!(piix3->pic_levels &
-                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
-                     (pic_irq * PIIX_NUM_PIRQS))));
-}
-
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-    uint64_t mask;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
-    piix3->pic_levels &= ~mask;
-    piix3->pic_levels |= mask * !!level;
-}
-
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
-{
-    int pic_irq;
-
-    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
-    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
-        return;
-    }
-
-    piix3_set_irq_level_internal(piix3, pirq, level);
-
-    piix3_set_irq_pic(piix3, pic_irq);
-}
-
-static void piix3_set_irq(void *opaque, int pirq, int level)
-{
-    PIIX3State *piix3 = opaque;
-    piix3_set_irq_level(piix3, pirq, level);
-}
-
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
-{
-    PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
-    PCIINTxRoute route;
-
-    if (irq < PIIX_NUM_PIC_IRQS) {
-        route.mode = PCI_INTX_ENABLED;
-        route.irq = irq;
-    } else {
-        route.mode = PCI_INTX_DISABLED;
-        route.irq = -1;
-    }
-    return route;
-}
-
-/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
-{
-    PCIBus *bus = pci_get_bus(&piix3->dev);
-    int pirq;
-
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
-    }
-}
-
-static void piix3_write_config(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
-        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
-        int pic_irq;
-
-        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
-        piix3_update_irq_levels(piix3);
-        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
-            piix3_set_irq_pic(piix3, pic_irq);
-        }
-    }
-}
-
-static void piix3_write_config_xen(PCIDevice *dev,
-                               uint32_t address, uint32_t val, int len)
-{
-    xen_piix_pci_write_config_client(address, val, len);
-    piix3_write_config(dev, address, val, len);
-}
-
-static void piix3_reset(void *opaque)
-{
-    PIIX3State *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
-
-    pci_conf[0x04] = 0x07; /* master, memory and I/O */
-    pci_conf[0x05] = 0x00;
-    pci_conf[0x06] = 0x00;
-    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
-    pci_conf[0x4c] = 0x4d;
-    pci_conf[0x4e] = 0x03;
-    pci_conf[0x4f] = 0x00;
-    pci_conf[0x60] = 0x80;
-    pci_conf[0x61] = 0x80;
-    pci_conf[0x62] = 0x80;
-    pci_conf[0x63] = 0x80;
-    pci_conf[0x69] = 0x02;
-    pci_conf[0x70] = 0x80;
-    pci_conf[0x76] = 0x0c;
-    pci_conf[0x77] = 0x0c;
-    pci_conf[0x78] = 0x02;
-    pci_conf[0x79] = 0x00;
-    pci_conf[0x80] = 0x00;
-    pci_conf[0x82] = 0x00;
-    pci_conf[0xa0] = 0x08;
-    pci_conf[0xa2] = 0x00;
-    pci_conf[0xa3] = 0x00;
-    pci_conf[0xa4] = 0x00;
-    pci_conf[0xa5] = 0x00;
-    pci_conf[0xa6] = 0x00;
-    pci_conf[0xa7] = 0x00;
-    pci_conf[0xa8] = 0x0f;
-    pci_conf[0xaa] = 0x00;
-    pci_conf[0xab] = 0x00;
-    pci_conf[0xac] = 0x00;
-    pci_conf[0xae] = 0x00;
-
-    d->pic_levels = 0;
-    d->rcr = 0;
-}
-
-static int piix3_post_load(void *opaque, int version_id)
-{
-    PIIX3State *piix3 = opaque;
-    int pirq;
-
-    /* Because the i8259 has not been deserialized yet, qemu_irq_raise
-     * might bring the system to a different state than the saved one;
-     * for example, the interrupt could be masked but the i8259 would
-     * not know that yet and would trigger an interrupt in the CPU.
-     *
-     * Here, we update irq levels without raising the interrupt.
-     * Interrupt state will be deserialized separately through the i8259.
-     */
-    piix3->pic_levels = 0;
-    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
-        piix3_set_irq_level_internal(piix3, pirq,
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
-    }
-    return 0;
-}
-
-static int piix3_pre_save(void *opaque)
-{
-    int i;
-    PIIX3State *piix3 = opaque;
-
-    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
-        piix3->pci_irq_levels_vmstate[i] =
-            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
-    }
-
-    return 0;
-}
-
-static bool piix3_rcr_needed(void *opaque)
-{
-    PIIX3State *piix3 = opaque;
-
-    return (piix3->rcr != 0);
-}
-
-static const VMStateDescription vmstate_piix3_rcr = {
-    .name = "PIIX3/rcr",
-    .version_id = 1,
-    .minimum_version_id = 1,
-    .needed = piix3_rcr_needed,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT8(rcr, PIIX3State),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-static const VMStateDescription vmstate_piix3 = {
-    .name = "PIIX3",
-    .version_id = 3,
-    .minimum_version_id = 2,
-    .post_load = piix3_post_load,
-    .pre_save = piix3_pre_save,
-    .fields = (VMStateField[]) {
-        VMSTATE_PCI_DEVICE(dev, PIIX3State),
-        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
-                              PIIX_NUM_PIRQS, 3),
-        VMSTATE_END_OF_LIST()
-    },
-    .subsections = (const VMStateDescription*[]) {
-        &vmstate_piix3_rcr,
-        NULL
-    }
-};
-
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    if (val & 4) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-        return;
-    }
-    d->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
-{
-    PIIX3State *d = opaque;
-
-    return d->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
-    .read = rcr_read,
-    .write = rcr_write,
-    .endianness = DEVICE_LITTLE_ENDIAN
-};
-
-static void piix3_realize(PCIDevice *dev, Error **errp)
-{
-    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
-
-    if (!isa_bus_new(DEVICE(d), get_system_memory(),
-                     pci_address_space_io(dev), errp)) {
-        return;
-    }
-
-    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
-                          "piix3-reset-control", 1);
-    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
-                                        &d->rcr_mem, 1);
-
-    qemu_register_reset(piix3_reset, d);
-}
-
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    dc->desc        = "ISA bridge";
-    dc->vmsd        = &vmstate_piix3;
-    dc->hotpluggable   = false;
-    k->realize      = piix3_realize;
-    k->vendor_id    = PCI_VENDOR_ID_INTEL;
-    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
-    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
-    k->class_id     = PCI_CLASS_BRIDGE_ISA;
-    /*
-     * Reason: part of PIIX3 southbridge, needs to be wired up by
-     * pc_piix.c's pc_init1()
-     */
-    dc->user_creatable = false;
-}
-
-static const TypeInfo piix3_pci_type_info = {
-    .name = TYPE_PIIX3_PCI_DEVICE,
-    .parent = TYPE_PCI_DEVICE,
-    .instance_size = sizeof(PIIX3State),
-    .abstract = true,
-    .class_init = pci_piix3_class_init,
-    .interfaces = (InterfaceInfo[]) {
-        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
-        { },
-    },
-};
-
-static void piix3_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config;
-}
-
-static const TypeInfo piix3_info = {
-    .name          = TYPE_PIIX3_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_class_init,
-};
-
-static void piix3_xen_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->config_write = piix3_write_config_xen;
-};
-
-static const TypeInfo piix3_xen_info = {
-    .name          = TYPE_PIIX3_XEN_DEVICE,
-    .parent        = TYPE_PIIX3_PCI_DEVICE,
-    .class_init    = piix3_xen_class_init,
-};
-
 static void i440fx_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -922,9 +523,6 @@ static void i440fx_register_types(void)
 {
     type_register_static(&i440fx_info);
     type_register_static(&igd_passthrough_i440fx_info);
-    type_register_static(&piix3_pci_type_info);
-    type_register_static(&piix3_info);
-    type_register_static(&piix3_xen_info);
     type_register_static(&i440fx_pcihost_info);
 }
 
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 9c92c37a4d..324a3a99fc 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -12,6 +12,8 @@
 #ifndef HW_SOUTHBRIDGE_PIIX_H
 #define HW_SOUTHBRIDGE_PIIX_H
 
+#include "hw/pci/pci.h"
+
 #define TYPE_PIIX4_PM "PIIX4_PM"
 
 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  */
 #define RCR_IOPORT 0xcf9
 
+#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
+#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+    PCIDevice dev;
+
+    /*
+     * bitmap to track pic levels.
+     * The pic level is the logical OR of all the PCI irqs mapped to it
+     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+     *
+     * PIRQ is mapped to PIC pins, we track it by
+     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+     * pic_irq * PIIX_NUM_PIRQS + pirq
+     */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+    uint64_t pic_levels;
+
+    qemu_irq *pic;
+
+    /* This member isn't used. Just for save/load compatibility */
+    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+    /* Reset Control Register contents */
+    uint8_t rcr;
+
+    /* IO memory region for Reset Control Register (RCR_IOPORT) */
+    MemoryRegion rcr_mem;
+} PIIX3State;
+
 extern PCIDevice *piix4_dev;
 
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
                           I2CBus **smbus, size_t ide_buses);
 
-- 
2.21.0


_______________________________________________
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Xen-devel@lists.xenproject.org
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[PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                      | 2 +-
 hw/i386/Kconfig                  | 2 +-
 hw/pci-host/Kconfig              | 2 +-
 hw/pci-host/Makefile.objs        | 2 +-
 hw/pci-host/{piix.c => i440fx.c} | 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename hw/pci-host/{piix.c => i440fx.c} (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4845f47d93..1bc9959b8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
 S: Supported
 F: include/hw/i386/
 F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 589d75e26a..cfe94aede7 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -60,7 +60,7 @@ config I440FX
     select PC_PCI
     select PC_ACPI
     select ACPI_SMBUS
-    select PCI_PIIX
+    select PCI_I440FX
     select PIIX3
     select IDE_PIIX
     select DIMM
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 397043b289..b0aa8351c4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -28,7 +28,7 @@ config PCI_SABRE
     select PCI
     bool
 
-config PCI_PIIX
+config PCI_I440FX
     bool
     select PCI
     select PAM
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e022d..efd752b766 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
 
 common-obj-$(CONFIG_PCI_SABRE) += sabre.o
 common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
 common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
 common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
 common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c
-- 
2.21.0

[PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                      | 2 +-
 hw/i386/Kconfig                  | 2 +-
 hw/pci-host/Kconfig              | 2 +-
 hw/pci-host/Makefile.objs        | 2 +-
 hw/pci-host/{piix.c => i440fx.c} | 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename hw/pci-host/{piix.c => i440fx.c} (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4845f47d93..1bc9959b8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
 S: Supported
 F: include/hw/i386/
 F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 589d75e26a..cfe94aede7 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -60,7 +60,7 @@ config I440FX
     select PC_PCI
     select PC_ACPI
     select ACPI_SMBUS
-    select PCI_PIIX
+    select PCI_I440FX
     select PIIX3
     select IDE_PIIX
     select DIMM
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 397043b289..b0aa8351c4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -28,7 +28,7 @@ config PCI_SABRE
     select PCI
     bool
 
-config PCI_PIIX
+config PCI_I440FX
     bool
     select PCI
     select PAM
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e022d..efd752b766 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
 
 common-obj-$(CONFIG_PCI_SABRE) += sabre.o
 common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
 common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
 common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
 common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c
-- 
2.21.0

[Xen-devel] [PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 MAINTAINERS                      | 2 +-
 hw/i386/Kconfig                  | 2 +-
 hw/pci-host/Kconfig              | 2 +-
 hw/pci-host/Makefile.objs        | 2 +-
 hw/pci-host/{piix.c => i440fx.c} | 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename hw/pci-host/{piix.c => i440fx.c} (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4845f47d93..1bc9959b8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
 S: Supported
 F: include/hw/i386/
 F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 589d75e26a..cfe94aede7 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -60,7 +60,7 @@ config I440FX
     select PC_PCI
     select PC_ACPI
     select ACPI_SMBUS
-    select PCI_PIIX
+    select PCI_I440FX
     select PIIX3
     select IDE_PIIX
     select DIMM
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 397043b289..b0aa8351c4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -28,7 +28,7 @@ config PCI_SABRE
     select PCI
     bool
 
-config PCI_PIIX
+config PCI_I440FX
     bool
     select PCI
     select PAM
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e022d..efd752b766 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
 
 common-obj-$(CONFIG_PCI_SABRE) += sabre.o
 common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
 common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
 common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
 common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c
-- 
2.21.0


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[PATCH 32/32] hw/pci-host/i440fx: Remove the last PIIX3 traces

[Philippe Mathieu-Daudé]

The PIIX3 is not tied to the i440FX and can even be used without it.
Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX
northbridge.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c            | 8 +++++++-
 hw/pci-host/i440fx.c         | 8 --------
 include/hw/pci-host/i440fx.h | 3 +--
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 8ac4bf12ca..cb4f4fc94c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -190,14 +190,20 @@ static void pc_init1(MachineState *machine,
     gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
+        PIIX3State *piix3;
+
         pci_bus = i440fx_init(host_type,
                               pci_type,
-                              &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+                              &i440fx_state,
                               system_memory, system_io, machine->ram_size,
                               pcms->below_4g_mem_size,
                               pcms->above_4g_mem_size,
                               pci_memory, ram_memory);
         pcms->bus = pci_bus;
+
+        piix3 = piix3_create(pci_bus, &isa_bus);
+        piix3->pic = pcms->gsi;
+        piix3_devfn = piix3->dev.devfn;
     } else {
         pci_bus = NULL;
         i440fx_state = NULL;
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 79ecd58a2b..f27131102d 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -27,7 +27,6 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
-                    int *piix3_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
     PCIBus *b;
     PCIDevice *d;
     PCIHostState *s;
-    PIIX3State *piix3;
     PCII440FXState *f;
     unsigned i;
     I440FXState *i440fx;
@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    piix3 = piix3_create(b, isa_bus);
-    piix3->pic = pic;
-    *piix3_devfn = piix3->dev.devfn;
-
     ram_size = ram_size / 8 / 1024 / 1024;
     if (ram_size > 255) {
         ram_size = 255;
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index e327f9bf87..f54e6466e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
+                    PCII440FXState **pi440fx_state,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
-- 
2.21.0

[PATCH 32/32] hw/pci-host/i440fx: Remove the last PIIX3 traces

[Philippe Mathieu-Daudé]

The PIIX3 is not tied to the i440FX and can even be used without it.
Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX
northbridge.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c            | 8 +++++++-
 hw/pci-host/i440fx.c         | 8 --------
 include/hw/pci-host/i440fx.h | 3 +--
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 8ac4bf12ca..cb4f4fc94c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -190,14 +190,20 @@ static void pc_init1(MachineState *machine,
     gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
+        PIIX3State *piix3;
+
         pci_bus = i440fx_init(host_type,
                               pci_type,
-                              &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+                              &i440fx_state,
                               system_memory, system_io, machine->ram_size,
                               pcms->below_4g_mem_size,
                               pcms->above_4g_mem_size,
                               pci_memory, ram_memory);
         pcms->bus = pci_bus;
+
+        piix3 = piix3_create(pci_bus, &isa_bus);
+        piix3->pic = pcms->gsi;
+        piix3_devfn = piix3->dev.devfn;
     } else {
         pci_bus = NULL;
         i440fx_state = NULL;
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 79ecd58a2b..f27131102d 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -27,7 +27,6 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
-                    int *piix3_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
     PCIBus *b;
     PCIDevice *d;
     PCIHostState *s;
-    PIIX3State *piix3;
     PCII440FXState *f;
     unsigned i;
     I440FXState *i440fx;
@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    piix3 = piix3_create(b, isa_bus);
-    piix3->pic = pic;
-    *piix3_devfn = piix3->dev.devfn;
-
     ram_size = ram_size / 8 / 1024 / 1024;
     if (ram_size > 255) {
         ram_size = 255;
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index e327f9bf87..f54e6466e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
+                    PCII440FXState **pi440fx_state,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
-- 
2.21.0

[Xen-devel] [PATCH 32/32] hw/pci-host/i440fx: Remove the last PIIX3 traces

[Philippe Mathieu-Daudé]

The PIIX3 is not tied to the i440FX and can even be used without it.
Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX
northbridge.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/i386/pc_piix.c            | 8 +++++++-
 hw/pci-host/i440fx.c         | 8 --------
 include/hw/pci-host/i440fx.h | 3 +--
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 8ac4bf12ca..cb4f4fc94c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -190,14 +190,20 @@ static void pc_init1(MachineState *machine,
     gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
+        PIIX3State *piix3;
+
         pci_bus = i440fx_init(host_type,
                               pci_type,
-                              &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+                              &i440fx_state,
                               system_memory, system_io, machine->ram_size,
                               pcms->below_4g_mem_size,
                               pcms->above_4g_mem_size,
                               pci_memory, ram_memory);
         pcms->bus = pci_bus;
+
+        piix3 = piix3_create(pci_bus, &isa_bus);
+        piix3->pic = pcms->gsi;
+        piix3_devfn = piix3->dev.devfn;
     } else {
         pci_bus = NULL;
         i440fx_state = NULL;
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 79ecd58a2b..f27131102d 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -27,7 +27,6 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"
@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
-                    int *piix3_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
     PCIBus *b;
     PCIDevice *d;
     PCIHostState *s;
-    PIIX3State *piix3;
     PCII440FXState *f;
     unsigned i;
     I440FXState *i440fx;
@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    piix3 = piix3_create(b, isa_bus);
-    piix3->pic = pic;
-    *piix3_devfn = piix3->dev.devfn;
-
     ram_size = ram_size / 8 / 1024 / 1024;
     if (ram_size > 255) {
         ram_size = 255;
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index e327f9bf87..f54e6466e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
+                    PCII440FXState **pi440fx_state,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,
-- 
2.21.0


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Re: [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

I forgot to Cc David and Daniel for this one.

On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> These devices implemented their load_state_old() handler 10 years
> ago, previous to QEMU v0.12.
> Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> we can drop this code.
> 
> Note: the mips_r4k machine started to use the i8254 device just
> after QEMU v0.5.0, but the MIPS machine types are not versioned,
> so there is no migration compatibility issue removing this handler.
> 
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>   hw/acpi/piix4.c         | 40 ---------------------------------
>   hw/intc/apic_common.c   | 49 -----------------------------------------
>   hw/pci-host/piix.c      | 25 ---------------------
>   hw/timer/i8254_common.c | 40 ---------------------------------
>   4 files changed, 154 deletions(-)
> 
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 5742c3df87..1d29d438c7 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -42,7 +42,6 @@
>   #include "hw/acpi/memory_hotplug.h"
>   #include "hw/acpi/acpi_dev_interface.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/core/cpu.h"
>   #include "trace.h"
> @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
>       }
>   };
>   
> -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PIIX4PMState *s = opaque;
> -    int ret, i;
> -    uint16_t temp;
> -
> -    ret = pci_device_load(PCI_DEVICE(s), f);
> -    if (ret < 0) {
> -        return ret;
> -    }
> -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> -
> -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> -    if (ret) {
> -        return ret;
> -    }
> -
> -    timer_get(f, s->ar.tmr.timer);
> -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    ret = vmstate_load_state(f, &vmstate_pci_status,
> -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> -    return ret;
> -}
> -
>   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
>   {
>       PIIX4PMState *s = opaque;
> @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
>       .name = "piix4_pm",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = acpi_load_old,
>       .post_load = vmstate_acpi_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index aafd8e0e33..375cb6abe9 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -31,7 +31,6 @@
>   #include "sysemu/kvm.h"
>   #include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   static int apic_irq_delivered;
> @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
>       apic_init_reset(dev);
>   }
>   
> -/* This function is only used for old state version 1 and 2 */
> -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    APICCommonState *s = opaque;
> -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> -    int i;
> -
> -    if (version_id > 2) {
> -        return -EINVAL;
> -    }
> -
> -    /* XXX: what if the base changes? (registered memory regions) */
> -    qemu_get_be32s(f, &s->apicbase);
> -    qemu_get_8s(f, &s->id);
> -    qemu_get_8s(f, &s->arb_id);
> -    qemu_get_8s(f, &s->tpr);
> -    qemu_get_be32s(f, &s->spurious_vec);
> -    qemu_get_8s(f, &s->log_dest);
> -    qemu_get_8s(f, &s->dest_mode);
> -    for (i = 0; i < 8; i++) {
> -        qemu_get_be32s(f, &s->isr[i]);
> -        qemu_get_be32s(f, &s->tmr[i]);
> -        qemu_get_be32s(f, &s->irr[i]);
> -    }
> -    for (i = 0; i < APIC_LVT_NB; i++) {
> -        qemu_get_be32s(f, &s->lvt[i]);
> -    }
> -    qemu_get_be32s(f, &s->esr);
> -    qemu_get_be32s(f, &s->icr[0]);
> -    qemu_get_be32s(f, &s->icr[1]);
> -    qemu_get_be32s(f, &s->divide_conf);
> -    s->count_shift = qemu_get_be32(f);
> -    qemu_get_be32s(f, &s->initial_count);
> -    s->initial_count_load_time = qemu_get_be64(f);
> -    s->next_time = qemu_get_be64(f);
> -
> -    if (version_id >= 2) {
> -        s->timer_expiry = qemu_get_be64(f);
> -    }
> -
> -    if (info->post_load) {
> -        info->post_load(s);
> -    }
> -    return 0;
> -}
> -
>   static const VMStateDescription vmstate_apic_common;
>   
>   static void apic_common_realize(DeviceState *dev, Error **errp)
> @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
>       .name = "apic",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = apic_load_old,
>       .pre_load = apic_pre_load,
>       .pre_save = apic_dispatch_pre_save,
>       .post_load = apic_dispatch_post_load,
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 135c645535..2f4cbcbfe9 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -33,7 +33,6 @@
>   #include "qapi/error.h"
>   #include "qemu/range.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/pci-host/pam.h"
>   #include "sysemu/reset.h"
> @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
>       }
>   }
>   
> -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> -{
> -    PCII440FXState *d = opaque;
> -    PCIDevice *pd = PCI_DEVICE(d);
> -    int ret, i;
> -    uint8_t smm_enabled;
> -
> -    ret = pci_device_load(pd, f);
> -    if (ret < 0)
> -        return ret;
> -    i440fx_update_memory_mappings(d);
> -    qemu_get_8s(f, &smm_enabled);
> -
> -    if (version_id == 2) {
> -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> -            qemu_get_be32(f); /* dummy load for compatibility */
> -        }
> -    }
> -
> -    return 0;
> -}
> -
>   static int i440fx_post_load(void *opaque, int version_id)
>   {
>       PCII440FXState *d = opaque;
> @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
>       .name = "I440FX",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = i440fx_load_old,
>       .post_load = i440fx_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> index 57bf10cc94..050875b497 100644
> --- a/hw/timer/i8254_common.c
> +++ b/hw/timer/i8254_common.c
> @@ -29,7 +29,6 @@
>   #include "qemu/timer.h"
>   #include "hw/timer/i8254.h"
>   #include "hw/timer/i8254_internal.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   /* val must be 0 or 1 */
> @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
>       }
>   };
>   
> -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PITCommonState *pit = opaque;
> -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> -    PITChannelState *s;
> -    int i;
> -
> -    if (version_id != 1) {
> -        return -EINVAL;
> -    }
> -
> -    for (i = 0; i < 3; i++) {
> -        s = &pit->channels[i];
> -        s->count = qemu_get_be32(f);
> -        qemu_get_be16s(f, &s->latched_count);
> -        qemu_get_8s(f, &s->count_latched);
> -        qemu_get_8s(f, &s->status_latched);
> -        qemu_get_8s(f, &s->status);
> -        qemu_get_8s(f, &s->read_state);
> -        qemu_get_8s(f, &s->write_state);
> -        qemu_get_8s(f, &s->write_latch);
> -        qemu_get_8s(f, &s->rw_mode);
> -        qemu_get_8s(f, &s->mode);
> -        qemu_get_8s(f, &s->bcd);
> -        qemu_get_8s(f, &s->gate);
> -        s->count_load_time = qemu_get_be64(f);
> -        s->irq_disabled = 0;
> -        if (i == 0) {
> -            s->next_transition_time = qemu_get_be64(f);
> -        }
> -    }
> -    if (c->post_load) {
> -        c->post_load(pit);
> -    }
> -    return 0;
> -}
> -
>   static int pit_dispatch_pre_save(void *opaque)
>   {
>       PITCommonState *s = opaque;
> @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
>       .name = "i8254",
>       .version_id = 3,
>       .minimum_version_id = 2,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = pit_load_old,
>       .pre_save = pit_dispatch_pre_save,
>       .post_load = pit_dispatch_post_load,
>       .fields = (VMStateField[]) {
> 

Re: [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

I forgot to Cc David and Daniel for this one.

On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> These devices implemented their load_state_old() handler 10 years
> ago, previous to QEMU v0.12.
> Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> we can drop this code.
> 
> Note: the mips_r4k machine started to use the i8254 device just
> after QEMU v0.5.0, but the MIPS machine types are not versioned,
> so there is no migration compatibility issue removing this handler.
> 
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>   hw/acpi/piix4.c         | 40 ---------------------------------
>   hw/intc/apic_common.c   | 49 -----------------------------------------
>   hw/pci-host/piix.c      | 25 ---------------------
>   hw/timer/i8254_common.c | 40 ---------------------------------
>   4 files changed, 154 deletions(-)
> 
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 5742c3df87..1d29d438c7 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -42,7 +42,6 @@
>   #include "hw/acpi/memory_hotplug.h"
>   #include "hw/acpi/acpi_dev_interface.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/core/cpu.h"
>   #include "trace.h"
> @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
>       }
>   };
>   
> -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PIIX4PMState *s = opaque;
> -    int ret, i;
> -    uint16_t temp;
> -
> -    ret = pci_device_load(PCI_DEVICE(s), f);
> -    if (ret < 0) {
> -        return ret;
> -    }
> -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> -
> -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> -    if (ret) {
> -        return ret;
> -    }
> -
> -    timer_get(f, s->ar.tmr.timer);
> -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    ret = vmstate_load_state(f, &vmstate_pci_status,
> -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> -    return ret;
> -}
> -
>   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
>   {
>       PIIX4PMState *s = opaque;
> @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
>       .name = "piix4_pm",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = acpi_load_old,
>       .post_load = vmstate_acpi_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index aafd8e0e33..375cb6abe9 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -31,7 +31,6 @@
>   #include "sysemu/kvm.h"
>   #include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   static int apic_irq_delivered;
> @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
>       apic_init_reset(dev);
>   }
>   
> -/* This function is only used for old state version 1 and 2 */
> -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    APICCommonState *s = opaque;
> -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> -    int i;
> -
> -    if (version_id > 2) {
> -        return -EINVAL;
> -    }
> -
> -    /* XXX: what if the base changes? (registered memory regions) */
> -    qemu_get_be32s(f, &s->apicbase);
> -    qemu_get_8s(f, &s->id);
> -    qemu_get_8s(f, &s->arb_id);
> -    qemu_get_8s(f, &s->tpr);
> -    qemu_get_be32s(f, &s->spurious_vec);
> -    qemu_get_8s(f, &s->log_dest);
> -    qemu_get_8s(f, &s->dest_mode);
> -    for (i = 0; i < 8; i++) {
> -        qemu_get_be32s(f, &s->isr[i]);
> -        qemu_get_be32s(f, &s->tmr[i]);
> -        qemu_get_be32s(f, &s->irr[i]);
> -    }
> -    for (i = 0; i < APIC_LVT_NB; i++) {
> -        qemu_get_be32s(f, &s->lvt[i]);
> -    }
> -    qemu_get_be32s(f, &s->esr);
> -    qemu_get_be32s(f, &s->icr[0]);
> -    qemu_get_be32s(f, &s->icr[1]);
> -    qemu_get_be32s(f, &s->divide_conf);
> -    s->count_shift = qemu_get_be32(f);
> -    qemu_get_be32s(f, &s->initial_count);
> -    s->initial_count_load_time = qemu_get_be64(f);
> -    s->next_time = qemu_get_be64(f);
> -
> -    if (version_id >= 2) {
> -        s->timer_expiry = qemu_get_be64(f);
> -    }
> -
> -    if (info->post_load) {
> -        info->post_load(s);
> -    }
> -    return 0;
> -}
> -
>   static const VMStateDescription vmstate_apic_common;
>   
>   static void apic_common_realize(DeviceState *dev, Error **errp)
> @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
>       .name = "apic",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = apic_load_old,
>       .pre_load = apic_pre_load,
>       .pre_save = apic_dispatch_pre_save,
>       .post_load = apic_dispatch_post_load,
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 135c645535..2f4cbcbfe9 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -33,7 +33,6 @@
>   #include "qapi/error.h"
>   #include "qemu/range.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/pci-host/pam.h"
>   #include "sysemu/reset.h"
> @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
>       }
>   }
>   
> -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> -{
> -    PCII440FXState *d = opaque;
> -    PCIDevice *pd = PCI_DEVICE(d);
> -    int ret, i;
> -    uint8_t smm_enabled;
> -
> -    ret = pci_device_load(pd, f);
> -    if (ret < 0)
> -        return ret;
> -    i440fx_update_memory_mappings(d);
> -    qemu_get_8s(f, &smm_enabled);
> -
> -    if (version_id == 2) {
> -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> -            qemu_get_be32(f); /* dummy load for compatibility */
> -        }
> -    }
> -
> -    return 0;
> -}
> -
>   static int i440fx_post_load(void *opaque, int version_id)
>   {
>       PCII440FXState *d = opaque;
> @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
>       .name = "I440FX",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = i440fx_load_old,
>       .post_load = i440fx_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> index 57bf10cc94..050875b497 100644
> --- a/hw/timer/i8254_common.c
> +++ b/hw/timer/i8254_common.c
> @@ -29,7 +29,6 @@
>   #include "qemu/timer.h"
>   #include "hw/timer/i8254.h"
>   #include "hw/timer/i8254_internal.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   /* val must be 0 or 1 */
> @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
>       }
>   };
>   
> -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PITCommonState *pit = opaque;
> -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> -    PITChannelState *s;
> -    int i;
> -
> -    if (version_id != 1) {
> -        return -EINVAL;
> -    }
> -
> -    for (i = 0; i < 3; i++) {
> -        s = &pit->channels[i];
> -        s->count = qemu_get_be32(f);
> -        qemu_get_be16s(f, &s->latched_count);
> -        qemu_get_8s(f, &s->count_latched);
> -        qemu_get_8s(f, &s->status_latched);
> -        qemu_get_8s(f, &s->status);
> -        qemu_get_8s(f, &s->read_state);
> -        qemu_get_8s(f, &s->write_state);
> -        qemu_get_8s(f, &s->write_latch);
> -        qemu_get_8s(f, &s->rw_mode);
> -        qemu_get_8s(f, &s->mode);
> -        qemu_get_8s(f, &s->bcd);
> -        qemu_get_8s(f, &s->gate);
> -        s->count_load_time = qemu_get_be64(f);
> -        s->irq_disabled = 0;
> -        if (i == 0) {
> -            s->next_transition_time = qemu_get_be64(f);
> -        }
> -    }
> -    if (c->post_load) {
> -        c->post_load(pit);
> -    }
> -    return 0;
> -}
> -
>   static int pit_dispatch_pre_save(void *opaque)
>   {
>       PITCommonState *s = opaque;
> @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
>       .name = "i8254",
>       .version_id = 3,
>       .minimum_version_id = 2,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = pit_load_old,
>       .pre_save = pit_dispatch_pre_save,
>       .post_load = pit_dispatch_post_load,
>       .fields = (VMStateField[]) {
> 

Re: [Xen-devel] [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Philippe Mathieu-Daudé]

I forgot to Cc David and Daniel for this one.

On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> These devices implemented their load_state_old() handler 10 years
> ago, previous to QEMU v0.12.
> Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> we can drop this code.
> 
> Note: the mips_r4k machine started to use the i8254 device just
> after QEMU v0.5.0, but the MIPS machine types are not versioned,
> so there is no migration compatibility issue removing this handler.
> 
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>   hw/acpi/piix4.c         | 40 ---------------------------------
>   hw/intc/apic_common.c   | 49 -----------------------------------------
>   hw/pci-host/piix.c      | 25 ---------------------
>   hw/timer/i8254_common.c | 40 ---------------------------------
>   4 files changed, 154 deletions(-)
> 
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 5742c3df87..1d29d438c7 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -42,7 +42,6 @@
>   #include "hw/acpi/memory_hotplug.h"
>   #include "hw/acpi/acpi_dev_interface.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/core/cpu.h"
>   #include "trace.h"
> @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
>       }
>   };
>   
> -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PIIX4PMState *s = opaque;
> -    int ret, i;
> -    uint16_t temp;
> -
> -    ret = pci_device_load(PCI_DEVICE(s), f);
> -    if (ret < 0) {
> -        return ret;
> -    }
> -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> -
> -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> -    if (ret) {
> -        return ret;
> -    }
> -
> -    timer_get(f, s->ar.tmr.timer);
> -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    ret = vmstate_load_state(f, &vmstate_pci_status,
> -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> -    return ret;
> -}
> -
>   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
>   {
>       PIIX4PMState *s = opaque;
> @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
>       .name = "piix4_pm",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = acpi_load_old,
>       .post_load = vmstate_acpi_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index aafd8e0e33..375cb6abe9 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -31,7 +31,6 @@
>   #include "sysemu/kvm.h"
>   #include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   static int apic_irq_delivered;
> @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
>       apic_init_reset(dev);
>   }
>   
> -/* This function is only used for old state version 1 and 2 */
> -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    APICCommonState *s = opaque;
> -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> -    int i;
> -
> -    if (version_id > 2) {
> -        return -EINVAL;
> -    }
> -
> -    /* XXX: what if the base changes? (registered memory regions) */
> -    qemu_get_be32s(f, &s->apicbase);
> -    qemu_get_8s(f, &s->id);
> -    qemu_get_8s(f, &s->arb_id);
> -    qemu_get_8s(f, &s->tpr);
> -    qemu_get_be32s(f, &s->spurious_vec);
> -    qemu_get_8s(f, &s->log_dest);
> -    qemu_get_8s(f, &s->dest_mode);
> -    for (i = 0; i < 8; i++) {
> -        qemu_get_be32s(f, &s->isr[i]);
> -        qemu_get_be32s(f, &s->tmr[i]);
> -        qemu_get_be32s(f, &s->irr[i]);
> -    }
> -    for (i = 0; i < APIC_LVT_NB; i++) {
> -        qemu_get_be32s(f, &s->lvt[i]);
> -    }
> -    qemu_get_be32s(f, &s->esr);
> -    qemu_get_be32s(f, &s->icr[0]);
> -    qemu_get_be32s(f, &s->icr[1]);
> -    qemu_get_be32s(f, &s->divide_conf);
> -    s->count_shift = qemu_get_be32(f);
> -    qemu_get_be32s(f, &s->initial_count);
> -    s->initial_count_load_time = qemu_get_be64(f);
> -    s->next_time = qemu_get_be64(f);
> -
> -    if (version_id >= 2) {
> -        s->timer_expiry = qemu_get_be64(f);
> -    }
> -
> -    if (info->post_load) {
> -        info->post_load(s);
> -    }
> -    return 0;
> -}
> -
>   static const VMStateDescription vmstate_apic_common;
>   
>   static void apic_common_realize(DeviceState *dev, Error **errp)
> @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
>       .name = "apic",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = apic_load_old,
>       .pre_load = apic_pre_load,
>       .pre_save = apic_dispatch_pre_save,
>       .post_load = apic_dispatch_post_load,
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 135c645535..2f4cbcbfe9 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -33,7 +33,6 @@
>   #include "qapi/error.h"
>   #include "qemu/range.h"
>   #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   #include "hw/pci-host/pam.h"
>   #include "sysemu/reset.h"
> @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
>       }
>   }
>   
> -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> -{
> -    PCII440FXState *d = opaque;
> -    PCIDevice *pd = PCI_DEVICE(d);
> -    int ret, i;
> -    uint8_t smm_enabled;
> -
> -    ret = pci_device_load(pd, f);
> -    if (ret < 0)
> -        return ret;
> -    i440fx_update_memory_mappings(d);
> -    qemu_get_8s(f, &smm_enabled);
> -
> -    if (version_id == 2) {
> -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> -            qemu_get_be32(f); /* dummy load for compatibility */
> -        }
> -    }
> -
> -    return 0;
> -}
> -
>   static int i440fx_post_load(void *opaque, int version_id)
>   {
>       PCII440FXState *d = opaque;
> @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
>       .name = "I440FX",
>       .version_id = 3,
>       .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = i440fx_load_old,
>       .post_load = i440fx_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> index 57bf10cc94..050875b497 100644
> --- a/hw/timer/i8254_common.c
> +++ b/hw/timer/i8254_common.c
> @@ -29,7 +29,6 @@
>   #include "qemu/timer.h"
>   #include "hw/timer/i8254.h"
>   #include "hw/timer/i8254_internal.h"
> -#include "migration/qemu-file-types.h"
>   #include "migration/vmstate.h"
>   
>   /* val must be 0 or 1 */
> @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
>       }
>   };
>   
> -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PITCommonState *pit = opaque;
> -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> -    PITChannelState *s;
> -    int i;
> -
> -    if (version_id != 1) {
> -        return -EINVAL;
> -    }
> -
> -    for (i = 0; i < 3; i++) {
> -        s = &pit->channels[i];
> -        s->count = qemu_get_be32(f);
> -        qemu_get_be16s(f, &s->latched_count);
> -        qemu_get_8s(f, &s->count_latched);
> -        qemu_get_8s(f, &s->status_latched);
> -        qemu_get_8s(f, &s->status);
> -        qemu_get_8s(f, &s->read_state);
> -        qemu_get_8s(f, &s->write_state);
> -        qemu_get_8s(f, &s->write_latch);
> -        qemu_get_8s(f, &s->rw_mode);
> -        qemu_get_8s(f, &s->mode);
> -        qemu_get_8s(f, &s->bcd);
> -        qemu_get_8s(f, &s->gate);
> -        s->count_load_time = qemu_get_be64(f);
> -        s->irq_disabled = 0;
> -        if (i == 0) {
> -            s->next_transition_time = qemu_get_be64(f);
> -        }
> -    }
> -    if (c->post_load) {
> -        c->post_load(pit);
> -    }
> -    return 0;
> -}
> -
>   static int pit_dispatch_pre_save(void *opaque)
>   {
>       PITCommonState *s = opaque;
> @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
>       .name = "i8254",
>       .version_id = 3,
>       .minimum_version_id = 2,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = pit_load_old,
>       .pre_save = pit_dispatch_pre_save,
>       .post_load = pit_dispatch_post_load,
>       .fields = (VMStateField[]) {
> 

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Re: [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[no-reply]

Patchew URL: https://patchew.org/QEMU/20191015162705.28087-1-philmd@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
Type: series
Message-id: 20191015162705.28087-1-philmd@redhat.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e28fc07 hw/pci-host/i440fx: Remove the last PIIX3 traces
4278fc5 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
b5bb11c hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
256b64d hw/pci-host/piix: Fix code style issues
e2e38d8 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
ec3e0e7 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
7da0dc4 hw/pci-host/piix: Move RCR_IOPORT register definition
de2f83b hw/pci-host/piix: Extract piix3_create()
1f33a16 hw/i386/pc: Remove kvm_i386.h include
120bf64 hw/i386/pc: Extract pc_i8259_create()
7f4aed6 hw/i386/pc: Move gsi_state creation code
af0863c hw/i386/pc: Reduce gsi_handler scope
a3f9ad9 hw/i386/pc: Extract pc_gsi_create()
933d1cd hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
223c701 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
3db0574 hw/mips/mips_malta: Create IDE hard drive array dynamically
59225b9 piix4: add a mc146818rtc controller as specified in datasheet
da01d59 piix4: add a i8254 pit controller as specified in datasheet
40518db piix4: add a i8257 dma controller as specified in datasheet
015de71 piix4: convert reset function to QOM
3a68c8f piix4: rename PIIX4 object to piix4-isa
da51c52 Revert "irq: introduce qemu_irq_proxy()"
8cdeacf piix4: add a i8259 interrupt controller as specified in datasheet
ecc92c2 piix4: add Reset Control Register
c2cd556 piix4: rename some variables in realize function
67d9be5 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
0567e9d mc146818rtc: always register rtc to rtc list
3d9897a mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
4c0fde0 mc146818rtc: Move RTC_ISA_IRQ definition
1a8427e mc146818rtc: move structure to header file
0e65956 hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
0201c90 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

=== OUTPUT BEGIN ===
1/32 Checking commit 0201c90e8aaf (hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers)
2/32 Checking commit 0e659563bbd2 (hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h)
3/32 Checking commit 1a8427ecaa92 (mc146818rtc: move structure to header file)
4/32 Checking commit 4c0fde00c150 (mc146818rtc: Move RTC_ISA_IRQ definition)
5/32 Checking commit 3d9897ae2cf0 (mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c)
6/32 Checking commit 0567e9df0795 (mc146818rtc: always register rtc to rtc list)
7/32 Checking commit 67d9be561c0c (MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets)
8/32 Checking commit c2cd5561adf9 (piix4: rename some variables in realize function)
9/32 Checking commit ecc92c2678b0 (piix4: add Reset Control Register)
10/32 Checking commit 8cdeacff34b5 (piix4: add a i8259 interrupt controller as specified in datasheet)
11/32 Checking commit da51c5247d1f (Revert "irq: introduce qemu_irq_proxy()")
12/32 Checking commit 3a68c8f5ff30 (piix4: rename PIIX4 object to piix4-isa)
13/32 Checking commit 015de71b6e75 (piix4: convert reset function to QOM)
14/32 Checking commit 40518dbbdc82 (piix4: add a i8257 dma controller as specified in datasheet)
15/32 Checking commit da01d594d8dd (piix4: add a i8254 pit controller as specified in datasheet)
16/32 Checking commit 59225b98d0d6 (piix4: add a mc146818rtc controller as specified in datasheet)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#192: 
deleted file mode 100644

total: 0 errors, 1 warnings, 166 lines checked

Patch 16/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/32 Checking commit 3db0574cf65a (hw/mips/mips_malta: Create IDE hard drive array dynamically)
18/32 Checking commit 223c701490d0 (hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create())
19/32 Checking commit 933d1cdd6cf9 (hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c)
20/32 Checking commit a3f9ad9887ff (hw/i386/pc: Extract pc_gsi_create())
21/32 Checking commit af0863c35ccb (hw/i386/pc: Reduce gsi_handler scope)
22/32 Checking commit 7f4aed6122ba (hw/i386/pc: Move gsi_state creation code)
23/32 Checking commit 120bf64ae89c (hw/i386/pc: Extract pc_i8259_create())
24/32 Checking commit 1f33a16f966e (hw/i386/pc: Remove kvm_i386.h include)
25/32 Checking commit de2f83ba41e7 (hw/pci-host/piix: Extract piix3_create())
26/32 Checking commit 7da0dc4034e4 (hw/pci-host/piix: Move RCR_IOPORT register definition)
27/32 Checking commit ec3e0e755fa9 (hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers)
28/32 Checking commit e2e38d869ec8 (hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97: 
new file mode 100644

total: 0 errors, 1 warnings, 101 lines checked

Patch 28/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/32 Checking commit 256b64d22f99 (hw/pci-host/piix: Fix code style issues)
30/32 Checking commit b5bb11cb4d85 (hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#64: 
new file mode 100644

ERROR: spaces required around that '*' (ctx:VxV)
#313: FILE: hw/isa/piix3.c:245:
+    .subsections = (const VMStateDescription*[]) {
                                             ^

total: 1 errors, 1 warnings, 937 lines checked

Patch 30/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/32 Checking commit 4278fc5f1a79 (hw/pci-host: Rename incorrectly named 'piix' as 'i440fx')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
rename from hw/pci-host/piix.c

total: 0 errors, 1 warnings, 32 lines checked

Patch 31/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/32 Checking commit e28fc07cc7c1 (hw/pci-host/i440fx: Remove the last PIIX3 traces)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20191015162705.28087-1-philmd@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[no-reply]

Patchew URL: https://patchew.org/QEMU/20191015162705.28087-1-philmd@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
Type: series
Message-id: 20191015162705.28087-1-philmd@redhat.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e28fc07 hw/pci-host/i440fx: Remove the last PIIX3 traces
4278fc5 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
b5bb11c hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
256b64d hw/pci-host/piix: Fix code style issues
e2e38d8 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
ec3e0e7 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
7da0dc4 hw/pci-host/piix: Move RCR_IOPORT register definition
de2f83b hw/pci-host/piix: Extract piix3_create()
1f33a16 hw/i386/pc: Remove kvm_i386.h include
120bf64 hw/i386/pc: Extract pc_i8259_create()
7f4aed6 hw/i386/pc: Move gsi_state creation code
af0863c hw/i386/pc: Reduce gsi_handler scope
a3f9ad9 hw/i386/pc: Extract pc_gsi_create()
933d1cd hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
223c701 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
3db0574 hw/mips/mips_malta: Create IDE hard drive array dynamically
59225b9 piix4: add a mc146818rtc controller as specified in datasheet
da01d59 piix4: add a i8254 pit controller as specified in datasheet
40518db piix4: add a i8257 dma controller as specified in datasheet
015de71 piix4: convert reset function to QOM
3a68c8f piix4: rename PIIX4 object to piix4-isa
da51c52 Revert "irq: introduce qemu_irq_proxy()"
8cdeacf piix4: add a i8259 interrupt controller as specified in datasheet
ecc92c2 piix4: add Reset Control Register
c2cd556 piix4: rename some variables in realize function
67d9be5 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
0567e9d mc146818rtc: always register rtc to rtc list
3d9897a mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
4c0fde0 mc146818rtc: Move RTC_ISA_IRQ definition
1a8427e mc146818rtc: move structure to header file
0e65956 hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
0201c90 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

=== OUTPUT BEGIN ===
1/32 Checking commit 0201c90e8aaf (hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers)
2/32 Checking commit 0e659563bbd2 (hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h)
3/32 Checking commit 1a8427ecaa92 (mc146818rtc: move structure to header file)
4/32 Checking commit 4c0fde00c150 (mc146818rtc: Move RTC_ISA_IRQ definition)
5/32 Checking commit 3d9897ae2cf0 (mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c)
6/32 Checking commit 0567e9df0795 (mc146818rtc: always register rtc to rtc list)
7/32 Checking commit 67d9be561c0c (MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets)
8/32 Checking commit c2cd5561adf9 (piix4: rename some variables in realize function)
9/32 Checking commit ecc92c2678b0 (piix4: add Reset Control Register)
10/32 Checking commit 8cdeacff34b5 (piix4: add a i8259 interrupt controller as specified in datasheet)
11/32 Checking commit da51c5247d1f (Revert "irq: introduce qemu_irq_proxy()")
12/32 Checking commit 3a68c8f5ff30 (piix4: rename PIIX4 object to piix4-isa)
13/32 Checking commit 015de71b6e75 (piix4: convert reset function to QOM)
14/32 Checking commit 40518dbbdc82 (piix4: add a i8257 dma controller as specified in datasheet)
15/32 Checking commit da01d594d8dd (piix4: add a i8254 pit controller as specified in datasheet)
16/32 Checking commit 59225b98d0d6 (piix4: add a mc146818rtc controller as specified in datasheet)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#192: 
deleted file mode 100644

total: 0 errors, 1 warnings, 166 lines checked

Patch 16/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/32 Checking commit 3db0574cf65a (hw/mips/mips_malta: Create IDE hard drive array dynamically)
18/32 Checking commit 223c701490d0 (hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create())
19/32 Checking commit 933d1cdd6cf9 (hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c)
20/32 Checking commit a3f9ad9887ff (hw/i386/pc: Extract pc_gsi_create())
21/32 Checking commit af0863c35ccb (hw/i386/pc: Reduce gsi_handler scope)
22/32 Checking commit 7f4aed6122ba (hw/i386/pc: Move gsi_state creation code)
23/32 Checking commit 120bf64ae89c (hw/i386/pc: Extract pc_i8259_create())
24/32 Checking commit 1f33a16f966e (hw/i386/pc: Remove kvm_i386.h include)
25/32 Checking commit de2f83ba41e7 (hw/pci-host/piix: Extract piix3_create())
26/32 Checking commit 7da0dc4034e4 (hw/pci-host/piix: Move RCR_IOPORT register definition)
27/32 Checking commit ec3e0e755fa9 (hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers)
28/32 Checking commit e2e38d869ec8 (hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97: 
new file mode 100644

total: 0 errors, 1 warnings, 101 lines checked

Patch 28/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/32 Checking commit 256b64d22f99 (hw/pci-host/piix: Fix code style issues)
30/32 Checking commit b5bb11cb4d85 (hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#64: 
new file mode 100644

ERROR: spaces required around that '*' (ctx:VxV)
#313: FILE: hw/isa/piix3.c:245:
+    .subsections = (const VMStateDescription*[]) {
                                             ^

total: 1 errors, 1 warnings, 937 lines checked

Patch 30/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/32 Checking commit 4278fc5f1a79 (hw/pci-host: Rename incorrectly named 'piix' as 'i440fx')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
rename from hw/pci-host/piix.c

total: 0 errors, 1 warnings, 32 lines checked

Patch 31/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/32 Checking commit e28fc07cc7c1 (hw/pci-host/i440fx: Remove the last PIIX3 traces)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20191015162705.28087-1-philmd@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [Xen-devel] [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

[no-reply]

Patchew URL: https://patchew.org/QEMU/20191015162705.28087-1-philmd@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
Type: series
Message-id: 20191015162705.28087-1-philmd@redhat.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e28fc07 hw/pci-host/i440fx: Remove the last PIIX3 traces
4278fc5 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
b5bb11c hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
256b64d hw/pci-host/piix: Fix code style issues
e2e38d8 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
ec3e0e7 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
7da0dc4 hw/pci-host/piix: Move RCR_IOPORT register definition
de2f83b hw/pci-host/piix: Extract piix3_create()
1f33a16 hw/i386/pc: Remove kvm_i386.h include
120bf64 hw/i386/pc: Extract pc_i8259_create()
7f4aed6 hw/i386/pc: Move gsi_state creation code
af0863c hw/i386/pc: Reduce gsi_handler scope
a3f9ad9 hw/i386/pc: Extract pc_gsi_create()
933d1cd hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
223c701 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
3db0574 hw/mips/mips_malta: Create IDE hard drive array dynamically
59225b9 piix4: add a mc146818rtc controller as specified in datasheet
da01d59 piix4: add a i8254 pit controller as specified in datasheet
40518db piix4: add a i8257 dma controller as specified in datasheet
015de71 piix4: convert reset function to QOM
3a68c8f piix4: rename PIIX4 object to piix4-isa
da51c52 Revert "irq: introduce qemu_irq_proxy()"
8cdeacf piix4: add a i8259 interrupt controller as specified in datasheet
ecc92c2 piix4: add Reset Control Register
c2cd556 piix4: rename some variables in realize function
67d9be5 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
0567e9d mc146818rtc: always register rtc to rtc list
3d9897a mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c
4c0fde0 mc146818rtc: Move RTC_ISA_IRQ definition
1a8427e mc146818rtc: move structure to header file
0e65956 hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h
0201c90 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

=== OUTPUT BEGIN ===
1/32 Checking commit 0201c90e8aaf (hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers)
2/32 Checking commit 0e659563bbd2 (hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h)
3/32 Checking commit 1a8427ecaa92 (mc146818rtc: move structure to header file)
4/32 Checking commit 4c0fde00c150 (mc146818rtc: Move RTC_ISA_IRQ definition)
5/32 Checking commit 3d9897ae2cf0 (mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c)
6/32 Checking commit 0567e9df0795 (mc146818rtc: always register rtc to rtc list)
7/32 Checking commit 67d9be561c0c (MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets)
8/32 Checking commit c2cd5561adf9 (piix4: rename some variables in realize function)
9/32 Checking commit ecc92c2678b0 (piix4: add Reset Control Register)
10/32 Checking commit 8cdeacff34b5 (piix4: add a i8259 interrupt controller as specified in datasheet)
11/32 Checking commit da51c5247d1f (Revert "irq: introduce qemu_irq_proxy()")
12/32 Checking commit 3a68c8f5ff30 (piix4: rename PIIX4 object to piix4-isa)
13/32 Checking commit 015de71b6e75 (piix4: convert reset function to QOM)
14/32 Checking commit 40518dbbdc82 (piix4: add a i8257 dma controller as specified in datasheet)
15/32 Checking commit da01d594d8dd (piix4: add a i8254 pit controller as specified in datasheet)
16/32 Checking commit 59225b98d0d6 (piix4: add a mc146818rtc controller as specified in datasheet)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#192: 
deleted file mode 100644

total: 0 errors, 1 warnings, 166 lines checked

Patch 16/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/32 Checking commit 3db0574cf65a (hw/mips/mips_malta: Create IDE hard drive array dynamically)
18/32 Checking commit 223c701490d0 (hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create())
19/32 Checking commit 933d1cdd6cf9 (hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c)
20/32 Checking commit a3f9ad9887ff (hw/i386/pc: Extract pc_gsi_create())
21/32 Checking commit af0863c35ccb (hw/i386/pc: Reduce gsi_handler scope)
22/32 Checking commit 7f4aed6122ba (hw/i386/pc: Move gsi_state creation code)
23/32 Checking commit 120bf64ae89c (hw/i386/pc: Extract pc_i8259_create())
24/32 Checking commit 1f33a16f966e (hw/i386/pc: Remove kvm_i386.h include)
25/32 Checking commit de2f83ba41e7 (hw/pci-host/piix: Extract piix3_create())
26/32 Checking commit 7da0dc4034e4 (hw/pci-host/piix: Move RCR_IOPORT register definition)
27/32 Checking commit ec3e0e755fa9 (hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers)
28/32 Checking commit e2e38d869ec8 (hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97: 
new file mode 100644

total: 0 errors, 1 warnings, 101 lines checked

Patch 28/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/32 Checking commit 256b64d22f99 (hw/pci-host/piix: Fix code style issues)
30/32 Checking commit b5bb11cb4d85 (hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#64: 
new file mode 100644

ERROR: spaces required around that '*' (ctx:VxV)
#313: FILE: hw/isa/piix3.c:245:
+    .subsections = (const VMStateDescription*[]) {
                                             ^

total: 1 errors, 1 warnings, 937 lines checked

Patch 30/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/32 Checking commit 4278fc5f1a79 (hw/pci-host: Rename incorrectly named 'piix' as 'i440fx')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
rename from hw/pci-host/piix.c

total: 0 errors, 1 warnings, 32 lines checked

Patch 31/32 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/32 Checking commit e28fc07cc7c1 (hw/pci-host/i440fx: Remove the last PIIX3 traces)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20191015162705.28087-1-philmd@redhat.com/testing.checkpatch/?type=message.
---
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Re: [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Paul Durrant]

On Tue, 15 Oct 2019 at 17:34, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Xen change...

Acked-by: Paul Durrant <paul@xen.org>

> ---
>  hw/i386/xen/xen-hvm.c         | 5 +++--
>  hw/mips/gt64xxx_pci.c         | 4 ++--
>  hw/pci-host/piix.c            | 9 ++++-----
>  include/hw/southbridge/piix.h | 6 ++++++
>  4 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 6b5e5bb7f5..4ce2fb9c89 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -14,6 +14,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/hw.h"
>  #include "hw/i386/apic-msidef.h"
> @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
>              v = 0;
>          }
>          v &= 0xf;
> -        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> -            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
> +        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
> +            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
>          }
>      }
>  }
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c277398c0d..5cab9c1ee1 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
>
>      /* now we change the pic irq level according to the piix irq mappings */
>      /* XXX: optimize */
> -    pic_irq = piix4_dev->config[0x60 + irq_num];
> +    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
>      if (pic_irq < 16) {
>          /* The pic level is the logical OR of all the PCI irqs mapped to it. */
>          pic_level = 0;
>          for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix4_dev->config[0x60 + i]) {
> +            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
>                  pic_level |= pci_irq_levels[i];
>              }
>          }
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3770575c1a..a450fc726e 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -61,7 +61,6 @@ typedef struct I440FXState {
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
>  #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
>  #define XEN_PIIX_NUM_PIRQS      128ULL
> -#define PIIX_PIRQC              0x60
>
>  typedef struct PIIX3State {
>      PCIDevice dev;
> @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
>      int pic_irq;
>      uint64_t mask;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
>  {
>      int pic_irq;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
>  static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
>  {
>      PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQC + pin];
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
>      PCIINTxRoute route;
>
>      if (irq < PIIX_NUM_PIC_IRQS) {
> @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len)
>  {
>      pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
>          PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
>          int pic_irq;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 79ebe0089b..9c92c37a4d 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/* PIRQRC[A:D]: PIRQx Route Control Registers */
> +#define PIIX_PIRQCA 0x60
> +#define PIIX_PIRQCB 0x61
> +#define PIIX_PIRQCC 0x62
> +#define PIIX_PIRQCD 0x63
> +
>  /*
>   * Reset Control Register: PCI-accessible ISA-Compatible Register at address
>   * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
> --
> 2.21.0
>

Re: [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Paul Durrant]

On Tue, 15 Oct 2019 at 17:34, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Xen change...

Acked-by: Paul Durrant <paul@xen.org>

> ---
>  hw/i386/xen/xen-hvm.c         | 5 +++--
>  hw/mips/gt64xxx_pci.c         | 4 ++--
>  hw/pci-host/piix.c            | 9 ++++-----
>  include/hw/southbridge/piix.h | 6 ++++++
>  4 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 6b5e5bb7f5..4ce2fb9c89 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -14,6 +14,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/hw.h"
>  #include "hw/i386/apic-msidef.h"
> @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
>              v = 0;
>          }
>          v &= 0xf;
> -        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> -            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
> +        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
> +            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
>          }
>      }
>  }
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c277398c0d..5cab9c1ee1 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
>
>      /* now we change the pic irq level according to the piix irq mappings */
>      /* XXX: optimize */
> -    pic_irq = piix4_dev->config[0x60 + irq_num];
> +    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
>      if (pic_irq < 16) {
>          /* The pic level is the logical OR of all the PCI irqs mapped to it. */
>          pic_level = 0;
>          for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix4_dev->config[0x60 + i]) {
> +            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
>                  pic_level |= pci_irq_levels[i];
>              }
>          }
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3770575c1a..a450fc726e 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -61,7 +61,6 @@ typedef struct I440FXState {
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
>  #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
>  #define XEN_PIIX_NUM_PIRQS      128ULL
> -#define PIIX_PIRQC              0x60
>
>  typedef struct PIIX3State {
>      PCIDevice dev;
> @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
>      int pic_irq;
>      uint64_t mask;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
>  {
>      int pic_irq;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
>  static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
>  {
>      PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQC + pin];
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
>      PCIINTxRoute route;
>
>      if (irq < PIIX_NUM_PIC_IRQS) {
> @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len)
>  {
>      pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
>          PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
>          int pic_irq;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 79ebe0089b..9c92c37a4d 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/* PIRQRC[A:D]: PIRQx Route Control Registers */
> +#define PIIX_PIRQCA 0x60
> +#define PIIX_PIRQCB 0x61
> +#define PIIX_PIRQCC 0x62
> +#define PIIX_PIRQCD 0x63
> +
>  /*
>   * Reset Control Register: PCI-accessible ISA-Compatible Register at address
>   * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
> --
> 2.21.0
>

Re: [Xen-devel] [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Paul Durrant]

On Tue, 15 Oct 2019 at 17:34, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Xen change...

Acked-by: Paul Durrant <paul@xen.org>

> ---
>  hw/i386/xen/xen-hvm.c         | 5 +++--
>  hw/mips/gt64xxx_pci.c         | 4 ++--
>  hw/pci-host/piix.c            | 9 ++++-----
>  include/hw/southbridge/piix.h | 6 ++++++
>  4 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 6b5e5bb7f5..4ce2fb9c89 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -14,6 +14,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/hw.h"
>  #include "hw/i386/apic-msidef.h"
> @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
>              v = 0;
>          }
>          v &= 0xf;
> -        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> -            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
> +        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
> +            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
>          }
>      }
>  }
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c277398c0d..5cab9c1ee1 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
>
>      /* now we change the pic irq level according to the piix irq mappings */
>      /* XXX: optimize */
> -    pic_irq = piix4_dev->config[0x60 + irq_num];
> +    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
>      if (pic_irq < 16) {
>          /* The pic level is the logical OR of all the PCI irqs mapped to it. */
>          pic_level = 0;
>          for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix4_dev->config[0x60 + i]) {
> +            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
>                  pic_level |= pci_irq_levels[i];
>              }
>          }
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3770575c1a..a450fc726e 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -61,7 +61,6 @@ typedef struct I440FXState {
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
>  #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
>  #define XEN_PIIX_NUM_PIRQS      128ULL
> -#define PIIX_PIRQC              0x60
>
>  typedef struct PIIX3State {
>      PCIDevice dev;
> @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
>      int pic_irq;
>      uint64_t mask;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
>  {
>      int pic_irq;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
>  static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
>  {
>      PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQC + pin];
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
>      PCIINTxRoute route;
>
>      if (irq < PIIX_NUM_PIC_IRQS) {
> @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len)
>  {
>      pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
>          PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
>          int pic_irq;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 79ebe0089b..9c92c37a4d 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/* PIRQRC[A:D]: PIRQx Route Control Registers */
> +#define PIIX_PIRQCA 0x60
> +#define PIIX_PIRQCB 0x61
> +#define PIIX_PIRQCC 0x62
> +#define PIIX_PIRQCD 0x63
> +
>  /*
>   * Reset Control Register: PCI-accessible ISA-Compatible Register at address
>   * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
> --
> 2.21.0
>

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Re: [PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The PIIX4 Southbridge is not used by the PC machine,
> but by the Malta board (MIPS). Add a new section to
> keep it covered.
>
> Suggested-by: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  MAINTAINERS | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)


Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fe4dc51b08..c9f625fc2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
> -F: hw/isa/piix4.c
>  F: hw/isa/lpc_ich9.c
>  F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
> @@ -1716,6 +1715,12 @@ F: hw/display/edid*
>  F: include/hw/display/edid.h
>  F: qemu-edid.c
>
> +PIIX4 South Bridge (i82371AB)
> +M: Hervé Poussineau <hpoussin@reactos.org>
> +M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +S: Maintained
> +F: hw/isa/piix4.c
> +
>  Firmware configuration (fw_cfg)
>  M: Philippe Mathieu-Daudé <philmd@redhat.com>
>  R: Laszlo Ersek <lersek@redhat.com>
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1328 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The PIIX4 Southbridge is not used by the PC machine,
> but by the Malta board (MIPS). Add a new section to
> keep it covered.
>
> Suggested-by: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  MAINTAINERS | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)


Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fe4dc51b08..c9f625fc2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
> -F: hw/isa/piix4.c
>  F: hw/isa/lpc_ich9.c
>  F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
> @@ -1716,6 +1715,12 @@ F: hw/display/edid*
>  F: include/hw/display/edid.h
>  F: qemu-edid.c
>
> +PIIX4 South Bridge (i82371AB)
> +M: Hervé Poussineau <hpoussin@reactos.org>
> +M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +S: Maintained
> +F: hw/isa/piix4.c
> +
>  Firmware configuration (fw_cfg)
>  M: Philippe Mathieu-Daudé <philmd@redhat.com>
>  R: Laszlo Ersek <lersek@redhat.com>
> --
> 2.21.0
>
>
>

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Re: [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 6792 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 41 ++++++++++++++++++++++++++++++-----------
>  hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>  include/hw/i386/pc.h |  1 -
>  3 files changed, 43 insertions(+), 31 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 6e2d9b9774..1cfc51335a 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "hw/irq.h"
>  #include "hw/i386/pc.h"
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
>  typedef struct PIIX4State {
>      PCIDevice dev;
> +    qemu_irq cpu_intr;
> +    qemu_irq *isa;
>
>      /* Reset Control Register */
>      MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> +    PIIX4State *s = opaque;
> +    qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> +    PIIX4State *s = opaque;
> +    qemu_set_irq(s->isa[irq], level);
> +}
> +
>  static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>                              unsigned int len)
>  {
> @@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>  {
>      DeviceState *dev = DEVICE(pci_dev);
>      PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
> +    ISABus *isa_bus;
> +    qemu_irq *i8259_out_irq;
>
> -    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> -                     pci_address_space_io(pci_dev), errp)) {
> +    isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
> +                          pci_address_space_io(pci_dev), errp);
> +    if (!isa_bus) {
>          return;
>      }
>
> +    qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa",
> ISA_NUM_IRQS);
> +    qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
> +
>      memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
>                            "reset-control", 1);
>      memory_region_add_subregion_overlap(pci_address_space_io(pci_dev),
> 0xcf9,
>                                          &s->rcr_mem, 1);
>
> +    /* initialize i8259 pic */
> +    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> +    s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> +    /* initialize ISA irqs */
> +    isa_bus_irqs(isa_bus, s->isa);
> +
>      piix4_dev = pci_dev;
>      qemu_register_reset(piix4_reset, s);
>  }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> -    PCIDevice *d;
> -
> -    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> -    return d->devfn;
> -}
> -
>  static void piix4_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
>      SysBusDevice parent_obj;
>
>      MIPSCPSState cps;
> -    qemu_irq *i8259;
> +    qemu_irq i8259[16];
>  } MaltaState;
>
>  static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>      int64_t kernel_entry, bootloader_run_addr;
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
> -    qemu_irq *isa_irq;
>      qemu_irq cbus_irq, i8259_irq;
> +    PCIDevice *pci;
>      int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>      /* Board ID = 0x420 (Malta Board with CoreLV) */
>      stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> -    /*
> -     * We have a circular dependency problem: pci_bus depends on isa_irq,
> -     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> -     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
> -     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> -     * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> -     */
> -    isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
>      /* Northbridge */
> -    pci_bus = gt64120_register(isa_irq);
> +    pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
>      ide_drive_get(hd, ARRAY_SIZE(hd));
>
> -    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, "PIIX4");
> +    dev = DEVICE(pci);
> +    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    piix4_devfn = pci->devfn;
>
> -    /*
> -     * Interrupt controller
> -     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> -     */
> -    s->i8259 = i8259_init(isa_bus, i8259_irq);
> +    /* Interrupt controller */
> +    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> +    for (int i = 0; i < ISA_NUM_IRQS; i++) {
> +        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> +    }
>
> -    isa_bus_irqs(isa_bus, s->i8259);
>      pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 09e74e7764..a95eab0d8a 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>  PCIBus *find_i440fx(void);
>  /* piix4.c */
>  extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 6792 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 41 ++++++++++++++++++++++++++++++-----------
>  hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>  include/hw/i386/pc.h |  1 -
>  3 files changed, 43 insertions(+), 31 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 6e2d9b9774..1cfc51335a 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "hw/irq.h"
>  #include "hw/i386/pc.h"
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
>  typedef struct PIIX4State {
>      PCIDevice dev;
> +    qemu_irq cpu_intr;
> +    qemu_irq *isa;
>
>      /* Reset Control Register */
>      MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> +    PIIX4State *s = opaque;
> +    qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> +    PIIX4State *s = opaque;
> +    qemu_set_irq(s->isa[irq], level);
> +}
> +
>  static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>                              unsigned int len)
>  {
> @@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>  {
>      DeviceState *dev = DEVICE(pci_dev);
>      PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
> +    ISABus *isa_bus;
> +    qemu_irq *i8259_out_irq;
>
> -    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> -                     pci_address_space_io(pci_dev), errp)) {
> +    isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
> +                          pci_address_space_io(pci_dev), errp);
> +    if (!isa_bus) {
>          return;
>      }
>
> +    qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa",
> ISA_NUM_IRQS);
> +    qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
> +
>      memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
>                            "reset-control", 1);
>      memory_region_add_subregion_overlap(pci_address_space_io(pci_dev),
> 0xcf9,
>                                          &s->rcr_mem, 1);
>
> +    /* initialize i8259 pic */
> +    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> +    s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> +    /* initialize ISA irqs */
> +    isa_bus_irqs(isa_bus, s->isa);
> +
>      piix4_dev = pci_dev;
>      qemu_register_reset(piix4_reset, s);
>  }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> -    PCIDevice *d;
> -
> -    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> -    return d->devfn;
> -}
> -
>  static void piix4_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
>      SysBusDevice parent_obj;
>
>      MIPSCPSState cps;
> -    qemu_irq *i8259;
> +    qemu_irq i8259[16];
>  } MaltaState;
>
>  static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>      int64_t kernel_entry, bootloader_run_addr;
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
> -    qemu_irq *isa_irq;
>      qemu_irq cbus_irq, i8259_irq;
> +    PCIDevice *pci;
>      int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>      /* Board ID = 0x420 (Malta Board with CoreLV) */
>      stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> -    /*
> -     * We have a circular dependency problem: pci_bus depends on isa_irq,
> -     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> -     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
> -     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> -     * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> -     */
> -    isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
>      /* Northbridge */
> -    pci_bus = gt64120_register(isa_irq);
> +    pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
>      ide_drive_get(hd, ARRAY_SIZE(hd));
>
> -    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, "PIIX4");
> +    dev = DEVICE(pci);
> +    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    piix4_devfn = pci->devfn;
>
> -    /*
> -     * Interrupt controller
> -     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> -     */
> -    s->i8259 = i8259_init(isa_bus, i8259_irq);
> +    /* Interrupt controller */
> +    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> +    for (int i = 0; i < ISA_NUM_IRQS; i++) {
> +        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> +    }
>
> -    isa_bus_irqs(isa_bus, s->i8259);
>      pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 09e74e7764..a95eab0d8a 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>  PCIBus *find_i440fx(void);
>  /* piix4.c */
>  extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>

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_______________________________________________
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Xen-devel@lists.xenproject.org
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Re: [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 9264 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> These devices implemented their load_state_old() handler 10 years
> ago, previous to QEMU v0.12.
> Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> we can drop this code.
>
> Note: the mips_r4k machine started to use the i8254 device just
> after QEMU v0.5.0, but the MIPS machine types are not versioned,
> so there is no migration compatibility issue removing this handler.
>
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/acpi/piix4.c         | 40 ---------------------------------
>  hw/intc/apic_common.c   | 49 -----------------------------------------
>  hw/pci-host/piix.c      | 25 ---------------------
>  hw/timer/i8254_common.c | 40 ---------------------------------
>  4 files changed, 154 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 5742c3df87..1d29d438c7 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -42,7 +42,6 @@
>  #include "hw/acpi/memory_hotplug.h"
>  #include "hw/acpi/acpi_dev_interface.h"
>  #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>  #include "hw/core/cpu.h"
>  #include "trace.h"
> @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
>      }
>  };
>
> -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PIIX4PMState *s = opaque;
> -    int ret, i;
> -    uint16_t temp;
> -
> -    ret = pci_device_load(PCI_DEVICE(s), f);
> -    if (ret < 0) {
> -        return ret;
> -    }
> -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> -
> -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> -    if (ret) {
> -        return ret;
> -    }
> -
> -    timer_get(f, s->ar.tmr.timer);
> -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    ret = vmstate_load_state(f, &vmstate_pci_status,
> -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
> 1);
> -    return ret;
> -}
> -
>  static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int
> version_id)
>  {
>      PIIX4PMState *s = opaque;
> @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
>      .name = "piix4_pm",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = acpi_load_old,
>      .post_load = vmstate_acpi_post_load,
>      .fields = (VMStateField[]) {
>          VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index aafd8e0e33..375cb6abe9 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -31,7 +31,6 @@
>  #include "sysemu/kvm.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/sysbus.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>
>  static int apic_irq_delivered;
> @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
>      apic_init_reset(dev);
>  }
>
> -/* This function is only used for old state version 1 and 2 */
> -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    APICCommonState *s = opaque;
> -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> -    int i;
> -
> -    if (version_id > 2) {
> -        return -EINVAL;
> -    }
> -
> -    /* XXX: what if the base changes? (registered memory regions) */
> -    qemu_get_be32s(f, &s->apicbase);
> -    qemu_get_8s(f, &s->id);
> -    qemu_get_8s(f, &s->arb_id);
> -    qemu_get_8s(f, &s->tpr);
> -    qemu_get_be32s(f, &s->spurious_vec);
> -    qemu_get_8s(f, &s->log_dest);
> -    qemu_get_8s(f, &s->dest_mode);
> -    for (i = 0; i < 8; i++) {
> -        qemu_get_be32s(f, &s->isr[i]);
> -        qemu_get_be32s(f, &s->tmr[i]);
> -        qemu_get_be32s(f, &s->irr[i]);
> -    }
> -    for (i = 0; i < APIC_LVT_NB; i++) {
> -        qemu_get_be32s(f, &s->lvt[i]);
> -    }
> -    qemu_get_be32s(f, &s->esr);
> -    qemu_get_be32s(f, &s->icr[0]);
> -    qemu_get_be32s(f, &s->icr[1]);
> -    qemu_get_be32s(f, &s->divide_conf);
> -    s->count_shift = qemu_get_be32(f);
> -    qemu_get_be32s(f, &s->initial_count);
> -    s->initial_count_load_time = qemu_get_be64(f);
> -    s->next_time = qemu_get_be64(f);
> -
> -    if (version_id >= 2) {
> -        s->timer_expiry = qemu_get_be64(f);
> -    }
> -
> -    if (info->post_load) {
> -        info->post_load(s);
> -    }
> -    return 0;
> -}
> -
>  static const VMStateDescription vmstate_apic_common;
>
>  static void apic_common_realize(DeviceState *dev, Error **errp)
> @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
>      .name = "apic",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = apic_load_old,
>      .pre_load = apic_pre_load,
>      .pre_save = apic_dispatch_pre_save,
>      .post_load = apic_dispatch_post_load,
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 135c645535..2f4cbcbfe9 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -33,7 +33,6 @@
>  #include "qapi/error.h"
>  #include "qemu/range.h"
>  #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>  #include "hw/pci-host/pam.h"
>  #include "sysemu/reset.h"
> @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
>      }
>  }
>
> -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> -{
> -    PCII440FXState *d = opaque;
> -    PCIDevice *pd = PCI_DEVICE(d);
> -    int ret, i;
> -    uint8_t smm_enabled;
> -
> -    ret = pci_device_load(pd, f);
> -    if (ret < 0)
> -        return ret;
> -    i440fx_update_memory_mappings(d);
> -    qemu_get_8s(f, &smm_enabled);
> -
> -    if (version_id == 2) {
> -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> -            qemu_get_be32(f); /* dummy load for compatibility */
> -        }
> -    }
> -
> -    return 0;
> -}
> -
>  static int i440fx_post_load(void *opaque, int version_id)
>  {
>      PCII440FXState *d = opaque;
> @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
>      .name = "I440FX",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = i440fx_load_old,
>      .post_load = i440fx_post_load,
>      .fields = (VMStateField[]) {
>          VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> index 57bf10cc94..050875b497 100644
> --- a/hw/timer/i8254_common.c
> +++ b/hw/timer/i8254_common.c
> @@ -29,7 +29,6 @@
>  #include "qemu/timer.h"
>  #include "hw/timer/i8254.h"
>  #include "hw/timer/i8254_internal.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>
>  /* val must be 0 or 1 */
> @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel =
> {
>      }
>  };
>
> -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PITCommonState *pit = opaque;
> -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> -    PITChannelState *s;
> -    int i;
> -
> -    if (version_id != 1) {
> -        return -EINVAL;
> -    }
> -
> -    for (i = 0; i < 3; i++) {
> -        s = &pit->channels[i];
> -        s->count = qemu_get_be32(f);
> -        qemu_get_be16s(f, &s->latched_count);
> -        qemu_get_8s(f, &s->count_latched);
> -        qemu_get_8s(f, &s->status_latched);
> -        qemu_get_8s(f, &s->status);
> -        qemu_get_8s(f, &s->read_state);
> -        qemu_get_8s(f, &s->write_state);
> -        qemu_get_8s(f, &s->write_latch);
> -        qemu_get_8s(f, &s->rw_mode);
> -        qemu_get_8s(f, &s->mode);
> -        qemu_get_8s(f, &s->bcd);
> -        qemu_get_8s(f, &s->gate);
> -        s->count_load_time = qemu_get_be64(f);
> -        s->irq_disabled = 0;
> -        if (i == 0) {
> -            s->next_transition_time = qemu_get_be64(f);
> -        }
> -    }
> -    if (c->post_load) {
> -        c->post_load(pit);
> -    }
> -    return 0;
> -}
> -
>  static int pit_dispatch_pre_save(void *opaque)
>  {
>      PITCommonState *s = opaque;
> @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
>      .name = "i8254",
>      .version_id = 3,
>      .minimum_version_id = 2,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = pit_load_old,
>      .pre_save = pit_dispatch_pre_save,
>      .post_load = pit_dispatch_post_load,
>      .fields = (VMStateField[]) {
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 9264 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> These devices implemented their load_state_old() handler 10 years
> ago, previous to QEMU v0.12.
> Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> we can drop this code.
>
> Note: the mips_r4k machine started to use the i8254 device just
> after QEMU v0.5.0, but the MIPS machine types are not versioned,
> so there is no migration compatibility issue removing this handler.
>
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/acpi/piix4.c         | 40 ---------------------------------
>  hw/intc/apic_common.c   | 49 -----------------------------------------
>  hw/pci-host/piix.c      | 25 ---------------------
>  hw/timer/i8254_common.c | 40 ---------------------------------
>  4 files changed, 154 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 5742c3df87..1d29d438c7 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -42,7 +42,6 @@
>  #include "hw/acpi/memory_hotplug.h"
>  #include "hw/acpi/acpi_dev_interface.h"
>  #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>  #include "hw/core/cpu.h"
>  #include "trace.h"
> @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
>      }
>  };
>
> -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PIIX4PMState *s = opaque;
> -    int ret, i;
> -    uint16_t temp;
> -
> -    ret = pci_device_load(PCI_DEVICE(s), f);
> -    if (ret < 0) {
> -        return ret;
> -    }
> -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> -
> -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> -    if (ret) {
> -        return ret;
> -    }
> -
> -    timer_get(f, s->ar.tmr.timer);
> -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> -    for (i = 0; i < 3; i++) {
> -        qemu_get_be16s(f, &temp);
> -    }
> -
> -    ret = vmstate_load_state(f, &vmstate_pci_status,
> -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
> 1);
> -    return ret;
> -}
> -
>  static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int
> version_id)
>  {
>      PIIX4PMState *s = opaque;
> @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
>      .name = "piix4_pm",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = acpi_load_old,
>      .post_load = vmstate_acpi_post_load,
>      .fields = (VMStateField[]) {
>          VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index aafd8e0e33..375cb6abe9 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -31,7 +31,6 @@
>  #include "sysemu/kvm.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/sysbus.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>
>  static int apic_irq_delivered;
> @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
>      apic_init_reset(dev);
>  }
>
> -/* This function is only used for old state version 1 and 2 */
> -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    APICCommonState *s = opaque;
> -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> -    int i;
> -
> -    if (version_id > 2) {
> -        return -EINVAL;
> -    }
> -
> -    /* XXX: what if the base changes? (registered memory regions) */
> -    qemu_get_be32s(f, &s->apicbase);
> -    qemu_get_8s(f, &s->id);
> -    qemu_get_8s(f, &s->arb_id);
> -    qemu_get_8s(f, &s->tpr);
> -    qemu_get_be32s(f, &s->spurious_vec);
> -    qemu_get_8s(f, &s->log_dest);
> -    qemu_get_8s(f, &s->dest_mode);
> -    for (i = 0; i < 8; i++) {
> -        qemu_get_be32s(f, &s->isr[i]);
> -        qemu_get_be32s(f, &s->tmr[i]);
> -        qemu_get_be32s(f, &s->irr[i]);
> -    }
> -    for (i = 0; i < APIC_LVT_NB; i++) {
> -        qemu_get_be32s(f, &s->lvt[i]);
> -    }
> -    qemu_get_be32s(f, &s->esr);
> -    qemu_get_be32s(f, &s->icr[0]);
> -    qemu_get_be32s(f, &s->icr[1]);
> -    qemu_get_be32s(f, &s->divide_conf);
> -    s->count_shift = qemu_get_be32(f);
> -    qemu_get_be32s(f, &s->initial_count);
> -    s->initial_count_load_time = qemu_get_be64(f);
> -    s->next_time = qemu_get_be64(f);
> -
> -    if (version_id >= 2) {
> -        s->timer_expiry = qemu_get_be64(f);
> -    }
> -
> -    if (info->post_load) {
> -        info->post_load(s);
> -    }
> -    return 0;
> -}
> -
>  static const VMStateDescription vmstate_apic_common;
>
>  static void apic_common_realize(DeviceState *dev, Error **errp)
> @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
>      .name = "apic",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = apic_load_old,
>      .pre_load = apic_pre_load,
>      .pre_save = apic_dispatch_pre_save,
>      .post_load = apic_dispatch_post_load,
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 135c645535..2f4cbcbfe9 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -33,7 +33,6 @@
>  #include "qapi/error.h"
>  #include "qemu/range.h"
>  #include "hw/xen/xen.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>  #include "hw/pci-host/pam.h"
>  #include "sysemu/reset.h"
> @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
>      }
>  }
>
> -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> -{
> -    PCII440FXState *d = opaque;
> -    PCIDevice *pd = PCI_DEVICE(d);
> -    int ret, i;
> -    uint8_t smm_enabled;
> -
> -    ret = pci_device_load(pd, f);
> -    if (ret < 0)
> -        return ret;
> -    i440fx_update_memory_mappings(d);
> -    qemu_get_8s(f, &smm_enabled);
> -
> -    if (version_id == 2) {
> -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> -            qemu_get_be32(f); /* dummy load for compatibility */
> -        }
> -    }
> -
> -    return 0;
> -}
> -
>  static int i440fx_post_load(void *opaque, int version_id)
>  {
>      PCII440FXState *d = opaque;
> @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
>      .name = "I440FX",
>      .version_id = 3,
>      .minimum_version_id = 3,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = i440fx_load_old,
>      .post_load = i440fx_post_load,
>      .fields = (VMStateField[]) {
>          VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> index 57bf10cc94..050875b497 100644
> --- a/hw/timer/i8254_common.c
> +++ b/hw/timer/i8254_common.c
> @@ -29,7 +29,6 @@
>  #include "qemu/timer.h"
>  #include "hw/timer/i8254.h"
>  #include "hw/timer/i8254_internal.h"
> -#include "migration/qemu-file-types.h"
>  #include "migration/vmstate.h"
>
>  /* val must be 0 or 1 */
> @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel =
> {
>      }
>  };
>
> -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> -{
> -    PITCommonState *pit = opaque;
> -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> -    PITChannelState *s;
> -    int i;
> -
> -    if (version_id != 1) {
> -        return -EINVAL;
> -    }
> -
> -    for (i = 0; i < 3; i++) {
> -        s = &pit->channels[i];
> -        s->count = qemu_get_be32(f);
> -        qemu_get_be16s(f, &s->latched_count);
> -        qemu_get_8s(f, &s->count_latched);
> -        qemu_get_8s(f, &s->status_latched);
> -        qemu_get_8s(f, &s->status);
> -        qemu_get_8s(f, &s->read_state);
> -        qemu_get_8s(f, &s->write_state);
> -        qemu_get_8s(f, &s->write_latch);
> -        qemu_get_8s(f, &s->rw_mode);
> -        qemu_get_8s(f, &s->mode);
> -        qemu_get_8s(f, &s->bcd);
> -        qemu_get_8s(f, &s->gate);
> -        s->count_load_time = qemu_get_be64(f);
> -        s->irq_disabled = 0;
> -        if (i == 0) {
> -            s->next_transition_time = qemu_get_be64(f);
> -        }
> -    }
> -    if (c->post_load) {
> -        c->post_load(pit);
> -    }
> -    return 0;
> -}
> -
>  static int pit_dispatch_pre_save(void *opaque)
>  {
>      PITCommonState *s = opaque;
> @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
>      .name = "i8254",
>      .version_id = 3,
>      .minimum_version_id = 2,
> -    .minimum_version_id_old = 1,
> -    .load_state_old = pit_load_old,
>      .pre_save = pit_dispatch_pre_save,
>      .post_load = pit_dispatch_post_load,
>      .fields = (VMStateField[]) {
> --
> 2.21.0
>
>
>

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Re: [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 4 ++++
>  hw/mips/mips_malta.c | 2 --
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>




> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 8998b0ca47..1bc91b590c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -164,6 +165,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* initialize ISA irqs */
>      isa_bus_irqs(isa_bus, s->isa);
>
> +    /* DMA */
> +    i8257_dma_init(isa_bus, 0);
> +
>      piix4_dev = pci_dev;
>  }
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
>  #include "cpu.h"
>  #include "hw/i386/pc.h"
>  #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
>  #include "hw/char/serial.h"
>  #include "net/net.h"
>  #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
>      pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> -    i8257_dma_init(isa_bus, 0);
>      mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 4 ++++
>  hw/mips/mips_malta.c | 2 --
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>




> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 8998b0ca47..1bc91b590c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -164,6 +165,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* initialize ISA irqs */
>      isa_bus_irqs(isa_bus, s->isa);
>
> +    /* DMA */
> +    i8257_dma_init(isa_bus, 0);
> +
>      piix4_dev = pci_dev;
>  }
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
>  #include "cpu.h"
>  #include "hw/i386/pc.h"
>  #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
>  #include "hw/char/serial.h"
>  #include "net/net.h"
>  #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
>      pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> -    i8257_dma_init(isa_bus, 0);
>      mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>

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Re: [PATCH 15/32] piix4: add a i8254 pit controller as specified in datasheet

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 2453 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8254 instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 4 ++++
>  hw/mips/mips_malta.c | 4 ----
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 1bc91b590c..0b0a0ecab1 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -30,6 +30,7 @@
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
> +#include "hw/timer/i8254.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -165,6 +166,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* initialize ISA irqs */
>      isa_bus_irqs(isa_bus, s->isa);
>
> +    /* initialize pit */
> +    i8254_pit_init(isa_bus, 0x40, 0, NULL);
> +
>      /* DMA */
>      i8257_dma_init(isa_bus, 0);
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index df247177ca..16d7a0e785 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -45,7 +45,6 @@
>  #include "hw/loader.h"
>  #include "elf.h"
>  #include "hw/timer/mc146818rtc.h"
> -#include "hw/timer/i8254.h"
>  #include "exec/address-spaces.h"
>  #include "hw/sysbus.h"             /* SysBusDevice */
>  #include "qemu/host-utils.h"
> @@ -99,8 +98,6 @@ typedef struct {
>      qemu_irq i8259[16];
>  } MaltaState;
>
> -static ISADevice *pit;
> -
>  static struct _loaderparams {
>      int ram_size, ram_low_size;
>      const char *kernel_filename;
> @@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> -    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
>      mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 15/32] piix4: add a i8254 pit controller as specified in datasheet

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 2453 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8254 instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 4 ++++
>  hw/mips/mips_malta.c | 4 ----
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 1bc91b590c..0b0a0ecab1 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -30,6 +30,7 @@
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
> +#include "hw/timer/i8254.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -165,6 +166,9 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* initialize ISA irqs */
>      isa_bus_irqs(isa_bus, s->isa);
>
> +    /* initialize pit */
> +    i8254_pit_init(isa_bus, 0x40, 0, NULL);
> +
>      /* DMA */
>      i8257_dma_init(isa_bus, 0);
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index df247177ca..16d7a0e785 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -45,7 +45,6 @@
>  #include "hw/loader.h"
>  #include "elf.h"
>  #include "hw/timer/mc146818rtc.h"
> -#include "hw/timer/i8254.h"
>  #include "exec/address-spaces.h"
>  #include "hw/sysbus.h"             /* SysBusDevice */
>  #include "qemu/host-utils.h"
> @@ -99,8 +98,6 @@ typedef struct {
>      qemu_irq i8259[16];
>  } MaltaState;
>
> -static ISADevice *pit;
> -
>  static struct _loaderparams {
>      int ram_size, ram_low_size;
>      const char *kernel_filename;
> @@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> -    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
>      mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>

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Re: [PATCH 16/32] piix4: add a mc146818rtc controller as specified in datasheet

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 8641 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Remove mc146818rtc instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
> [PMD: rebased, set RTC base_year to 2000]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                   |  3 ++-
>  hw/acpi/piix4.c               |  2 +-
>  hw/i386/acpi-build.c          |  3 +--
>  hw/i386/pc_piix.c             |  1 +
>  hw/isa/piix4.c                | 22 ++++++++++++++++++++++
>  hw/mips/mips_malta.c          |  4 +---
>  include/hw/acpi/piix4.h       |  6 ------
>  include/hw/i386/pc.h          |  6 ------
>  include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
>  9 files changed, 48 insertions(+), 19 deletions(-)
>  delete mode 100644 include/hw/acpi/piix4.h
>  create mode 100644 include/hw/southbridge/piix.h
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index c9f625fc2e..556f58bd8c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
>  F: hw/acpi/ich9.c
>  F: include/hw/acpi/ich9.h
> -F: include/hw/acpi/piix4.h
> +F: include/hw/southbridge/piix.h
>  F: hw/misc/sga.c
>  F: hw/isa/apm.c
>  F: include/hw/isa/apm.h
> @@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
>  M: Philippe Mathieu-Daudé <f4bug@amsat.org>
>  S: Maintained
>  F: hw/isa/piix4.c
> +F: include/hw/southbridge/piix.h
>
>  Firmware configuration (fw_cfg)
>  M: Philippe Mathieu-Daudé <philmd@redhat.com>
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 1d29d438c7..27270621ab 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -21,6 +21,7 @@
>
>  #include "qemu/osdep.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/isa/apm.h"
>  #include "hw/i2c/pm_smbus.h"
> @@ -33,7 +34,6 @@
>  #include "qapi/error.h"
>  #include "qemu/range.h"
>  #include "exec/address-spaces.h"
> -#include "hw/acpi/piix4.h"
>  #include "hw/acpi/pcihp.h"
>  #include "hw/acpi/cpu_hotplug.h"
>  #include "hw/acpi/cpu.h"
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 4e0f9f425a..aa6fe61191 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -34,7 +34,6 @@
>  #include "hw/acpi/acpi-defs.h"
>  #include "hw/acpi/acpi.h"
>  #include "hw/acpi/cpu.h"
> -#include "hw/acpi/piix4.h"
>  #include "hw/nvram/fw_cfg.h"
>  #include "hw/acpi/bios-linker-loader.h"
>  #include "hw/isa/isa.h"
> @@ -52,7 +51,7 @@
>  #include "sysemu/reset.h"
>
>  /* Supported chipsets: */
> -#include "hw/acpi/piix4.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/acpi/pcihp.h"
>  #include "hw/i386/ich9.h"
>  #include "hw/pci/pci_bus.h"
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 6824b72124..431965d921 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -29,6 +29,7 @@
>  #include "hw/loader.h"
>  #include "hw/i386/pc.h"
>  #include "hw/i386/apic.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/display/ramfb.h"
>  #include "hw/firmware/smbios.h"
>  #include "hw/pci/pci.h"
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 0b0a0ecab1..9f554747af 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qapi/error.h"
>  #include "hw/irq.h"
>  #include "hw/i386/pc.h"
>  #include "hw/pci/pci.h"
> @@ -31,6 +32,7 @@
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
>  #include "hw/timer/i8254.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -42,6 +44,7 @@ typedef struct PIIX4State {
>      qemu_irq cpu_intr;
>      qemu_irq *isa;
>
> +    RTCState rtc;
>      /* Reset Control Register */
>      MemoryRegion rcr_mem;
>      uint8_t rcr;
> @@ -144,6 +147,7 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>      ISABus *isa_bus;
>      qemu_irq *i8259_out_irq;
> +    Error *err = NULL;
>
>      isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
>                            pci_address_space_io(pci_dev), errp);
> @@ -172,9 +176,26 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* DMA */
>      i8257_dma_init(isa_bus, 0);
>
> +    /* RTC */
> +    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
> +    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
> +    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
> +    if (err) {
> +        error_propagate(errp, err);
> +        return;
> +    }
> +    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
> +
>      piix4_dev = pci_dev;
>  }
>
> +static void piix4_init(Object *obj)
> +{
> +    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
> +
> +    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
> +}
> +
>  static void piix4_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -199,6 +220,7 @@ static const TypeInfo piix4_info = {
>      .name          = TYPE_PIIX4_PCI_DEVICE,
>      .parent        = TYPE_PCI_DEVICE,
>      .instance_size = sizeof(PIIX4State),
> +    .instance_init = piix4_init,
>      .class_init    = piix4_class_init,
>      .interfaces = (InterfaceInfo[]) {
>          { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 16d7a0e785..528c34a1c3 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -26,7 +26,7 @@
>  #include "qemu/units.h"
>  #include "qemu-common.h"
>  #include "cpu.h"
> -#include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/isa/superio.h"
>  #include "hw/char/serial.h"
>  #include "net/net.h"
> @@ -44,7 +44,6 @@
>  #include "hw/irq.h"
>  #include "hw/loader.h"
>  #include "elf.h"
> -#include "hw/timer/mc146818rtc.h"
>  #include "exec/address-spaces.h"
>  #include "hw/sysbus.h"             /* SysBusDevice */
>  #include "qemu/host-utils.h"
> @@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> -    mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
>      generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
> diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
> deleted file mode 100644
> index 028bb53e3d..0000000000
> --- a/include/hw/acpi/piix4.h
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#ifndef HW_ACPI_PIIX4_H
> -#define HW_ACPI_PIIX4_H
> -
> -#define TYPE_PIIX4_PM "PIIX4_PM"
> -
> -#endif
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index a95eab0d8a..c671c9fd2a 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -244,12 +244,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
>
>  #define PORT92_A20_LINE "a20"
>
> -/* acpi_piix.c */
> -
> -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> -                      qemu_irq sci_irq, qemu_irq smi_irq,
> -                      int smm_enabled, DeviceState **piix4_pm);
> -
>  /* hpet.c */
>  extern int no_hpet;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> new file mode 100644
> index 0000000000..b8ce26fec4
> --- /dev/null
> +++ b/include/hw/southbridge/piix.h
> @@ -0,0 +1,20 @@
> +/*
> + * QEMU PIIX South Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_SOUTHBRIDGE_PIIX_H
> +#define HW_SOUTHBRIDGE_PIIX_H
> +
> +#define TYPE_PIIX4_PM "PIIX4_PM"
> +
> +I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> +                      qemu_irq sci_irq, qemu_irq smi_irq,
> +                      int smm_enabled, DeviceState **piix4_pm);
> +
> +#endif
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 16/32] piix4: add a mc146818rtc controller as specified in datasheet

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Remove mc146818rtc instanciated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
> [PMD: rebased, set RTC base_year to 2000]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                   |  3 ++-
>  hw/acpi/piix4.c               |  2 +-
>  hw/i386/acpi-build.c          |  3 +--
>  hw/i386/pc_piix.c             |  1 +
>  hw/isa/piix4.c                | 22 ++++++++++++++++++++++
>  hw/mips/mips_malta.c          |  4 +---
>  include/hw/acpi/piix4.h       |  6 ------
>  include/hw/i386/pc.h          |  6 ------
>  include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
>  9 files changed, 48 insertions(+), 19 deletions(-)
>  delete mode 100644 include/hw/acpi/piix4.h
>  create mode 100644 include/hw/southbridge/piix.h
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index c9f625fc2e..556f58bd8c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
>  F: hw/acpi/ich9.c
>  F: include/hw/acpi/ich9.h
> -F: include/hw/acpi/piix4.h
> +F: include/hw/southbridge/piix.h
>  F: hw/misc/sga.c
>  F: hw/isa/apm.c
>  F: include/hw/isa/apm.h
> @@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
>  M: Philippe Mathieu-Daudé <f4bug@amsat.org>
>  S: Maintained
>  F: hw/isa/piix4.c
> +F: include/hw/southbridge/piix.h
>
>  Firmware configuration (fw_cfg)
>  M: Philippe Mathieu-Daudé <philmd@redhat.com>
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 1d29d438c7..27270621ab 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -21,6 +21,7 @@
>
>  #include "qemu/osdep.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/isa/apm.h"
>  #include "hw/i2c/pm_smbus.h"
> @@ -33,7 +34,6 @@
>  #include "qapi/error.h"
>  #include "qemu/range.h"
>  #include "exec/address-spaces.h"
> -#include "hw/acpi/piix4.h"
>  #include "hw/acpi/pcihp.h"
>  #include "hw/acpi/cpu_hotplug.h"
>  #include "hw/acpi/cpu.h"
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 4e0f9f425a..aa6fe61191 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -34,7 +34,6 @@
>  #include "hw/acpi/acpi-defs.h"
>  #include "hw/acpi/acpi.h"
>  #include "hw/acpi/cpu.h"
> -#include "hw/acpi/piix4.h"
>  #include "hw/nvram/fw_cfg.h"
>  #include "hw/acpi/bios-linker-loader.h"
>  #include "hw/isa/isa.h"
> @@ -52,7 +51,7 @@
>  #include "sysemu/reset.h"
>
>  /* Supported chipsets: */
> -#include "hw/acpi/piix4.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/acpi/pcihp.h"
>  #include "hw/i386/ich9.h"
>  #include "hw/pci/pci_bus.h"
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 6824b72124..431965d921 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -29,6 +29,7 @@
>  #include "hw/loader.h"
>  #include "hw/i386/pc.h"
>  #include "hw/i386/apic.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/display/ramfb.h"
>  #include "hw/firmware/smbios.h"
>  #include "hw/pci/pci.h"
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 0b0a0ecab1..9f554747af 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qapi/error.h"
>  #include "hw/irq.h"
>  #include "hw/i386/pc.h"
>  #include "hw/pci/pci.h"
> @@ -31,6 +32,7 @@
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
>  #include "hw/timer/i8254.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -42,6 +44,7 @@ typedef struct PIIX4State {
>      qemu_irq cpu_intr;
>      qemu_irq *isa;
>
> +    RTCState rtc;
>      /* Reset Control Register */
>      MemoryRegion rcr_mem;
>      uint8_t rcr;
> @@ -144,6 +147,7 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>      ISABus *isa_bus;
>      qemu_irq *i8259_out_irq;
> +    Error *err = NULL;
>
>      isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),
>                            pci_address_space_io(pci_dev), errp);
> @@ -172,9 +176,26 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      /* DMA */
>      i8257_dma_init(isa_bus, 0);
>
> +    /* RTC */
> +    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
> +    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
> +    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
> +    if (err) {
> +        error_propagate(errp, err);
> +        return;
> +    }
> +    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
> +
>      piix4_dev = pci_dev;
>  }
>
> +static void piix4_init(Object *obj)
> +{
> +    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
> +
> +    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
> +}
> +
>  static void piix4_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -199,6 +220,7 @@ static const TypeInfo piix4_info = {
>      .name          = TYPE_PIIX4_PCI_DEVICE,
>      .parent        = TYPE_PCI_DEVICE,
>      .instance_size = sizeof(PIIX4State),
> +    .instance_init = piix4_init,
>      .class_init    = piix4_class_init,
>      .interfaces = (InterfaceInfo[]) {
>          { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 16d7a0e785..528c34a1c3 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -26,7 +26,7 @@
>  #include "qemu/units.h"
>  #include "qemu-common.h"
>  #include "cpu.h"
> -#include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/isa/superio.h"
>  #include "hw/char/serial.h"
>  #include "net/net.h"
> @@ -44,7 +44,6 @@
>  #include "hw/irq.h"
>  #include "hw/loader.h"
>  #include "elf.h"
> -#include "hw/timer/mc146818rtc.h"
>  #include "exec/address-spaces.h"
>  #include "hw/sysbus.h"             /* SysBusDevice */
>  #include "qemu/host-utils.h"
> @@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> -    mc146818_rtc_init(isa_bus, 2000, NULL);
>
>      /* generate SPD EEPROM data */
>      generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
> diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
> deleted file mode 100644
> index 028bb53e3d..0000000000
> --- a/include/hw/acpi/piix4.h
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#ifndef HW_ACPI_PIIX4_H
> -#define HW_ACPI_PIIX4_H
> -
> -#define TYPE_PIIX4_PM "PIIX4_PM"
> -
> -#endif
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index a95eab0d8a..c671c9fd2a 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -244,12 +244,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
>
>  #define PORT92_A20_LINE "a20"
>
> -/* acpi_piix.c */
> -
> -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> -                      qemu_irq sci_irq, qemu_irq smi_irq,
> -                      int smm_enabled, DeviceState **piix4_pm);
> -
>  /* hpet.c */
>  extern int no_hpet;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> new file mode 100644
> index 0000000000..b8ce26fec4
> --- /dev/null
> +++ b/include/hw/southbridge/piix.h
> @@ -0,0 +1,20 @@
> +/*
> + * QEMU PIIX South Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_SOUTHBRIDGE_PIIX_H
> +#define HW_SOUTHBRIDGE_PIIX_H
> +
> +#define TYPE_PIIX4_PM "PIIX4_PM"
> +
> +I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> +                      qemu_irq sci_irq, qemu_irq smi_irq,
> +                      int smm_enabled, DeviceState **piix4_pm);
> +
> +#endif
> --
> 2.21.0
>
>
>

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Re: [PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> In the next commit we'll refactor the PIIX4 code out of
> mips_malta_init(). As a preliminary step, add the 'ide_drives'
> variable and create the drive array dynamically.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/mips/mips_malta.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 528c34a1c3..774bb810f6 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
>      int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> -    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> +    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> +    DriveInfo **hd;
>      int fl_idx = 0;
>      int be;
>
> @@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
>      pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
> -    ide_drive_get(hd, ARRAY_SIZE(hd));
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
>
>      pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>                                            true, TYPE_PIIX4_PCI_DEVICE);
> @@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
>      }
>
>      pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> +    g_free(hd);
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> In the next commit we'll refactor the PIIX4 code out of
> mips_malta_init(). As a preliminary step, add the 'ide_drives'
> variable and create the drive array dynamically.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/mips/mips_malta.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 528c34a1c3..774bb810f6 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
>      int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> -    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> +    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> +    DriveInfo **hd;
>      int fl_idx = 0;
>      int be;
>
> @@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
>      pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
> -    ide_drive_get(hd, ARRAY_SIZE(hd));
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
>
>      pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>                                            true, TYPE_PIIX4_PCI_DEVICE);
> @@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
>      }
>
>      pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> +    g_free(hd);
>      pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>                            isa_get_irq(NULL, 9), NULL, 0, NULL);
> --
> 2.21.0
>
>
>

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Re: [PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The Malta board instantiate a PIIX4 chipset doing various
> calls. Refactor all those related calls into a single
> function: piix4_create().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
>  1 file changed, 29 insertions(+), 18 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 774bb810f6..0d4312840b 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms,
> MaltaState *s,
>      }
>  }
>
> +static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                                 I2CBus **smbus, size_t ide_buses)
> +{
> +    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> +    DriveInfo **hd;
> +    PCIDevice *pci;
> +    DeviceState *dev;
> +
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
> +    dev = DEVICE(pci);
> +    if (isa_bus) {
> +        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    }
> +
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
> +    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> +    g_free(hd);
> +    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> +    if (smbus) {
> +        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> +                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> +   }
> +
> +    return dev;
> +}
> +
>  static
>  void mips_malta_init(MachineState *machine)
>  {
> @@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
>      qemu_irq cbus_irq, i8259_irq;
> -    PCIDevice *pci;
> -    int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> -    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> -    DriveInfo **hd;
>      int fl_idx = 0;
>      int be;
>
> @@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
>      pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
> -    hd = g_new(DriveInfo *, ide_drives);
> -    ide_drive_get(hd, ide_drives);
> -
> -    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, TYPE_PIIX4_PCI_DEVICE);
> -    dev = DEVICE(pci);
> -    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> -    piix4_devfn = pci->devfn;
> +    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
>
>      /* Interrupt controller */
>      qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> @@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
>          s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>      }
>
> -    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> -    g_free(hd);
> -    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> -    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> -                          isa_get_irq(NULL, 9), NULL, 0, NULL);
> -
>      /* generate SPD EEPROM data */
>      generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
>      generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 3528 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The Malta board instantiate a PIIX4 chipset doing various
> calls. Refactor all those related calls into a single
> function: piix4_create().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
>  1 file changed, 29 insertions(+), 18 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 774bb810f6..0d4312840b 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms,
> MaltaState *s,
>      }
>  }
>
> +static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                                 I2CBus **smbus, size_t ide_buses)
> +{
> +    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> +    DriveInfo **hd;
> +    PCIDevice *pci;
> +    DeviceState *dev;
> +
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
> +    dev = DEVICE(pci);
> +    if (isa_bus) {
> +        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    }
> +
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
> +    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> +    g_free(hd);
> +    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> +    if (smbus) {
> +        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> +                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> +   }
> +
> +    return dev;
> +}
> +
>  static
>  void mips_malta_init(MachineState *machine)
>  {
> @@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
>      qemu_irq cbus_irq, i8259_irq;
> -    PCIDevice *pci;
> -    int piix4_devfn;
>      I2CBus *smbus;
>      DriveInfo *dinfo;
> -    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> -    DriveInfo **hd;
>      int fl_idx = 0;
>      int be;
>
> @@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
>      pci_bus = gt64120_register(s->i8259);
>
>      /* Southbridge */
> -    hd = g_new(DriveInfo *, ide_drives);
> -    ide_drive_get(hd, ide_drives);
> -
> -    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, TYPE_PIIX4_PCI_DEVICE);
> -    dev = DEVICE(pci);
> -    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> -    piix4_devfn = pci->devfn;
> +    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
>
>      /* Interrupt controller */
>      qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> @@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
>          s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>      }
>
> -    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> -    g_free(hd);
> -    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> -    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> -                          isa_get_irq(NULL, 9), NULL, 0, NULL);
> -
>      /* generate SPD EEPROM data */
>      generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
>      generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
> --
> 2.21.0
>
>
>

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Re: [PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 5566 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Now that we properly refactored the piix4_create() function, let's
> move it to hw/isa/piix4.c where it belongs, so it can be reused
> on other places.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
>  hw/mips/gt64xxx_pci.c         |  1 +
>  hw/mips/mips_malta.c          | 28 ----------------------------
>  include/hw/i386/pc.h          |  2 --
>  include/hw/southbridge/piix.h |  6 ++++++
>  5 files changed, 37 insertions(+), 30 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9f554747af..d90899e122 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -27,12 +27,14 @@
>  #include "qapi/error.h"
>  #include "hw/irq.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
>  #include "hw/timer/i8254.h"
>  #include "hw/timer/mc146818rtc.h"
> +#include "hw/ide.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -234,3 +236,31 @@ static void piix4_register_types(void)
>  }
>
>  type_init(piix4_register_types)
> +
> +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                          I2CBus **smbus, size_t ide_buses)
> +{
> +    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> +    DriveInfo **hd;
> +    PCIDevice *pci;
> +    DeviceState *dev;
> +
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
> +    dev = DEVICE(pci);
> +    if (isa_bus) {
> +        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    }
> +
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
> +    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> +    g_free(hd);
> +    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> +    if (smbus) {
> +        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> +                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> +   }
> +
> +    return dev;
> +}
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index f325bd6c1c..c277398c0d 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -28,6 +28,7 @@
>  #include "hw/mips/mips.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/southbridge/piix.h"
>  #include "migration/vmstate.h"
>  #include "hw/i386/pc.h"
>  #include "hw/irq.h"
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 0d4312840b..477a4725c0 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms,
> MaltaState *s,
>      }
>  }
>
> -static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> -                                 I2CBus **smbus, size_t ide_buses)
> -{
> -    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> -    DriveInfo **hd;
> -    PCIDevice *pci;
> -    DeviceState *dev;
> -
> -    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, TYPE_PIIX4_PCI_DEVICE);
> -    dev = DEVICE(pci);
> -    if (isa_bus) {
> -        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> -    }
> -
> -    hd = g_new(DriveInfo *, ide_drives);
> -    ide_drive_get(hd, ide_drives);
> -    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> -    g_free(hd);
> -    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> -    if (smbus) {
> -        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> -                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> -   }
> -
> -    return dev;
> -}
> -
>  static
>  void mips_malta_init(MachineState *machine)
>  {
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index c671c9fd2a..b63fc7631e 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -274,8 +274,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>                      MemoryRegion *ram_memory);
>
>  PCIBus *find_i440fx(void);
> -/* piix4.c */
> -extern PCIDevice *piix4_dev;
>
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index b8ce26fec4..add352456b 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -2,6 +2,7 @@
>   * QEMU PIIX South Bridge Emulation
>   *
>   * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
>   *
>   * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
>   * See the COPYING file in the top-level directory.
> @@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +extern PCIDevice *piix4_dev;
> +
> +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                          I2CBus **smbus, size_t ide_buses);
> +
>  #endif
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 5566 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Now that we properly refactored the piix4_create() function, let's
> move it to hw/isa/piix4.c where it belongs, so it can be reused
> on other places.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
>  hw/mips/gt64xxx_pci.c         |  1 +
>  hw/mips/mips_malta.c          | 28 ----------------------------
>  include/hw/i386/pc.h          |  2 --
>  include/hw/southbridge/piix.h |  6 ++++++
>  5 files changed, 37 insertions(+), 30 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9f554747af..d90899e122 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -27,12 +27,14 @@
>  #include "qapi/error.h"
>  #include "hw/irq.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/pci/pci.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "hw/dma/i8257.h"
>  #include "hw/timer/i8254.h"
>  #include "hw/timer/mc146818rtc.h"
> +#include "hw/ide.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/runstate.h"
> @@ -234,3 +236,31 @@ static void piix4_register_types(void)
>  }
>
>  type_init(piix4_register_types)
> +
> +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                          I2CBus **smbus, size_t ide_buses)
> +{
> +    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> +    DriveInfo **hd;
> +    PCIDevice *pci;
> +    DeviceState *dev;
> +
> +    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
> +    dev = DEVICE(pci);
> +    if (isa_bus) {
> +        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +    }
> +
> +    hd = g_new(DriveInfo *, ide_drives);
> +    ide_drive_get(hd, ide_drives);
> +    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> +    g_free(hd);
> +    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> +    if (smbus) {
> +        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> +                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> +   }
> +
> +    return dev;
> +}
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index f325bd6c1c..c277398c0d 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -28,6 +28,7 @@
>  #include "hw/mips/mips.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/southbridge/piix.h"
>  #include "migration/vmstate.h"
>  #include "hw/i386/pc.h"
>  #include "hw/irq.h"
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 0d4312840b..477a4725c0 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms,
> MaltaState *s,
>      }
>  }
>
> -static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> -                                 I2CBus **smbus, size_t ide_buses)
> -{
> -    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
> -    DriveInfo **hd;
> -    PCIDevice *pci;
> -    DeviceState *dev;
> -
> -    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, TYPE_PIIX4_PCI_DEVICE);
> -    dev = DEVICE(pci);
> -    if (isa_bus) {
> -        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> -    }
> -
> -    hd = g_new(DriveInfo *, ide_drives);
> -    ide_drive_get(hd, ide_drives);
> -    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
> -    g_free(hd);
> -    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
> -    if (smbus) {
> -        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
> -                               isa_get_irq(NULL, 9), NULL, 0, NULL);
> -   }
> -
> -    return dev;
> -}
> -
>  static
>  void mips_malta_init(MachineState *machine)
>  {
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index c671c9fd2a..b63fc7631e 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -274,8 +274,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>                      MemoryRegion *ram_memory);
>
>  PCIBus *find_i440fx(void);
> -/* piix4.c */
> -extern PCIDevice *piix4_dev;
>
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index b8ce26fec4..add352456b 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -2,6 +2,7 @@
>   * QEMU PIIX South Bridge Emulation
>   *
>   * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
>   *
>   * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
>   * See the COPYING file in the top-level directory.
> @@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +extern PCIDevice *piix4_dev;
> +
> +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> +                          I2CBus **smbus, size_t ide_buses);
> +
>  #endif
> --
> 2.21.0
>
>
>

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Re: [PATCH 12/32] piix4: rename PIIX4 object to piix4-isa

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 1 -
>  hw/mips/mips_malta.c | 2 +-
>  include/hw/isa/isa.h | 2 ++
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 1cfc51335a..c3a2bd0d70 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
>      uint8_t rcr;
>  } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
>  #define PIIX4_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
>      ide_drive_get(hd, ARRAY_SIZE(hd));
>
>      pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, "PIIX4");
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
>      dev = DEVICE(pci);
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>      piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
>      return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
>  }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
>  #endif
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 12/32] piix4: rename PIIX4 object to piix4-isa

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c       | 1 -
>  hw/mips/mips_malta.c | 2 +-
>  include/hw/isa/isa.h | 2 ++
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 1cfc51335a..c3a2bd0d70 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
>      uint8_t rcr;
>  } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
>  #define PIIX4_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
>      ide_drive_get(hd, ARRAY_SIZE(hd));
>
>      pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> -                                          true, "PIIX4");
> +                                          true, TYPE_PIIX4_PCI_DEVICE);
>      dev = DEVICE(pci);
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>      piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
>      return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
>  }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
>  #endif
> --
> 2.21.0
>
>
>

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Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Move the KVM-related call to "sysemu/kvm.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/i386/pc.h | 1 -
>  include/sysemu/kvm.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
>
>
Is there any other similar case in our code base?

A.



> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 6df4f4b6fb..09e74e7764 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>
>  extern DeviceState *isa_pic;
>  qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
> -qemu_irq *kvm_i8259_init(ISABus *bus);
>  int pic_read_irq(DeviceState *d);
>  int pic_get_output(DeviceState *d);
>
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 9d143282bc..da8aa9f5a8 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
> qemu_irq irq, int gsi);
>  void kvm_pc_gsi_handler(void *opaque, int n, int level);
>  void kvm_pc_setup_irq_routing(bool pci_enabled);
>  void kvm_init_irq_routing(KVMState *s);
> +qemu_irq *kvm_i8259_init(ISABus *bus);
>
>  /**
>   * kvm_arch_irqchip_create:
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Move the KVM-related call to "sysemu/kvm.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/i386/pc.h | 1 -
>  include/sysemu/kvm.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
>
>
Is there any other similar case in our code base?

A.



> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 6df4f4b6fb..09e74e7764 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>
>  extern DeviceState *isa_pic;
>  qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
> -qemu_irq *kvm_i8259_init(ISABus *bus);
>  int pic_read_irq(DeviceState *d);
>  int pic_get_output(DeviceState *d);
>
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 9d143282bc..da8aa9f5a8 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
> qemu_irq irq, int gsi);
>  void kvm_pc_gsi_handler(void *opaque, int n, int level);
>  void kvm_pc_setup_irq_routing(bool pci_enabled);
>  void kvm_init_irq_routing(KVMState *s);
> +qemu_irq *kvm_i8259_init(ISABus *bus);
>
>  /**
>   * kvm_arch_irqchip_create:
> --
> 2.21.0
>
>
>

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Re: [PATCH 03/32] mc146818rtc: move structure to header file

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> We are now able to embed a timer in another object.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/timer/mc146818rtc.c         | 30 ------------------------------
>  include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 33 insertions(+), 30 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
> index 6cb378751b..e40b54e743 100644
> --- a/hw/timer/mc146818rtc.c
> +++ b/hw/timer/mc146818rtc.c
> @@ -71,36 +71,6 @@
>  #define RTC_CLOCK_RATE            32768
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
>
> -#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
> -
> -typedef struct RTCState {
> -    ISADevice parent_obj;
> -
> -    MemoryRegion io;
> -    MemoryRegion coalesced_io;
> -    uint8_t cmos_data[128];
> -    uint8_t cmos_index;
> -    int32_t base_year;
> -    uint64_t base_rtc;
> -    uint64_t last_update;
> -    int64_t offset;
> -    qemu_irq irq;
> -    int it_shift;
> -    /* periodic timer */
> -    QEMUTimer *periodic_timer;
> -    int64_t next_periodic_time;
> -    /* update-ended timer */
> -    QEMUTimer *update_timer;
> -    uint64_t next_alarm_time;
> -    uint16_t irq_reinject_on_ack_count;
> -    uint32_t irq_coalesced;
> -    uint32_t period;
> -    QEMUTimer *coalesced_timer;
> -    LostTickPolicy lost_tick_policy;
> -    Notifier suspend_notifier;
> -    QLIST_ENTRY(RTCState) link;
> -} RTCState;
> -
>  static void rtc_set_time(RTCState *s);
>  static void rtc_update_time(RTCState *s);
>  static void rtc_set_cmos(RTCState *s, const struct tm *tm);
> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index fe6ed63f71..0f1c886e5b 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -1,10 +1,43 @@
>  #ifndef MC146818RTC_H
>  #define MC146818RTC_H
>
> +#include "qapi/qapi-types-misc.h"
> +#include "qemu/queue.h"
> +#include "qemu/timer.h"
>  #include "hw/isa/isa.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define TYPE_MC146818_RTC "mc146818rtc"
> +#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
> +
> +typedef struct RTCState {
> +    ISADevice parent_obj;
> +
> +    MemoryRegion io;
> +    MemoryRegion coalesced_io;
> +    uint8_t cmos_data[128];
> +    uint8_t cmos_index;
> +    int32_t base_year;
> +    uint64_t base_rtc;
> +    uint64_t last_update;
> +    int64_t offset;
> +    qemu_irq irq;
> +    int it_shift;
> +    /* periodic timer */
> +    QEMUTimer *periodic_timer;
> +    int64_t next_periodic_time;
> +    /* update-ended timer */
> +    QEMUTimer *update_timer;
> +    uint64_t next_alarm_time;
> +    uint16_t irq_reinject_on_ack_count;
> +    uint32_t irq_coalesced;
> +    uint32_t period;
> +    QEMUTimer *coalesced_timer;
> +    Notifier clock_reset_notifier;
> +    LostTickPolicy lost_tick_policy;
> +    Notifier suspend_notifier;
> +    QLIST_ENTRY(RTCState) link;
> +} RTCState;
>
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 03/32] mc146818rtc: move structure to header file

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> We are now able to embed a timer in another object.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/timer/mc146818rtc.c         | 30 ------------------------------
>  include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 33 insertions(+), 30 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
> index 6cb378751b..e40b54e743 100644
> --- a/hw/timer/mc146818rtc.c
> +++ b/hw/timer/mc146818rtc.c
> @@ -71,36 +71,6 @@
>  #define RTC_CLOCK_RATE            32768
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
>
> -#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
> -
> -typedef struct RTCState {
> -    ISADevice parent_obj;
> -
> -    MemoryRegion io;
> -    MemoryRegion coalesced_io;
> -    uint8_t cmos_data[128];
> -    uint8_t cmos_index;
> -    int32_t base_year;
> -    uint64_t base_rtc;
> -    uint64_t last_update;
> -    int64_t offset;
> -    qemu_irq irq;
> -    int it_shift;
> -    /* periodic timer */
> -    QEMUTimer *periodic_timer;
> -    int64_t next_periodic_time;
> -    /* update-ended timer */
> -    QEMUTimer *update_timer;
> -    uint64_t next_alarm_time;
> -    uint16_t irq_reinject_on_ack_count;
> -    uint32_t irq_coalesced;
> -    uint32_t period;
> -    QEMUTimer *coalesced_timer;
> -    LostTickPolicy lost_tick_policy;
> -    Notifier suspend_notifier;
> -    QLIST_ENTRY(RTCState) link;
> -} RTCState;
> -
>  static void rtc_set_time(RTCState *s);
>  static void rtc_update_time(RTCState *s);
>  static void rtc_set_cmos(RTCState *s, const struct tm *tm);
> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index fe6ed63f71..0f1c886e5b 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -1,10 +1,43 @@
>  #ifndef MC146818RTC_H
>  #define MC146818RTC_H
>
> +#include "qapi/qapi-types-misc.h"
> +#include "qemu/queue.h"
> +#include "qemu/timer.h"
>  #include "hw/isa/isa.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define TYPE_MC146818_RTC "mc146818rtc"
> +#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
> +
> +typedef struct RTCState {
> +    ISADevice parent_obj;
> +
> +    MemoryRegion io;
> +    MemoryRegion coalesced_io;
> +    uint8_t cmos_data[128];
> +    uint8_t cmos_index;
> +    int32_t base_year;
> +    uint64_t base_rtc;
> +    uint64_t last_update;
> +    int64_t offset;
> +    qemu_irq irq;
> +    int it_shift;
> +    /* periodic timer */
> +    QEMUTimer *periodic_timer;
> +    int64_t next_periodic_time;
> +    /* update-ended timer */
> +    QEMUTimer *update_timer;
> +    uint64_t next_alarm_time;
> +    uint16_t irq_reinject_on_ack_count;
> +    uint32_t irq_coalesced;
> +    uint32_t period;
> +    QEMUTimer *coalesced_timer;
> +    Notifier clock_reset_notifier;
> +    LostTickPolicy lost_tick_policy;
> +    Notifier suspend_notifier;
> +    QLIST_ENTRY(RTCState) link;
> +} RTCState;
>
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
> --
> 2.21.0
>
>
>

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Re: [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The ISA default number for the RTC devices is not related to its
> registers neither. Move this definition to "hw/timer/mc146818rtc.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/timer/mc146818rtc.h      | 2 ++
>  include/hw/timer/mc146818rtc_regs.h | 2 --
>  tests/rtc-test.c                    | 1 +
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Philippe, do this and related patches clash with your recent reorganization
of timers/rtcs?

A.



> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index 0f1c886e5b..17761cf6d9 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -39,6 +39,8 @@ typedef struct RTCState {
>      QLIST_ENTRY(RTCState) link;
>  } RTCState;
>
> +#define RTC_ISA_IRQ 8
> +
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
>  void rtc_set_memory(ISADevice *dev, int addr, int val);
> diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/
> mc146818rtc_regs.h
> index bfbb57e570..631f71cfd9 100644
> --- a/include/hw/timer/mc146818rtc_regs.h
> +++ b/include/hw/timer/mc146818rtc_regs.h
> @@ -27,8 +27,6 @@
>
>  #include "qemu/timer.h"
>
> -#define RTC_ISA_IRQ 8
> -
>  #define RTC_SECONDS             0
>  #define RTC_SECONDS_ALARM       1
>  #define RTC_MINUTES             2
> diff --git a/tests/rtc-test.c b/tests/rtc-test.c
> index 6309b0ef6c..18f895690f 100644
> --- a/tests/rtc-test.c
> +++ b/tests/rtc-test.c
> @@ -15,6 +15,7 @@
>
>  #include "libqtest-single.h"
>  #include "qemu/timer.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The ISA default number for the RTC devices is not related to its
> registers neither. Move this definition to "hw/timer/mc146818rtc.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/timer/mc146818rtc.h      | 2 ++
>  include/hw/timer/mc146818rtc_regs.h | 2 --
>  tests/rtc-test.c                    | 1 +
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Philippe, do this and related patches clash with your recent reorganization
of timers/rtcs?

A.



> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index 0f1c886e5b..17761cf6d9 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -39,6 +39,8 @@ typedef struct RTCState {
>      QLIST_ENTRY(RTCState) link;
>  } RTCState;
>
> +#define RTC_ISA_IRQ 8
> +
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
>  void rtc_set_memory(ISADevice *dev, int addr, int val);
> diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/
> mc146818rtc_regs.h
> index bfbb57e570..631f71cfd9 100644
> --- a/include/hw/timer/mc146818rtc_regs.h
> +++ b/include/hw/timer/mc146818rtc_regs.h
> @@ -27,8 +27,6 @@
>
>  #include "qemu/timer.h"
>
> -#define RTC_ISA_IRQ 8
> -
>  #define RTC_SECONDS             0
>  #define RTC_SECONDS_ALARM       1
>  #define RTC_MINUTES             2
> diff --git a/tests/rtc-test.c b/tests/rtc-test.c
> index 6309b0ef6c..18f895690f 100644
> --- a/tests/rtc-test.c
> +++ b/tests/rtc-test.c
> @@ -15,6 +15,7 @@
>
>  #include "libqtest-single.h"
>  #include "qemu/timer.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
> --
> 2.21.0
>
>
>

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Re: [PATCH 08/32] piix4: rename some variables in realize function

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>
> -    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> -                     pci_address_space_io(dev), errp)) {
> +    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> +                     pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> -    piix4_dev = &d->dev;
> -    qemu_register_reset(piix4_reset, d);
> +    piix4_dev = pci_dev;
> +    qemu_register_reset(piix4_reset, s);
>  }
>
>  int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 08/32] piix4: rename some variables in realize function

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1706 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>
> -    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> -                     pci_address_space_io(dev), errp)) {
> +    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> +                     pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> -    piix4_dev = &d->dev;
> -    qemu_register_reset(piix4_reset, d);
> +    piix4_dev = pci_dev;
> +    qemu_register_reset(piix4_reset, s);
>  }
>
>  int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>

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Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> Move the KVM-related call to "sysemu/kvm.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/i386/pc.h | 1 -
>  include/sysemu/kvm.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 6df4f4b6fb..09e74e7764 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>  
>  extern DeviceState *isa_pic;
>  qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
> -qemu_irq *kvm_i8259_init(ISABus *bus);
>  int pic_read_irq(DeviceState *d);
>  int pic_get_output(DeviceState *d);
>  
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 9d143282bc..da8aa9f5a8 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>  void kvm_pc_gsi_handler(void *opaque, int n, int level);
>  void kvm_pc_setup_irq_routing(bool pci_enabled);
>  void kvm_init_irq_routing(KVMState *s);
> +qemu_irq *kvm_i8259_init(ISABus *bus);

Why? The function is defined in hw/i386/kvm/ - so moving its prototype
to a generic header sounds wrong to me.

 Thomas

Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> Move the KVM-related call to "sysemu/kvm.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/i386/pc.h | 1 -
>  include/sysemu/kvm.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 6df4f4b6fb..09e74e7764 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>  
>  extern DeviceState *isa_pic;
>  qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
> -qemu_irq *kvm_i8259_init(ISABus *bus);
>  int pic_read_irq(DeviceState *d);
>  int pic_get_output(DeviceState *d);
>  
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 9d143282bc..da8aa9f5a8 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>  void kvm_pc_gsi_handler(void *opaque, int n, int level);
>  void kvm_pc_setup_irq_routing(bool pci_enabled);
>  void kvm_init_irq_routing(KVMState *s);
> +qemu_irq *kvm_i8259_init(ISABus *bus);

Why? The function is defined in hw/i386/kvm/ - so moving its prototype
to a generic header sounds wrong to me.

 Thomas

Re: [Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> Move the KVM-related call to "sysemu/kvm.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/i386/pc.h | 1 -
>  include/sysemu/kvm.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 6df4f4b6fb..09e74e7764 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>  
>  extern DeviceState *isa_pic;
>  qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
> -qemu_irq *kvm_i8259_init(ISABus *bus);
>  int pic_read_irq(DeviceState *d);
>  int pic_get_output(DeviceState *d);
>  
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 9d143282bc..da8aa9f5a8 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>  void kvm_pc_gsi_handler(void *opaque, int n, int level);
>  void kvm_pc_setup_irq_routing(bool pci_enabled);
>  void kvm_init_irq_routing(KVMState *s);
> +qemu_irq *kvm_i8259_init(ISABus *bus);

Why? The function is defined in hw/i386/kvm/ - so moving its prototype
to a generic header sounds wrong to me.

 Thomas

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Re: [PATCH 08/32] piix4: rename some variables in realize function

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1708 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>
> -    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> -                     pci_address_space_io(dev), errp)) {
> +    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> +                     pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> -    piix4_dev = &d->dev;
> -    qemu_register_reset(piix4_reset, d);
> +    piix4_dev = pci_dev;
> +    qemu_register_reset(piix4_reset, s);
>  }
>
>  int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 08/32] piix4: rename some variables in realize function

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1708 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);
>
> -    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> -                     pci_address_space_io(dev), errp)) {
> +    if (!isa_bus_new(dev, pci_address_space(pci_dev),
> +                     pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> -    piix4_dev = &d->dev;
> -    qemu_register_reset(piix4_reset, d);
> +    piix4_dev = pci_dev;
> +    qemu_register_reset(piix4_reset, s);
>  }
>
>  int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>

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Re: [PATCH 09/32] piix4: add Reset Control Register

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 3130 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 4202243e41..6e2d9b9774 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
>   * QEMU PIIX4 PCI Bridge Emulation
>   *
>   * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
>   *
>   * Permission is hereby granted, free of charge, to any person obtaining
> a copy
>   * of this software and associated documentation files (the "Software"),
> to deal
> @@ -29,11 +30,16 @@
>  #include "hw/sysbus.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
>  PCIDevice *piix4_dev;
>
>  typedef struct PIIX4State {
>      PCIDevice dev;
> +
> +    /* Reset Control Register */
> +    MemoryRegion rcr_mem;
> +    uint8_t rcr;
>  } PIIX4State;
>
>  #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> +                            unsigned int len)
> +{
> +    PIIX4State *s = opaque;
> +
> +    if (val & 4) {
> +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +        return;
> +    }
> +    s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int
> len)
> +{
> +    PIIX4State *s = opaque;
> +    return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> +    .read = piix4_rcr_read,
> +    .write = piix4_rcr_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .impl = {
> +        .min_access_size = 1,
> +        .max_access_size = 1,
> +    },
> +};
> +
>  static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
>      DeviceState *dev = DEVICE(pci_dev);
> @@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>                       pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> +
> +    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> +                          "reset-control", 1);
> +    memory_region_add_subregion_overlap(pci_address_space_io(pci_dev),
> 0xcf9,
> +                                        &s->rcr_mem, 1);
> +
>      piix4_dev = pci_dev;
>      qemu_register_reset(piix4_reset, s);
>  }
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 09/32] piix4: add Reset Control Register

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 4202243e41..6e2d9b9774 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
>   * QEMU PIIX4 PCI Bridge Emulation
>   *
>   * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
>   *
>   * Permission is hereby granted, free of charge, to any person obtaining
> a copy
>   * of this software and associated documentation files (the "Software"),
> to deal
> @@ -29,11 +30,16 @@
>  #include "hw/sysbus.h"
>  #include "migration/vmstate.h"
>  #include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
>  PCIDevice *piix4_dev;
>
>  typedef struct PIIX4State {
>      PCIDevice dev;
> +
> +    /* Reset Control Register */
> +    MemoryRegion rcr_mem;
> +    uint8_t rcr;
>  } PIIX4State;
>
>  #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> +                            unsigned int len)
> +{
> +    PIIX4State *s = opaque;
> +
> +    if (val & 4) {
> +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +        return;
> +    }
> +    s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int
> len)
> +{
> +    PIIX4State *s = opaque;
> +    return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> +    .read = piix4_rcr_read,
> +    .write = piix4_rcr_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .impl = {
> +        .min_access_size = 1,
> +        .max_access_size = 1,
> +    },
> +};
> +
>  static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
>      DeviceState *dev = DEVICE(pci_dev);
> @@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>                       pci_address_space_io(pci_dev), errp)) {
>          return;
>      }
> +
> +    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> +                          "reset-control", 1);
> +    memory_region_add_subregion_overlap(pci_address_space_io(pci_dev),
> 0xcf9,
> +                                        &s->rcr_mem, 1);
> +
>      piix4_dev = pci_dev;
>      qemu_register_reset(piix4_reset, s);
>  }
> --
> 2.21.0
>
>
>

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Re: [PATCH 13/32] piix4: convert reset function to QOM

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20180106153730.30313-15-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index c3a2bd0d70..8998b0ca47 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -48,10 +48,10 @@ typedef struct PIIX4State {
>  #define PIIX4_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> -static void piix4_reset(void *opaque)
> +static void piix4_reset(DeviceState *dev)
>  {
> -    PIIX4State *d = opaque;
> -    uint8_t *pci_conf = d->dev.config;
> +    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> +    uint8_t *pci_conf = s->dev.config;
>
>      pci_conf[0x04] = 0x07; // master, memory and I/O
>      pci_conf[0x05] = 0x00;
> @@ -165,7 +165,6 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      isa_bus_irqs(isa_bus, s->isa);
>
>      piix4_dev = pci_dev;
> -    qemu_register_reset(piix4_reset, s);
>  }
>
>  static void piix4_class_init(ObjectClass *klass, void *data)
> @@ -177,6 +176,7 @@ static void piix4_class_init(ObjectClass *klass, void
> *data)
>      k->vendor_id = PCI_VENDOR_ID_INTEL;
>      k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
>      k->class_id = PCI_CLASS_BRIDGE_ISA;
> +    dc->reset = piix4_reset;
>      dc->desc = "ISA bridge";
>      dc->vmsd = &vmstate_piix4;
>      /*
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 13/32] piix4: convert reset function to QOM

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20180106153730.30313-15-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index c3a2bd0d70..8998b0ca47 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -48,10 +48,10 @@ typedef struct PIIX4State {
>  #define PIIX4_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> -static void piix4_reset(void *opaque)
> +static void piix4_reset(DeviceState *dev)
>  {
> -    PIIX4State *d = opaque;
> -    uint8_t *pci_conf = d->dev.config;
> +    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> +    uint8_t *pci_conf = s->dev.config;
>
>      pci_conf[0x04] = 0x07; // master, memory and I/O
>      pci_conf[0x05] = 0x00;
> @@ -165,7 +165,6 @@ static void piix4_realize(PCIDevice *pci_dev, Error
> **errp)
>      isa_bus_irqs(isa_bus, s->isa);
>
>      piix4_dev = pci_dev;
> -    qemu_register_reset(piix4_reset, s);
>  }
>
>  static void piix4_class_init(ObjectClass *klass, void *data)
> @@ -177,6 +176,7 @@ static void piix4_class_init(ObjectClass *klass, void
> *data)
>      k->vendor_id = PCI_VENDOR_ID_INTEL;
>      k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
>      k->class_id = PCI_CLASS_BRIDGE_ISA;
> +    dc->reset = piix4_reset;
>      dc->desc = "ISA bridge";
>      dc->vmsd = &vmstate_piix4;
>      /*
> --
> 2.21.0
>
>
>

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Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 4:57 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     Move the KVM-related call to "sysemu/kvm.h".

Maybe s/call/function declaration/

> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/i386/pc.h | 1 -
>       include/sysemu/kvm.h | 1 +
>       2 files changed, 1 insertion(+), 1 deletion(-)
> 
> 
> Is there any other similar case in our code base?

These look appropriate:

include/hw/ppc/openpic_kvm.h:5:int kvm_openpic_connect_vcpu(DeviceState 
*d, CPUState *cs);
include/hw/timer/i8254.h:67:static inline ISADevice *kvm_pit_init(ISABus 
*bus, int base)
hw/intc/vgic_common.h:25: * kvm_arm_gic_set_irq - Send an IRQ to the 
in-kernel vGIC
hw/intc/vgic_common.h:33:void kvm_arm_gic_set_irq(uint32_t num_irq, int 
irq, int level);

although kvm_pit_init() is probably borderline.

> 
> A.
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 6df4f4b6fb..09e74e7764 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
> 
>       extern DeviceState *isa_pic;
>       qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>     -qemu_irq *kvm_i8259_init(ISABus *bus);
>       int pic_read_irq(DeviceState *d);
>       int pic_get_output(DeviceState *d);
> 
>     diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>     index 9d143282bc..da8aa9f5a8 100644
>     --- a/include/sysemu/kvm.h
>     +++ b/include/sysemu/kvm.h
>     @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>     qemu_irq irq, int gsi);
>       void kvm_pc_gsi_handler(void *opaque, int n, int level);
>       void kvm_pc_setup_irq_routing(bool pci_enabled);
>       void kvm_init_irq_routing(KVMState *s);
>     +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
>       /**
>        * kvm_arch_irqchip_create:
>     -- 
>     2.21.0
> 
> 

Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 4:57 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     Move the KVM-related call to "sysemu/kvm.h".

Maybe s/call/function declaration/

> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/i386/pc.h | 1 -
>       include/sysemu/kvm.h | 1 +
>       2 files changed, 1 insertion(+), 1 deletion(-)
> 
> 
> Is there any other similar case in our code base?

These look appropriate:

include/hw/ppc/openpic_kvm.h:5:int kvm_openpic_connect_vcpu(DeviceState 
*d, CPUState *cs);
include/hw/timer/i8254.h:67:static inline ISADevice *kvm_pit_init(ISABus 
*bus, int base)
hw/intc/vgic_common.h:25: * kvm_arm_gic_set_irq - Send an IRQ to the 
in-kernel vGIC
hw/intc/vgic_common.h:33:void kvm_arm_gic_set_irq(uint32_t num_irq, int 
irq, int level);

although kvm_pit_init() is probably borderline.

> 
> A.
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 6df4f4b6fb..09e74e7764 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
> 
>       extern DeviceState *isa_pic;
>       qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>     -qemu_irq *kvm_i8259_init(ISABus *bus);
>       int pic_read_irq(DeviceState *d);
>       int pic_get_output(DeviceState *d);
> 
>     diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>     index 9d143282bc..da8aa9f5a8 100644
>     --- a/include/sysemu/kvm.h
>     +++ b/include/sysemu/kvm.h
>     @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>     qemu_irq irq, int gsi);
>       void kvm_pc_gsi_handler(void *opaque, int n, int level);
>       void kvm_pc_setup_irq_routing(bool pci_enabled);
>       void kvm_init_irq_routing(KVMState *s);
>     +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
>       /**
>        * kvm_arch_irqchip_create:
>     -- 
>     2.21.0
> 
> 

Re: [Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 4:57 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     Move the KVM-related call to "sysemu/kvm.h".

Maybe s/call/function declaration/

> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/i386/pc.h | 1 -
>       include/sysemu/kvm.h | 1 +
>       2 files changed, 1 insertion(+), 1 deletion(-)
> 
> 
> Is there any other similar case in our code base?

These look appropriate:

include/hw/ppc/openpic_kvm.h:5:int kvm_openpic_connect_vcpu(DeviceState 
*d, CPUState *cs);
include/hw/timer/i8254.h:67:static inline ISADevice *kvm_pit_init(ISABus 
*bus, int base)
hw/intc/vgic_common.h:25: * kvm_arm_gic_set_irq - Send an IRQ to the 
in-kernel vGIC
hw/intc/vgic_common.h:33:void kvm_arm_gic_set_irq(uint32_t num_irq, int 
irq, int level);

although kvm_pit_init() is probably borderline.

> 
> A.
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 6df4f4b6fb..09e74e7764 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
> 
>       extern DeviceState *isa_pic;
>       qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>     -qemu_irq *kvm_i8259_init(ISABus *bus);
>       int pic_read_irq(DeviceState *d);
>       int pic_get_output(DeviceState *d);
> 
>     diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>     index 9d143282bc..da8aa9f5a8 100644
>     --- a/include/sysemu/kvm.h
>     +++ b/include/sysemu/kvm.h
>     @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>     qemu_irq irq, int gsi);
>       void kvm_pc_gsi_handler(void *opaque, int n, int level);
>       void kvm_pc_setup_irq_routing(bool pci_enabled);
>       void kvm_init_irq_routing(KVMState *s);
>     +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
>       /**
>        * kvm_arch_irqchip_create:
>     -- 
>     2.21.0
> 
> 

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Re: [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

On 10/17/19 5:02 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The ISA default number for the RTC devices is not related to its
>     registers neither. Move this definition to "hw/timer/mc146818rtc.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/timer/mc146818rtc.h      | 2 ++
>       include/hw/timer/mc146818rtc_regs.h | 2 --
>       tests/rtc-test.c                    | 1 +
>       3 files changed, 3 insertions(+), 2 deletions(-)
> 
> 
> Philippe, do this and related patches clash with your recent 
> reorganization of timers/rtcs?

Indeed, but since big boring series take time to get merged, I prefer to 
have it reviewed already, then I'll rebase and fix conflicts on the one 
that isn't merged.

Thanks for reviewing the other patches!

> A.
> 
>     diff --git a/include/hw/timer/mc146818rtc.h
>     b/include/hw/timer/mc146818rtc.h
>     index 0f1c886e5b..17761cf6d9 100644
>     --- a/include/hw/timer/mc146818rtc.h
>     +++ b/include/hw/timer/mc146818rtc.h
>     @@ -39,6 +39,8 @@ typedef struct RTCState {
>           QLIST_ENTRY(RTCState) link;
>       } RTCState;
> 
>     +#define RTC_ISA_IRQ 8
>     +
>       ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                                    qemu_irq intercept_irq);
>       void rtc_set_memory(ISADevice *dev, int addr, int val);
>     diff --git a/include/hw/timer/mc146818rtc_regs.h
>     b/include/hw/timer/mc146818rtc_regs.h
>     index bfbb57e570..631f71cfd9 100644
>     --- a/include/hw/timer/mc146818rtc_regs.h
>     +++ b/include/hw/timer/mc146818rtc_regs.h
>     @@ -27,8 +27,6 @@
> 
>       #include "qemu/timer.h"
> 
>     -#define RTC_ISA_IRQ 8
>     -
>       #define RTC_SECONDS             0
>       #define RTC_SECONDS_ALARM       1
>       #define RTC_MINUTES             2
>     diff --git a/tests/rtc-test.c b/tests/rtc-test.c
>     index 6309b0ef6c..18f895690f 100644
>     --- a/tests/rtc-test.c
>     +++ b/tests/rtc-test.c
>     @@ -15,6 +15,7 @@
> 
>       #include "libqtest-single.h"
>       #include "qemu/timer.h"
>     +#include "hw/timer/mc146818rtc.h"
>       #include "hw/timer/mc146818rtc_regs.h"
> 
>       #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
>     -- 
>     2.21.0
> 
> 

Re: [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

On 10/17/19 5:02 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The ISA default number for the RTC devices is not related to its
>     registers neither. Move this definition to "hw/timer/mc146818rtc.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/timer/mc146818rtc.h      | 2 ++
>       include/hw/timer/mc146818rtc_regs.h | 2 --
>       tests/rtc-test.c                    | 1 +
>       3 files changed, 3 insertions(+), 2 deletions(-)
> 
> 
> Philippe, do this and related patches clash with your recent 
> reorganization of timers/rtcs?

Indeed, but since big boring series take time to get merged, I prefer to 
have it reviewed already, then I'll rebase and fix conflicts on the one 
that isn't merged.

Thanks for reviewing the other patches!

> A.
> 
>     diff --git a/include/hw/timer/mc146818rtc.h
>     b/include/hw/timer/mc146818rtc.h
>     index 0f1c886e5b..17761cf6d9 100644
>     --- a/include/hw/timer/mc146818rtc.h
>     +++ b/include/hw/timer/mc146818rtc.h
>     @@ -39,6 +39,8 @@ typedef struct RTCState {
>           QLIST_ENTRY(RTCState) link;
>       } RTCState;
> 
>     +#define RTC_ISA_IRQ 8
>     +
>       ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                                    qemu_irq intercept_irq);
>       void rtc_set_memory(ISADevice *dev, int addr, int val);
>     diff --git a/include/hw/timer/mc146818rtc_regs.h
>     b/include/hw/timer/mc146818rtc_regs.h
>     index bfbb57e570..631f71cfd9 100644
>     --- a/include/hw/timer/mc146818rtc_regs.h
>     +++ b/include/hw/timer/mc146818rtc_regs.h
>     @@ -27,8 +27,6 @@
> 
>       #include "qemu/timer.h"
> 
>     -#define RTC_ISA_IRQ 8
>     -
>       #define RTC_SECONDS             0
>       #define RTC_SECONDS_ALARM       1
>       #define RTC_MINUTES             2
>     diff --git a/tests/rtc-test.c b/tests/rtc-test.c
>     index 6309b0ef6c..18f895690f 100644
>     --- a/tests/rtc-test.c
>     +++ b/tests/rtc-test.c
>     @@ -15,6 +15,7 @@
> 
>       #include "libqtest-single.h"
>       #include "qemu/timer.h"
>     +#include "hw/timer/mc146818rtc.h"
>       #include "hw/timer/mc146818rtc_regs.h"
> 
>       #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
>     -- 
>     2.21.0
> 
> 

Re: [Xen-devel] [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Philippe Mathieu-Daudé]

On 10/17/19 5:02 PM, Aleksandar Markovic wrote:
> 
> 
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The ISA default number for the RTC devices is not related to its
>     registers neither. Move this definition to "hw/timer/mc146818rtc.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       include/hw/timer/mc146818rtc.h      | 2 ++
>       include/hw/timer/mc146818rtc_regs.h | 2 --
>       tests/rtc-test.c                    | 1 +
>       3 files changed, 3 insertions(+), 2 deletions(-)
> 
> 
> Philippe, do this and related patches clash with your recent 
> reorganization of timers/rtcs?

Indeed, but since big boring series take time to get merged, I prefer to 
have it reviewed already, then I'll rebase and fix conflicts on the one 
that isn't merged.

Thanks for reviewing the other patches!

> A.
> 
>     diff --git a/include/hw/timer/mc146818rtc.h
>     b/include/hw/timer/mc146818rtc.h
>     index 0f1c886e5b..17761cf6d9 100644
>     --- a/include/hw/timer/mc146818rtc.h
>     +++ b/include/hw/timer/mc146818rtc.h
>     @@ -39,6 +39,8 @@ typedef struct RTCState {
>           QLIST_ENTRY(RTCState) link;
>       } RTCState;
> 
>     +#define RTC_ISA_IRQ 8
>     +
>       ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                                    qemu_irq intercept_irq);
>       void rtc_set_memory(ISADevice *dev, int addr, int val);
>     diff --git a/include/hw/timer/mc146818rtc_regs.h
>     b/include/hw/timer/mc146818rtc_regs.h
>     index bfbb57e570..631f71cfd9 100644
>     --- a/include/hw/timer/mc146818rtc_regs.h
>     +++ b/include/hw/timer/mc146818rtc_regs.h
>     @@ -27,8 +27,6 @@
> 
>       #include "qemu/timer.h"
> 
>     -#define RTC_ISA_IRQ 8
>     -
>       #define RTC_SECONDS             0
>       #define RTC_SECONDS_ALARM       1
>       #define RTC_MINUTES             2
>     diff --git a/tests/rtc-test.c b/tests/rtc-test.c
>     index 6309b0ef6c..18f895690f 100644
>     --- a/tests/rtc-test.c
>     +++ b/tests/rtc-test.c
>     @@ -15,6 +15,7 @@
> 
>       #include "libqtest-single.h"
>       #include "qemu/timer.h"
>     +#include "hw/timer/mc146818rtc.h"
>       #include "hw/timer/mc146818rtc_regs.h"
> 
>       #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
>     -- 
>     2.21.0
> 
> 

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Re: [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 3434 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The GSI creation code is common to all PC machines, extract the
> common code.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 15 +++++++++++++++
>  hw/i386/pc_piix.c    |  9 +--------
>  hw/i386/pc_q35.c     |  9 +--------
>  include/hw/i386/pc.h |  2 ++
>  4 files changed, 19 insertions(+), 16 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index bcda50efcc..a7597c6c44 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -357,6 +357,21 @@ void gsi_handler(void *opaque, int n, int level)
>      qemu_set_irq(s->ioapic_irq[n], level);
>  }
>
> +GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
> +{
> +    GSIState *s;
> +
> +    s = g_new0(GSIState, 1);
> +    if (kvm_ioapic_in_kernel()) {
> +        kvm_pc_setup_irq_routing(pci_enabled);
> +        *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
> +    } else {
> +        *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
> +    }
> +
> +    return s;
> +}
> +
>  static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
>                             unsigned size)
>  {
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 431965d921..452b107e1b 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -188,14 +188,7 @@ static void pc_init1(MachineState *machine,
>          xen_load_linux(pcms);
>      }
>
> -    gsi_state = g_malloc0(sizeof(*gsi_state));
> -    if (kvm_ioapic_in_kernel()) {
> -        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
> -        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
> -                                       GSI_NUM_PINS);
> -    } else {
> -        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
> GSI_NUM_PINS);
> -    }
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
>
>      if (pcmc->pci_enabled) {
>          pci_bus = i440fx_init(host_type,
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 8fad20f314..52261962b8 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -210,14 +210,7 @@ static void pc_q35_init(MachineState *machine)
>      }
>
>      /* irq lines */
> -    gsi_state = g_malloc0(sizeof(*gsi_state));
> -    if (kvm_ioapic_in_kernel()) {
> -        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
> -        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
> -                                       GSI_NUM_PINS);
> -    } else {
> -        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
> GSI_NUM_PINS);
> -    }
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
>
>      /* create pci host bus */
>      q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index b63fc7631e..d0c6b9d469 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -174,6 +174,8 @@ typedef struct GSIState {
>
>  void gsi_handler(void *opaque, int n, int level);
>
> +GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
> +
>  /* vmport.c */
>  #define TYPE_VMPORT "vmport"
>  typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 3434 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The GSI creation code is common to all PC machines, extract the
> common code.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 15 +++++++++++++++
>  hw/i386/pc_piix.c    |  9 +--------
>  hw/i386/pc_q35.c     |  9 +--------
>  include/hw/i386/pc.h |  2 ++
>  4 files changed, 19 insertions(+), 16 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index bcda50efcc..a7597c6c44 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -357,6 +357,21 @@ void gsi_handler(void *opaque, int n, int level)
>      qemu_set_irq(s->ioapic_irq[n], level);
>  }
>
> +GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
> +{
> +    GSIState *s;
> +
> +    s = g_new0(GSIState, 1);
> +    if (kvm_ioapic_in_kernel()) {
> +        kvm_pc_setup_irq_routing(pci_enabled);
> +        *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
> +    } else {
> +        *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
> +    }
> +
> +    return s;
> +}
> +
>  static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
>                             unsigned size)
>  {
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 431965d921..452b107e1b 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -188,14 +188,7 @@ static void pc_init1(MachineState *machine,
>          xen_load_linux(pcms);
>      }
>
> -    gsi_state = g_malloc0(sizeof(*gsi_state));
> -    if (kvm_ioapic_in_kernel()) {
> -        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
> -        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
> -                                       GSI_NUM_PINS);
> -    } else {
> -        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
> GSI_NUM_PINS);
> -    }
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
>
>      if (pcmc->pci_enabled) {
>          pci_bus = i440fx_init(host_type,
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 8fad20f314..52261962b8 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -210,14 +210,7 @@ static void pc_q35_init(MachineState *machine)
>      }
>
>      /* irq lines */
> -    gsi_state = g_malloc0(sizeof(*gsi_state));
> -    if (kvm_ioapic_in_kernel()) {
> -        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
> -        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
> -                                       GSI_NUM_PINS);
> -    } else {
> -        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
> GSI_NUM_PINS);
> -    }
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
>
>      /* create pci host bus */
>      q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index b63fc7631e..d0c6b9d469 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -174,6 +174,8 @@ typedef struct GSIState {
>
>  void gsi_handler(void *opaque, int n, int level);
>
> +GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
> +
>  /* vmport.c */
>  #define TYPE_VMPORT "vmport"
>  typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
> --
> 2.21.0
>
>
>

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Re: [PATCH 08/32] piix4: rename some variables in realize function

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Hervé Poussineau <hpoussin@reactos.org>
> 
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'

Why? Just for the sake of it?

> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>  
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);

AFAIK we rather want to get rid of DO_UPCAST in the long run, so please
don't introduce new ones!

See:
https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg05244.html

Unless there is a real need for the rename, I'd suggest to rather drop
this patch.

 Thomas

Re: [PATCH 08/32] piix4: rename some variables in realize function

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Hervé Poussineau <hpoussin@reactos.org>
> 
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'

Why? Just for the sake of it?

> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>  
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);

AFAIK we rather want to get rid of DO_UPCAST in the long run, so please
don't introduce new ones!

See:
https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg05244.html

Unless there is a real need for the rename, I'd suggest to rather drop
this patch.

 Thomas

Re: [Xen-devel] [PATCH 08/32] piix4: rename some variables in realize function

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Hervé Poussineau <hpoussin@reactos.org>
> 
> PIIX4 structure is now 's'
> PCI device is now 'pci_dev'
> DeviceState is now 'dev'

Why? Just for the sake of it?

> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-6-hpoussin@reactos.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/isa/piix4.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 3294056cd5..4202243e41 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -88,16 +88,17 @@ static const VMStateDescription vmstate_piix4 = {
>      }
>  };
>  
> -static void piix4_realize(PCIDevice *dev, Error **errp)
> +static void piix4_realize(PCIDevice *pci_dev, Error **errp)
>  {
> -    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> +    DeviceState *dev = DEVICE(pci_dev);
> +    PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);

AFAIK we rather want to get rid of DO_UPCAST in the long run, so please
don't introduce new ones!

See:
https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg05244.html

Unless there is a real need for the rename, I'd suggest to rather drop
this patch.

 Thomas

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Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1367 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> pc_gsi_create() is the single function that uses gsi_handler.
> Make it a static variable.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 2 +-
>  include/hw/i386/pc.h | 2 --
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a7597c6c44..59de0c8a1f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>  };
>  const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>
> -void gsi_handler(void *opaque, int n, int level)
> +static void gsi_handler(void *opaque, int n, int level)
>  {
>      GSIState *s = opaque;
>
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index d0c6b9d469..75b44e156c 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -172,8 +172,6 @@ typedef struct GSIState {
>      qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>  } GSIState;
>
> -void gsi_handler(void *opaque, int n, int level);
> -
>  GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>
>
Philippe, this 2-line deletion seems not to belong to this patch. If true,
please place it in another or a separate patch.

A.



>  /* vmport.c */
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> pc_gsi_create() is the single function that uses gsi_handler.
> Make it a static variable.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 2 +-
>  include/hw/i386/pc.h | 2 --
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a7597c6c44..59de0c8a1f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>  };
>  const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>
> -void gsi_handler(void *opaque, int n, int level)
> +static void gsi_handler(void *opaque, int n, int level)
>  {
>      GSIState *s = opaque;
>
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index d0c6b9d469..75b44e156c 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -172,8 +172,6 @@ typedef struct GSIState {
>      qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>  } GSIState;
>
> -void gsi_handler(void *opaque, int n, int level);
> -
>  GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>
>
Philippe, this 2-line deletion seems not to belong to this patch. If true,
please place it in another or a separate patch.

A.



>  /* vmport.c */
> --
> 2.21.0
>
>
>

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Re: [PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> This function isn't used anymore.
> 
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/core/irq.c    | 14 --------------
>  include/hw/irq.h |  5 -----
>  2 files changed, 19 deletions(-)
>
Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> This function isn't used anymore.
> 
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/core/irq.c    | 14 --------------
>  include/hw/irq.h |  5 -----
>  2 files changed, 19 deletions(-)
>
Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Xen-devel] [PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()"

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> This function isn't used anymore.
> 
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/core/irq.c    | 14 --------------
>  include/hw/irq.h |  5 -----
>  2 files changed, 19 deletions(-)
>
Reviewed-by: Thomas Huth <thuth@redhat.com>

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Re: [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> 
> Remove i8257 instanciated in malta board, to not have it twice.

s/instanciated/instantiated/

 Thomas

Re: [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> 
> Remove i8257 instanciated in malta board, to not have it twice.

s/instanciated/instantiated/

 Thomas

Re: [Xen-devel] [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> 
> Remove i8257 instanciated in malta board, to not have it twice.

s/instanciated/instantiated/

 Thomas

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Re: [PATCH 22/32] hw/i386/pc: Move gsi_state creation code

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The block code related to IRQ start few lines later. Move


block code -> code block
start -> starts

the comment and the pc_gsi_create() call

where we start


call -> invocation


> to use the IRQs.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc_q35.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 52261962b8..6d096eff28 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -209,9 +209,6 @@ static void pc_q35_init(MachineState *machine)
>                         rom_memory, &ram_memory);
>      }
>
> -    /* irq lines */
> -    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
> -
>      /* create pci host bus */
>      q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
>
> @@ -245,6 +242,9 @@ static void pc_q35_init(MachineState *machine)
>      object_property_set_link(OBJECT(machine), OBJECT(lpc),
>                               PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
>
> +    /* irq lines */
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
> +
>      ich9_lpc = ICH9_LPC_DEVICE(lpc);
>      lpc_dev = DEVICE(lpc);
>      for (i = 0; i < GSI_NUM_PINS; i++) {
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 22/32] hw/i386/pc: Move gsi_state creation code

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1400 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The block code related to IRQ start few lines later. Move


block code -> code block
start -> starts

the comment and the pc_gsi_create() call

where we start


call -> invocation


> to use the IRQs.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc_q35.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 52261962b8..6d096eff28 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -209,9 +209,6 @@ static void pc_q35_init(MachineState *machine)
>                         rom_memory, &ram_memory);
>      }
>
> -    /* irq lines */
> -    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
> -
>      /* create pci host bus */
>      q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
>
> @@ -245,6 +242,9 @@ static void pc_q35_init(MachineState *machine)
>      object_property_set_link(OBJECT(machine), OBJECT(lpc),
>                               PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
>
> +    /* irq lines */
> +    gsi_state = pc_gsi_create(&pcms->gsi, pcmc->pci_enabled);
> +
>      ich9_lpc = ICH9_LPC_DEVICE(lpc);
>      lpc_dev = DEVICE(lpc);
>      for (i = 0; i < GSI_NUM_PINS; i++) {
> --
> 2.21.0
>
>
>

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Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 5:04 PM, Thomas Huth wrote:
> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>> Move the KVM-related call to "sysemu/kvm.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>>   include/hw/i386/pc.h | 1 -
>>   include/sysemu/kvm.h | 1 +
>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 6df4f4b6fb..09e74e7764 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>   
>>   extern DeviceState *isa_pic;
>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>   int pic_read_irq(DeviceState *d);
>>   int pic_get_output(DeviceState *d);
>>   
>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>> index 9d143282bc..da8aa9f5a8 100644
>> --- a/include/sysemu/kvm.h
>> +++ b/include/sysemu/kvm.h
>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>   void kvm_init_irq_routing(KVMState *s);
>> +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
> to a generic header sounds wrong to me.

This function is declared when compiling without KVM, and is available 
on the Alpha/HPPA/MIPS which don't have it.

You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 5:04 PM, Thomas Huth wrote:
> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>> Move the KVM-related call to "sysemu/kvm.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>>   include/hw/i386/pc.h | 1 -
>>   include/sysemu/kvm.h | 1 +
>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 6df4f4b6fb..09e74e7764 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>   
>>   extern DeviceState *isa_pic;
>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>   int pic_read_irq(DeviceState *d);
>>   int pic_get_output(DeviceState *d);
>>   
>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>> index 9d143282bc..da8aa9f5a8 100644
>> --- a/include/sysemu/kvm.h
>> +++ b/include/sysemu/kvm.h
>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>   void kvm_init_irq_routing(KVMState *s);
>> +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
> to a generic header sounds wrong to me.

This function is declared when compiling without KVM, and is available 
on the Alpha/HPPA/MIPS which don't have it.

You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

Re: [Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Philippe Mathieu-Daudé]

On 10/17/19 5:04 PM, Thomas Huth wrote:
> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>> Move the KVM-related call to "sysemu/kvm.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>>   include/hw/i386/pc.h | 1 -
>>   include/sysemu/kvm.h | 1 +
>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 6df4f4b6fb..09e74e7764 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>   
>>   extern DeviceState *isa_pic;
>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>   int pic_read_irq(DeviceState *d);
>>   int pic_get_output(DeviceState *d);
>>   
>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>> index 9d143282bc..da8aa9f5a8 100644
>> --- a/include/sysemu/kvm.h
>> +++ b/include/sysemu/kvm.h
>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s, qemu_irq irq, int gsi);
>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>   void kvm_init_irq_routing(KVMState *s);
>> +qemu_irq *kvm_i8259_init(ISABus *bus);
> 
> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
> to a generic header sounds wrong to me.

This function is declared when compiling without KVM, and is available 
on the Alpha/HPPA/MIPS which don't have it.

You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

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Re: [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> The GSI creation code is common to all PC machines, extract the
> common code.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 15 +++++++++++++++
>  hw/i386/pc_piix.c    |  9 +--------
>  hw/i386/pc_q35.c     |  9 +--------
>  include/hw/i386/pc.h |  2 ++
>  4 files changed, 19 insertions(+), 16 deletions(-)

Is this really needed for this series here, or should this and the
following patches maybe rather be handled seperately?

Anyway, it looks like a good modification, so:
Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> The GSI creation code is common to all PC machines, extract the
> common code.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 15 +++++++++++++++
>  hw/i386/pc_piix.c    |  9 +--------
>  hw/i386/pc_q35.c     |  9 +--------
>  include/hw/i386/pc.h |  2 ++
>  4 files changed, 19 insertions(+), 16 deletions(-)

Is this really needed for this series here, or should this and the
following patches maybe rather be handled seperately?

Anyway, it looks like a good modification, so:
Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Xen-devel] [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create()

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> The GSI creation code is common to all PC machines, extract the
> common code.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 15 +++++++++++++++
>  hw/i386/pc_piix.c    |  9 +--------
>  hw/i386/pc_q35.c     |  9 +--------
>  include/hw/i386/pc.h |  2 ++
>  4 files changed, 19 insertions(+), 16 deletions(-)

Is this really needed for this series here, or should this and the
following patches maybe rather be handled seperately?

Anyway, it looks like a good modification, so:
Reviewed-by: Thomas Huth <thuth@redhat.com>

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Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

On 10/17/19 5:16 PM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     pc_gsi_create() is the single function that uses gsi_handler.
>     Make it a static variable.
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/i386/pc.c         | 2 +-
>       include/hw/i386/pc.h | 2 --
>       2 files changed, 1 insertion(+), 3 deletions(-)
> 
>     diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>     index a7597c6c44..59de0c8a1f 100644
>     --- a/hw/i386/pc.c
>     +++ b/hw/i386/pc.c
>     @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>       };
>       const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
> 
>     -void gsi_handler(void *opaque, int n, int level)
>     +static void gsi_handler(void *opaque, int n, int level)
>       {
>           GSIState *s = opaque;
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index d0c6b9d469..75b44e156c 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -172,8 +172,6 @@ typedef struct GSIState {
>           qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>       } GSIState;
> 
>     -void gsi_handler(void *opaque, int n, int level);
>     -
>       GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
> 
> 
> Philippe, this 2-line deletion seems not to belong to this patch. If 
> true, please place it in another or a separate patch.

It does, this is the point of the change, make it static and remove its 
declaration :)

Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

On 10/17/19 5:16 PM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     pc_gsi_create() is the single function that uses gsi_handler.
>     Make it a static variable.
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/i386/pc.c         | 2 +-
>       include/hw/i386/pc.h | 2 --
>       2 files changed, 1 insertion(+), 3 deletions(-)
> 
>     diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>     index a7597c6c44..59de0c8a1f 100644
>     --- a/hw/i386/pc.c
>     +++ b/hw/i386/pc.c
>     @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>       };
>       const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
> 
>     -void gsi_handler(void *opaque, int n, int level)
>     +static void gsi_handler(void *opaque, int n, int level)
>       {
>           GSIState *s = opaque;
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index d0c6b9d469..75b44e156c 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -172,8 +172,6 @@ typedef struct GSIState {
>           qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>       } GSIState;
> 
>     -void gsi_handler(void *opaque, int n, int level);
>     -
>       GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
> 
> 
> Philippe, this 2-line deletion seems not to belong to this patch. If 
> true, please place it in another or a separate patch.

It does, this is the point of the change, make it static and remove its 
declaration :)

Re: [Xen-devel] [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Philippe Mathieu-Daudé]

On 10/17/19 5:16 PM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     pc_gsi_create() is the single function that uses gsi_handler.
>     Make it a static variable.
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/i386/pc.c         | 2 +-
>       include/hw/i386/pc.h | 2 --
>       2 files changed, 1 insertion(+), 3 deletions(-)
> 
>     diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>     index a7597c6c44..59de0c8a1f 100644
>     --- a/hw/i386/pc.c
>     +++ b/hw/i386/pc.c
>     @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>       };
>       const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
> 
>     -void gsi_handler(void *opaque, int n, int level)
>     +static void gsi_handler(void *opaque, int n, int level)
>       {
>           GSIState *s = opaque;
> 
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index d0c6b9d469..75b44e156c 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -172,8 +172,6 @@ typedef struct GSIState {
>           qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>       } GSIState;
> 
>     -void gsi_handler(void *opaque, int n, int level);
>     -
>       GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
> 
> 
> Philippe, this 2-line deletion seems not to belong to this patch. If 
> true, please place it in another or a separate patch.

It does, this is the point of the change, make it static and remove its 
declaration :)

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Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 17/10/2019 17.31, Philippe Mathieu-Daudé wrote:
> On 10/17/19 5:04 PM, Thomas Huth wrote:
>> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>>> Move the KVM-related call to "sysemu/kvm.h".
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>>   include/hw/i386/pc.h | 1 -
>>>   include/sysemu/kvm.h | 1 +
>>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>> index 6df4f4b6fb..09e74e7764 100644
>>> --- a/include/hw/i386/pc.h
>>> +++ b/include/hw/i386/pc.h
>>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>>     extern DeviceState *isa_pic;
>>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>>   int pic_read_irq(DeviceState *d);
>>>   int pic_get_output(DeviceState *d);
>>>   diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>>> index 9d143282bc..da8aa9f5a8 100644
>>> --- a/include/sysemu/kvm.h
>>> +++ b/include/sysemu/kvm.h
>>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>>> qemu_irq irq, int gsi);
>>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>>   void kvm_init_irq_routing(KVMState *s);
>>> +qemu_irq *kvm_i8259_init(ISABus *bus);
>>
>> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
>> to a generic header sounds wrong to me.
> 
> This function is declared when compiling without KVM, and is available
> on the Alpha/HPPA/MIPS which don't have it.

Sorry, I failed to parse your last sentence. It's only used by hw/i386
code as far as I can see.

> You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

Maybe, but that's certainly something for a different patch series.

This series here should focus on what you've mentioned in the cover
letter, I think. It's already big enough.

 Thomas

Re: [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 17/10/2019 17.31, Philippe Mathieu-Daudé wrote:
> On 10/17/19 5:04 PM, Thomas Huth wrote:
>> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>>> Move the KVM-related call to "sysemu/kvm.h".
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>>   include/hw/i386/pc.h | 1 -
>>>   include/sysemu/kvm.h | 1 +
>>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>> index 6df4f4b6fb..09e74e7764 100644
>>> --- a/include/hw/i386/pc.h
>>> +++ b/include/hw/i386/pc.h
>>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>>     extern DeviceState *isa_pic;
>>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>>   int pic_read_irq(DeviceState *d);
>>>   int pic_get_output(DeviceState *d);
>>>   diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>>> index 9d143282bc..da8aa9f5a8 100644
>>> --- a/include/sysemu/kvm.h
>>> +++ b/include/sysemu/kvm.h
>>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>>> qemu_irq irq, int gsi);
>>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>>   void kvm_init_irq_routing(KVMState *s);
>>> +qemu_irq *kvm_i8259_init(ISABus *bus);
>>
>> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
>> to a generic header sounds wrong to me.
> 
> This function is declared when compiling without KVM, and is available
> on the Alpha/HPPA/MIPS which don't have it.

Sorry, I failed to parse your last sentence. It's only used by hw/i386
code as far as I can see.

> You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

Maybe, but that's certainly something for a different patch series.

This series here should focus on what you've mentioned in the cover
letter, I think. It's already big enough.

 Thomas

Re: [Xen-devel] [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h

[Thomas Huth]

On 17/10/2019 17.31, Philippe Mathieu-Daudé wrote:
> On 10/17/19 5:04 PM, Thomas Huth wrote:
>> On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
>>> Move the KVM-related call to "sysemu/kvm.h".
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>>   include/hw/i386/pc.h | 1 -
>>>   include/sysemu/kvm.h | 1 +
>>>   2 files changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>> index 6df4f4b6fb..09e74e7764 100644
>>> --- a/include/hw/i386/pc.h
>>> +++ b/include/hw/i386/pc.h
>>> @@ -158,7 +158,6 @@ typedef struct PCMachineClass {
>>>     extern DeviceState *isa_pic;
>>>   qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
>>> -qemu_irq *kvm_i8259_init(ISABus *bus);
>>>   int pic_read_irq(DeviceState *d);
>>>   int pic_get_output(DeviceState *d);
>>>   diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>>> index 9d143282bc..da8aa9f5a8 100644
>>> --- a/include/sysemu/kvm.h
>>> +++ b/include/sysemu/kvm.h
>>> @@ -513,6 +513,7 @@ void kvm_irqchip_set_qemuirq_gsi(KVMState *s,
>>> qemu_irq irq, int gsi);
>>>   void kvm_pc_gsi_handler(void *opaque, int n, int level);
>>>   void kvm_pc_setup_irq_routing(bool pci_enabled);
>>>   void kvm_init_irq_routing(KVMState *s);
>>> +qemu_irq *kvm_i8259_init(ISABus *bus);
>>
>> Why? The function is defined in hw/i386/kvm/ - so moving its prototype
>> to a generic header sounds wrong to me.
> 
> This function is declared when compiling without KVM, and is available
> on the Alpha/HPPA/MIPS which don't have it.

Sorry, I failed to parse your last sentence. It's only used by hw/i386
code as far as I can see.

> You'd rather move the kvm_pc_* declarations to hw/i386/kvm/?

Maybe, but that's certainly something for a different patch series.

This series here should focus on what you've mentioned in the cover
letter, I think. It's already big enough.

 Thomas

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Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> pc_gsi_create() is the single function that uses gsi_handler.
> Make it a static variable.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 2 +-
>  include/hw/i386/pc.h | 2 --
>  2 files changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a7597c6c44..59de0c8a1f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>  };
>  const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>  
> -void gsi_handler(void *opaque, int n, int level)
> +static void gsi_handler(void *opaque, int n, int level)
>  {
>      GSIState *s = opaque;
>  
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index d0c6b9d469..75b44e156c 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -172,8 +172,6 @@ typedef struct GSIState {
>      qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>  } GSIState;
>  
> -void gsi_handler(void *opaque, int n, int level);
> -
>  GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>  
>  /* vmport.c */
> 

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> pc_gsi_create() is the single function that uses gsi_handler.
> Make it a static variable.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 2 +-
>  include/hw/i386/pc.h | 2 --
>  2 files changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a7597c6c44..59de0c8a1f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>  };
>  const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>  
> -void gsi_handler(void *opaque, int n, int level)
> +static void gsi_handler(void *opaque, int n, int level)
>  {
>      GSIState *s = opaque;
>  
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index d0c6b9d469..75b44e156c 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -172,8 +172,6 @@ typedef struct GSIState {
>      qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>  } GSIState;
>  
> -void gsi_handler(void *opaque, int n, int level);
> -
>  GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>  
>  /* vmport.c */
> 

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Xen-devel] [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Thomas Huth]

On 15/10/2019 18.26, Philippe Mathieu-Daudé wrote:
> pc_gsi_create() is the single function that uses gsi_handler.
> Make it a static variable.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/pc.c         | 2 +-
>  include/hw/i386/pc.h | 2 --
>  2 files changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index a7597c6c44..59de0c8a1f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>  };
>  const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>  
> -void gsi_handler(void *opaque, int n, int level)
> +static void gsi_handler(void *opaque, int n, int level)
>  {
>      GSIState *s = opaque;
>  
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index d0c6b9d469..75b44e156c 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -172,8 +172,6 @@ typedef struct GSIState {
>      qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>  } GSIState;
>  
> -void gsi_handler(void *opaque, int n, int level);
> -
>  GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>  
>  /* vmport.c */
> 

Reviewed-by: Thomas Huth <thuth@redhat.com>

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Re: [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1864 bytes --]

On Thursday, October 17, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> On 10/17/19 5:16 PM, Aleksandar Markovic wrote:
>
>> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
>> <mailto:philmd@redhat.com>> wrote:
>>
>>     pc_gsi_create() is the single function that uses gsi_handler.
>>     Make it a static variable.
>>
>>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>>     <mailto:philmd@redhat.com>>
>>     ---
>>       hw/i386/pc.c         | 2 +-
>>       include/hw/i386/pc.h | 2 --
>>       2 files changed, 1 insertion(+), 3 deletions(-)
>>
>>     diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>>     index a7597c6c44..59de0c8a1f 100644
>>     --- a/hw/i386/pc.c
>>     +++ b/hw/i386/pc.c
>>     @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>>       };
>>       const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>>
>>     -void gsi_handler(void *opaque, int n, int level)
>>     +static void gsi_handler(void *opaque, int n, int level)
>>       {
>>           GSIState *s = opaque;
>>
>>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>     index d0c6b9d469..75b44e156c 100644
>>     --- a/include/hw/i386/pc.h
>>     +++ b/include/hw/i386/pc.h
>>     @@ -172,8 +172,6 @@ typedef struct GSIState {
>>           qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>>       } GSIState;
>>
>>     -void gsi_handler(void *opaque, int n, int level);
>>     -
>>       GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>>
>>
>> Philippe, this 2-line deletion seems not to belong to this patch. If
>> true, please place it in another or a separate patch.
>>
>
> It does, this is the point of the change, make it static and remove its
> declaration :)
>


OK, I see.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

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Re: [Xen-devel] [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1864 bytes --]

On Thursday, October 17, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> On 10/17/19 5:16 PM, Aleksandar Markovic wrote:
>
>> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
>> <mailto:philmd@redhat.com>> wrote:
>>
>>     pc_gsi_create() is the single function that uses gsi_handler.
>>     Make it a static variable.
>>
>>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>>     <mailto:philmd@redhat.com>>
>>     ---
>>       hw/i386/pc.c         | 2 +-
>>       include/hw/i386/pc.h | 2 --
>>       2 files changed, 1 insertion(+), 3 deletions(-)
>>
>>     diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>>     index a7597c6c44..59de0c8a1f 100644
>>     --- a/hw/i386/pc.c
>>     +++ b/hw/i386/pc.c
>>     @@ -346,7 +346,7 @@ GlobalProperty pc_compat_1_4[] = {
>>       };
>>       const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
>>
>>     -void gsi_handler(void *opaque, int n, int level)
>>     +static void gsi_handler(void *opaque, int n, int level)
>>       {
>>           GSIState *s = opaque;
>>
>>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>     index d0c6b9d469..75b44e156c 100644
>>     --- a/include/hw/i386/pc.h
>>     +++ b/include/hw/i386/pc.h
>>     @@ -172,8 +172,6 @@ typedef struct GSIState {
>>           qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
>>       } GSIState;
>>
>>     -void gsi_handler(void *opaque, int n, int level);
>>     -
>>       GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
>>
>>
>> Philippe, this 2-line deletion seems not to belong to this patch. If
>> true, please place it in another or a separate patch.
>>
>
> It does, this is the point of the change, make it static and remove its
> declaration :)
>


OK, I see.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

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[-- Attachment #2: Type: text/plain, Size: 157 bytes --]

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Re: [PATCH 25/32] hw/pci-host/piix: Extract piix3_create()

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 3529 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Extract the PIIX3 creation code from the i440fx_init() function.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
>  1 file changed, 31 insertions(+), 20 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 2f4cbcbfe9..3292703de7 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>      }
>  }
>
> +static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> +    PIIX3State *piix3;
> +    PCIDevice *pci_dev;
> +
> +    /*
> +     * Xen supports additional interrupt routes from the PCI devices to
> +     * the IOAPIC: the four pins of each PCI device on the bus are also
> +     * connected to the IOAPIC directly.
> +     * These additional routes can be discovered through ACPI.
> +     */
> +    if (xen_enabled()) {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_XEN_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> +                     piix3, XEN_PIIX_NUM_PIRQS);
> +    } else {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> +                     piix3, PIIX_NUM_PIRQS);
> +        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> +    }
> +    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> +    return piix3;
> +}
> +
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state,
>                      int *piix3_devfn,
> @@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>                   PAM_EXPAN_SIZE);
>      }
>
> -    /* Xen supports additional interrupt routes from the PCI devices to
> -     * the IOAPIC: the four pins of each PCI device on the bus are also
> -     * connected to the IOAPIC directly.
> -     * These additional routes can be discovered through ACPI. */
> -    if (xen_enabled()) {
> -        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> -                             -1, true, TYPE_PIIX3_XEN_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> -                piix3, XEN_PIIX_NUM_PIRQS);
> -    } else {
> -        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> -                             -1, true, TYPE_PIIX3_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
> -                PIIX_NUM_PIRQS);
> -        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
> -    }
> +    piix3 = piix3_create(b, isa_bus);
>      piix3->pic = pic;
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
>      *piix3_devfn = piix3->dev.devfn;
>
>      ram_size = ram_size / 8 / 1024 / 1024;
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 25/32] hw/pci-host/piix: Extract piix3_create()

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 3529 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Extract the PIIX3 creation code from the i440fx_init() function.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
>  1 file changed, 31 insertions(+), 20 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 2f4cbcbfe9..3292703de7 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>      }
>  }
>
> +static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> +    PIIX3State *piix3;
> +    PCIDevice *pci_dev;
> +
> +    /*
> +     * Xen supports additional interrupt routes from the PCI devices to
> +     * the IOAPIC: the four pins of each PCI device on the bus are also
> +     * connected to the IOAPIC directly.
> +     * These additional routes can be discovered through ACPI.
> +     */
> +    if (xen_enabled()) {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_XEN_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> +                     piix3, XEN_PIIX_NUM_PIRQS);
> +    } else {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> +                     piix3, PIIX_NUM_PIRQS);
> +        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> +    }
> +    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> +    return piix3;
> +}
> +
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state,
>                      int *piix3_devfn,
> @@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
>                   PAM_EXPAN_SIZE);
>      }
>
> -    /* Xen supports additional interrupt routes from the PCI devices to
> -     * the IOAPIC: the four pins of each PCI device on the bus are also
> -     * connected to the IOAPIC directly.
> -     * These additional routes can be discovered through ACPI. */
> -    if (xen_enabled()) {
> -        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> -                             -1, true, TYPE_PIIX3_XEN_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> -                piix3, XEN_PIIX_NUM_PIRQS);
> -    } else {
> -        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> -                             -1, true, TYPE_PIIX3_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
> -                PIIX_NUM_PIRQS);
> -        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
> -    }
> +    piix3 = piix3_create(b, isa_bus);
>      piix3->pic = pic;
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
>      *piix3_devfn = piix3->dev.devfn;
>
>      ram_size = ram_size / 8 / 1024 / 1024;
> --
> 2.21.0
>
>
>

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Re: [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 2527 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The RCR_IOPORT register belongs to the PIIX chipset.
> Move the definition to "piix.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c            | 1 +
>  include/hw/i386/pc.h          | 6 ------
>  include/hw/southbridge/piix.h | 6 ++++++
>  3 files changed, 7 insertions(+), 6 deletions(-)
>
>
Does it make sense to add prefix PIIX_ or a similar one to the register
name?

In any case:

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3292703de7..3770575c1a 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -27,6 +27,7 @@
>  #include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 183326d9fe..1c20b96571 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
>
>  #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
>
> -/*
> - * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
> - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> - */
> -#define RCR_IOPORT 0xcf9
> -
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state, int *piix_devfn,
>                      ISABus **isa_bus, qemu_irq *pic,
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index add352456b..79ebe0089b 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/*
> + * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
> + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> + */
> +#define RCR_IOPORT 0xcf9
> +
>  extern PCIDevice *piix4_dev;
>
>  DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 2527 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The RCR_IOPORT register belongs to the PIIX chipset.
> Move the definition to "piix.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c            | 1 +
>  include/hw/i386/pc.h          | 6 ------
>  include/hw/southbridge/piix.h | 6 ++++++
>  3 files changed, 7 insertions(+), 6 deletions(-)
>
>
Does it make sense to add prefix PIIX_ or a similar one to the register
name?

In any case:

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3292703de7..3770575c1a 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -27,6 +27,7 @@
>  #include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 183326d9fe..1c20b96571 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
>
>  #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
>
> -/*
> - * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
> - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> - */
> -#define RCR_IOPORT 0xcf9
> -
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state, int *piix_devfn,
>                      ISABus **isa_bus, qemu_irq *pic,
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index add352456b..79ebe0089b 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/*
> + * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
> + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> + */
> +#define RCR_IOPORT 0xcf9
> +
>  extern PCIDevice *piix4_dev;
>
>  DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
> --
> 2.21.0
>
>
>

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Re: [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/xen/xen-hvm.c         | 5 +++--
>  hw/mips/gt64xxx_pci.c         | 4 ++--
>  hw/pci-host/piix.c            | 9 ++++-----
>  include/hw/southbridge/piix.h | 6 ++++++
>  4 files changed, 15 insertions(+), 9 deletions(-)
>
>
The register from the patch 27/32 doesn't have prefix and the registers
ftom this patch do - inconsistency?

In any case:

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 6b5e5bb7f5..4ce2fb9c89 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -14,6 +14,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/hw.h"
>  #include "hw/i386/apic-msidef.h"
> @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t
> address, uint32_t val, int len)
>              v = 0;
>          }
>          v &= 0xf;
> -        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> -            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
> +        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <=
> PIIX_PIRQCD)) {
> +            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA,
> v);
>          }
>      }
>  }
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c277398c0d..5cab9c1ee1 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int
> irq_num, int level)
>
>      /* now we change the pic irq level according to the piix irq mappings
> */
>      /* XXX: optimize */
> -    pic_irq = piix4_dev->config[0x60 + irq_num];
> +    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
>      if (pic_irq < 16) {
>          /* The pic level is the logical OR of all the PCI irqs mapped to
> it. */
>          pic_level = 0;
>          for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix4_dev->config[0x60 + i]) {
> +            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
>                  pic_level |= pci_irq_levels[i];
>              }
>          }
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3770575c1a..a450fc726e 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -61,7 +61,6 @@ typedef struct I440FXState {
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
>  #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
>  #define XEN_PIIX_NUM_PIRQS      128ULL
> -#define PIIX_PIRQC              0x60
>
>  typedef struct PIIX3State {
>      PCIDevice dev;
> @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State
> *piix3, int pirq, int level)
>      int pic_irq;
>      uint64_t mask;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int
> pirq, int level)
>  {
>      int pic_irq;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int
> level)
>  static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
>  {
>      PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQC + pin];
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
>      PCIINTxRoute route;
>
>      if (irq < PIIX_NUM_PIC_IRQS) {
> @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len)
>  {
>      pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
>          PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
>          int pic_irq;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 79ebe0089b..9c92c37a4d 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/* PIRQRC[A:D]: PIRQx Route Control Registers */
> +#define PIIX_PIRQCA 0x60
> +#define PIIX_PIRQCB 0x61
> +#define PIIX_PIRQCC 0x62
> +#define PIIX_PIRQCD 0x63
> +
>  /*
>   * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
>   * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 5263 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> The IRQ Route Control registers definitions belong to the PIIX
> chipset. We were only defining the 'A' register. Define the other
> B, C and D registers, and use them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/i386/xen/xen-hvm.c         | 5 +++--
>  hw/mips/gt64xxx_pci.c         | 4 ++--
>  hw/pci-host/piix.c            | 9 ++++-----
>  include/hw/southbridge/piix.h | 6 ++++++
>  4 files changed, 15 insertions(+), 9 deletions(-)
>
>
The register from the patch 27/32 doesn't have prefix and the registers
ftom this patch do - inconsistency?

In any case:

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 6b5e5bb7f5..4ce2fb9c89 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -14,6 +14,7 @@
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
> +#include "hw/southbridge/piix.h"
>  #include "hw/irq.h"
>  #include "hw/hw.h"
>  #include "hw/i386/apic-msidef.h"
> @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t
> address, uint32_t val, int len)
>              v = 0;
>          }
>          v &= 0xf;
> -        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> -            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
> +        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <=
> PIIX_PIRQCD)) {
> +            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA,
> v);
>          }
>      }
>  }
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c277398c0d..5cab9c1ee1 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int
> irq_num, int level)
>
>      /* now we change the pic irq level according to the piix irq mappings
> */
>      /* XXX: optimize */
> -    pic_irq = piix4_dev->config[0x60 + irq_num];
> +    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
>      if (pic_irq < 16) {
>          /* The pic level is the logical OR of all the PCI irqs mapped to
> it. */
>          pic_level = 0;
>          for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix4_dev->config[0x60 + i]) {
> +            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
>                  pic_level |= pci_irq_levels[i];
>              }
>          }
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 3770575c1a..a450fc726e 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -61,7 +61,6 @@ typedef struct I440FXState {
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
>  #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
>  #define XEN_PIIX_NUM_PIRQS      128ULL
> -#define PIIX_PIRQC              0x60
>
>  typedef struct PIIX3State {
>      PCIDevice dev;
> @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State
> *piix3, int pirq, int level)
>      int pic_irq;
>      uint64_t mask;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int
> pirq, int level)
>  {
>      int pic_irq;
>
> -    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
>      if (pic_irq >= PIIX_NUM_PIC_IRQS) {
>          return;
>      }
> @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int
> level)
>  static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
>  {
>      PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQC + pin];
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
>      PCIINTxRoute route;
>
>      if (irq < PIIX_NUM_PIC_IRQS) {
> @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len)
>  {
>      pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
>          PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
>          int pic_irq;
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 79ebe0089b..9c92c37a4d 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>                        qemu_irq sci_irq, qemu_irq smi_irq,
>                        int smm_enabled, DeviceState **piix4_pm);
>
> +/* PIRQRC[A:D]: PIRQx Route Control Registers */
> +#define PIIX_PIRQCA 0x60
> +#define PIIX_PIRQCB 0x61
> +#define PIIX_PIRQCC 0x62
> +#define PIIX_PIRQCD 0x63
> +
>  /*
>   * Reset Control Register: PCI-accessible ISA-Compatible Register at
> address
>   * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
> 8086:7000).
> --
> 2.21.0
>
>
>

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Re: [PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 5561 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
> functions. To be able to split it, we need to export some
> declarations first.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                  |  1 +
>  hw/acpi/pcihp.c              |  2 +-
>  hw/i386/pc_piix.c            |  1 +
>  hw/pci-host/piix.c           |  1 +
>  include/hw/i386/pc.h         | 22 ---------------------
>  include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
>  stubs/pci-host-piix.c        |  3 ++-
>  7 files changed, 43 insertions(+), 24 deletions(-)
>  create mode 100644 include/hw/pci-host/i440fx.h
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index 556f58bd8c..adf059a164 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1228,6 +1228,7 @@ F: hw/i386/
>  F: hw/pci-host/piix.c
>  F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
> +F: include/hw/pci-host/i440fx.h
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
>  F: hw/isa/lpc_ich9.c
> diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
> index 82d295b6e8..8413348a33 100644
> --- a/hw/acpi/pcihp.c
> +++ b/hw/acpi/pcihp.c
> @@ -27,7 +27,7 @@
>  #include "qemu/osdep.h"
>  #include "hw/acpi/pcihp.h"
>
> -#include "hw/i386/pc.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_bridge.h"
>  #include "hw/acpi/acpi.h"
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 5b35ff04c7..8ac4bf12ca 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -29,6 +29,7 @@
>  #include "hw/loader.h"
>  #include "hw/i386/pc.h"
>  #include "hw/i386/apic.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/display/ramfb.h"
>  #include "hw/firmware/smbios.h"
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index a450fc726e..0b5da5bc94 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -27,6 +27,7 @@
>  #include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/isa/isa.h"
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 1c20b96571..cead2828de 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -248,28 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
>  /* hpet.c */
>  extern int no_hpet;
>
> -/* piix_pci.c */
> -struct PCII440FXState;
> -typedef struct PCII440FXState PCII440FXState;
> -
> -#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
> -#define TYPE_I440FX_PCI_DEVICE "i440FX"
> -
> -#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
> -
> -PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> -                    PCII440FXState **pi440fx_state, int *piix_devfn,
> -                    ISABus **isa_bus, qemu_irq *pic,
> -                    MemoryRegion *address_space_mem,
> -                    MemoryRegion *address_space_io,
> -                    ram_addr_t ram_size,
> -                    ram_addr_t below_4g_mem_size,
> -                    ram_addr_t above_4g_mem_size,
> -                    MemoryRegion *pci_memory,
> -                    MemoryRegion *ram_memory);
> -
> -PCIBus *find_i440fx(void);
> -
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
>  void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion
> *rom_memory);
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> new file mode 100644
> index 0000000000..e327f9bf87
> --- /dev/null
> +++ b/include/hw/pci-host/i440fx.h
> @@ -0,0 +1,37 @@
> +/*
> + * QEMU i440FX North Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_PCI_I440FX_H
> +#define HW_PCI_I440FX_H
> +
> +#include "hw/hw.h"
> +#include "hw/pci/pci_bus.h"
> +
> +typedef struct PCII440FXState PCII440FXState;
> +
> +#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
> +#define TYPE_I440FX_PCI_DEVICE "i440FX"
> +
> +#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
> +
> +PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> +                    PCII440FXState **pi440fx_state, int *piix_devfn,
> +                    ISABus **isa_bus, qemu_irq *pic,
> +                    MemoryRegion *address_space_mem,
> +                    MemoryRegion *address_space_io,
> +                    ram_addr_t ram_size,
> +                    ram_addr_t below_4g_mem_size,
> +                    ram_addr_t above_4g_mem_size,
> +                    MemoryRegion *pci_memory,
> +                    MemoryRegion *ram_memory);
> +
> +PCIBus *find_i440fx(void);
> +
> +#endif
> diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
> index 6ed81b1f21..93975adbfe 100644
> --- a/stubs/pci-host-piix.c
> +++ b/stubs/pci-host-piix.c
> @@ -1,5 +1,6 @@
>  #include "qemu/osdep.h"
> -#include "hw/i386/pc.h"
> +#include "hw/pci-host/i440fx.h"
> +
>  PCIBus *find_i440fx(void)
>  {
>      return NULL;
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
> functions. To be able to split it, we need to export some
> declarations first.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                  |  1 +
>  hw/acpi/pcihp.c              |  2 +-
>  hw/i386/pc_piix.c            |  1 +
>  hw/pci-host/piix.c           |  1 +
>  include/hw/i386/pc.h         | 22 ---------------------
>  include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
>  stubs/pci-host-piix.c        |  3 ++-
>  7 files changed, 43 insertions(+), 24 deletions(-)
>  create mode 100644 include/hw/pci-host/i440fx.h
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>



> diff --git a/MAINTAINERS b/MAINTAINERS
> index 556f58bd8c..adf059a164 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1228,6 +1228,7 @@ F: hw/i386/
>  F: hw/pci-host/piix.c
>  F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
> +F: include/hw/pci-host/i440fx.h
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
>  F: hw/isa/lpc_ich9.c
> diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
> index 82d295b6e8..8413348a33 100644
> --- a/hw/acpi/pcihp.c
> +++ b/hw/acpi/pcihp.c
> @@ -27,7 +27,7 @@
>  #include "qemu/osdep.h"
>  #include "hw/acpi/pcihp.h"
>
> -#include "hw/i386/pc.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_bridge.h"
>  #include "hw/acpi/acpi.h"
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 5b35ff04c7..8ac4bf12ca 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -29,6 +29,7 @@
>  #include "hw/loader.h"
>  #include "hw/i386/pc.h"
>  #include "hw/i386/apic.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/display/ramfb.h"
>  #include "hw/firmware/smbios.h"
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index a450fc726e..0b5da5bc94 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -27,6 +27,7 @@
>  #include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
> +#include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/isa/isa.h"
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 1c20b96571..cead2828de 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -248,28 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
>  /* hpet.c */
>  extern int no_hpet;
>
> -/* piix_pci.c */
> -struct PCII440FXState;
> -typedef struct PCII440FXState PCII440FXState;
> -
> -#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
> -#define TYPE_I440FX_PCI_DEVICE "i440FX"
> -
> -#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
> -
> -PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> -                    PCII440FXState **pi440fx_state, int *piix_devfn,
> -                    ISABus **isa_bus, qemu_irq *pic,
> -                    MemoryRegion *address_space_mem,
> -                    MemoryRegion *address_space_io,
> -                    ram_addr_t ram_size,
> -                    ram_addr_t below_4g_mem_size,
> -                    ram_addr_t above_4g_mem_size,
> -                    MemoryRegion *pci_memory,
> -                    MemoryRegion *ram_memory);
> -
> -PCIBus *find_i440fx(void);
> -
>  /* pc_sysfw.c */
>  void pc_system_flash_create(PCMachineState *pcms);
>  void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion
> *rom_memory);
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> new file mode 100644
> index 0000000000..e327f9bf87
> --- /dev/null
> +++ b/include/hw/pci-host/i440fx.h
> @@ -0,0 +1,37 @@
> +/*
> + * QEMU i440FX North Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_PCI_I440FX_H
> +#define HW_PCI_I440FX_H
> +
> +#include "hw/hw.h"
> +#include "hw/pci/pci_bus.h"
> +
> +typedef struct PCII440FXState PCII440FXState;
> +
> +#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
> +#define TYPE_I440FX_PCI_DEVICE "i440FX"
> +
> +#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
> +
> +PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> +                    PCII440FXState **pi440fx_state, int *piix_devfn,
> +                    ISABus **isa_bus, qemu_irq *pic,
> +                    MemoryRegion *address_space_mem,
> +                    MemoryRegion *address_space_io,
> +                    ram_addr_t ram_size,
> +                    ram_addr_t below_4g_mem_size,
> +                    ram_addr_t above_4g_mem_size,
> +                    MemoryRegion *pci_memory,
> +                    MemoryRegion *ram_memory);
> +
> +PCIBus *find_i440fx(void);
> +
> +#endif
> diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
> index 6ed81b1f21..93975adbfe 100644
> --- a/stubs/pci-host-piix.c
> +++ b/stubs/pci-host-piix.c
> @@ -1,5 +1,6 @@
>  #include "qemu/osdep.h"
> -#include "hw/i386/pc.h"
> +#include "hw/pci-host/i440fx.h"
> +
>  PCIBus *find_i440fx(void)
>  {
>      return NULL;
> --
> 2.21.0
>
>
>

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Re: [PATCH 29/32] hw/pci-host/piix: Fix code style issues

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1197 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> We will move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 0b5da5bc94..61f91ff561 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void
> *opaque, int pci_intx);
>  static void piix3_write_config_xen(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len);
>
> -/* return the global irq number corresponding to a given device irq
> -   pin. We could also use the bus number to have a more precise
> -   mapping. */
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise mapping.
> + */
>  static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
>  {
>      int slot_addend;
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 29/32] hw/pci-host/piix: Fix code style issues

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1197 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> We will move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/pci-host/piix.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 0b5da5bc94..61f91ff561 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void
> *opaque, int pci_intx);
>  static void piix3_write_config_xen(PCIDevice *dev,
>                                 uint32_t address, uint32_t val, int len);
>
> -/* return the global irq number corresponding to a given device irq
> -   pin. We could also use the bus number to have a more precise
> -   mapping. */
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise mapping.
> + */
>  static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
>  {
>      int slot_addend;
> --
> 2.21.0
>
>
>

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Re: [PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 33311 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Move all the PIIX3 functions to a new file: hw/isa/piix3.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Checkpatch warning:
>
>  ERROR: spaces required around that '*' (ctx:VxV)
>  #312: FILE: hw/isa/piix3.c:248:
>  +    .subsections = (const VMStateDescription*[]) {
>                                               ^
> ---
>  MAINTAINERS                   |   1 +
>  hw/i386/Kconfig               |   1 +
>  hw/isa/Kconfig                |   4 +
>  hw/isa/Makefile.objs          |   1 +
>  hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
>  hw/pci-host/Kconfig           |   1 -
>  hw/pci-host/piix.c            | 402 ----------------------------------
>  include/hw/southbridge/piix.h |  36 +++
>  8 files changed, 442 insertions(+), 403 deletions(-)
>  create mode 100644 hw/isa/piix3.c
>
>

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/MAINTAINERS b/MAINTAINERS
> index adf059a164..4845f47d93 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
>  F: include/hw/pci-host/i440fx.h
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
> +F: hw/isa/piix3.c
>  F: hw/isa/lpc_ich9.c
>  F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index c5c9d4900e..589d75e26a 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -61,6 +61,7 @@ config I440FX
>      select PC_ACPI
>      select ACPI_SMBUS
>      select PCI_PIIX
> +    select PIIX3
>      select IDE_PIIX
>      select DIMM
>      select SMBIOS
> diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
> index 98a289957e..8a38813cc1 100644
> --- a/hw/isa/Kconfig
> +++ b/hw/isa/Kconfig
> @@ -29,6 +29,10 @@ config PC87312
>      select FDC
>      select IDE_ISA
>
> +config PIIX3
> +    bool
> +    select ISA_BUS
> +
>  config PIIX4
>      bool
>      # For historical reasons, SuperIO devices are created in the board
> diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
> index ff97485504..8e73960a75 100644
> --- a/hw/isa/Makefile.objs
> +++ b/hw/isa/Makefile.objs
> @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
>  common-obj-$(CONFIG_APM) += apm.o
>  common-obj-$(CONFIG_I82378) += i82378.o
>  common-obj-$(CONFIG_PC87312) += pc87312.o
> +common-obj-$(CONFIG_PIIX3) += piix3.o
>  common-obj-$(CONFIG_PIIX4) += piix4.o
>  common-obj-$(CONFIG_VT82C686) += vt82c686.o
>  common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
> diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
> new file mode 100644
> index 0000000000..05146447ef
> --- /dev/null
> +++ b/hw/isa/piix3.c
> @@ -0,0 +1,399 @@
> +/*
> + * QEMU PIIX PCI ISA Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> + * of this software and associated documentation files (the "Software"),
> to deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/range.h"
> +#include "hw/southbridge/piix.h"
> +#include "hw/irq.h"
> +#include "hw/isa/isa.h"
> +#include "hw/xen/xen.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
> +#include "migration/vmstate.h"
> +
> +#define XEN_PIIX_NUM_PIRQS      128ULL
> +
> +#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
> +#define PIIX3_PCI_DEVICE(obj) \
> +    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
> +
> +#define TYPE_PIIX3_DEVICE "PIIX3"
> +#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
> +
> +static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> +{
> +    qemu_set_irq(piix3->pic[pic_irq],
> +                 !!(piix3->pic_levels &
> +                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
> +                     (pic_irq * PIIX_NUM_PIRQS))));
> +}
> +
> +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq,
> int level)
> +{
> +    int pic_irq;
> +    uint64_t mask;
> +
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> +    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> +        return;
> +    }
> +
> +    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
> +    piix3->pic_levels &= ~mask;
> +    piix3->pic_levels |= mask * !!level;
> +}
> +
> +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
> +{
> +    int pic_irq;
> +
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> +    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> +        return;
> +    }
> +
> +    piix3_set_irq_level_internal(piix3, pirq, level);
> +
> +    piix3_set_irq_pic(piix3, pic_irq);
> +}
> +
> +static void piix3_set_irq(void *opaque, int pirq, int level)
> +{
> +    PIIX3State *piix3 = opaque;
> +    piix3_set_irq_level(piix3, pirq, level);
> +}
> +
> +static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
> +{
> +    PIIX3State *piix3 = opaque;
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
> +    PCIINTxRoute route;
> +
> +    if (irq < PIIX_NUM_PIC_IRQS) {
> +        route.mode = PCI_INTX_ENABLED;
> +        route.irq = irq;
> +    } else {
> +        route.mode = PCI_INTX_DISABLED;
> +        route.irq = -1;
> +    }
> +    return route;
> +}
> +
> +/* irq routing is changed. so rebuild bitmap */
> +static void piix3_update_irq_levels(PIIX3State *piix3)
> +{
> +    PCIBus *bus = pci_get_bus(&piix3->dev);
> +    int pirq;
> +
> +    piix3->pic_levels = 0;
> +    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> +        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus,
> pirq));
> +    }
> +}
> +
> +static void piix3_write_config(PCIDevice *dev,
> +                               uint32_t address, uint32_t val, int len)
> +{
> +    pci_default_write_config(dev, address, val, len);
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
> +        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
> +        int pic_irq;
> +
> +        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
> +        piix3_update_irq_levels(piix3);
> +        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
> +            piix3_set_irq_pic(piix3, pic_irq);
> +        }
> +    }
> +}
> +
> +static void piix3_write_config_xen(PCIDevice *dev,
> +                                   uint32_t address, uint32_t val, int
> len)
> +{
> +    xen_piix_pci_write_config_client(address, val, len);
> +    piix3_write_config(dev, address, val, len);
> +}
> +
> +static void piix3_reset(void *opaque)
> +{
> +    PIIX3State *d = opaque;
> +    uint8_t *pci_conf = d->dev.config;
> +
> +    pci_conf[0x04] = 0x07; /* master, memory and I/O */
> +    pci_conf[0x05] = 0x00;
> +    pci_conf[0x06] = 0x00;
> +    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
> +    pci_conf[0x4c] = 0x4d;
> +    pci_conf[0x4e] = 0x03;
> +    pci_conf[0x4f] = 0x00;
> +    pci_conf[0x60] = 0x80;
> +    pci_conf[0x61] = 0x80;
> +    pci_conf[0x62] = 0x80;
> +    pci_conf[0x63] = 0x80;
> +    pci_conf[0x69] = 0x02;
> +    pci_conf[0x70] = 0x80;
> +    pci_conf[0x76] = 0x0c;
> +    pci_conf[0x77] = 0x0c;
> +    pci_conf[0x78] = 0x02;
> +    pci_conf[0x79] = 0x00;
> +    pci_conf[0x80] = 0x00;
> +    pci_conf[0x82] = 0x00;
> +    pci_conf[0xa0] = 0x08;
> +    pci_conf[0xa2] = 0x00;
> +    pci_conf[0xa3] = 0x00;
> +    pci_conf[0xa4] = 0x00;
> +    pci_conf[0xa5] = 0x00;
> +    pci_conf[0xa6] = 0x00;
> +    pci_conf[0xa7] = 0x00;
> +    pci_conf[0xa8] = 0x0f;
> +    pci_conf[0xaa] = 0x00;
> +    pci_conf[0xab] = 0x00;
> +    pci_conf[0xac] = 0x00;
> +    pci_conf[0xae] = 0x00;
> +
> +    d->pic_levels = 0;
> +    d->rcr = 0;
> +}
> +
> +static int piix3_post_load(void *opaque, int version_id)
> +{
> +    PIIX3State *piix3 = opaque;
> +    int pirq;
> +
> +    /*
> +     * Because the i8259 has not been deserialized yet, qemu_irq_raise
> +     * might bring the system to a different state than the saved one;
> +     * for example, the interrupt could be masked but the i8259 would
> +     * not know that yet and would trigger an interrupt in the CPU.
> +     *
> +     * Here, we update irq levels without raising the interrupt.
> +     * Interrupt state will be deserialized separately through the i8259.
> +     */
> +    piix3->pic_levels = 0;
> +    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> +        piix3_set_irq_level_internal(piix3, pirq,
> +            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
> +    }
> +    return 0;
> +}
> +
> +static int piix3_pre_save(void *opaque)
> +{
> +    int i;
> +    PIIX3State *piix3 = opaque;
> +
> +    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
> +        piix3->pci_irq_levels_vmstate[i] =
> +            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
> +    }
> +
> +    return 0;
> +}
> +
> +static bool piix3_rcr_needed(void *opaque)
> +{
> +    PIIX3State *piix3 = opaque;
> +
> +    return (piix3->rcr != 0);
> +}
> +
> +static const VMStateDescription vmstate_piix3_rcr = {
> +    .name = "PIIX3/rcr",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = piix3_rcr_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT8(rcr, PIIX3State),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static const VMStateDescription vmstate_piix3 = {
> +    .name = "PIIX3",
> +    .version_id = 3,
> +    .minimum_version_id = 2,
> +    .post_load = piix3_post_load,
> +    .pre_save = piix3_pre_save,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_PCI_DEVICE(dev, PIIX3State),
> +        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
> +                              PIIX_NUM_PIRQS, 3),
> +        VMSTATE_END_OF_LIST()
> +    },
> +    .subsections = (const VMStateDescription*[]) {
> +        &vmstate_piix3_rcr,
> +        NULL
> +    }
> +};
> +
> +
> +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned
> len)
> +{
> +    PIIX3State *d = opaque;
> +
> +    if (val & 4) {
> +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +        return;
> +    }
> +    d->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
> +{
> +    PIIX3State *d = opaque;
> +
> +    return d->rcr;
> +}
> +
> +static const MemoryRegionOps rcr_ops = {
> +    .read = rcr_read,
> +    .write = rcr_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN
> +};
> +
> +static void piix3_realize(PCIDevice *dev, Error **errp)
> +{
> +    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
> +
> +    if (!isa_bus_new(DEVICE(d), get_system_memory(),
> +                     pci_address_space_io(dev), errp)) {
> +        return;
> +    }
> +
> +    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
> +                          "piix3-reset-control", 1);
> +    memory_region_add_subregion_overlap(pci_address_space_io(dev),
> RCR_IOPORT,
> +                                        &d->rcr_mem, 1);
> +
> +    qemu_register_reset(piix3_reset, d);
> +}
> +
> +static void pci_piix3_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    dc->desc        = "ISA bridge";
> +    dc->vmsd        = &vmstate_piix3;
> +    dc->hotpluggable   = false;
> +    k->realize      = piix3_realize;
> +    k->vendor_id    = PCI_VENDOR_ID_INTEL;
> +    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
> +    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
> +    k->class_id     = PCI_CLASS_BRIDGE_ISA;
> +    /*
> +     * Reason: part of PIIX3 southbridge, needs to be wired up by
> +     * pc_piix.c's pc_init1()
> +     */
> +    dc->user_creatable = false;
> +}
> +
> +static const TypeInfo piix3_pci_type_info = {
> +    .name = TYPE_PIIX3_PCI_DEVICE,
> +    .parent = TYPE_PCI_DEVICE,
> +    .instance_size = sizeof(PIIX3State),
> +    .abstract = true,
> +    .class_init = pci_piix3_class_init,
> +    .interfaces = (InterfaceInfo[]) {
> +        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> +        { },
> +    },
> +};
> +
> +static void piix3_class_init(ObjectClass *klass, void *data)
> +{
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    k->config_write = piix3_write_config;
> +}
> +
> +static const TypeInfo piix3_info = {
> +    .name          = TYPE_PIIX3_DEVICE,
> +    .parent        = TYPE_PIIX3_PCI_DEVICE,
> +    .class_init    = piix3_class_init,
> +};
> +
> +static void piix3_xen_class_init(ObjectClass *klass, void *data)
> +{
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    k->config_write = piix3_write_config_xen;
> +};
> +
> +static const TypeInfo piix3_xen_info = {
> +    .name          = TYPE_PIIX3_XEN_DEVICE,
> +    .parent        = TYPE_PIIX3_PCI_DEVICE,
> +    .class_init    = piix3_xen_class_init,
> +};
> +
> +static void piix3_register_types(void)
> +{
> +    type_register_static(&piix3_pci_type_info);
> +    type_register_static(&piix3_info);
> +    type_register_static(&piix3_xen_info);
> +}
> +
> +type_init(piix3_register_types)
> +
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise mapping.
> + */
> +static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> +{
> +    int slot_addend;
> +    slot_addend = (pci_dev->devfn >> 3) - 1;
> +    return (pci_intx + slot_addend) & 3;
> +}
> +
> +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> +    PIIX3State *piix3;
> +    PCIDevice *pci_dev;
> +
> +    /*
> +     * Xen supports additional interrupt routes from the PCI devices to
> +     * the IOAPIC: the four pins of each PCI device on the bus are also
> +     * connected to the IOAPIC directly.
> +     * These additional routes can be discovered through ACPI.
> +     */
> +    if (xen_enabled()) {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_XEN_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> +                     piix3, XEN_PIIX_NUM_PIRQS);
> +    } else {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> +                     piix3, PIIX_NUM_PIRQS);
> +        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> +    }
> +    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> +    return piix3;
> +}
> diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
> index 1edc1a31d4..397043b289 100644
> --- a/hw/pci-host/Kconfig
> +++ b/hw/pci-host/Kconfig
> @@ -32,7 +32,6 @@ config PCI_PIIX
>      bool
>      select PCI
>      select PAM
> -    select ISA_BUS
>
>  config PCI_EXPRESS_Q35
>      bool
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 61f91ff561..79ecd58a2b 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -24,22 +24,15 @@
>
>  #include "qemu/osdep.h"
>  #include "hw/i386/pc.h"
> -#include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "qapi/error.h"
> -#include "qemu/range.h"
> -#include "hw/xen/xen.h"
>  #include "migration/vmstate.h"
>  #include "hw/pci-host/pam.h"
> -#include "sysemu/reset.h"
> -#include "sysemu/runstate.h"
> -#include "hw/i386/ioapic.h"
>  #include "qapi/visitor.h"
>  #include "qemu/error-report.h"
>
> @@ -59,49 +52,9 @@ typedef struct I440FXState {
>      uint32_t short_root_bus;
>  } I440FXState;
>
> -#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
> -#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
> -#define XEN_PIIX_NUM_PIRQS      128ULL
> -
> -typedef struct PIIX3State {
> -    PCIDevice dev;
> -
> -    /*
> -     * bitmap to track pic levels.
> -     * The pic level is the logical OR of all the PCI irqs mapped to it
> -     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
> -     *
> -     * PIRQ is mapped to PIC pins, we track it by
> -     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
> -     * pic_irq * PIIX_NUM_PIRQS + pirq
> -     */
> -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
> -#error "unable to encode pic state in 64bit in pic_levels."
> -#endif
> -    uint64_t pic_levels;
> -
> -    qemu_irq *pic;
> -
> -    /* This member isn't used. Just for save/load compatibility */
> -    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> -
> -    /* Reset Control Register contents */
> -    uint8_t rcr;
> -
> -    /* IO memory region for Reset Control Register (RCR_IOPORT) */
> -    MemoryRegion rcr_mem;
> -} PIIX3State;
> -
> -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
> -#define PIIX3_PCI_DEVICE(obj) \
> -    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
> -
>  #define I440FX_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
>
> -#define TYPE_PIIX3_DEVICE "PIIX3"
> -#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
> -
>  struct PCII440FXState {
>      /*< private >*/
>      PCIDevice parent_obj;
> @@ -128,22 +81,6 @@ struct PCII440FXState {
>   */
>  #define I440FX_COREBOOT_RAM_SIZE 0x57
>
> -static void piix3_set_irq(void *opaque, int pirq, int level);
> -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int
> pci_intx);
> -static void piix3_write_config_xen(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len);
> -
> -/*
> - * Return the global irq number corresponding to a given device irq
> - * pin. We could also use the bus number to have a more precise mapping.
> - */
> -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> -{
> -    int slot_addend;
> -    slot_addend = (pci_dev->devfn >> 3) - 1;
> -    return (pci_intx + slot_addend) & 3;
> -}
> -
>  static void i440fx_update_memory_mappings(PCII440FXState *d)
>  {
>      int i;
> @@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>      }
>  }
>
> -static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> -{
> -    PIIX3State *piix3;
> -    PCIDevice *pci_dev;
> -
> -    /*
> -     * Xen supports additional interrupt routes from the PCI devices to
> -     * the IOAPIC: the four pins of each PCI device on the bus are also
> -     * connected to the IOAPIC directly.
> -     * These additional routes can be discovered through ACPI.
> -     */
> -    if (xen_enabled()) {
> -        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> -                                                  TYPE_PIIX3_XEN_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> -                     piix3, XEN_PIIX_NUM_PIRQS);
> -    } else {
> -        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> -                                                  TYPE_PIIX3_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> -                     piix3, PIIX_NUM_PIRQS);
> -        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> -    }
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
> -    return piix3;
> -}
> -
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state,
>                      int *piix3_devfn,
> @@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
>      return s ? s->bus : NULL;
>  }
>
> -/* PIIX3 PCI to ISA bridge */
> -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> -{
> -    qemu_set_irq(piix3->pic[pic_irq],
> -                 !!(piix3->pic_levels &
> -                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
> -                     (pic_irq * PIIX_NUM_PIRQS))));
> -}
> -
> -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq,
> int level)
> -{
> -    int pic_irq;
> -    uint64_t mask;
> -
> -    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> -    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> -        return;
> -    }
> -
> -    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
> -    piix3->pic_levels &= ~mask;
> -    piix3->pic_levels |= mask * !!level;
> -}
> -
> -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
> -{
> -    int pic_irq;
> -
> -    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> -    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> -        return;
> -    }
> -
> -    piix3_set_irq_level_internal(piix3, pirq, level);
> -
> -    piix3_set_irq_pic(piix3, pic_irq);
> -}
> -
> -static void piix3_set_irq(void *opaque, int pirq, int level)
> -{
> -    PIIX3State *piix3 = opaque;
> -    piix3_set_irq_level(piix3, pirq, level);
> -}
> -
> -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
> -{
> -    PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
> -    PCIINTxRoute route;
> -
> -    if (irq < PIIX_NUM_PIC_IRQS) {
> -        route.mode = PCI_INTX_ENABLED;
> -        route.irq = irq;
> -    } else {
> -        route.mode = PCI_INTX_DISABLED;
> -        route.irq = -1;
> -    }
> -    return route;
> -}
> -
> -/* irq routing is changed. so rebuild bitmap */
> -static void piix3_update_irq_levels(PIIX3State *piix3)
> -{
> -    PCIBus *bus = pci_get_bus(&piix3->dev);
> -    int pirq;
> -
> -    piix3->pic_levels = 0;
> -    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> -        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus,
> pirq));
> -    }
> -}
> -
> -static void piix3_write_config(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len)
> -{
> -    pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
> -        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
> -        int pic_irq;
> -
> -        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
> -        piix3_update_irq_levels(piix3);
> -        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
> -            piix3_set_irq_pic(piix3, pic_irq);
> -        }
> -    }
> -}
> -
> -static void piix3_write_config_xen(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len)
> -{
> -    xen_piix_pci_write_config_client(address, val, len);
> -    piix3_write_config(dev, address, val, len);
> -}
> -
> -static void piix3_reset(void *opaque)
> -{
> -    PIIX3State *d = opaque;
> -    uint8_t *pci_conf = d->dev.config;
> -
> -    pci_conf[0x04] = 0x07; /* master, memory and I/O */
> -    pci_conf[0x05] = 0x00;
> -    pci_conf[0x06] = 0x00;
> -    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
> -    pci_conf[0x4c] = 0x4d;
> -    pci_conf[0x4e] = 0x03;
> -    pci_conf[0x4f] = 0x00;
> -    pci_conf[0x60] = 0x80;
> -    pci_conf[0x61] = 0x80;
> -    pci_conf[0x62] = 0x80;
> -    pci_conf[0x63] = 0x80;
> -    pci_conf[0x69] = 0x02;
> -    pci_conf[0x70] = 0x80;
> -    pci_conf[0x76] = 0x0c;
> -    pci_conf[0x77] = 0x0c;
> -    pci_conf[0x78] = 0x02;
> -    pci_conf[0x79] = 0x00;
> -    pci_conf[0x80] = 0x00;
> -    pci_conf[0x82] = 0x00;
> -    pci_conf[0xa0] = 0x08;
> -    pci_conf[0xa2] = 0x00;
> -    pci_conf[0xa3] = 0x00;
> -    pci_conf[0xa4] = 0x00;
> -    pci_conf[0xa5] = 0x00;
> -    pci_conf[0xa6] = 0x00;
> -    pci_conf[0xa7] = 0x00;
> -    pci_conf[0xa8] = 0x0f;
> -    pci_conf[0xaa] = 0x00;
> -    pci_conf[0xab] = 0x00;
> -    pci_conf[0xac] = 0x00;
> -    pci_conf[0xae] = 0x00;
> -
> -    d->pic_levels = 0;
> -    d->rcr = 0;
> -}
> -
> -static int piix3_post_load(void *opaque, int version_id)
> -{
> -    PIIX3State *piix3 = opaque;
> -    int pirq;
> -
> -    /* Because the i8259 has not been deserialized yet, qemu_irq_raise
> -     * might bring the system to a different state than the saved one;
> -     * for example, the interrupt could be masked but the i8259 would
> -     * not know that yet and would trigger an interrupt in the CPU.
> -     *
> -     * Here, we update irq levels without raising the interrupt.
> -     * Interrupt state will be deserialized separately through the i8259.
> -     */
> -    piix3->pic_levels = 0;
> -    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> -        piix3_set_irq_level_internal(piix3, pirq,
> -            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
> -    }
> -    return 0;
> -}
> -
> -static int piix3_pre_save(void *opaque)
> -{
> -    int i;
> -    PIIX3State *piix3 = opaque;
> -
> -    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
> -        piix3->pci_irq_levels_vmstate[i] =
> -            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
> -    }
> -
> -    return 0;
> -}
> -
> -static bool piix3_rcr_needed(void *opaque)
> -{
> -    PIIX3State *piix3 = opaque;
> -
> -    return (piix3->rcr != 0);
> -}
> -
> -static const VMStateDescription vmstate_piix3_rcr = {
> -    .name = "PIIX3/rcr",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> -    .needed = piix3_rcr_needed,
> -    .fields = (VMStateField[]) {
> -        VMSTATE_UINT8(rcr, PIIX3State),
> -        VMSTATE_END_OF_LIST()
> -    }
> -};
> -
> -static const VMStateDescription vmstate_piix3 = {
> -    .name = "PIIX3",
> -    .version_id = 3,
> -    .minimum_version_id = 2,
> -    .post_load = piix3_post_load,
> -    .pre_save = piix3_pre_save,
> -    .fields = (VMStateField[]) {
> -        VMSTATE_PCI_DEVICE(dev, PIIX3State),
> -        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
> -                              PIIX_NUM_PIRQS, 3),
> -        VMSTATE_END_OF_LIST()
> -    },
> -    .subsections = (const VMStateDescription*[]) {
> -        &vmstate_piix3_rcr,
> -        NULL
> -    }
> -};
> -
> -
> -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned
> len)
> -{
> -    PIIX3State *d = opaque;
> -
> -    if (val & 4) {
> -        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> -        return;
> -    }
> -    d->rcr = val & 2; /* keep System Reset type only */
> -}
> -
> -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
> -{
> -    PIIX3State *d = opaque;
> -
> -    return d->rcr;
> -}
> -
> -static const MemoryRegionOps rcr_ops = {
> -    .read = rcr_read,
> -    .write = rcr_write,
> -    .endianness = DEVICE_LITTLE_ENDIAN
> -};
> -
> -static void piix3_realize(PCIDevice *dev, Error **errp)
> -{
> -    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
> -
> -    if (!isa_bus_new(DEVICE(d), get_system_memory(),
> -                     pci_address_space_io(dev), errp)) {
> -        return;
> -    }
> -
> -    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
> -                          "piix3-reset-control", 1);
> -    memory_region_add_subregion_overlap(pci_address_space_io(dev),
> RCR_IOPORT,
> -                                        &d->rcr_mem, 1);
> -
> -    qemu_register_reset(piix3_reset, d);
> -}
> -
> -static void pci_piix3_class_init(ObjectClass *klass, void *data)
> -{
> -    DeviceClass *dc = DEVICE_CLASS(klass);
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    dc->desc        = "ISA bridge";
> -    dc->vmsd        = &vmstate_piix3;
> -    dc->hotpluggable   = false;
> -    k->realize      = piix3_realize;
> -    k->vendor_id    = PCI_VENDOR_ID_INTEL;
> -    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
> -    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
> -    k->class_id     = PCI_CLASS_BRIDGE_ISA;
> -    /*
> -     * Reason: part of PIIX3 southbridge, needs to be wired up by
> -     * pc_piix.c's pc_init1()
> -     */
> -    dc->user_creatable = false;
> -}
> -
> -static const TypeInfo piix3_pci_type_info = {
> -    .name = TYPE_PIIX3_PCI_DEVICE,
> -    .parent = TYPE_PCI_DEVICE,
> -    .instance_size = sizeof(PIIX3State),
> -    .abstract = true,
> -    .class_init = pci_piix3_class_init,
> -    .interfaces = (InterfaceInfo[]) {
> -        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> -        { },
> -    },
> -};
> -
> -static void piix3_class_init(ObjectClass *klass, void *data)
> -{
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    k->config_write = piix3_write_config;
> -}
> -
> -static const TypeInfo piix3_info = {
> -    .name          = TYPE_PIIX3_DEVICE,
> -    .parent        = TYPE_PIIX3_PCI_DEVICE,
> -    .class_init    = piix3_class_init,
> -};
> -
> -static void piix3_xen_class_init(ObjectClass *klass, void *data)
> -{
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    k->config_write = piix3_write_config_xen;
> -};
> -
> -static const TypeInfo piix3_xen_info = {
> -    .name          = TYPE_PIIX3_XEN_DEVICE,
> -    .parent        = TYPE_PIIX3_PCI_DEVICE,
> -    .class_init    = piix3_xen_class_init,
> -};
> -
>  static void i440fx_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -922,9 +523,6 @@ static void i440fx_register_types(void)
>  {
>      type_register_static(&i440fx_info);
>      type_register_static(&igd_passthrough_i440fx_info);
> -    type_register_static(&piix3_pci_type_info);
> -    type_register_static(&piix3_info);
> -    type_register_static(&piix3_xen_info);
>      type_register_static(&i440fx_pcihost_info);
>  }
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 9c92c37a4d..324a3a99fc 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -12,6 +12,8 @@
>  #ifndef HW_SOUTHBRIDGE_PIIX_H
>  #define HW_SOUTHBRIDGE_PIIX_H
>
> +#include "hw/pci/pci.h"
> +
>  #define TYPE_PIIX4_PM "PIIX4_PM"
>
>  I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> @@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>   */
>  #define RCR_IOPORT 0xcf9
>
> +#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
> +#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
> +
> +typedef struct PIIXState {
> +    PCIDevice dev;
> +
> +    /*
> +     * bitmap to track pic levels.
> +     * The pic level is the logical OR of all the PCI irqs mapped to it
> +     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
> +     *
> +     * PIRQ is mapped to PIC pins, we track it by
> +     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
> +     * pic_irq * PIIX_NUM_PIRQS + pirq
> +     */
> +#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
> +#error "unable to encode pic state in 64bit in pic_levels."
> +#endif
> +    uint64_t pic_levels;
> +
> +    qemu_irq *pic;
> +
> +    /* This member isn't used. Just for save/load compatibility */
> +    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> +
> +    /* Reset Control Register contents */
> +    uint8_t rcr;
> +
> +    /* IO memory region for Reset Control Register (RCR_IOPORT) */
> +    MemoryRegion rcr_mem;
> +} PIIX3State;
> +
>  extern PCIDevice *piix4_dev;
>
> +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
> +
>  DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>                            I2CBus **smbus, size_t ide_buses);
>
> --
> 2.21.0
>
>
>

[-- Attachment #2: Type: text/html, Size: 39301 bytes --]

Re: [Xen-devel] [PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 33311 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Move all the PIIX3 functions to a new file: hw/isa/piix3.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Checkpatch warning:
>
>  ERROR: spaces required around that '*' (ctx:VxV)
>  #312: FILE: hw/isa/piix3.c:248:
>  +    .subsections = (const VMStateDescription*[]) {
>                                               ^
> ---
>  MAINTAINERS                   |   1 +
>  hw/i386/Kconfig               |   1 +
>  hw/isa/Kconfig                |   4 +
>  hw/isa/Makefile.objs          |   1 +
>  hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
>  hw/pci-host/Kconfig           |   1 -
>  hw/pci-host/piix.c            | 402 ----------------------------------
>  include/hw/southbridge/piix.h |  36 +++
>  8 files changed, 442 insertions(+), 403 deletions(-)
>  create mode 100644 hw/isa/piix3.c
>
>

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/MAINTAINERS b/MAINTAINERS
> index adf059a164..4845f47d93 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
>  F: include/hw/pci-host/i440fx.h
>  F: include/hw/pci-host/q35.h
>  F: include/hw/pci-host/pam.h
> +F: hw/isa/piix3.c
>  F: hw/isa/lpc_ich9.c
>  F: hw/i2c/smbus_ich9.c
>  F: hw/acpi/piix4.c
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index c5c9d4900e..589d75e26a 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -61,6 +61,7 @@ config I440FX
>      select PC_ACPI
>      select ACPI_SMBUS
>      select PCI_PIIX
> +    select PIIX3
>      select IDE_PIIX
>      select DIMM
>      select SMBIOS
> diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
> index 98a289957e..8a38813cc1 100644
> --- a/hw/isa/Kconfig
> +++ b/hw/isa/Kconfig
> @@ -29,6 +29,10 @@ config PC87312
>      select FDC
>      select IDE_ISA
>
> +config PIIX3
> +    bool
> +    select ISA_BUS
> +
>  config PIIX4
>      bool
>      # For historical reasons, SuperIO devices are created in the board
> diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
> index ff97485504..8e73960a75 100644
> --- a/hw/isa/Makefile.objs
> +++ b/hw/isa/Makefile.objs
> @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
>  common-obj-$(CONFIG_APM) += apm.o
>  common-obj-$(CONFIG_I82378) += i82378.o
>  common-obj-$(CONFIG_PC87312) += pc87312.o
> +common-obj-$(CONFIG_PIIX3) += piix3.o
>  common-obj-$(CONFIG_PIIX4) += piix4.o
>  common-obj-$(CONFIG_VT82C686) += vt82c686.o
>  common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
> diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
> new file mode 100644
> index 0000000000..05146447ef
> --- /dev/null
> +++ b/hw/isa/piix3.c
> @@ -0,0 +1,399 @@
> +/*
> + * QEMU PIIX PCI ISA Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> + * of this software and associated documentation files (the "Software"),
> to deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/range.h"
> +#include "hw/southbridge/piix.h"
> +#include "hw/irq.h"
> +#include "hw/isa/isa.h"
> +#include "hw/xen/xen.h"
> +#include "sysemu/sysemu.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
> +#include "migration/vmstate.h"
> +
> +#define XEN_PIIX_NUM_PIRQS      128ULL
> +
> +#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
> +#define PIIX3_PCI_DEVICE(obj) \
> +    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
> +
> +#define TYPE_PIIX3_DEVICE "PIIX3"
> +#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
> +
> +static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> +{
> +    qemu_set_irq(piix3->pic[pic_irq],
> +                 !!(piix3->pic_levels &
> +                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
> +                     (pic_irq * PIIX_NUM_PIRQS))));
> +}
> +
> +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq,
> int level)
> +{
> +    int pic_irq;
> +    uint64_t mask;
> +
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> +    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> +        return;
> +    }
> +
> +    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
> +    piix3->pic_levels &= ~mask;
> +    piix3->pic_levels |= mask * !!level;
> +}
> +
> +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
> +{
> +    int pic_irq;
> +
> +    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> +    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> +        return;
> +    }
> +
> +    piix3_set_irq_level_internal(piix3, pirq, level);
> +
> +    piix3_set_irq_pic(piix3, pic_irq);
> +}
> +
> +static void piix3_set_irq(void *opaque, int pirq, int level)
> +{
> +    PIIX3State *piix3 = opaque;
> +    piix3_set_irq_level(piix3, pirq, level);
> +}
> +
> +static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
> +{
> +    PIIX3State *piix3 = opaque;
> +    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
> +    PCIINTxRoute route;
> +
> +    if (irq < PIIX_NUM_PIC_IRQS) {
> +        route.mode = PCI_INTX_ENABLED;
> +        route.irq = irq;
> +    } else {
> +        route.mode = PCI_INTX_DISABLED;
> +        route.irq = -1;
> +    }
> +    return route;
> +}
> +
> +/* irq routing is changed. so rebuild bitmap */
> +static void piix3_update_irq_levels(PIIX3State *piix3)
> +{
> +    PCIBus *bus = pci_get_bus(&piix3->dev);
> +    int pirq;
> +
> +    piix3->pic_levels = 0;
> +    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> +        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus,
> pirq));
> +    }
> +}
> +
> +static void piix3_write_config(PCIDevice *dev,
> +                               uint32_t address, uint32_t val, int len)
> +{
> +    pci_default_write_config(dev, address, val, len);
> +    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
> +        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
> +        int pic_irq;
> +
> +        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
> +        piix3_update_irq_levels(piix3);
> +        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
> +            piix3_set_irq_pic(piix3, pic_irq);
> +        }
> +    }
> +}
> +
> +static void piix3_write_config_xen(PCIDevice *dev,
> +                                   uint32_t address, uint32_t val, int
> len)
> +{
> +    xen_piix_pci_write_config_client(address, val, len);
> +    piix3_write_config(dev, address, val, len);
> +}
> +
> +static void piix3_reset(void *opaque)
> +{
> +    PIIX3State *d = opaque;
> +    uint8_t *pci_conf = d->dev.config;
> +
> +    pci_conf[0x04] = 0x07; /* master, memory and I/O */
> +    pci_conf[0x05] = 0x00;
> +    pci_conf[0x06] = 0x00;
> +    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
> +    pci_conf[0x4c] = 0x4d;
> +    pci_conf[0x4e] = 0x03;
> +    pci_conf[0x4f] = 0x00;
> +    pci_conf[0x60] = 0x80;
> +    pci_conf[0x61] = 0x80;
> +    pci_conf[0x62] = 0x80;
> +    pci_conf[0x63] = 0x80;
> +    pci_conf[0x69] = 0x02;
> +    pci_conf[0x70] = 0x80;
> +    pci_conf[0x76] = 0x0c;
> +    pci_conf[0x77] = 0x0c;
> +    pci_conf[0x78] = 0x02;
> +    pci_conf[0x79] = 0x00;
> +    pci_conf[0x80] = 0x00;
> +    pci_conf[0x82] = 0x00;
> +    pci_conf[0xa0] = 0x08;
> +    pci_conf[0xa2] = 0x00;
> +    pci_conf[0xa3] = 0x00;
> +    pci_conf[0xa4] = 0x00;
> +    pci_conf[0xa5] = 0x00;
> +    pci_conf[0xa6] = 0x00;
> +    pci_conf[0xa7] = 0x00;
> +    pci_conf[0xa8] = 0x0f;
> +    pci_conf[0xaa] = 0x00;
> +    pci_conf[0xab] = 0x00;
> +    pci_conf[0xac] = 0x00;
> +    pci_conf[0xae] = 0x00;
> +
> +    d->pic_levels = 0;
> +    d->rcr = 0;
> +}
> +
> +static int piix3_post_load(void *opaque, int version_id)
> +{
> +    PIIX3State *piix3 = opaque;
> +    int pirq;
> +
> +    /*
> +     * Because the i8259 has not been deserialized yet, qemu_irq_raise
> +     * might bring the system to a different state than the saved one;
> +     * for example, the interrupt could be masked but the i8259 would
> +     * not know that yet and would trigger an interrupt in the CPU.
> +     *
> +     * Here, we update irq levels without raising the interrupt.
> +     * Interrupt state will be deserialized separately through the i8259.
> +     */
> +    piix3->pic_levels = 0;
> +    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> +        piix3_set_irq_level_internal(piix3, pirq,
> +            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
> +    }
> +    return 0;
> +}
> +
> +static int piix3_pre_save(void *opaque)
> +{
> +    int i;
> +    PIIX3State *piix3 = opaque;
> +
> +    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
> +        piix3->pci_irq_levels_vmstate[i] =
> +            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
> +    }
> +
> +    return 0;
> +}
> +
> +static bool piix3_rcr_needed(void *opaque)
> +{
> +    PIIX3State *piix3 = opaque;
> +
> +    return (piix3->rcr != 0);
> +}
> +
> +static const VMStateDescription vmstate_piix3_rcr = {
> +    .name = "PIIX3/rcr",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = piix3_rcr_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT8(rcr, PIIX3State),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static const VMStateDescription vmstate_piix3 = {
> +    .name = "PIIX3",
> +    .version_id = 3,
> +    .minimum_version_id = 2,
> +    .post_load = piix3_post_load,
> +    .pre_save = piix3_pre_save,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_PCI_DEVICE(dev, PIIX3State),
> +        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
> +                              PIIX_NUM_PIRQS, 3),
> +        VMSTATE_END_OF_LIST()
> +    },
> +    .subsections = (const VMStateDescription*[]) {
> +        &vmstate_piix3_rcr,
> +        NULL
> +    }
> +};
> +
> +
> +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned
> len)
> +{
> +    PIIX3State *d = opaque;
> +
> +    if (val & 4) {
> +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +        return;
> +    }
> +    d->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
> +{
> +    PIIX3State *d = opaque;
> +
> +    return d->rcr;
> +}
> +
> +static const MemoryRegionOps rcr_ops = {
> +    .read = rcr_read,
> +    .write = rcr_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN
> +};
> +
> +static void piix3_realize(PCIDevice *dev, Error **errp)
> +{
> +    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
> +
> +    if (!isa_bus_new(DEVICE(d), get_system_memory(),
> +                     pci_address_space_io(dev), errp)) {
> +        return;
> +    }
> +
> +    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
> +                          "piix3-reset-control", 1);
> +    memory_region_add_subregion_overlap(pci_address_space_io(dev),
> RCR_IOPORT,
> +                                        &d->rcr_mem, 1);
> +
> +    qemu_register_reset(piix3_reset, d);
> +}
> +
> +static void pci_piix3_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    dc->desc        = "ISA bridge";
> +    dc->vmsd        = &vmstate_piix3;
> +    dc->hotpluggable   = false;
> +    k->realize      = piix3_realize;
> +    k->vendor_id    = PCI_VENDOR_ID_INTEL;
> +    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
> +    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
> +    k->class_id     = PCI_CLASS_BRIDGE_ISA;
> +    /*
> +     * Reason: part of PIIX3 southbridge, needs to be wired up by
> +     * pc_piix.c's pc_init1()
> +     */
> +    dc->user_creatable = false;
> +}
> +
> +static const TypeInfo piix3_pci_type_info = {
> +    .name = TYPE_PIIX3_PCI_DEVICE,
> +    .parent = TYPE_PCI_DEVICE,
> +    .instance_size = sizeof(PIIX3State),
> +    .abstract = true,
> +    .class_init = pci_piix3_class_init,
> +    .interfaces = (InterfaceInfo[]) {
> +        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> +        { },
> +    },
> +};
> +
> +static void piix3_class_init(ObjectClass *klass, void *data)
> +{
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    k->config_write = piix3_write_config;
> +}
> +
> +static const TypeInfo piix3_info = {
> +    .name          = TYPE_PIIX3_DEVICE,
> +    .parent        = TYPE_PIIX3_PCI_DEVICE,
> +    .class_init    = piix3_class_init,
> +};
> +
> +static void piix3_xen_class_init(ObjectClass *klass, void *data)
> +{
> +    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> +    k->config_write = piix3_write_config_xen;
> +};
> +
> +static const TypeInfo piix3_xen_info = {
> +    .name          = TYPE_PIIX3_XEN_DEVICE,
> +    .parent        = TYPE_PIIX3_PCI_DEVICE,
> +    .class_init    = piix3_xen_class_init,
> +};
> +
> +static void piix3_register_types(void)
> +{
> +    type_register_static(&piix3_pci_type_info);
> +    type_register_static(&piix3_info);
> +    type_register_static(&piix3_xen_info);
> +}
> +
> +type_init(piix3_register_types)
> +
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise mapping.
> + */
> +static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> +{
> +    int slot_addend;
> +    slot_addend = (pci_dev->devfn >> 3) - 1;
> +    return (pci_intx + slot_addend) & 3;
> +}
> +
> +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> +    PIIX3State *piix3;
> +    PCIDevice *pci_dev;
> +
> +    /*
> +     * Xen supports additional interrupt routes from the PCI devices to
> +     * the IOAPIC: the four pins of each PCI device on the bus are also
> +     * connected to the IOAPIC directly.
> +     * These additional routes can be discovered through ACPI.
> +     */
> +    if (xen_enabled()) {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_XEN_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> +                     piix3, XEN_PIIX_NUM_PIRQS);
> +    } else {
> +        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> +                                                  TYPE_PIIX3_DEVICE);
> +        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> +        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> +                     piix3, PIIX_NUM_PIRQS);
> +        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> +    }
> +    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> +    return piix3;
> +}
> diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
> index 1edc1a31d4..397043b289 100644
> --- a/hw/pci-host/Kconfig
> +++ b/hw/pci-host/Kconfig
> @@ -32,7 +32,6 @@ config PCI_PIIX
>      bool
>      select PCI
>      select PAM
> -    select ISA_BUS
>
>  config PCI_EXPRESS_Q35
>      bool
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 61f91ff561..79ecd58a2b 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -24,22 +24,15 @@
>
>  #include "qemu/osdep.h"
>  #include "hw/i386/pc.h"
> -#include "hw/irq.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci/pci_host.h"
>  #include "hw/pci-host/i440fx.h"
>  #include "hw/southbridge/piix.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/isa/isa.h"
>  #include "hw/sysbus.h"
>  #include "qapi/error.h"
> -#include "qemu/range.h"
> -#include "hw/xen/xen.h"
>  #include "migration/vmstate.h"
>  #include "hw/pci-host/pam.h"
> -#include "sysemu/reset.h"
> -#include "sysemu/runstate.h"
> -#include "hw/i386/ioapic.h"
>  #include "qapi/visitor.h"
>  #include "qemu/error-report.h"
>
> @@ -59,49 +52,9 @@ typedef struct I440FXState {
>      uint32_t short_root_bus;
>  } I440FXState;
>
> -#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
> -#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
> -#define XEN_PIIX_NUM_PIRQS      128ULL
> -
> -typedef struct PIIX3State {
> -    PCIDevice dev;
> -
> -    /*
> -     * bitmap to track pic levels.
> -     * The pic level is the logical OR of all the PCI irqs mapped to it
> -     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
> -     *
> -     * PIRQ is mapped to PIC pins, we track it by
> -     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
> -     * pic_irq * PIIX_NUM_PIRQS + pirq
> -     */
> -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
> -#error "unable to encode pic state in 64bit in pic_levels."
> -#endif
> -    uint64_t pic_levels;
> -
> -    qemu_irq *pic;
> -
> -    /* This member isn't used. Just for save/load compatibility */
> -    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> -
> -    /* Reset Control Register contents */
> -    uint8_t rcr;
> -
> -    /* IO memory region for Reset Control Register (RCR_IOPORT) */
> -    MemoryRegion rcr_mem;
> -} PIIX3State;
> -
> -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
> -#define PIIX3_PCI_DEVICE(obj) \
> -    OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
> -
>  #define I440FX_PCI_DEVICE(obj) \
>      OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
>
> -#define TYPE_PIIX3_DEVICE "PIIX3"
> -#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
> -
>  struct PCII440FXState {
>      /*< private >*/
>      PCIDevice parent_obj;
> @@ -128,22 +81,6 @@ struct PCII440FXState {
>   */
>  #define I440FX_COREBOOT_RAM_SIZE 0x57
>
> -static void piix3_set_irq(void *opaque, int pirq, int level);
> -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int
> pci_intx);
> -static void piix3_write_config_xen(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len);
> -
> -/*
> - * Return the global irq number corresponding to a given device irq
> - * pin. We could also use the bus number to have a more precise mapping.
> - */
> -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> -{
> -    int slot_addend;
> -    slot_addend = (pci_dev->devfn >> 3) - 1;
> -    return (pci_intx + slot_addend) & 3;
> -}
> -
>  static void i440fx_update_memory_mappings(PCII440FXState *d)
>  {
>      int i;
> @@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>      }
>  }
>
> -static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> -{
> -    PIIX3State *piix3;
> -    PCIDevice *pci_dev;
> -
> -    /*
> -     * Xen supports additional interrupt routes from the PCI devices to
> -     * the IOAPIC: the four pins of each PCI device on the bus are also
> -     * connected to the IOAPIC directly.
> -     * These additional routes can be discovered through ACPI.
> -     */
> -    if (xen_enabled()) {
> -        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> -                                                  TYPE_PIIX3_XEN_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> -                     piix3, XEN_PIIX_NUM_PIRQS);
> -    } else {
> -        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> -                                                  TYPE_PIIX3_DEVICE);
> -        piix3 = PIIX3_PCI_DEVICE(pci_dev);
> -        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> -                     piix3, PIIX_NUM_PIRQS);
> -        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
> -    }
> -    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
> -    return piix3;
> -}
> -
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                      PCII440FXState **pi440fx_state,
>                      int *piix3_devfn,
> @@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
>      return s ? s->bus : NULL;
>  }
>
> -/* PIIX3 PCI to ISA bridge */
> -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
> -{
> -    qemu_set_irq(piix3->pic[pic_irq],
> -                 !!(piix3->pic_levels &
> -                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
> -                     (pic_irq * PIIX_NUM_PIRQS))));
> -}
> -
> -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq,
> int level)
> -{
> -    int pic_irq;
> -    uint64_t mask;
> -
> -    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> -    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> -        return;
> -    }
> -
> -    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
> -    piix3->pic_levels &= ~mask;
> -    piix3->pic_levels |= mask * !!level;
> -}
> -
> -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
> -{
> -    int pic_irq;
> -
> -    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
> -    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
> -        return;
> -    }
> -
> -    piix3_set_irq_level_internal(piix3, pirq, level);
> -
> -    piix3_set_irq_pic(piix3, pic_irq);
> -}
> -
> -static void piix3_set_irq(void *opaque, int pirq, int level)
> -{
> -    PIIX3State *piix3 = opaque;
> -    piix3_set_irq_level(piix3, pirq, level);
> -}
> -
> -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
> -{
> -    PIIX3State *piix3 = opaque;
> -    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
> -    PCIINTxRoute route;
> -
> -    if (irq < PIIX_NUM_PIC_IRQS) {
> -        route.mode = PCI_INTX_ENABLED;
> -        route.irq = irq;
> -    } else {
> -        route.mode = PCI_INTX_DISABLED;
> -        route.irq = -1;
> -    }
> -    return route;
> -}
> -
> -/* irq routing is changed. so rebuild bitmap */
> -static void piix3_update_irq_levels(PIIX3State *piix3)
> -{
> -    PCIBus *bus = pci_get_bus(&piix3->dev);
> -    int pirq;
> -
> -    piix3->pic_levels = 0;
> -    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> -        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus,
> pirq));
> -    }
> -}
> -
> -static void piix3_write_config(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len)
> -{
> -    pci_default_write_config(dev, address, val, len);
> -    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
> -        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
> -        int pic_irq;
> -
> -        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
> -        piix3_update_irq_levels(piix3);
> -        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
> -            piix3_set_irq_pic(piix3, pic_irq);
> -        }
> -    }
> -}
> -
> -static void piix3_write_config_xen(PCIDevice *dev,
> -                               uint32_t address, uint32_t val, int len)
> -{
> -    xen_piix_pci_write_config_client(address, val, len);
> -    piix3_write_config(dev, address, val, len);
> -}
> -
> -static void piix3_reset(void *opaque)
> -{
> -    PIIX3State *d = opaque;
> -    uint8_t *pci_conf = d->dev.config;
> -
> -    pci_conf[0x04] = 0x07; /* master, memory and I/O */
> -    pci_conf[0x05] = 0x00;
> -    pci_conf[0x06] = 0x00;
> -    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
> -    pci_conf[0x4c] = 0x4d;
> -    pci_conf[0x4e] = 0x03;
> -    pci_conf[0x4f] = 0x00;
> -    pci_conf[0x60] = 0x80;
> -    pci_conf[0x61] = 0x80;
> -    pci_conf[0x62] = 0x80;
> -    pci_conf[0x63] = 0x80;
> -    pci_conf[0x69] = 0x02;
> -    pci_conf[0x70] = 0x80;
> -    pci_conf[0x76] = 0x0c;
> -    pci_conf[0x77] = 0x0c;
> -    pci_conf[0x78] = 0x02;
> -    pci_conf[0x79] = 0x00;
> -    pci_conf[0x80] = 0x00;
> -    pci_conf[0x82] = 0x00;
> -    pci_conf[0xa0] = 0x08;
> -    pci_conf[0xa2] = 0x00;
> -    pci_conf[0xa3] = 0x00;
> -    pci_conf[0xa4] = 0x00;
> -    pci_conf[0xa5] = 0x00;
> -    pci_conf[0xa6] = 0x00;
> -    pci_conf[0xa7] = 0x00;
> -    pci_conf[0xa8] = 0x0f;
> -    pci_conf[0xaa] = 0x00;
> -    pci_conf[0xab] = 0x00;
> -    pci_conf[0xac] = 0x00;
> -    pci_conf[0xae] = 0x00;
> -
> -    d->pic_levels = 0;
> -    d->rcr = 0;
> -}
> -
> -static int piix3_post_load(void *opaque, int version_id)
> -{
> -    PIIX3State *piix3 = opaque;
> -    int pirq;
> -
> -    /* Because the i8259 has not been deserialized yet, qemu_irq_raise
> -     * might bring the system to a different state than the saved one;
> -     * for example, the interrupt could be masked but the i8259 would
> -     * not know that yet and would trigger an interrupt in the CPU.
> -     *
> -     * Here, we update irq levels without raising the interrupt.
> -     * Interrupt state will be deserialized separately through the i8259.
> -     */
> -    piix3->pic_levels = 0;
> -    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
> -        piix3_set_irq_level_internal(piix3, pirq,
> -            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
> -    }
> -    return 0;
> -}
> -
> -static int piix3_pre_save(void *opaque)
> -{
> -    int i;
> -    PIIX3State *piix3 = opaque;
> -
> -    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
> -        piix3->pci_irq_levels_vmstate[i] =
> -            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
> -    }
> -
> -    return 0;
> -}
> -
> -static bool piix3_rcr_needed(void *opaque)
> -{
> -    PIIX3State *piix3 = opaque;
> -
> -    return (piix3->rcr != 0);
> -}
> -
> -static const VMStateDescription vmstate_piix3_rcr = {
> -    .name = "PIIX3/rcr",
> -    .version_id = 1,
> -    .minimum_version_id = 1,
> -    .needed = piix3_rcr_needed,
> -    .fields = (VMStateField[]) {
> -        VMSTATE_UINT8(rcr, PIIX3State),
> -        VMSTATE_END_OF_LIST()
> -    }
> -};
> -
> -static const VMStateDescription vmstate_piix3 = {
> -    .name = "PIIX3",
> -    .version_id = 3,
> -    .minimum_version_id = 2,
> -    .post_load = piix3_post_load,
> -    .pre_save = piix3_pre_save,
> -    .fields = (VMStateField[]) {
> -        VMSTATE_PCI_DEVICE(dev, PIIX3State),
> -        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
> -                              PIIX_NUM_PIRQS, 3),
> -        VMSTATE_END_OF_LIST()
> -    },
> -    .subsections = (const VMStateDescription*[]) {
> -        &vmstate_piix3_rcr,
> -        NULL
> -    }
> -};
> -
> -
> -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned
> len)
> -{
> -    PIIX3State *d = opaque;
> -
> -    if (val & 4) {
> -        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> -        return;
> -    }
> -    d->rcr = val & 2; /* keep System Reset type only */
> -}
> -
> -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
> -{
> -    PIIX3State *d = opaque;
> -
> -    return d->rcr;
> -}
> -
> -static const MemoryRegionOps rcr_ops = {
> -    .read = rcr_read,
> -    .write = rcr_write,
> -    .endianness = DEVICE_LITTLE_ENDIAN
> -};
> -
> -static void piix3_realize(PCIDevice *dev, Error **errp)
> -{
> -    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
> -
> -    if (!isa_bus_new(DEVICE(d), get_system_memory(),
> -                     pci_address_space_io(dev), errp)) {
> -        return;
> -    }
> -
> -    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
> -                          "piix3-reset-control", 1);
> -    memory_region_add_subregion_overlap(pci_address_space_io(dev),
> RCR_IOPORT,
> -                                        &d->rcr_mem, 1);
> -
> -    qemu_register_reset(piix3_reset, d);
> -}
> -
> -static void pci_piix3_class_init(ObjectClass *klass, void *data)
> -{
> -    DeviceClass *dc = DEVICE_CLASS(klass);
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    dc->desc        = "ISA bridge";
> -    dc->vmsd        = &vmstate_piix3;
> -    dc->hotpluggable   = false;
> -    k->realize      = piix3_realize;
> -    k->vendor_id    = PCI_VENDOR_ID_INTEL;
> -    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
> -    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
> -    k->class_id     = PCI_CLASS_BRIDGE_ISA;
> -    /*
> -     * Reason: part of PIIX3 southbridge, needs to be wired up by
> -     * pc_piix.c's pc_init1()
> -     */
> -    dc->user_creatable = false;
> -}
> -
> -static const TypeInfo piix3_pci_type_info = {
> -    .name = TYPE_PIIX3_PCI_DEVICE,
> -    .parent = TYPE_PCI_DEVICE,
> -    .instance_size = sizeof(PIIX3State),
> -    .abstract = true,
> -    .class_init = pci_piix3_class_init,
> -    .interfaces = (InterfaceInfo[]) {
> -        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> -        { },
> -    },
> -};
> -
> -static void piix3_class_init(ObjectClass *klass, void *data)
> -{
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    k->config_write = piix3_write_config;
> -}
> -
> -static const TypeInfo piix3_info = {
> -    .name          = TYPE_PIIX3_DEVICE,
> -    .parent        = TYPE_PIIX3_PCI_DEVICE,
> -    .class_init    = piix3_class_init,
> -};
> -
> -static void piix3_xen_class_init(ObjectClass *klass, void *data)
> -{
> -    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> -    k->config_write = piix3_write_config_xen;
> -};
> -
> -static const TypeInfo piix3_xen_info = {
> -    .name          = TYPE_PIIX3_XEN_DEVICE,
> -    .parent        = TYPE_PIIX3_PCI_DEVICE,
> -    .class_init    = piix3_xen_class_init,
> -};
> -
>  static void i440fx_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -922,9 +523,6 @@ static void i440fx_register_types(void)
>  {
>      type_register_static(&i440fx_info);
>      type_register_static(&igd_passthrough_i440fx_info);
> -    type_register_static(&piix3_pci_type_info);
> -    type_register_static(&piix3_info);
> -    type_register_static(&piix3_xen_info);
>      type_register_static(&i440fx_pcihost_info);
>  }
>
> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
> index 9c92c37a4d..324a3a99fc 100644
> --- a/include/hw/southbridge/piix.h
> +++ b/include/hw/southbridge/piix.h
> @@ -12,6 +12,8 @@
>  #ifndef HW_SOUTHBRIDGE_PIIX_H
>  #define HW_SOUTHBRIDGE_PIIX_H
>
> +#include "hw/pci/pci.h"
> +
>  #define TYPE_PIIX4_PM "PIIX4_PM"
>
>  I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> @@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
> smb_io_base,
>   */
>  #define RCR_IOPORT 0xcf9
>
> +#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
> +#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
> +
> +typedef struct PIIXState {
> +    PCIDevice dev;
> +
> +    /*
> +     * bitmap to track pic levels.
> +     * The pic level is the logical OR of all the PCI irqs mapped to it
> +     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
> +     *
> +     * PIRQ is mapped to PIC pins, we track it by
> +     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
> +     * pic_irq * PIIX_NUM_PIRQS + pirq
> +     */
> +#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
> +#error "unable to encode pic state in 64bit in pic_levels."
> +#endif
> +    uint64_t pic_levels;
> +
> +    qemu_irq *pic;
> +
> +    /* This member isn't used. Just for save/load compatibility */
> +    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> +
> +    /* Reset Control Register contents */
> +    uint8_t rcr;
> +
> +    /* IO memory region for Reset Control Register (RCR_IOPORT) */
> +    MemoryRegion rcr_mem;
> +} PIIX3State;
> +
>  extern PCIDevice *piix4_dev;
>
> +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
> +
>  DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>                            I2CBus **smbus, size_t ide_buses);
>
> --
> 2.21.0
>
>
>

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Re: [PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

[Aleksandar Markovic]

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On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
> it now only contains i440FX northbridge code.
> Rename it to match the chipset modelled.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                      | 2 +-
>  hw/i386/Kconfig                  | 2 +-
>  hw/pci-host/Kconfig              | 2 +-
>  hw/pci-host/Makefile.objs        | 2 +-
>  hw/pci-host/{piix.c => i440fx.c} | 0
>  5 files changed, 4 insertions(+), 4 deletions(-)
>  rename hw/pci-host/{piix.c => i440fx.c} (100%)
>
>

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4845f47d93..1bc9959b8a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>  S: Supported
>  F: include/hw/i386/
>  F: hw/i386/
> -F: hw/pci-host/piix.c
> +F: hw/pci-host/i440fx.c
>  F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
>  F: include/hw/pci-host/i440fx.h
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index 589d75e26a..cfe94aede7 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -60,7 +60,7 @@ config I440FX
>      select PC_PCI
>      select PC_ACPI
>      select ACPI_SMBUS
> -    select PCI_PIIX
> +    select PCI_I440FX
>      select PIIX3
>      select IDE_PIIX
>      select DIMM
> diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
> index 397043b289..b0aa8351c4 100644
> --- a/hw/pci-host/Kconfig
> +++ b/hw/pci-host/Kconfig
> @@ -28,7 +28,7 @@ config PCI_SABRE
>      select PCI
>      bool
>
> -config PCI_PIIX
> +config PCI_I440FX
>      bool
>      select PCI
>      select PAM
> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
> index a9cd3e022d..efd752b766 100644
> --- a/hw/pci-host/Makefile.objs
> +++ b/hw/pci-host/Makefile.objs
> @@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
>
>  common-obj-$(CONFIG_PCI_SABRE) += sabre.o
>  common-obj-$(CONFIG_FULONG) += bonito.o
> -common-obj-$(CONFIG_PCI_PIIX) += piix.o
> +common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
>  common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
>  common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
>  common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
> similarity index 100%
> rename from hw/pci-host/piix.c
> rename to hw/pci-host/i440fx.c
> --
> 2.21.0
>
>
>

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Re: [Xen-devel] [PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 2625 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
> it now only contains i440FX northbridge code.
> Rename it to match the chipset modelled.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  MAINTAINERS                      | 2 +-
>  hw/i386/Kconfig                  | 2 +-
>  hw/pci-host/Kconfig              | 2 +-
>  hw/pci-host/Makefile.objs        | 2 +-
>  hw/pci-host/{piix.c => i440fx.c} | 0
>  5 files changed, 4 insertions(+), 4 deletions(-)
>  rename hw/pci-host/{piix.c => i440fx.c} (100%)
>
>

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>


> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4845f47d93..1bc9959b8a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>  S: Supported
>  F: include/hw/i386/
>  F: hw/i386/
> -F: hw/pci-host/piix.c
> +F: hw/pci-host/i440fx.c
>  F: hw/pci-host/q35.c
>  F: hw/pci-host/pam.c
>  F: include/hw/pci-host/i440fx.h
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index 589d75e26a..cfe94aede7 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -60,7 +60,7 @@ config I440FX
>      select PC_PCI
>      select PC_ACPI
>      select ACPI_SMBUS
> -    select PCI_PIIX
> +    select PCI_I440FX
>      select PIIX3
>      select IDE_PIIX
>      select DIMM
> diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
> index 397043b289..b0aa8351c4 100644
> --- a/hw/pci-host/Kconfig
> +++ b/hw/pci-host/Kconfig
> @@ -28,7 +28,7 @@ config PCI_SABRE
>      select PCI
>      bool
>
> -config PCI_PIIX
> +config PCI_I440FX
>      bool
>      select PCI
>      select PAM
> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
> index a9cd3e022d..efd752b766 100644
> --- a/hw/pci-host/Makefile.objs
> +++ b/hw/pci-host/Makefile.objs
> @@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
>
>  common-obj-$(CONFIG_PCI_SABRE) += sabre.o
>  common-obj-$(CONFIG_FULONG) += bonito.o
> -common-obj-$(CONFIG_PCI_PIIX) += piix.o
> +common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
>  common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
>  common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
>  common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
> similarity index 100%
> rename from hw/pci-host/piix.c
> rename to hw/pci-host/i440fx.c
> --
> 2.21.0
>
>
>

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Re: [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

On 10/18/19 11:19 AM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The RCR_IOPORT register belongs to the PIIX chipset.
>     Move the definition to "piix.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/pci-host/piix.c            | 1 +
>       include/hw/i386/pc.h          | 6 ------
>       include/hw/southbridge/piix.h | 6 ++++++
>       3 files changed, 7 insertions(+), 6 deletions(-)
> 
> 
> Does it make sense to add prefix PIIX_ or a similar one to the register 
> name?

Good idea, it will make the comment in hw/i386/acpi-build.c:213 cleaner:

     /* The above need not be conditional on machine type because the 
reset port
      * happens to be the same on PIIX (pc) and ICH9 (q35). */
     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);

> 
> In any case:
> 
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com 
> <mailto:amarkovic@wavecomp.com>>

Thanks!

> 
>     diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>     index 3292703de7..3770575c1a 100644
>     --- a/hw/pci-host/piix.c
>     +++ b/hw/pci-host/piix.c
>     @@ -27,6 +27,7 @@
>       #include "hw/irq.h"
>       #include "hw/pci/pci.h"
>       #include "hw/pci/pci_host.h"
>     +#include "hw/southbridge/piix.h"
>       #include "hw/qdev-properties.h"
>       #include "hw/isa/isa.h"
>       #include "hw/sysbus.h"
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 183326d9fe..1c20b96571 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
> 
>       #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
>     "igd-passthrough-i440FX"
> 
>     -/*
>     - * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     - */
>     -#define RCR_IOPORT 0xcf9
>     -
>       PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                           PCII440FXState **pi440fx_state, int *piix_devfn,
>                           ISABus **isa_bus, qemu_irq *pic,
>     diff --git a/include/hw/southbridge/piix.h
>     b/include/hw/southbridge/piix.h
>     index add352456b..79ebe0089b 100644
>     --- a/include/hw/southbridge/piix.h
>     +++ b/include/hw/southbridge/piix.h
>     @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn,
>     uint32_t smb_io_base,
>                             qemu_irq sci_irq, qemu_irq smi_irq,
>                             int smm_enabled, DeviceState **piix4_pm);
> 
>     +/*
>     + * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     + */
>     +#define RCR_IOPORT 0xcf9
>     +
>       extern PCIDevice *piix4_dev;
> 
>       DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>     -- 
>     2.21.0
> 
> 

Re: [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

On 10/18/19 11:19 AM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The RCR_IOPORT register belongs to the PIIX chipset.
>     Move the definition to "piix.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/pci-host/piix.c            | 1 +
>       include/hw/i386/pc.h          | 6 ------
>       include/hw/southbridge/piix.h | 6 ++++++
>       3 files changed, 7 insertions(+), 6 deletions(-)
> 
> 
> Does it make sense to add prefix PIIX_ or a similar one to the register 
> name?

Good idea, it will make the comment in hw/i386/acpi-build.c:213 cleaner:

     /* The above need not be conditional on machine type because the 
reset port
      * happens to be the same on PIIX (pc) and ICH9 (q35). */
     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);

> 
> In any case:
> 
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com 
> <mailto:amarkovic@wavecomp.com>>

Thanks!

> 
>     diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>     index 3292703de7..3770575c1a 100644
>     --- a/hw/pci-host/piix.c
>     +++ b/hw/pci-host/piix.c
>     @@ -27,6 +27,7 @@
>       #include "hw/irq.h"
>       #include "hw/pci/pci.h"
>       #include "hw/pci/pci_host.h"
>     +#include "hw/southbridge/piix.h"
>       #include "hw/qdev-properties.h"
>       #include "hw/isa/isa.h"
>       #include "hw/sysbus.h"
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 183326d9fe..1c20b96571 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
> 
>       #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
>     "igd-passthrough-i440FX"
> 
>     -/*
>     - * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     - */
>     -#define RCR_IOPORT 0xcf9
>     -
>       PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                           PCII440FXState **pi440fx_state, int *piix_devfn,
>                           ISABus **isa_bus, qemu_irq *pic,
>     diff --git a/include/hw/southbridge/piix.h
>     b/include/hw/southbridge/piix.h
>     index add352456b..79ebe0089b 100644
>     --- a/include/hw/southbridge/piix.h
>     +++ b/include/hw/southbridge/piix.h
>     @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn,
>     uint32_t smb_io_base,
>                             qemu_irq sci_irq, qemu_irq smi_irq,
>                             int smm_enabled, DeviceState **piix4_pm);
> 
>     +/*
>     + * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     + */
>     +#define RCR_IOPORT 0xcf9
>     +
>       extern PCIDevice *piix4_dev;
> 
>       DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>     -- 
>     2.21.0
> 
> 

Re: [Xen-devel] [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Philippe Mathieu-Daudé]

On 10/18/19 11:19 AM, Aleksandar Markovic wrote:
> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com 
> <mailto:philmd@redhat.com>> wrote:
> 
>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org>>
> 
>     The RCR_IOPORT register belongs to the PIIX chipset.
>     Move the definition to "piix.h".
> 
>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>     <mailto:philmd@redhat.com>>
>     ---
>       hw/pci-host/piix.c            | 1 +
>       include/hw/i386/pc.h          | 6 ------
>       include/hw/southbridge/piix.h | 6 ++++++
>       3 files changed, 7 insertions(+), 6 deletions(-)
> 
> 
> Does it make sense to add prefix PIIX_ or a similar one to the register 
> name?

Good idea, it will make the comment in hw/i386/acpi-build.c:213 cleaner:

     /* The above need not be conditional on machine type because the 
reset port
      * happens to be the same on PIIX (pc) and ICH9 (q35). */
     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);

> 
> In any case:
> 
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com 
> <mailto:amarkovic@wavecomp.com>>

Thanks!

> 
>     diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>     index 3292703de7..3770575c1a 100644
>     --- a/hw/pci-host/piix.c
>     +++ b/hw/pci-host/piix.c
>     @@ -27,6 +27,7 @@
>       #include "hw/irq.h"
>       #include "hw/pci/pci.h"
>       #include "hw/pci/pci_host.h"
>     +#include "hw/southbridge/piix.h"
>       #include "hw/qdev-properties.h"
>       #include "hw/isa/isa.h"
>       #include "hw/sysbus.h"
>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>     index 183326d9fe..1c20b96571 100644
>     --- a/include/hw/i386/pc.h
>     +++ b/include/hw/i386/pc.h
>     @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
> 
>       #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
>     "igd-passthrough-i440FX"
> 
>     -/*
>     - * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     - */
>     -#define RCR_IOPORT 0xcf9
>     -
>       PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>                           PCII440FXState **pi440fx_state, int *piix_devfn,
>                           ISABus **isa_bus, qemu_irq *pic,
>     diff --git a/include/hw/southbridge/piix.h
>     b/include/hw/southbridge/piix.h
>     index add352456b..79ebe0089b 100644
>     --- a/include/hw/southbridge/piix.h
>     +++ b/include/hw/southbridge/piix.h
>     @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn,
>     uint32_t smb_io_base,
>                             qemu_irq sci_irq, qemu_irq smi_irq,
>                             int smm_enabled, DeviceState **piix4_pm);
> 
>     +/*
>     + * Reset Control Register: PCI-accessible ISA-Compatible Register
>     at address
>     + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>     8086:7000).
>     + */
>     +#define RCR_IOPORT 0xcf9
>     +
>       extern PCIDevice *piix4_dev;
> 
>       DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>     -- 
>     2.21.0
> 
> 

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Re: [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 3544 bytes --]

On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> On 10/18/19 11:19 AM, Aleksandar Markovic wrote:
>
>> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
>> <mailto:philmd@redhat.com>> wrote:
>>
>>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org
>> >>
>>
>>     The RCR_IOPORT register belongs to the PIIX chipset.
>>     Move the definition to "piix.h".
>>
>>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>>     <mailto:philmd@redhat.com>>
>>     ---
>>       hw/pci-host/piix.c            | 1 +
>>       include/hw/i386/pc.h          | 6 ------
>>       include/hw/southbridge/piix.h | 6 ++++++
>>       3 files changed, 7 insertions(+), 6 deletions(-)
>>
>>
>> Does it make sense to add prefix PIIX_ or a similar one to the register
>> name?
>>
>
> Good idea, it will make the comment in hw/i386/acpi-build.c:213 cleaner:


Correct. Let's than add PIIX_ prefix.

Thanks in advance.

A.



>     /* The above need not be conditional on machine type because the reset
> port
>      * happens to be the same on PIIX (pc) and ICH9 (q35). */
>     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
>
>
>> In any case:
>>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com <mailto:
>> amarkovic@wavecomp.com>>
>>
>
> Thanks!
>
>
>>     diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>>     index 3292703de7..3770575c1a 100644
>>     --- a/hw/pci-host/piix.c
>>     +++ b/hw/pci-host/piix.c
>>     @@ -27,6 +27,7 @@
>>       #include "hw/irq.h"
>>       #include "hw/pci/pci.h"
>>       #include "hw/pci/pci_host.h"
>>     +#include "hw/southbridge/piix.h"
>>       #include "hw/qdev-properties.h"
>>       #include "hw/isa/isa.h"
>>       #include "hw/sysbus.h"
>>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>     index 183326d9fe..1c20b96571 100644
>>     --- a/include/hw/i386/pc.h
>>     +++ b/include/hw/i386/pc.h
>>     @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
>>
>>       #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
>>     "igd-passthrough-i440FX"
>>
>>     -/*
>>     - * Reset Control Register: PCI-accessible ISA-Compatible Register
>>     at address
>>     - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>>     8086:7000).
>>     - */
>>     -#define RCR_IOPORT 0xcf9
>>     -
>>       PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>>                           PCII440FXState **pi440fx_state, int *piix_devfn,
>>                           ISABus **isa_bus, qemu_irq *pic,
>>     diff --git a/include/hw/southbridge/piix.h
>>     b/include/hw/southbridge/piix.h
>>     index add352456b..79ebe0089b 100644
>>     --- a/include/hw/southbridge/piix.h
>>     +++ b/include/hw/southbridge/piix.h
>>     @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn,
>>     uint32_t smb_io_base,
>>                             qemu_irq sci_irq, qemu_irq smi_irq,
>>                             int smm_enabled, DeviceState **piix4_pm);
>>
>>     +/*
>>     + * Reset Control Register: PCI-accessible ISA-Compatible Register
>>     at address
>>     + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>>     8086:7000).
>>     + */
>>     +#define RCR_IOPORT 0xcf9
>>     +
>>       extern PCIDevice *piix4_dev;
>>
>>       DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>>     --     2.21.0
>>
>>
>>

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Re: [Xen-devel] [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 3544 bytes --]

On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> On 10/18/19 11:19 AM, Aleksandar Markovic wrote:
>
>> On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
>> <mailto:philmd@redhat.com>> wrote:
>>
>>     From: Philippe Mathieu-Daudé <f4bug@amsat.org <mailto:f4bug@amsat.org
>> >>
>>
>>     The RCR_IOPORT register belongs to the PIIX chipset.
>>     Move the definition to "piix.h".
>>
>>     Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
>>     <mailto:philmd@redhat.com>>
>>     ---
>>       hw/pci-host/piix.c            | 1 +
>>       include/hw/i386/pc.h          | 6 ------
>>       include/hw/southbridge/piix.h | 6 ++++++
>>       3 files changed, 7 insertions(+), 6 deletions(-)
>>
>>
>> Does it make sense to add prefix PIIX_ or a similar one to the register
>> name?
>>
>
> Good idea, it will make the comment in hw/i386/acpi-build.c:213 cleaner:


Correct. Let's than add PIIX_ prefix.

Thanks in advance.

A.



>     /* The above need not be conditional on machine type because the reset
> port
>      * happens to be the same on PIIX (pc) and ICH9 (q35). */
>     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
>
>
>> In any case:
>>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com <mailto:
>> amarkovic@wavecomp.com>>
>>
>
> Thanks!
>
>
>>     diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>>     index 3292703de7..3770575c1a 100644
>>     --- a/hw/pci-host/piix.c
>>     +++ b/hw/pci-host/piix.c
>>     @@ -27,6 +27,7 @@
>>       #include "hw/irq.h"
>>       #include "hw/pci/pci.h"
>>       #include "hw/pci/pci_host.h"
>>     +#include "hw/southbridge/piix.h"
>>       #include "hw/qdev-properties.h"
>>       #include "hw/isa/isa.h"
>>       #include "hw/sysbus.h"
>>     diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>>     index 183326d9fe..1c20b96571 100644
>>     --- a/include/hw/i386/pc.h
>>     +++ b/include/hw/i386/pc.h
>>     @@ -257,12 +257,6 @@ typedef struct PCII440FXState PCII440FXState;
>>
>>       #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
>>     "igd-passthrough-i440FX"
>>
>>     -/*
>>     - * Reset Control Register: PCI-accessible ISA-Compatible Register
>>     at address
>>     - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>>     8086:7000).
>>     - */
>>     -#define RCR_IOPORT 0xcf9
>>     -
>>       PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>>                           PCII440FXState **pi440fx_state, int *piix_devfn,
>>                           ISABus **isa_bus, qemu_irq *pic,
>>     diff --git a/include/hw/southbridge/piix.h
>>     b/include/hw/southbridge/piix.h
>>     index add352456b..79ebe0089b 100644
>>     --- a/include/hw/southbridge/piix.h
>>     +++ b/include/hw/southbridge/piix.h
>>     @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn,
>>     uint32_t smb_io_base,
>>                             qemu_irq sci_irq, qemu_irq smi_irq,
>>                             int smm_enabled, DeviceState **piix4_pm);
>>
>>     +/*
>>     + * Reset Control Register: PCI-accessible ISA-Compatible Register
>>     at address
>>     + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0,
>>     8086:7000).
>>     + */
>>     +#define RCR_IOPORT 0xcf9
>>     +
>>       extern PCIDevice *piix4_dev;
>>
>>       DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
>>     --     2.21.0
>>
>>
>>

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Re: [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1967 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The ISA default number for the RTC devices is not related to its
> registers neither. Move this definition to "hw/timer/mc146818rtc.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/timer/mc146818rtc.h      | 2 ++
>  include/hw/timer/mc146818rtc_regs.h | 2 --
>  tests/rtc-test.c                    | 1 +
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>




> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index 0f1c886e5b..17761cf6d9 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -39,6 +39,8 @@ typedef struct RTCState {
>      QLIST_ENTRY(RTCState) link;
>  } RTCState;
>
> +#define RTC_ISA_IRQ 8
> +
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
>  void rtc_set_memory(ISADevice *dev, int addr, int val);
> diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/
> mc146818rtc_regs.h
> index bfbb57e570..631f71cfd9 100644
> --- a/include/hw/timer/mc146818rtc_regs.h
> +++ b/include/hw/timer/mc146818rtc_regs.h
> @@ -27,8 +27,6 @@
>
>  #include "qemu/timer.h"
>
> -#define RTC_ISA_IRQ 8
> -
>  #define RTC_SECONDS             0
>  #define RTC_SECONDS_ALARM       1
>  #define RTC_MINUTES             2
> diff --git a/tests/rtc-test.c b/tests/rtc-test.c
> index 6309b0ef6c..18f895690f 100644
> --- a/tests/rtc-test.c
> +++ b/tests/rtc-test.c
> @@ -15,6 +15,7 @@
>
>  #include "libqtest-single.h"
>  #include "qemu/timer.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
> --
> 2.21.0
>
>
>

[-- Attachment #2: Type: text/html, Size: 3248 bytes --]

Re: [Xen-devel] [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition

[Aleksandar Markovic]

[-- Attachment #1.1: Type: text/plain, Size: 1967 bytes --]

On Tuesday, October 15, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The ISA default number for the RTC devices is not related to its
> registers neither. Move this definition to "hw/timer/mc146818rtc.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/hw/timer/mc146818rtc.h      | 2 ++
>  include/hw/timer/mc146818rtc_regs.h | 2 --
>  tests/rtc-test.c                    | 1 +
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>




> diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/
> mc146818rtc.h
> index 0f1c886e5b..17761cf6d9 100644
> --- a/include/hw/timer/mc146818rtc.h
> +++ b/include/hw/timer/mc146818rtc.h
> @@ -39,6 +39,8 @@ typedef struct RTCState {
>      QLIST_ENTRY(RTCState) link;
>  } RTCState;
>
> +#define RTC_ISA_IRQ 8
> +
>  ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
>                               qemu_irq intercept_irq);
>  void rtc_set_memory(ISADevice *dev, int addr, int val);
> diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/
> mc146818rtc_regs.h
> index bfbb57e570..631f71cfd9 100644
> --- a/include/hw/timer/mc146818rtc_regs.h
> +++ b/include/hw/timer/mc146818rtc_regs.h
> @@ -27,8 +27,6 @@
>
>  #include "qemu/timer.h"
>
> -#define RTC_ISA_IRQ 8
> -
>  #define RTC_SECONDS             0
>  #define RTC_SECONDS_ALARM       1
>  #define RTC_MINUTES             2
> diff --git a/tests/rtc-test.c b/tests/rtc-test.c
> index 6309b0ef6c..18f895690f 100644
> --- a/tests/rtc-test.c
> +++ b/tests/rtc-test.c
> @@ -15,6 +15,7 @@
>
>  #include "libqtest-single.h"
>  #include "qemu/timer.h"
> +#include "hw/timer/mc146818rtc.h"
>  #include "hw/timer/mc146818rtc_regs.h"
>
>  #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
> --
> 2.21.0
>
>
>

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Re: [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Dr. David Alan Gilbert]

* Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> I forgot to Cc David and Daniel for this one.
> 
> On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> > These devices implemented their load_state_old() handler 10 years
> > ago, previous to QEMU v0.12.
> > Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> > we can drop this code.
> > 
> > Note: the mips_r4k machine started to use the i8254 device just
> > after QEMU v0.5.0, but the MIPS machine types are not versioned,
> > so there is no migration compatibility issue removing this handler.
> > 
> > Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> >   hw/acpi/piix4.c         | 40 ---------------------------------
> >   hw/intc/apic_common.c   | 49 -----------------------------------------
> >   hw/pci-host/piix.c      | 25 ---------------------
> >   hw/timer/i8254_common.c | 40 ---------------------------------
> >   4 files changed, 154 deletions(-)
> > 
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index 5742c3df87..1d29d438c7 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -42,7 +42,6 @@
> >   #include "hw/acpi/memory_hotplug.h"
> >   #include "hw/acpi/acpi_dev_interface.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/core/cpu.h"
> >   #include "trace.h"
> > @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
> >       }
> >   };
> > -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PIIX4PMState *s = opaque;
> > -    int ret, i;
> > -    uint16_t temp;
> > -
> > -    ret = pci_device_load(PCI_DEVICE(s), f);
> > -    if (ret < 0) {
> > -        return ret;
> > -    }
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> > -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> > -
> > -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> > -    if (ret) {
> > -        return ret;
> > -    }
> > -
> > -    timer_get(f, s->ar.tmr.timer);
> > -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    ret = vmstate_load_state(f, &vmstate_pci_status,
> > -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> > -    return ret;
> > -}
> > -
> >   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
> >   {
> >       PIIX4PMState *s = opaque;
> > @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
> >       .name = "piix4_pm",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = acpi_load_old,

Can you exlain why this is old enough?  That was chnanged by b0b873a
that was some version id specific hack, but also 4cf3e6f3d85 - isn't
that before 0.12.0 ?

> >       .post_load = vmstate_acpi_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> > index aafd8e0e33..375cb6abe9 100644
> > --- a/hw/intc/apic_common.c
> > +++ b/hw/intc/apic_common.c
> > @@ -31,7 +31,6 @@
> >   #include "sysemu/kvm.h"
> >   #include "hw/qdev-properties.h"
> >   #include "hw/sysbus.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   static int apic_irq_delivered;
> > @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
> >       apic_init_reset(dev);
> >   }
> > -/* This function is only used for old state version 1 and 2 */
> > -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    APICCommonState *s = opaque;
> > -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> > -    int i;
> > -
> > -    if (version_id > 2) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    /* XXX: what if the base changes? (registered memory regions) */
> > -    qemu_get_be32s(f, &s->apicbase);
> > -    qemu_get_8s(f, &s->id);
> > -    qemu_get_8s(f, &s->arb_id);
> > -    qemu_get_8s(f, &s->tpr);
> > -    qemu_get_be32s(f, &s->spurious_vec);
> > -    qemu_get_8s(f, &s->log_dest);
> > -    qemu_get_8s(f, &s->dest_mode);
> > -    for (i = 0; i < 8; i++) {
> > -        qemu_get_be32s(f, &s->isr[i]);
> > -        qemu_get_be32s(f, &s->tmr[i]);
> > -        qemu_get_be32s(f, &s->irr[i]);
> > -    }
> > -    for (i = 0; i < APIC_LVT_NB; i++) {
> > -        qemu_get_be32s(f, &s->lvt[i]);
> > -    }
> > -    qemu_get_be32s(f, &s->esr);
> > -    qemu_get_be32s(f, &s->icr[0]);
> > -    qemu_get_be32s(f, &s->icr[1]);
> > -    qemu_get_be32s(f, &s->divide_conf);
> > -    s->count_shift = qemu_get_be32(f);
> > -    qemu_get_be32s(f, &s->initial_count);
> > -    s->initial_count_load_time = qemu_get_be64(f);
> > -    s->next_time = qemu_get_be64(f);
> > -
> > -    if (version_id >= 2) {
> > -        s->timer_expiry = qemu_get_be64(f);
> > -    }
> > -
> > -    if (info->post_load) {
> > -        info->post_load(s);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static const VMStateDescription vmstate_apic_common;
> >   static void apic_common_realize(DeviceState *dev, Error **errp)
> > @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
> >       .name = "apic",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = apic_load_old,

OK, I see that was changed by 695dcf71 in 2009 before 0.12.0

> >       .pre_load = apic_pre_load,
> >       .pre_save = apic_dispatch_pre_save,
> >       .post_load = apic_dispatch_post_load,
> > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> > index 135c645535..2f4cbcbfe9 100644
> > --- a/hw/pci-host/piix.c
> > +++ b/hw/pci-host/piix.c
> > @@ -33,7 +33,6 @@
> >   #include "qapi/error.h"
> >   #include "qemu/range.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/pci-host/pam.h"
> >   #include "sysemu/reset.h"
> > @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
> >       }
> >   }
> > -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> > -{
> > -    PCII440FXState *d = opaque;
> > -    PCIDevice *pd = PCI_DEVICE(d);
> > -    int ret, i;
> > -    uint8_t smm_enabled;
> > -
> > -    ret = pci_device_load(pd, f);
> > -    if (ret < 0)
> > -        return ret;
> > -    i440fx_update_memory_mappings(d);
> > -    qemu_get_8s(f, &smm_enabled);
> > -
> > -    if (version_id == 2) {
> > -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> > -            qemu_get_be32(f); /* dummy load for compatibility */
> > -        }
> > -    }
> > -
> > -    return 0;
> > -}
> > -
> >   static int i440fx_post_load(void *opaque, int version_id)
> >   {
> >       PCII440FXState *d = opaque;
> > @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
> >       .name = "I440FX",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = i440fx_load_old,

Changed in 2009 before 0.12; OK

> >       .post_load = i440fx_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> > diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> > index 57bf10cc94..050875b497 100644
> > --- a/hw/timer/i8254_common.c
> > +++ b/hw/timer/i8254_common.c
> > @@ -29,7 +29,6 @@
> >   #include "qemu/timer.h"
> >   #include "hw/timer/i8254.h"
> >   #include "hw/timer/i8254_internal.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   /* val must be 0 or 1 */
> > @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
> >       }
> >   };
> > -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PITCommonState *pit = opaque;
> > -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> > -    PITChannelState *s;
> > -    int i;
> > -
> > -    if (version_id != 1) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    for (i = 0; i < 3; i++) {
> > -        s = &pit->channels[i];
> > -        s->count = qemu_get_be32(f);
> > -        qemu_get_be16s(f, &s->latched_count);
> > -        qemu_get_8s(f, &s->count_latched);
> > -        qemu_get_8s(f, &s->status_latched);
> > -        qemu_get_8s(f, &s->status);
> > -        qemu_get_8s(f, &s->read_state);
> > -        qemu_get_8s(f, &s->write_state);
> > -        qemu_get_8s(f, &s->write_latch);
> > -        qemu_get_8s(f, &s->rw_mode);
> > -        qemu_get_8s(f, &s->mode);
> > -        qemu_get_8s(f, &s->bcd);
> > -        qemu_get_8s(f, &s->gate);
> > -        s->count_load_time = qemu_get_be64(f);
> > -        s->irq_disabled = 0;
> > -        if (i == 0) {
> > -            s->next_transition_time = qemu_get_be64(f);
> > -        }
> > -    }
> > -    if (c->post_load) {
> > -        c->post_load(pit);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static int pit_dispatch_pre_save(void *opaque)
> >   {
> >       PITCommonState *s = opaque;
> > @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
> >       .name = "i8254",
> >       .version_id = 3,
> >       .minimum_version_id = 2,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = pit_load_old,

Also 2009 pre 0.12

> >       .pre_save = pit_dispatch_pre_save,
> >       .post_load = pit_dispatch_post_load,
> >       .fields = (VMStateField[]) {
> > 
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK

Re: [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Dr. David Alan Gilbert]

* Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> I forgot to Cc David and Daniel for this one.
> 
> On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> > These devices implemented their load_state_old() handler 10 years
> > ago, previous to QEMU v0.12.
> > Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> > we can drop this code.
> > 
> > Note: the mips_r4k machine started to use the i8254 device just
> > after QEMU v0.5.0, but the MIPS machine types are not versioned,
> > so there is no migration compatibility issue removing this handler.
> > 
> > Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> >   hw/acpi/piix4.c         | 40 ---------------------------------
> >   hw/intc/apic_common.c   | 49 -----------------------------------------
> >   hw/pci-host/piix.c      | 25 ---------------------
> >   hw/timer/i8254_common.c | 40 ---------------------------------
> >   4 files changed, 154 deletions(-)
> > 
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index 5742c3df87..1d29d438c7 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -42,7 +42,6 @@
> >   #include "hw/acpi/memory_hotplug.h"
> >   #include "hw/acpi/acpi_dev_interface.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/core/cpu.h"
> >   #include "trace.h"
> > @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
> >       }
> >   };
> > -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PIIX4PMState *s = opaque;
> > -    int ret, i;
> > -    uint16_t temp;
> > -
> > -    ret = pci_device_load(PCI_DEVICE(s), f);
> > -    if (ret < 0) {
> > -        return ret;
> > -    }
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> > -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> > -
> > -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> > -    if (ret) {
> > -        return ret;
> > -    }
> > -
> > -    timer_get(f, s->ar.tmr.timer);
> > -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    ret = vmstate_load_state(f, &vmstate_pci_status,
> > -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> > -    return ret;
> > -}
> > -
> >   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
> >   {
> >       PIIX4PMState *s = opaque;
> > @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
> >       .name = "piix4_pm",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = acpi_load_old,

Can you exlain why this is old enough?  That was chnanged by b0b873a
that was some version id specific hack, but also 4cf3e6f3d85 - isn't
that before 0.12.0 ?

> >       .post_load = vmstate_acpi_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> > index aafd8e0e33..375cb6abe9 100644
> > --- a/hw/intc/apic_common.c
> > +++ b/hw/intc/apic_common.c
> > @@ -31,7 +31,6 @@
> >   #include "sysemu/kvm.h"
> >   #include "hw/qdev-properties.h"
> >   #include "hw/sysbus.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   static int apic_irq_delivered;
> > @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
> >       apic_init_reset(dev);
> >   }
> > -/* This function is only used for old state version 1 and 2 */
> > -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    APICCommonState *s = opaque;
> > -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> > -    int i;
> > -
> > -    if (version_id > 2) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    /* XXX: what if the base changes? (registered memory regions) */
> > -    qemu_get_be32s(f, &s->apicbase);
> > -    qemu_get_8s(f, &s->id);
> > -    qemu_get_8s(f, &s->arb_id);
> > -    qemu_get_8s(f, &s->tpr);
> > -    qemu_get_be32s(f, &s->spurious_vec);
> > -    qemu_get_8s(f, &s->log_dest);
> > -    qemu_get_8s(f, &s->dest_mode);
> > -    for (i = 0; i < 8; i++) {
> > -        qemu_get_be32s(f, &s->isr[i]);
> > -        qemu_get_be32s(f, &s->tmr[i]);
> > -        qemu_get_be32s(f, &s->irr[i]);
> > -    }
> > -    for (i = 0; i < APIC_LVT_NB; i++) {
> > -        qemu_get_be32s(f, &s->lvt[i]);
> > -    }
> > -    qemu_get_be32s(f, &s->esr);
> > -    qemu_get_be32s(f, &s->icr[0]);
> > -    qemu_get_be32s(f, &s->icr[1]);
> > -    qemu_get_be32s(f, &s->divide_conf);
> > -    s->count_shift = qemu_get_be32(f);
> > -    qemu_get_be32s(f, &s->initial_count);
> > -    s->initial_count_load_time = qemu_get_be64(f);
> > -    s->next_time = qemu_get_be64(f);
> > -
> > -    if (version_id >= 2) {
> > -        s->timer_expiry = qemu_get_be64(f);
> > -    }
> > -
> > -    if (info->post_load) {
> > -        info->post_load(s);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static const VMStateDescription vmstate_apic_common;
> >   static void apic_common_realize(DeviceState *dev, Error **errp)
> > @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
> >       .name = "apic",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = apic_load_old,

OK, I see that was changed by 695dcf71 in 2009 before 0.12.0

> >       .pre_load = apic_pre_load,
> >       .pre_save = apic_dispatch_pre_save,
> >       .post_load = apic_dispatch_post_load,
> > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> > index 135c645535..2f4cbcbfe9 100644
> > --- a/hw/pci-host/piix.c
> > +++ b/hw/pci-host/piix.c
> > @@ -33,7 +33,6 @@
> >   #include "qapi/error.h"
> >   #include "qemu/range.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/pci-host/pam.h"
> >   #include "sysemu/reset.h"
> > @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
> >       }
> >   }
> > -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> > -{
> > -    PCII440FXState *d = opaque;
> > -    PCIDevice *pd = PCI_DEVICE(d);
> > -    int ret, i;
> > -    uint8_t smm_enabled;
> > -
> > -    ret = pci_device_load(pd, f);
> > -    if (ret < 0)
> > -        return ret;
> > -    i440fx_update_memory_mappings(d);
> > -    qemu_get_8s(f, &smm_enabled);
> > -
> > -    if (version_id == 2) {
> > -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> > -            qemu_get_be32(f); /* dummy load for compatibility */
> > -        }
> > -    }
> > -
> > -    return 0;
> > -}
> > -
> >   static int i440fx_post_load(void *opaque, int version_id)
> >   {
> >       PCII440FXState *d = opaque;
> > @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
> >       .name = "I440FX",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = i440fx_load_old,

Changed in 2009 before 0.12; OK

> >       .post_load = i440fx_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> > diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> > index 57bf10cc94..050875b497 100644
> > --- a/hw/timer/i8254_common.c
> > +++ b/hw/timer/i8254_common.c
> > @@ -29,7 +29,6 @@
> >   #include "qemu/timer.h"
> >   #include "hw/timer/i8254.h"
> >   #include "hw/timer/i8254_internal.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   /* val must be 0 or 1 */
> > @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
> >       }
> >   };
> > -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PITCommonState *pit = opaque;
> > -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> > -    PITChannelState *s;
> > -    int i;
> > -
> > -    if (version_id != 1) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    for (i = 0; i < 3; i++) {
> > -        s = &pit->channels[i];
> > -        s->count = qemu_get_be32(f);
> > -        qemu_get_be16s(f, &s->latched_count);
> > -        qemu_get_8s(f, &s->count_latched);
> > -        qemu_get_8s(f, &s->status_latched);
> > -        qemu_get_8s(f, &s->status);
> > -        qemu_get_8s(f, &s->read_state);
> > -        qemu_get_8s(f, &s->write_state);
> > -        qemu_get_8s(f, &s->write_latch);
> > -        qemu_get_8s(f, &s->rw_mode);
> > -        qemu_get_8s(f, &s->mode);
> > -        qemu_get_8s(f, &s->bcd);
> > -        qemu_get_8s(f, &s->gate);
> > -        s->count_load_time = qemu_get_be64(f);
> > -        s->irq_disabled = 0;
> > -        if (i == 0) {
> > -            s->next_transition_time = qemu_get_be64(f);
> > -        }
> > -    }
> > -    if (c->post_load) {
> > -        c->post_load(pit);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static int pit_dispatch_pre_save(void *opaque)
> >   {
> >       PITCommonState *s = opaque;
> > @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
> >       .name = "i8254",
> >       .version_id = 3,
> >       .minimum_version_id = 2,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = pit_load_old,

Also 2009 pre 0.12

> >       .pre_save = pit_dispatch_pre_save,
> >       .post_load = pit_dispatch_post_load,
> >       .fields = (VMStateField[]) {
> > 
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK

Re: [Xen-devel] [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

[Dr. David Alan Gilbert]

* Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> I forgot to Cc David and Daniel for this one.
> 
> On 10/15/19 6:26 PM, Philippe Mathieu-Daudé wrote:
> > These devices implemented their load_state_old() handler 10 years
> > ago, previous to QEMU v0.12.
> > Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
> > we can drop this code.
> > 
> > Note: the mips_r4k machine started to use the i8254 device just
> > after QEMU v0.5.0, but the MIPS machine types are not versioned,
> > so there is no migration compatibility issue removing this handler.
> > 
> > Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> >   hw/acpi/piix4.c         | 40 ---------------------------------
> >   hw/intc/apic_common.c   | 49 -----------------------------------------
> >   hw/pci-host/piix.c      | 25 ---------------------
> >   hw/timer/i8254_common.c | 40 ---------------------------------
> >   4 files changed, 154 deletions(-)
> > 
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index 5742c3df87..1d29d438c7 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -42,7 +42,6 @@
> >   #include "hw/acpi/memory_hotplug.h"
> >   #include "hw/acpi/acpi_dev_interface.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/core/cpu.h"
> >   #include "trace.h"
> > @@ -205,43 +204,6 @@ static const VMStateDescription vmstate_pci_status = {
> >       }
> >   };
> > -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PIIX4PMState *s = opaque;
> > -    int ret, i;
> > -    uint16_t temp;
> > -
> > -    ret = pci_device_load(PCI_DEVICE(s), f);
> > -    if (ret < 0) {
> > -        return ret;
> > -    }
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
> > -    qemu_get_be16s(f, &s->ar.pm1.evt.en);
> > -    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
> > -
> > -    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
> > -    if (ret) {
> > -        return ret;
> > -    }
> > -
> > -    timer_get(f, s->ar.tmr.timer);
> > -    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
> > -    for (i = 0; i < 3; i++) {
> > -        qemu_get_be16s(f, &temp);
> > -    }
> > -
> > -    ret = vmstate_load_state(f, &vmstate_pci_status,
> > -        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
> > -    return ret;
> > -}
> > -
> >   static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
> >   {
> >       PIIX4PMState *s = opaque;
> > @@ -313,8 +275,6 @@ static const VMStateDescription vmstate_acpi = {
> >       .name = "piix4_pm",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = acpi_load_old,

Can you exlain why this is old enough?  That was chnanged by b0b873a
that was some version id specific hack, but also 4cf3e6f3d85 - isn't
that before 0.12.0 ?

> >       .post_load = vmstate_acpi_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
> > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> > index aafd8e0e33..375cb6abe9 100644
> > --- a/hw/intc/apic_common.c
> > +++ b/hw/intc/apic_common.c
> > @@ -31,7 +31,6 @@
> >   #include "sysemu/kvm.h"
> >   #include "hw/qdev-properties.h"
> >   #include "hw/sysbus.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   static int apic_irq_delivered;
> > @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
> >       apic_init_reset(dev);
> >   }
> > -/* This function is only used for old state version 1 and 2 */
> > -static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    APICCommonState *s = opaque;
> > -    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> > -    int i;
> > -
> > -    if (version_id > 2) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    /* XXX: what if the base changes? (registered memory regions) */
> > -    qemu_get_be32s(f, &s->apicbase);
> > -    qemu_get_8s(f, &s->id);
> > -    qemu_get_8s(f, &s->arb_id);
> > -    qemu_get_8s(f, &s->tpr);
> > -    qemu_get_be32s(f, &s->spurious_vec);
> > -    qemu_get_8s(f, &s->log_dest);
> > -    qemu_get_8s(f, &s->dest_mode);
> > -    for (i = 0; i < 8; i++) {
> > -        qemu_get_be32s(f, &s->isr[i]);
> > -        qemu_get_be32s(f, &s->tmr[i]);
> > -        qemu_get_be32s(f, &s->irr[i]);
> > -    }
> > -    for (i = 0; i < APIC_LVT_NB; i++) {
> > -        qemu_get_be32s(f, &s->lvt[i]);
> > -    }
> > -    qemu_get_be32s(f, &s->esr);
> > -    qemu_get_be32s(f, &s->icr[0]);
> > -    qemu_get_be32s(f, &s->icr[1]);
> > -    qemu_get_be32s(f, &s->divide_conf);
> > -    s->count_shift = qemu_get_be32(f);
> > -    qemu_get_be32s(f, &s->initial_count);
> > -    s->initial_count_load_time = qemu_get_be64(f);
> > -    s->next_time = qemu_get_be64(f);
> > -
> > -    if (version_id >= 2) {
> > -        s->timer_expiry = qemu_get_be64(f);
> > -    }
> > -
> > -    if (info->post_load) {
> > -        info->post_load(s);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static const VMStateDescription vmstate_apic_common;
> >   static void apic_common_realize(DeviceState *dev, Error **errp)
> > @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
> >       .name = "apic",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = apic_load_old,

OK, I see that was changed by 695dcf71 in 2009 before 0.12.0

> >       .pre_load = apic_pre_load,
> >       .pre_save = apic_dispatch_pre_save,
> >       .post_load = apic_dispatch_post_load,
> > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> > index 135c645535..2f4cbcbfe9 100644
> > --- a/hw/pci-host/piix.c
> > +++ b/hw/pci-host/piix.c
> > @@ -33,7 +33,6 @@
> >   #include "qapi/error.h"
> >   #include "qemu/range.h"
> >   #include "hw/xen/xen.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   #include "hw/pci-host/pam.h"
> >   #include "sysemu/reset.h"
> > @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
> >       }
> >   }
> > -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> > -{
> > -    PCII440FXState *d = opaque;
> > -    PCIDevice *pd = PCI_DEVICE(d);
> > -    int ret, i;
> > -    uint8_t smm_enabled;
> > -
> > -    ret = pci_device_load(pd, f);
> > -    if (ret < 0)
> > -        return ret;
> > -    i440fx_update_memory_mappings(d);
> > -    qemu_get_8s(f, &smm_enabled);
> > -
> > -    if (version_id == 2) {
> > -        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
> > -            qemu_get_be32(f); /* dummy load for compatibility */
> > -        }
> > -    }
> > -
> > -    return 0;
> > -}
> > -
> >   static int i440fx_post_load(void *opaque, int version_id)
> >   {
> >       PCII440FXState *d = opaque;
> > @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
> >       .name = "I440FX",
> >       .version_id = 3,
> >       .minimum_version_id = 3,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = i440fx_load_old,

Changed in 2009 before 0.12; OK

> >       .post_load = i440fx_post_load,
> >       .fields = (VMStateField[]) {
> >           VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
> > diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
> > index 57bf10cc94..050875b497 100644
> > --- a/hw/timer/i8254_common.c
> > +++ b/hw/timer/i8254_common.c
> > @@ -29,7 +29,6 @@
> >   #include "qemu/timer.h"
> >   #include "hw/timer/i8254.h"
> >   #include "hw/timer/i8254_internal.h"
> > -#include "migration/qemu-file-types.h"
> >   #include "migration/vmstate.h"
> >   /* val must be 0 or 1 */
> > @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
> >       }
> >   };
> > -static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
> > -{
> > -    PITCommonState *pit = opaque;
> > -    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
> > -    PITChannelState *s;
> > -    int i;
> > -
> > -    if (version_id != 1) {
> > -        return -EINVAL;
> > -    }
> > -
> > -    for (i = 0; i < 3; i++) {
> > -        s = &pit->channels[i];
> > -        s->count = qemu_get_be32(f);
> > -        qemu_get_be16s(f, &s->latched_count);
> > -        qemu_get_8s(f, &s->count_latched);
> > -        qemu_get_8s(f, &s->status_latched);
> > -        qemu_get_8s(f, &s->status);
> > -        qemu_get_8s(f, &s->read_state);
> > -        qemu_get_8s(f, &s->write_state);
> > -        qemu_get_8s(f, &s->write_latch);
> > -        qemu_get_8s(f, &s->rw_mode);
> > -        qemu_get_8s(f, &s->mode);
> > -        qemu_get_8s(f, &s->bcd);
> > -        qemu_get_8s(f, &s->gate);
> > -        s->count_load_time = qemu_get_be64(f);
> > -        s->irq_disabled = 0;
> > -        if (i == 0) {
> > -            s->next_transition_time = qemu_get_be64(f);
> > -        }
> > -    }
> > -    if (c->post_load) {
> > -        c->post_load(pit);
> > -    }
> > -    return 0;
> > -}
> > -
> >   static int pit_dispatch_pre_save(void *opaque)
> >   {
> >       PITCommonState *s = opaque;
> > @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
> >       .name = "i8254",
> >       .version_id = 3,
> >       .minimum_version_id = 2,
> > -    .minimum_version_id_old = 1,
> > -    .load_state_old = pit_load_old,

Also 2009 pre 0.12

> >       .pre_save = pit_dispatch_pre_save,
> >       .post_load = pit_dispatch_post_load,
> >       .fields = (VMStateField[]) {
> > 
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK


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