* [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt
@ 2019-10-16 12:28 Tvrtko Ursulin
2019-10-16 12:28 ` [PATCH 2/3] drm/i915: Store engine mask in intel_gt Tvrtko Ursulin
2019-10-16 12:28 ` [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites Tvrtko Ursulin
0 siblings, 2 replies; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 12:28 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
The code underneath works on intel_gt and also rename to
i915_gem_load_gt_power_context to signify it is operating on GT.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +++++++++++++-----------
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 7987b54fb1f5..b2c18674c455 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -56,9 +56,9 @@ static bool switch_to_kernel_context_sync(struct intel_gt *gt)
return result;
}
-bool i915_gem_load_power_context(struct drm_i915_private *i915)
+bool i915_gem_load_gt_power_context(struct intel_gt *gt)
{
- return switch_to_kernel_context_sync(&i915->gt);
+ return switch_to_kernel_context_sync(gt);
}
static void user_forcewake(struct intel_gt *gt, bool suspend)
@@ -172,11 +172,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ struct intel_gt *gt = &i915->gt;
+
GEM_TRACE("\n");
- intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
- if (intel_gt_init_hw(&i915->gt))
+ if (intel_gt_init_hw(gt))
goto err_wedged;
/*
@@ -184,26 +186,26 @@ void i915_gem_resume(struct drm_i915_private *i915)
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
- if (intel_gt_resume(&i915->gt))
+ if (intel_gt_resume(gt))
goto err_wedged;
- intel_uc_resume(&i915->gt.uc);
+ intel_uc_resume(>->uc);
/* Always reload a context for powersaving. */
- if (!i915_gem_load_power_context(i915))
+ if (!i915_gem_load_gt_power_context(gt))
goto err_wedged;
- user_forcewake(&i915->gt, false);
+ user_forcewake(gt, false);
out_unlock:
- intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
return;
err_wedged:
- if (!intel_gt_is_wedged(&i915->gt)) {
+ if (!intel_gt_is_wedged(gt)) {
dev_err(i915->drm.dev,
"Failed to re-initialize GPU, declaring it wedged!\n");
- intel_gt_set_wedged(&i915->gt);
+ intel_gt_set_wedged(gt);
}
goto out_unlock;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index 6f7d5d11ac3b..38eace4cb6ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -10,11 +10,12 @@
#include <linux/types.h>
struct drm_i915_private;
+struct intel_gt;
struct work_struct;
void i915_gem_init__pm(struct drm_i915_private *i915);
-bool i915_gem_load_power_context(struct drm_i915_private *i915);
+bool i915_gem_load_gt_power_context(struct intel_gt *gt);
void i915_gem_resume(struct drm_i915_private *i915);
void i915_gem_idle_work_handler(struct work_struct *work);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0ddbd3a5fb8d..c4ebc21c6820 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1132,7 +1132,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
}
/* Flush the default context image to memory, and enable powersaving. */
- if (!i915_gem_load_power_context(i915)) {
+ if (!i915_gem_load_gt_power_context(&i915->gt)) {
err = -EIO;
goto out;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/i915: Store engine mask in intel_gt
2019-10-16 12:28 [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt Tvrtko Ursulin
@ 2019-10-16 12:28 ` Tvrtko Ursulin
2019-10-16 13:03 ` Chris Wilson
2019-10-16 12:28 ` [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites Tvrtko Ursulin
1 sibling, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 12:28 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
To allow for_each_engine_masked call sites to pass in gt instead of i915
we need to have a copy of INTEL_INFO()->engine_mask in intel_gt.
For this to work we also need to use engine->id as index when populating
the gt->engine[] array.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++
drivers/gpu/drm/i915/i915_drv.c | 2 ++
5 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 77cd5de83930..099abae860ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -183,8 +183,8 @@ static void add_legacy_ring(struct legacy_ring *ring,
if (unlikely(idx == -1))
return;
- GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
- ring->gt->engine[idx] = engine;
+ GEM_BUG_ON(engine->id >= ARRAY_SIZE(ring->gt->engine));
+ ring->gt->engine[engine->id] = engine;
ring->instance++;
engine->legacy_idx = idx;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index b3619a2a5d0e..7a3a9925359b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -37,6 +37,11 @@ void intel_gt_init_hw_early(struct drm_i915_private *i915)
intel_gt_pm_disable(&i915->gt);
}
+void intel_gt_init_mmio(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+ gt->__info.engine_mask = INTEL_INFO(i915)->engine_mask;
+}
+
static void init_unused_ring(struct intel_gt *gt, u32 base)
{
struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index e6ab0bff0efb..a141f9208f69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -29,6 +29,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw_early(struct drm_i915_private *i915);
+void intel_gt_init_mmio(struct intel_gt *gt, struct drm_i915_private *i915);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
void intel_gt_driver_register(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index be4b263621c8..bb813e0a8fa3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -94,6 +94,10 @@ struct intel_gt {
u32 pm_guc_events;
+ struct {
+ intel_engine_mask_t engine_mask;
+ } __info; /* Hack to enable poly-morphic for_each_engine_masked. */
+
struct intel_engine_cs *engine[I915_NUM_ENGINES];
struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
[MAX_ENGINE_INSTANCE + 1];
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f02a34722217..4d8ee8c54abd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -592,6 +592,8 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
intel_device_info_init_mmio(dev_priv);
+ intel_gt_init_mmio(&dev_priv->gt, dev_priv);
+
intel_uncore_prune_mmio_domains(&dev_priv->uncore);
intel_uc_init_mmio(&dev_priv->gt.uc);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites
2019-10-16 12:28 [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt Tvrtko Ursulin
2019-10-16 12:28 ` [PATCH 2/3] drm/i915: Store engine mask in intel_gt Tvrtko Ursulin
@ 2019-10-16 12:28 ` Tvrtko Ursulin
2019-10-16 13:04 ` Chris Wilson
1 sibling, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 12:28 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Where the function, or code segment, operates on intel_gt, we need to
start passing it instead of i915 to for_each_engine(_masked).
This is another partial step in migration of i915->engines[] to
gt->engines[].
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +--
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 6 ++--
drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++++++++----------
drivers/gpu/drm/i915/gt/selftest_context.c | 6 ++--
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 20 ++++++-------
drivers/gpu/drm/i915/gt/selftest_lrc.c | 6 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++--
drivers/gpu/drm/i915/selftests/igt_reset.c | 4 +--
14 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c9d639c6becb..c8c8ee5627ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1118,7 +1118,7 @@ bool intel_engines_are_idle(struct intel_gt *gt)
if (!READ_ONCE(gt->awake))
return true;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
if (!intel_engine_is_idle(engine))
return false;
}
@@ -1131,7 +1131,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
engine->set_default_submission(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 7a3a9925359b..e6c4020834a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -202,7 +202,7 @@ static void gen6_check_faults(struct intel_gt *gt)
enum intel_engine_id id;
u32 fault;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index bd1bd3e00a94..b866d5b1eee0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -136,16 +136,16 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
intel_uc_sanitize(>->uc);
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
if (engine->reset.prepare)
engine->reset.prepare(engine);
if (reset_engines(gt) || force) {
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
__intel_engine_reset(engine, false);
}
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
if (engine->reset.finish)
engine->reset.finish(engine);
}
@@ -177,7 +177,7 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
intel_rc6_sanitize(>->rc6);
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct intel_context *ce;
intel_engine_pm_get(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index cbb4069b11e1..b73229a84d85 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -25,7 +25,7 @@ static void flush_submission(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
intel_engine_flush_submission(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index c14dbeb3ccc3..0fdef00af9e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -237,7 +237,7 @@ static void hangcheck_declare_hang(struct intel_gt *gt,
hung &= ~stuck;
len = scnprintf(msg, sizeof(msg),
"%s on ", stuck == hung ? "no progress" : "hang");
- for_each_engine_masked(engine, gt->i915, hung, tmp)
+ for_each_engine_masked(engine, gt, hung, tmp)
len += scnprintf(msg + len, sizeof(msg) - len,
"%s, ", engine->name);
msg[len-2] = '\0';
@@ -281,7 +281,7 @@ static void hangcheck_elapsed(struct work_struct *work)
*/
intel_uncore_arm_unclaimed_mmio_detection(gt->uncore);
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct hangcheck hc;
intel_engine_breadcrumbs_irq(engine);
@@ -303,7 +303,7 @@ static void hangcheck_elapsed(struct work_struct *work)
if (GEM_SHOW_DEBUG() && (hung | stuck)) {
struct drm_printer p = drm_debug_printer("hangcheck");
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
if (intel_engine_is_idle(engine))
continue;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 77445d100ca8..fdbc7c181962 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -298,7 +298,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
intel_engine_mask_t tmp;
hw_mask = 0;
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
+ for_each_engine_masked(engine, gt, engine_mask, tmp) {
GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
hw_mask |= hw_engine_mask[engine->id];
}
@@ -432,7 +432,7 @@ static int gen11_reset_engines(struct intel_gt *gt,
hw_mask = GEN11_GRDOM_FULL;
} else {
hw_mask = 0;
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
+ for_each_engine_masked(engine, gt, engine_mask, tmp) {
GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
hw_mask |= hw_engine_mask[engine->id];
ret = gen11_lock_sfc(engine, &hw_mask);
@@ -451,7 +451,7 @@ static int gen11_reset_engines(struct intel_gt *gt,
* expiration).
*/
if (engine_mask != ALL_ENGINES)
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
+ for_each_engine_masked(engine, gt, engine_mask, tmp)
gen11_unlock_sfc(engine);
return ret;
@@ -510,7 +510,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
intel_engine_mask_t tmp;
int ret;
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
+ for_each_engine_masked(engine, gt, engine_mask, tmp) {
ret = gen8_engine_reset_prepare(engine);
if (ret && !reset_non_ready)
goto skip_reset;
@@ -536,7 +536,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
ret = gen6_reset_engines(gt, engine_mask, retry);
skip_reset:
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
+ for_each_engine_masked(engine, gt, engine_mask, tmp)
gen8_engine_reset_cancel(engine);
return ret;
@@ -682,7 +682,7 @@ static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
intel_engine_mask_t awake = 0;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
if (intel_engine_pm_get_if_awake(engine))
awake |= engine->mask;
reset_prepare_engine(engine);
@@ -712,7 +712,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
if (err)
return err;
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
__intel_engine_reset(engine, stalled_mask & engine->mask);
i915_gem_restore_fences(gt->i915);
@@ -733,7 +733,7 @@ static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
reset_finish_engine(engine);
if (awake & engine->mask)
intel_engine_pm_put(engine);
@@ -769,7 +769,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
struct drm_printer p = drm_debug_printer(__func__);
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
intel_engine_dump(engine, &p, "%s\n", engine->name);
}
@@ -786,7 +786,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
__intel_gt_reset(gt, ALL_ENGINES);
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
engine->submit_request = nop_submit_request;
/*
@@ -798,7 +798,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
set_bit(I915_WEDGED, >->reset.flags);
/* Mark all executing requests as skipped */
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
engine->cancel_requests(engine);
reset_finish(gt, awake);
@@ -934,7 +934,7 @@ static int resume(struct intel_gt *gt)
enum intel_engine_id id;
int ret;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
ret = engine->resume(engine);
if (ret)
return ret;
@@ -1206,7 +1206,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
* single reset fails.
*/
if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
- for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
+ for_each_engine_masked(engine, gt, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>->reset.flags))
@@ -1234,7 +1234,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
synchronize_rcu_expedited();
/* Prevent any other reset-engine attempt. */
- for_each_engine(engine, gt->i915, tmp) {
+ for_each_engine(engine, gt, tmp) {
while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>->reset.flags))
wait_on_bit(>->reset.flags,
@@ -1244,7 +1244,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
intel_gt_reset_global(gt, engine_mask, msg);
- for_each_engine(engine, gt->i915, tmp)
+ for_each_engine(engine, gt, tmp)
clear_bit_unlock(I915_RESET_ENGINE + engine->id,
>->reset.flags);
clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index 7c838a57e174..f63a26a3e620 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -159,7 +159,7 @@ static int live_context_size(void *arg)
if (IS_ERR(fixme))
return PTR_ERR(fixme);
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct {
struct drm_i915_gem_object *state;
void *pinned;
@@ -305,7 +305,7 @@ static int live_active_context(void *arg)
goto out_file;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
err = __live_active_context(engine, fixme);
if (err)
break;
@@ -415,7 +415,7 @@ static int live_remote_context(void *arg)
goto out_file;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
err = __live_remote_context(engine, fixme);
if (err)
break;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 3a1419376912..20b9c83f43ad 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -25,7 +25,7 @@ static int live_engine_pm(void *arg)
}
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
const typeof(*igt_atomic_phases) *p;
for (p = igt_atomic_phases; p->name; p++) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 569a4105d49e..8e0016464325 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -323,7 +323,7 @@ static int igt_hang_sanitycheck(void *arg)
if (err)
return err;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct intel_wedge_me w;
long timeout;
@@ -400,7 +400,7 @@ static int igt_reset_nop(void *arg)
reset_count = i915_reset_count(global);
count = 0;
do {
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
int i;
for (i = 0; i < 16; i++) {
@@ -471,7 +471,7 @@ static int igt_reset_nop_engine(void *arg)
}
i915_gem_context_clear_bannable(ctx);
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
unsigned int count;
IGT_TIMEOUT(end_time);
@@ -560,7 +560,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active)
return err;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
IGT_TIMEOUT(end_time);
@@ -782,7 +782,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
h.ctx->sched.priority = 1024;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct active_engine threads[I915_NUM_ENGINES] = {};
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
@@ -800,7 +800,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
memset(threads, 0, sizeof(threads));
- for_each_engine(other, gt->i915, tmp) {
+ for_each_engine(other, gt, tmp) {
struct task_struct *tsk;
threads[tmp].resets =
@@ -914,7 +914,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
unwind:
- for_each_engine(other, gt->i915, tmp) {
+ for_each_engine(other, gt, tmp) {
int ret;
if (!threads[tmp].task)
@@ -1335,7 +1335,7 @@ static int wait_for_others(struct intel_gt *gt,
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
if (engine == exclude)
continue;
@@ -1363,7 +1363,7 @@ static int igt_reset_queue(void *arg)
if (err)
goto unlock;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
struct i915_request *prev;
IGT_TIMEOUT(end_time);
unsigned int count;
@@ -1651,7 +1651,7 @@ static int igt_reset_engines_atomic(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
err = igt_atomic_reset_engine(engine, p);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 9c1f34fb5882..fa78695afd86 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -2512,7 +2512,7 @@ static int live_lrc_layout(void *arg)
return -ENOMEM;
err = 0;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
u32 *hw, *lrc;
int dw;
@@ -2705,7 +2705,7 @@ static int live_lrc_state(void *arg)
goto out_close;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
err = __live_lrc_state(fixme, engine, scratch);
if (err)
break;
@@ -2848,7 +2848,7 @@ static int live_gpr_clear(void *arg)
goto out_close;
}
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
err = __live_gpr_clear(fixme, engine, scratch);
if (err)
break;
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 419b38fa7828..6efb9221b7fa 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -125,7 +125,7 @@ static int igt_atomic_engine_reset(void *arg)
if (!igt_force_reset(gt))
goto out_unlock;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
tasklet_disable_nosync(&engine->execlists.tasklet);
intel_engine_pm_get(engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index d6df40cdc8a6..9b4be4b25404 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -664,7 +664,7 @@ static int live_hwsp_wrap(void *arg)
if (err)
goto out_free;
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
const u32 *hwsp_seqno[2];
struct i915_request *rq;
u32 seqno[2];
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..e9713a21779e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1014,7 +1014,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
* to GuC
*/
irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route USER_INTERRUPT to Host, all others are sent to GuC. */
@@ -1062,7 +1062,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
*/
irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route all GT interrupts to the host */
@@ -1145,7 +1145,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
/* Take over from manual control of ELSP (execlists) */
guc_interrupts_capture(gt);
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
engine->set_default_submission = guc_set_default_submission;
engine->set_default_submission(engine);
}
diff --git a/drivers/gpu/drm/i915/selftests/igt_reset.c b/drivers/gpu/drm/i915/selftests/igt_reset.c
index 7ec8f8b049c6..9f8590b868a9 100644
--- a/drivers/gpu/drm/i915/selftests/igt_reset.c
+++ b/drivers/gpu/drm/i915/selftests/igt_reset.c
@@ -22,7 +22,7 @@ void igt_global_reset_lock(struct intel_gt *gt)
wait_event(gt->reset.queue,
!test_bit(I915_RESET_BACKOFF, >->reset.flags));
- for_each_engine(engine, gt->i915, id) {
+ for_each_engine(engine, gt, id) {
while (test_and_set_bit(I915_RESET_ENGINE + id,
>->reset.flags))
wait_on_bit(>->reset.flags, I915_RESET_ENGINE + id,
@@ -35,7 +35,7 @@ void igt_global_reset_unlock(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt->i915, id)
+ for_each_engine(engine, gt, id)
clear_bit(I915_RESET_ENGINE + id, >->reset.flags);
clear_bit(I915_RESET_BACKOFF, >->reset.flags);
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: Store engine mask in intel_gt
2019-10-16 12:28 ` [PATCH 2/3] drm/i915: Store engine mask in intel_gt Tvrtko Ursulin
@ 2019-10-16 13:03 ` Chris Wilson
2019-10-16 13:31 ` Tvrtko Ursulin
0 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2019-10-16 13:03 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2019-10-16 13:28:42)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Medium term goal is to eliminate the i915->engine[] array and to get there
> we have recently introduced equivalent array in intel_gt. Now we need to
> migrate the code further towards this state.
>
> To allow for_each_engine_masked call sites to pass in gt instead of i915
> we need to have a copy of INTEL_INFO()->engine_mask in intel_gt.
>
> For this to work we also need to use engine->id as index when populating
> the gt->engine[] array.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 5 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 77cd5de83930..099abae860ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -183,8 +183,8 @@ static void add_legacy_ring(struct legacy_ring *ring,
> if (unlikely(idx == -1))
> return;
>
> - GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
> - ring->gt->engine[idx] = engine;
This is used for the legacy uapi mapping. So we need to adjust the loop
in i915_gem_context.c::default_engines() to use engine->legacy_idx
instead of id. And all other users of engine->legacy_idx are now
backwards.
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites
2019-10-16 12:28 ` [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites Tvrtko Ursulin
@ 2019-10-16 13:04 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-10-16 13:04 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2019-10-16 13:28:43)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Where the function, or code segment, operates on intel_gt, we need to
> start passing it instead of i915 to for_each_engine(_masked).
>
> This is another partial step in migration of i915->engines[] to
> gt->engines[].
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: Store engine mask in intel_gt
2019-10-16 13:03 ` Chris Wilson
@ 2019-10-16 13:31 ` Tvrtko Ursulin
2019-10-16 13:41 ` Chris Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 13:31 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 16/10/2019 14:03, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-10-16 13:28:42)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Medium term goal is to eliminate the i915->engine[] array and to get there
>> we have recently introduced equivalent array in intel_gt. Now we need to
>> migrate the code further towards this state.
>>
>> To allow for_each_engine_masked call sites to pass in gt instead of i915
>> we need to have a copy of INTEL_INFO()->engine_mask in intel_gt.
>>
>> For this to work we also need to use engine->id as index when populating
>> the gt->engine[] array.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++--
>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++
>> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++
>> drivers/gpu/drm/i915/i915_drv.c | 2 ++
>> 5 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 77cd5de83930..099abae860ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -183,8 +183,8 @@ static void add_legacy_ring(struct legacy_ring *ring,
>> if (unlikely(idx == -1))
>> return;
>>
>> - GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
>> - ring->gt->engine[idx] = engine;
>
> This is used for the legacy uapi mapping. So we need to adjust the loop
> in i915_gem_context.c::default_engines() to use engine->legacy_idx
> instead of id. And all other users of engine->legacy_idx are now
> backwards.
Hmmm that's evil.. I mean so well hidden dependency and contrary to
years of decoupling efforts. But I gather some mess is expected in these
circumstances. I'll update.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: Store engine mask in intel_gt
2019-10-16 13:31 ` Tvrtko Ursulin
@ 2019-10-16 13:41 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2019-10-16 13:41 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2019-10-16 14:31:45)
>
> On 16/10/2019 14:03, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-16 13:28:42)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Medium term goal is to eliminate the i915->engine[] array and to get there
> >> we have recently introduced equivalent array in intel_gt. Now we need to
> >> migrate the code further towards this state.
> >>
> >> To allow for_each_engine_masked call sites to pass in gt instead of i915
> >> we need to have a copy of INTEL_INFO()->engine_mask in intel_gt.
> >>
> >> For this to work we also need to use engine->id as index when populating
> >> the gt->engine[] array.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++--
> >> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++
> >> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> >> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++
> >> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> >> 5 files changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> >> index 77cd5de83930..099abae860ec 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> >> @@ -183,8 +183,8 @@ static void add_legacy_ring(struct legacy_ring *ring,
> >> if (unlikely(idx == -1))
> >> return;
> >>
> >> - GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
> >> - ring->gt->engine[idx] = engine;
> >
> > This is used for the legacy uapi mapping. So we need to adjust the loop
> > in i915_gem_context.c::default_engines() to use engine->legacy_idx
> > instead of id. And all other users of engine->legacy_idx are now
> > backwards.
>
> Hmmm that's evil.. I mean so well hidden dependency and contrary to
> years of decoupling efforts. But I gather some mess is expected in these
> circumstances. I'll update.
The decoupling effort is on the uAPI side, I do think the effort in
moving all the implicit legacy layout to a subset of the explicit user
controls is paying off nicely. The next goal was to remove gt->engine[],
so assumptions that it existed and engine->id was an index into it were
removed.
-Chris
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt
2019-10-16 12:53 ` Tvrtko Ursulin
@ 2019-10-16 21:05 ` Andi Shyti
0 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2019-10-16 21:05 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
> > > - if (!i915_gem_load_power_context(i915)) {
> > > + if (!i915_gem_load_gt_power_context(&i915->gt)) {
> > > err = -EIO;
> > > goto out;
> > > }
> >
> > Not quite, the plan is to move this all to the gt. Paging Andi, come in
> > Andi!
>
> Have you copied him? :) I now have.
loud and clear... will prioritize ;)
Andi
> I don't have any complaints there - but can it be done quickly?
>
> Regards,
>
> Tvrtko
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt
2019-10-16 12:42 ` Chris Wilson
@ 2019-10-16 12:53 ` Tvrtko Ursulin
2019-10-16 21:05 ` Andi Shyti
0 siblings, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 12:53 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 16/10/2019 13:42, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-10-16 13:25:55)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> The code underneath works on intel_gt and also rename to
>> i915_gem_load_gt_power_context to signify it is operating on GT.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +++++++++++++-----------
>> drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 ++-
>> drivers/gpu/drm/i915/i915_gem.c | 2 +-
>> 3 files changed, 16 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> index 7987b54fb1f5..b2c18674c455 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> @@ -56,9 +56,9 @@ static bool switch_to_kernel_context_sync(struct intel_gt *gt)
>> return result;
>> }
>>
>> -bool i915_gem_load_power_context(struct drm_i915_private *i915)
>> +bool i915_gem_load_gt_power_context(struct intel_gt *gt)
>> {
>> - return switch_to_kernel_context_sync(&i915->gt);
>> + return switch_to_kernel_context_sync(gt);
>> }
>>
>> static void user_forcewake(struct intel_gt *gt, bool suspend)
>> @@ -172,11 +172,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
>>
>> void i915_gem_resume(struct drm_i915_private *i915)
>> {
>> + struct intel_gt *gt = &i915->gt;
>> +
>> GEM_TRACE("\n");
>>
>> - intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>> + intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>>
>> - if (intel_gt_init_hw(&i915->gt))
>> + if (intel_gt_init_hw(gt))
>> goto err_wedged;
>>
>> /*
>> @@ -184,26 +186,26 @@ void i915_gem_resume(struct drm_i915_private *i915)
>> * guarantee that the context image is complete. So let's just reset
>> * it and start again.
>> */
>> - if (intel_gt_resume(&i915->gt))
>> + if (intel_gt_resume(gt))
>> goto err_wedged;
>>
>> - intel_uc_resume(&i915->gt.uc);
>> + intel_uc_resume(>->uc);
>>
>> /* Always reload a context for powersaving. */
>> - if (!i915_gem_load_power_context(i915))
>> + if (!i915_gem_load_gt_power_context(gt))
>> goto err_wedged;
>>
>> - user_forcewake(&i915->gt, false);
>> + user_forcewake(gt, false);
>>
>> out_unlock:
>> - intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>> + intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
>> return;
>>
>> err_wedged:
>> - if (!intel_gt_is_wedged(&i915->gt)) {
>> + if (!intel_gt_is_wedged(gt)) {
>> dev_err(i915->drm.dev,
>> "Failed to re-initialize GPU, declaring it wedged!\n");
>> - intel_gt_set_wedged(&i915->gt);
>> + intel_gt_set_wedged(gt);
>> }
>> goto out_unlock;
>> }
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
>> index 6f7d5d11ac3b..38eace4cb6ba 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
>> @@ -10,11 +10,12 @@
>> #include <linux/types.h>
>>
>> struct drm_i915_private;
>> +struct intel_gt;
>> struct work_struct;
>>
>> void i915_gem_init__pm(struct drm_i915_private *i915);
>>
>> -bool i915_gem_load_power_context(struct drm_i915_private *i915);
>> +bool i915_gem_load_gt_power_context(struct intel_gt *gt);
>> void i915_gem_resume(struct drm_i915_private *i915);
>>
>> void i915_gem_idle_work_handler(struct work_struct *work);
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index 0ddbd3a5fb8d..c4ebc21c6820 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -1132,7 +1132,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
>> }
>>
>> /* Flush the default context image to memory, and enable powersaving. */
>> - if (!i915_gem_load_power_context(i915)) {
>> + if (!i915_gem_load_gt_power_context(&i915->gt)) {
>> err = -EIO;
>> goto out;
>> }
>
> Not quite, the plan is to move this all to the gt. Paging Andi, come in
> Andi!
Have you copied him? :) I now have.
I don't have any complaints there - but can it be done quickly?
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt
2019-10-16 12:25 [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt Tvrtko Ursulin
@ 2019-10-16 12:42 ` Chris Wilson
2019-10-16 12:53 ` Tvrtko Ursulin
0 siblings, 1 reply; 11+ messages in thread
From: Chris Wilson @ 2019-10-16 12:42 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2019-10-16 13:25:55)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> The code underneath works on intel_gt and also rename to
> i915_gem_load_gt_power_context to signify it is operating on GT.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +++++++++++++-----------
> drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 ++-
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 3 files changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 7987b54fb1f5..b2c18674c455 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -56,9 +56,9 @@ static bool switch_to_kernel_context_sync(struct intel_gt *gt)
> return result;
> }
>
> -bool i915_gem_load_power_context(struct drm_i915_private *i915)
> +bool i915_gem_load_gt_power_context(struct intel_gt *gt)
> {
> - return switch_to_kernel_context_sync(&i915->gt);
> + return switch_to_kernel_context_sync(gt);
> }
>
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> @@ -172,11 +172,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
>
> void i915_gem_resume(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = &i915->gt;
> +
> GEM_TRACE("\n");
>
> - intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>
> - if (intel_gt_init_hw(&i915->gt))
> + if (intel_gt_init_hw(gt))
> goto err_wedged;
>
> /*
> @@ -184,26 +186,26 @@ void i915_gem_resume(struct drm_i915_private *i915)
> * guarantee that the context image is complete. So let's just reset
> * it and start again.
> */
> - if (intel_gt_resume(&i915->gt))
> + if (intel_gt_resume(gt))
> goto err_wedged;
>
> - intel_uc_resume(&i915->gt.uc);
> + intel_uc_resume(>->uc);
>
> /* Always reload a context for powersaving. */
> - if (!i915_gem_load_power_context(i915))
> + if (!i915_gem_load_gt_power_context(gt))
> goto err_wedged;
>
> - user_forcewake(&i915->gt, false);
> + user_forcewake(gt, false);
>
> out_unlock:
> - intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
> return;
>
> err_wedged:
> - if (!intel_gt_is_wedged(&i915->gt)) {
> + if (!intel_gt_is_wedged(gt)) {
> dev_err(i915->drm.dev,
> "Failed to re-initialize GPU, declaring it wedged!\n");
> - intel_gt_set_wedged(&i915->gt);
> + intel_gt_set_wedged(gt);
> }
> goto out_unlock;
> }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
> index 6f7d5d11ac3b..38eace4cb6ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
> @@ -10,11 +10,12 @@
> #include <linux/types.h>
>
> struct drm_i915_private;
> +struct intel_gt;
> struct work_struct;
>
> void i915_gem_init__pm(struct drm_i915_private *i915);
>
> -bool i915_gem_load_power_context(struct drm_i915_private *i915);
> +bool i915_gem_load_gt_power_context(struct intel_gt *gt);
> void i915_gem_resume(struct drm_i915_private *i915);
>
> void i915_gem_idle_work_handler(struct work_struct *work);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0ddbd3a5fb8d..c4ebc21c6820 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1132,7 +1132,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
> }
>
> /* Flush the default context image to memory, and enable powersaving. */
> - if (!i915_gem_load_power_context(i915)) {
> + if (!i915_gem_load_gt_power_context(&i915->gt)) {
> err = -EIO;
> goto out;
> }
Not quite, the plan is to move this all to the gt. Paging Andi, come in
Andi!
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt
@ 2019-10-16 12:25 Tvrtko Ursulin
2019-10-16 12:42 ` Chris Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Tvrtko Ursulin @ 2019-10-16 12:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
The code underneath works on intel_gt and also rename to
i915_gem_load_gt_power_context to signify it is operating on GT.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 24 +++++++++++++-----------
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 7987b54fb1f5..b2c18674c455 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -56,9 +56,9 @@ static bool switch_to_kernel_context_sync(struct intel_gt *gt)
return result;
}
-bool i915_gem_load_power_context(struct drm_i915_private *i915)
+bool i915_gem_load_gt_power_context(struct intel_gt *gt)
{
- return switch_to_kernel_context_sync(&i915->gt);
+ return switch_to_kernel_context_sync(gt);
}
static void user_forcewake(struct intel_gt *gt, bool suspend)
@@ -172,11 +172,13 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ struct intel_gt *gt = &i915->gt;
+
GEM_TRACE("\n");
- intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
- if (intel_gt_init_hw(&i915->gt))
+ if (intel_gt_init_hw(gt))
goto err_wedged;
/*
@@ -184,26 +186,26 @@ void i915_gem_resume(struct drm_i915_private *i915)
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
- if (intel_gt_resume(&i915->gt))
+ if (intel_gt_resume(gt))
goto err_wedged;
- intel_uc_resume(&i915->gt.uc);
+ intel_uc_resume(>->uc);
/* Always reload a context for powersaving. */
- if (!i915_gem_load_power_context(i915))
+ if (!i915_gem_load_gt_power_context(gt))
goto err_wedged;
- user_forcewake(&i915->gt, false);
+ user_forcewake(gt, false);
out_unlock:
- intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
return;
err_wedged:
- if (!intel_gt_is_wedged(&i915->gt)) {
+ if (!intel_gt_is_wedged(gt)) {
dev_err(i915->drm.dev,
"Failed to re-initialize GPU, declaring it wedged!\n");
- intel_gt_set_wedged(&i915->gt);
+ intel_gt_set_wedged(gt);
}
goto out_unlock;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index 6f7d5d11ac3b..38eace4cb6ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -10,11 +10,12 @@
#include <linux/types.h>
struct drm_i915_private;
+struct intel_gt;
struct work_struct;
void i915_gem_init__pm(struct drm_i915_private *i915);
-bool i915_gem_load_power_context(struct drm_i915_private *i915);
+bool i915_gem_load_gt_power_context(struct intel_gt *gt);
void i915_gem_resume(struct drm_i915_private *i915);
void i915_gem_idle_work_handler(struct work_struct *work);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0ddbd3a5fb8d..c4ebc21c6820 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1132,7 +1132,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
}
/* Flush the default context image to memory, and enable powersaving. */
- if (!i915_gem_load_power_context(i915)) {
+ if (!i915_gem_load_gt_power_context(&i915->gt)) {
err = -EIO;
goto out;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-10-16 21:05 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-16 12:28 [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt Tvrtko Ursulin
2019-10-16 12:28 ` [PATCH 2/3] drm/i915: Store engine mask in intel_gt Tvrtko Ursulin
2019-10-16 13:03 ` Chris Wilson
2019-10-16 13:31 ` Tvrtko Ursulin
2019-10-16 13:41 ` Chris Wilson
2019-10-16 12:28 ` [PATCH 3/3] drm/i915: Pass in intel_gt at some for_each_engine sites Tvrtko Ursulin
2019-10-16 13:04 ` Chris Wilson
-- strict thread matches above, loose matches on Subject: below --
2019-10-16 12:25 [PATCH 1/3] drm/i915: Make i915_gem_load_power_context take struct intel_gt Tvrtko Ursulin
2019-10-16 12:42 ` Chris Wilson
2019-10-16 12:53 ` Tvrtko Ursulin
2019-10-16 21:05 ` Andi Shyti
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