[v1 0/6] Enable HDR on MCA LSPCON based Gen9 devices

[v1 0/6] Enable HDR on MCA LSPCON based Gen9 devices

[Uma Shankar]

Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
support for MCA LSPCON based GEN9 devices.

SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.

Uma Shankar (6):
  drm/i915/display: Add HDR Capability detection for LSPCON
  drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
  drm/i915/display: Attach HDR property for capable Gen9 devices
  drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices
  drm/i915/display: Enable BT2020 for HDR on LSPCON devices
  drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

 drivers/gpu/drm/drm_atomic_state_helper.c     |  1 +
 drivers/gpu/drm/drm_atomic_uapi.c             |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 10 ++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 19 +++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 33 +++++++
 drivers/gpu/drm/i915/display/intel_lspcon.c   | 91 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_lspcon.h   |  7 ++
 include/drm/drm_connector.h                   |  1 +
 9 files changed, 152 insertions(+), 12 deletions(-)

-- 
2.22.0

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[v1 1/6] drm/i915/display: Add HDR Capability detection for LSPCON

[Uma Shankar]

LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_lspcon.c   | 32 +++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..560af086259a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1268,6 +1268,7 @@ struct intel_lspcon {
 	bool active;
 	enum drm_lspcon_mode mode;
 	enum lspcon_vendor vendor;
+	bool hdr_supported;
 };
 
 struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f8f1308643a9..a1d0127b7f57 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
+#define DPCD_MCA_LSPCON_HDR_STATUS	0x70003
+
 /* AUX addresses to write MCA AVI IF */
 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
 	return true;
 }
 
+static bool lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+	struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+	u8 hdr_caps;
+	int ret;
+
+	/* Enable HDR for MCA based LSPCON devices */
+	if (lspcon->vendor == LSPCON_VENDOR_MCA)
+		ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
+				       &hdr_caps, 1);
+	else
+		return false;
+
+	if (ret < 0) {
+		DRM_DEBUG_KMS("hdr capability detection failed\n");
+		lspcon->hdr_supported = false;
+		return false;
+	} else if (hdr_caps & 0x1) {
+		DRM_DEBUG_KMS("lspcon capable of HDR\n");
+		lspcon->hdr_supported = true;
+	}
+
+	return true;
+}
+
 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
 {
 	enum drm_lspcon_mode current_mode;
@@ -581,6 +608,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
 		return false;
 	}
 
+	if (!lspcon_detect_hdr_capability(lspcon)) {
+		DRM_ERROR("LSPCON hdr detection failed\n");
+		return false;
+	}
+
 	connector->ycbcr_420_allowed = true;
 	lspcon->active = true;
 	DRM_DEBUG_KMS("Success: LSPCON init\n");
-- 
2.22.0

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[v1 2/6] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon

[Uma Shankar]

Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.

SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 33 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lspcon.c | 36 ++++++++++++++-------
 drivers/gpu/drm/i915/display/intel_lspcon.h |  4 +++
 3 files changed, 62 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 92d1cbbbee2b..460e10fb1782 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -576,6 +576,39 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 	return val & mask;
 }
 
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state,
+				unsigned int type,
+				const void *frame, ssize_t len)
+{
+	const u32 *data = frame;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
+	int data_size;
+	int i;
+	u32 val = I915_READ(ctl_reg);
+
+	data_size = hsw_dip_data_size(dev_priv, type);
+
+	val &= ~hsw_infoframe_enable(type);
+	I915_WRITE(ctl_reg, val);
+
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+					    type, i >> 2), *data);
+		data++;
+	}
+	/* Write every possible data byte to force correct ECC calculation. */
+	for (; i < data_size; i += 4)
+		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+					    type, i >> 2), 0);
+
+	val |= hsw_infoframe_enable(type);
+	I915_WRITE(ctl_reg, val);
+	POSTING_READ(ctl_reg);
+}
+
 static const u8 infoframe_type_to_idx[] = {
 	HDMI_PACKET_TYPE_GENERAL_CONTROL,
 	HDMI_PACKET_TYPE_GAMUT_METADATA,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index a1d0127b7f57..51ad5f02e700 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -460,27 +460,41 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
 			    unsigned int type,
 			    const void *frame, ssize_t len)
 {
-	bool ret;
+	bool ret = true;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
 
-	/* LSPCON only needs AVI IF */
-	if (type != HDMI_INFOFRAME_TYPE_AVI)
+	if (!(type == HDMI_INFOFRAME_TYPE_AVI ||
+	      type == HDMI_PACKET_TYPE_GAMUT_METADATA))
 		return;
 
-	if (lspcon->vendor == LSPCON_VENDOR_MCA)
-		ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
-						      frame, len);
-	else
-		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
-							 frame, len);
+	/*
+	 * Supporting HDR on MCA LSPCON
+	 * Todo: Add support for Parade later
+	 */
+	if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
+	    lspcon->vendor != LSPCON_VENDOR_MCA)
+		return;
+
+	if (lspcon->vendor == LSPCON_VENDOR_MCA) {
+		if (type == HDMI_INFOFRAME_TYPE_AVI)
+			ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
+							      frame, len);
+		else if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
+			lspcon_drm_write_infoframe(encoder, crtc_state,
+						   HDMI_PACKET_TYPE_GAMUT_METADATA,
+						   frame, VIDEO_DIP_DATA_SIZE);
+	} else {
+		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, frame,
+							 len);
+	}
 
 	if (!ret) {
-		DRM_ERROR("Failed to write AVI infoframes\n");
+		DRM_ERROR("Failed to write infoframes\n");
 		return;
 	}
 
-	DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
+	DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
 }
 
 void lspcon_read_infoframe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 37cfddf8a9c5..65878904f672 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -35,4 +35,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
 void lspcon_ycbcr420_config(struct drm_connector *connector,
 			    struct intel_crtc_state *crtc_state);
 
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state,
+				unsigned int type,
+				const void *frame, ssize_t len);
 #endif /* __INTEL_LSPCON_H__ */
-- 
2.22.0

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[v1 3/6] drm/i915/display: Attach HDR property for capable Gen9 devices

[Uma Shankar]

Attach HDR property for Gen9 devices with MCA LSPCON
chips.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 51ad5f02e700..c32452360eeb 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -627,6 +627,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
 		return false;
 	}
 
+	if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+		drm_object_attach_property(&connector->base,
+					   connector->dev->mode_config.hdr_output_metadata_property,
+					   0);
+
 	connector->ycbcr_420_allowed = true;
 	lspcon->active = true;
 	DRM_DEBUG_KMS("Success: LSPCON init\n");
-- 
2.22.0

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[v1 4/6] drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices

[Uma Shankar]

Send Dynamic Range and Mastering Infoframe (DRM for HDR metadata)
as SDP packet to LSPCON following the DP spec. LSPCON receives the
same and sends it to HDMI sink.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/drm_atomic_state_helper.c   |  1 +
 drivers/gpu/drm/drm_atomic_uapi.c           |  1 +
 drivers/gpu/drm/i915/display/intel_ddi.c    | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_dp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_lspcon.h |  3 +++
 include/drm/drm_connector.h                 |  1 +
 6 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c
index d0a937fb0c56..e78b3a1626fd 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -416,6 +416,7 @@ __drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector,
 
 	if (state->hdr_output_metadata)
 		drm_property_blob_get(state->hdr_output_metadata);
+	state->hdr_metadata_changed = false;
 
 	/* Don't copy over a writeback job, they are used only once */
 	state->writeback_job = NULL;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 0d466d3b0809..5beabcd42d30 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -734,6 +734,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector,
 				val,
 				sizeof(struct hdr_output_metadata), -1,
 				&replaced);
+		state->hdr_metadata_changed |= replaced;
 		return ret;
 	} else if (property == config->aspect_ratio_property) {
 		state->picture_aspect_ratio = val;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 80f8e2698be0..bfb680d3f4cf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3847,6 +3847,8 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_lspcon *lspcon =
+				enc_to_intel_lspcon(&encoder->base);
 	enum port port = encoder->port;
 
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
@@ -3856,6 +3858,12 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 	intel_psr_enable(intel_dp, crtc_state);
 	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
 	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+
+	/* Set the infoframe for NON modeset cases as well */
+	if (lspcon->active && lspcon->hdr_supported &&
+	    conn_state->hdr_metadata_changed)
+		intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp, crtc_state,
+							  conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
@@ -4027,6 +4035,8 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder,
 {
 	struct intel_connector *connector =
 				to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
 	struct intel_hdcp *hdcp = &connector->hdcp;
 	bool content_protection_type_changed =
 			(conn_state->hdcp_content_type != hdcp->content_type &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd5dc1e38495..d92777bd3bed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4624,7 +4624,7 @@ intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
 			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
 }
 
-static void
+void
 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					  const struct intel_crtc_state *crtc_state,
 					  const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 65878904f672..2a175ea7eac2 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -39,4 +39,7 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state,
 				unsigned int type,
 				const void *frame, ssize_t len);
+void intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+					       const struct intel_crtc_state *crtc_state,
+					       const struct drm_connector_state *conn_state);
 #endif /* __INTEL_LSPCON_H__ */
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 5f8c3389d46f..1f0b4fcf0bd3 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -661,6 +661,7 @@ struct drm_connector_state {
 	 * DRM blob property for HDR output metadata
 	 */
 	struct drm_property_blob *hdr_output_metadata;
+	u8 hdr_metadata_changed : 1;
 };
 
 /**
-- 
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[v1 5/6] drm/i915/display: Enable BT2020 for HDR on LSPCON devices

[Uma Shankar]

Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index c32452360eeb..8565bf73c4cd 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -505,6 +505,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
 	/* FIXME implement this */
 }
 
+/* HDMI HDR Colorspace Spec Definitions */
+#define NORMAL_COLORIMETRY_MASK		0x3
+#define EXTENDED_COLORIMETRY_MASK	0x7
+#define HDMI_COLORIMETRY_BT2020_YCC	((3 << 0) | (6 << 2) | (0 << 5))
+
 void lspcon_set_infoframes(struct intel_encoder *encoder,
 			   bool enable,
 			   const struct intel_crtc_state *crtc_state,
@@ -549,6 +554,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 					   HDMI_QUANTIZATION_RANGE_LIMITED :
 					   HDMI_QUANTIZATION_RANGE_FULL);
 
+	/*
+	 * Set BT2020 colorspace if driving HDR data
+	 * ToDo: Make this generic and expose all colorspaces for lspcon
+	 */
+	if (lspcon->active && conn_state->hdr_metadata_changed) {
+		frame.avi.colorimetry =
+				HDMI_COLORIMETRY_BT2020_YCC &
+				NORMAL_COLORIMETRY_MASK;
+		frame.avi.extended_colorimetry =
+				(HDMI_COLORIMETRY_BT2020_YCC >> 2) &
+				 EXTENDED_COLORIMETRY_MASK;
+	}
+
 	ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
 	if (ret < 0) {
 		DRM_ERROR("Failed to pack AVI IF\n");
-- 
2.22.0

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[v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

[Uma Shankar]

Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d92777bd3bed..a12b6916023d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -597,8 +597,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&intel_encoder->base);
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk;
@@ -620,6 +622,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
 		target_clock = fixed_mode->clock;
 	}
 
+	/*
+	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+	 * cause mode to blank out. Reduced Htotal by shortening the back porch
+	 * and front porch within permissible limits.
+	 */
+	if (lspcon->active && lspcon->hdr_supported &&
+	    mode->clock > 570000) {
+		mode->clock = 570000;
+		mode->htotal -= 180;
+		mode->hsync_start -= 72;
+		mode->hsync_end -= 72;
+	}
+
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
-- 
2.22.0

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✗ Fi.CI.BUILD: failure for Enable HDR on MCA LSPCON based Gen9 devices

[Patchwork]

== Series Details ==

Series: Enable HDR on MCA LSPCON based Gen9 devices
URL   : https://patchwork.freedesktop.org/series/68081/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  CC      drivers/gpu/drm/i915/display/intel_gmbus.h.s
  CC      drivers/gpu/drm/i915/display/intel_display_types.h.s
  CC      drivers/gpu/drm/i915/display/intel_overlay.h.s
  CC      drivers/gpu/drm/i915/display/intel_panel.h.s
  CC      drivers/gpu/drm/i915/display/intel_dp_link_training.h.s
  CC      drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h.s
  CC      drivers/gpu/drm/i915/display/intel_bios.h.s
  CC      drivers/gpu/drm/i915/display/intel_tv.h.s
  CC      drivers/gpu/drm/i915/display/intel_opregion.h.s
  CC      drivers/gpu/drm/i915/display/intel_dp_mst.h.s
  CC      drivers/gpu/drm/i915/display/intel_pipe_crc.h.s
  CC      drivers/gpu/drm/i915/display/intel_fifo_underrun.h.s
  CC      drivers/gpu/drm/i915/display/intel_quirks.h.s
  CC      drivers/gpu/drm/i915/display/intel_display_power.h.s
  CC      drivers/gpu/drm/i915/display/intel_connector.h.s
  CC      drivers/gpu/drm/i915/display/intel_hdcp.h.s
  CC      drivers/gpu/drm/i915/display/intel_tc.h.s
  CC      drivers/gpu/drm/i915/display/intel_vga.h.s
  CC      drivers/gpu/drm/i915/display/intel_display.h.s
  CC      drivers/gpu/drm/i915/display/intel_lvds.h.s
  CC      drivers/gpu/drm/i915/display/intel_hdmi.h.s
  CC      drivers/gpu/drm/i915/display/intel_dpio_phy.h.s
  CC      drivers/gpu/drm/i915/display/intel_bw.h.s
  CC      drivers/gpu/drm/i915/display/intel_lspcon.h.s
In file included from <command-line>:0:0:
./drivers/gpu/drm/i915/display/intel_lspcon.h:42:55: error: ‘struct intel_dp’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
 void intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
                                                       ^~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/display/intel_lspcon.h.s' failed
make[5]: *** [drivers/gpu/drm/i915/display/intel_lspcon.h.s] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915/display' failed
make[4]: *** [drivers/gpu/drm/i915/display] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1649: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

[Ville Syrjälä]

On Wed, Oct 16, 2019 at 04:02:49PM +0530, Uma Shankar wrote:
> Blanking needs to be reduced to incorporate DP and HDMI timing/link
> bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
> 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
> This will cause mode to blank out. Reduced Htotal by shortening the
> back porch and front porch within permissible limits.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d92777bd3bed..a12b6916023d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -597,8 +597,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
> +	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
>  	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&intel_encoder->base);
>  	int target_clock = mode->clock;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>  	int max_dotclk;
> @@ -620,6 +622,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  		target_clock = fixed_mode->clock;
>  	}
>  
> +	/*
> +	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
> +	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
> +	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
> +	 * cause mode to blank out. Reduced Htotal by shortening the back porch
> +	 * and front porch within permissible limits.
> +	 */
> +	if (lspcon->active && lspcon->hdr_supported &&
> +	    mode->clock > 570000) {
> +		mode->clock = 570000;
> +		mode->htotal -= 180;
> +		mode->hsync_start -= 72;
> +		mode->hsync_end -= 72;
> +	}

I don't think we want these kind of hacks. Either the mode works or it
doesn't.

> +
>  	max_link_clock = intel_dp_max_link_rate(intel_dp);
>  	max_lanes = intel_dp_max_lane_count(intel_dp);
>  
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [v1 2/6] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon

[Ville Syrjälä]

On Wed, Oct 16, 2019 at 04:02:45PM +0530, Uma Shankar wrote:
> Gen9 hardware supports HDMI2.0 through LSPCON chips.
> Extending HDR support for MCA LSPCON based GEN9 devices.
> 
> SOC will drive LSPCON as DP and send HDR metadata as standard
> DP SDP packets. LSPCON will be set to operate in PCON mode,
> will receive the metadata and create Dynamic Range and
> Mastering Infoframe (DRM packets) and send it to HDR capable
> HDMI sink devices.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c   | 33 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 36 ++++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_lspcon.h |  4 +++
>  3 files changed, 62 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 92d1cbbbee2b..460e10fb1782 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -576,6 +576,39 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
>  	return val & mask;
>  }
>  
> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state,
> +				unsigned int type,
> +				const void *frame, ssize_t len)
> +{
> +	const u32 *data = frame;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> +	int data_size;
> +	int i;
> +	u32 val = I915_READ(ctl_reg);
> +
> +	data_size = hsw_dip_data_size(dev_priv, type);
> +
> +	val &= ~hsw_infoframe_enable(type);
> +	I915_WRITE(ctl_reg, val);
> +
> +	for (i = 0; i < len; i += 4) {
> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> +					    type, i >> 2), *data);
> +		data++;
> +	}
> +	/* Write every possible data byte to force correct ECC calculation. */
> +	for (; i < data_size; i += 4)
> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
> +					    type, i >> 2), 0);
> +
> +	val |= hsw_infoframe_enable(type);
> +	I915_WRITE(ctl_reg, val);
> +	POSTING_READ(ctl_reg);
> +}

We already have that code.

> +
>  static const u8 infoframe_type_to_idx[] = {
>  	HDMI_PACKET_TYPE_GENERAL_CONTROL,
>  	HDMI_PACKET_TYPE_GAMUT_METADATA,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index a1d0127b7f57..51ad5f02e700 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -460,27 +460,41 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
>  			    unsigned int type,
>  			    const void *frame, ssize_t len)
>  {
> -	bool ret;
> +	bool ret = true;
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
>  
> -	/* LSPCON only needs AVI IF */
> -	if (type != HDMI_INFOFRAME_TYPE_AVI)
> +	if (!(type == HDMI_INFOFRAME_TYPE_AVI ||
> +	      type == HDMI_PACKET_TYPE_GAMUT_METADATA))
>  		return;
>  
> -	if (lspcon->vendor == LSPCON_VENDOR_MCA)
> -		ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> -						      frame, len);
> -	else
> -		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> -							 frame, len);
> +	/*
> +	 * Supporting HDR on MCA LSPCON
> +	 * Todo: Add support for Parade later
> +	 */
> +	if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> +	    lspcon->vendor != LSPCON_VENDOR_MCA)
> +		return;
> +
> +	if (lspcon->vendor == LSPCON_VENDOR_MCA) {
> +		if (type == HDMI_INFOFRAME_TYPE_AVI)
> +			ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> +							      frame, len);
> +		else if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
> +			lspcon_drm_write_infoframe(encoder, crtc_state,
> +						   HDMI_PACKET_TYPE_GAMUT_METADATA,
> +						   frame, VIDEO_DIP_DATA_SIZE);
> +	} else {
> +		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, frame,
> +							 len);
> +	}
>  
>  	if (!ret) {
> -		DRM_ERROR("Failed to write AVI infoframes\n");
> +		DRM_ERROR("Failed to write infoframes\n");
>  		return;
>  	}
>  
> -	DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
> +	DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
>  }
>  
>  void lspcon_read_infoframe(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index 37cfddf8a9c5..65878904f672 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -35,4 +35,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
>  void lspcon_ycbcr420_config(struct drm_connector *connector,
>  			    struct intel_crtc_state *crtc_state);
>  
> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state,
> +				unsigned int type,
> +				const void *frame, ssize_t len);
>  #endif /* __INTEL_LSPCON_H__ */
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [v1 0/6] Enable HDR on MCA LSPCON based Gen9 devices

[Ville Syrjälä]

On Wed, Oct 16, 2019 at 04:02:43PM +0530, Uma Shankar wrote:
> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
> support for MCA LSPCON based GEN9 devices.

Couple of general comments about the LSPCON stuff.

a) we need infoframe readout support
b) we need to stop sending infoframes to DVI sinks
c) we need to figure out how to disable the AVI infoframe
   once enabled (if it doesn't get automagically disabled
   when do a modeset), because otherwise when we switch
   displays from HDMI to DVI we will still send the infoframe
   to the DVI sink

I think those should be fixed first before we add more
infoframes to the mix.

Also if we use the SDP stuff for the HDR infoframe we should
just integrate it properly with the already existing DP HDR
metadata stuff. And we need to add readout support for that.

-- 
Ville Syrjälä
Intel
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Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Sent: Wednesday, October 16, 2019 6:44 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
>gyeong.mun@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
>Subject: Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for
>LSPCON
>
>On Wed, Oct 16, 2019 at 04:02:49PM +0530, Uma Shankar wrote:
>> Blanking needs to be reduced to incorporate DP and HDMI timing/link
>> bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
>> 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
>> This will cause mode to blank out. Reduced Htotal by shortening the
>> back porch and front porch within permissible limits.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index d92777bd3bed..a12b6916023d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -597,8 +597,10 @@ intel_dp_mode_valid(struct drm_connector
>> *connector,  {
>>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>>  	struct intel_connector *intel_connector =
>> to_intel_connector(connector);
>> +	struct intel_encoder *intel_encoder =
>> +intel_attached_encoder(connector);
>>  	struct drm_display_mode *fixed_mode = intel_connector-
>>panel.fixed_mode;
>>  	struct drm_i915_private *dev_priv = to_i915(connector->dev);
>> +	struct intel_lspcon *lspcon =
>> +enc_to_intel_lspcon(&intel_encoder->base);
>>  	int target_clock = mode->clock;
>>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>>  	int max_dotclk;
>> @@ -620,6 +622,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
>>  		target_clock = fixed_mode->clock;
>>  	}
>>
>> +	/*
>> +	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
>> +	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
>> +	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
>> +	 * cause mode to blank out. Reduced Htotal by shortening the back porch
>> +	 * and front porch within permissible limits.
>> +	 */
>> +	if (lspcon->active && lspcon->hdr_supported &&
>> +	    mode->clock > 570000) {
>> +		mode->clock = 570000;
>> +		mode->htotal -= 180;
>> +		mode->hsync_start -= 72;
>> +		mode->hsync_end -= 72;
>> +	}
>
>I don't think we want these kind of hacks. Either the mode works or it doesn't.

Hi Ville,
Yeah this is not ideal. But in order to enable HDR which is mostly 10bit content on Lspcon based
Gen9 devices there are limitations on bandwidth side on DP. So with that limit, we cannot drive
10bit content at 4k@60. But practically we can get this working and able to drive the sink without
any real issues with above timing adjustments. This gets enabled if firmware advertise HDR capabilities,
 so in case a vendor doesn't want this, it can be disabled in the LSPCON firmware.

I tested on HDMI analyzer and multiple sinks and also data from other OS teams suggest that this
configuration works and is enabled in some of the products as well.

Definitely not ideal, but at least we get HDR working on Gen9 devices with this, with an option
of disabling if not required. This can be more of quirk kind of thing.

What do you suggest.

Regards,
Uma Shankar

>> +
>>  	max_link_clock = intel_dp_max_link_rate(intel_dp);
>>  	max_lanes = intel_dp_max_lane_count(intel_dp);
>>
>> --
>> 2.22.0
>
>--
>Ville Syrjälä
>Intel
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Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

[Ville Syrjälä]

On Wed, Oct 16, 2019 at 01:46:24PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Sent: Wednesday, October 16, 2019 6:44 PM
> >To: Shankar, Uma <uma.shankar@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
> >gyeong.mun@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
> >Subject: Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for
> >LSPCON
> >
> >On Wed, Oct 16, 2019 at 04:02:49PM +0530, Uma Shankar wrote:
> >> Blanking needs to be reduced to incorporate DP and HDMI timing/link
> >> bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
> >> 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
> >> This will cause mode to blank out. Reduced Htotal by shortening the
> >> back porch and front porch within permissible limits.
> >>
> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
> >>  1 file changed, 17 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index d92777bd3bed..a12b6916023d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -597,8 +597,10 @@ intel_dp_mode_valid(struct drm_connector
> >> *connector,  {
> >>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
> >>  	struct intel_connector *intel_connector =
> >> to_intel_connector(connector);
> >> +	struct intel_encoder *intel_encoder =
> >> +intel_attached_encoder(connector);
> >>  	struct drm_display_mode *fixed_mode = intel_connector-
> >>panel.fixed_mode;
> >>  	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> >> +	struct intel_lspcon *lspcon =
> >> +enc_to_intel_lspcon(&intel_encoder->base);
> >>  	int target_clock = mode->clock;
> >>  	int max_rate, mode_rate, max_lanes, max_link_clock;
> >>  	int max_dotclk;
> >> @@ -620,6 +622,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
> >>  		target_clock = fixed_mode->clock;
> >>  	}
> >>
> >> +	/*
> >> +	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
> >> +	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
> >> +	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
> >> +	 * cause mode to blank out. Reduced Htotal by shortening the back porch
> >> +	 * and front porch within permissible limits.
> >> +	 */
> >> +	if (lspcon->active && lspcon->hdr_supported &&
> >> +	    mode->clock > 570000) {
> >> +		mode->clock = 570000;
> >> +		mode->htotal -= 180;
> >> +		mode->hsync_start -= 72;
> >> +		mode->hsync_end -= 72;
> >> +	}
> >
> >I don't think we want these kind of hacks. Either the mode works or it doesn't.
> 
> Hi Ville,
> Yeah this is not ideal. But in order to enable HDR which is mostly 10bit content on Lspcon based
> Gen9 devices there are limitations on bandwidth side on DP. So with that limit, we cannot drive
> 10bit content at 4k@60. But practically we can get this working and able to drive the sink without
> any real issues with above timing adjustments. This gets enabled if firmware advertise HDR capabilities,
>  so in case a vendor doesn't want this, it can be disabled in the LSPCON firmware.
> 
> I tested on HDMI analyzer and multiple sinks and also data from other OS teams suggest that this
> configuration works and is enabled in some of the products as well.
> 
> Definitely not ideal, but at least we get HDR working on Gen9 devices with this, with an option
> of disabling if not required. This can be more of quirk kind of thing.
> 
> What do you suggest.

If user wants HDR user overrides the mode manually.

-- 
Ville Syrjälä
Intel
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Re: [v1 6/6] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

[Shankar, Uma]

>> >-----Original Message-----
>> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >Sent: Wednesday, October 16, 2019 6:44 PM
>> >To: Shankar, Uma <uma.shankar@intel.com>
>> >Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
>> >gyeong.mun@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
>> >Subject: Re: [v1 6/6] drm/i915/display: Reduce blanking to support
>> >4k60@10bpp for LSPCON
>> >
>> >On Wed, Oct 16, 2019 at 04:02:49PM +0530, Uma Shankar wrote:
>> >> Blanking needs to be reduced to incorporate DP and HDMI timing/link
>> >> bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
>> >> 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
>> >> This will cause mode to blank out. Reduced Htotal by shortening the
>> >> back porch and front porch within permissible limits.
>> >>
>> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++
>> >>  1 file changed, 17 insertions(+)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> index d92777bd3bed..a12b6916023d 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> @@ -597,8 +597,10 @@ intel_dp_mode_valid(struct drm_connector
>> >> *connector,  {
>> >>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>> >>  	struct intel_connector *intel_connector =
>> >> to_intel_connector(connector);
>> >> +	struct intel_encoder *intel_encoder =
>> >> +intel_attached_encoder(connector);
>> >>  	struct drm_display_mode *fixed_mode = intel_connector-
>> >>panel.fixed_mode;
>> >>  	struct drm_i915_private *dev_priv = to_i915(connector->dev);
>> >> +	struct intel_lspcon *lspcon =
>> >> +enc_to_intel_lspcon(&intel_encoder->base);
>> >>  	int target_clock = mode->clock;
>> >>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>> >>  	int max_dotclk;
>> >> @@ -620,6 +622,21 @@ intel_dp_mode_valid(struct drm_connector
>*connector,
>> >>  		target_clock = fixed_mode->clock;
>> >>  	}
>> >>
>> >> +	/*
>> >> +	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
>> >> +	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
>> >> +	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
>> >> +	 * cause mode to blank out. Reduced Htotal by shortening the back porch
>> >> +	 * and front porch within permissible limits.
>> >> +	 */
>> >> +	if (lspcon->active && lspcon->hdr_supported &&
>> >> +	    mode->clock > 570000) {
>> >> +		mode->clock = 570000;
>> >> +		mode->htotal -= 180;
>> >> +		mode->hsync_start -= 72;
>> >> +		mode->hsync_end -= 72;
>> >> +	}
>> >
>> >I don't think we want these kind of hacks. Either the mode works or it doesn't.
>>
>> Hi Ville,
>> Yeah this is not ideal. But in order to enable HDR which is mostly
>> 10bit content on Lspcon based
>> Gen9 devices there are limitations on bandwidth side on DP. So with
>> that limit, we cannot drive 10bit content at 4k@60. But practically we
>> can get this working and able to drive the sink without any real
>> issues with above timing adjustments. This gets enabled if firmware advertise HDR
>capabilities,  so in case a vendor doesn't want this, it can be disabled in the LSPCON
>firmware.
>>
>> I tested on HDMI analyzer and multiple sinks and also data from other
>> OS teams suggest that this configuration works and is enabled in some of the
>products as well.
>>
>> Definitely not ideal, but at least we get HDR working on Gen9 devices
>> with this, with an option of disabling if not required. This can be more of quirk kind
>of thing.
>>
>> What do you suggest.
>
>If user wants HDR user overrides the mode manually.

Yeah that can also be an option. We can tell product teams to have these hacks on the
userspace side. We just need to educate them of these.

Thanks Ville for your inputs. Will drop this from the series.

Regards,
Uma Shankar

>--
>Ville Syrjälä
>Intel
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Re: [v1 2/6] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Sent: Wednesday, October 16, 2019 6:44 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
>gyeong.mun@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
>Subject: Re: [v1 2/6] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
>
>On Wed, Oct 16, 2019 at 04:02:45PM +0530, Uma Shankar wrote:
>> Gen9 hardware supports HDMI2.0 through LSPCON chips.
>> Extending HDR support for MCA LSPCON based GEN9 devices.
>>
>> SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP
>> packets. LSPCON will be set to operate in PCON mode, will receive the
>> metadata and create Dynamic Range and Mastering Infoframe (DRM
>> packets) and send it to HDR capable HDMI sink devices.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_hdmi.c   | 33 +++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_lspcon.c | 36
>> ++++++++++++++-------  drivers/gpu/drm/i915/display/intel_lspcon.h |
>> 4 +++
>>  3 files changed, 62 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 92d1cbbbee2b..460e10fb1782 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -576,6 +576,39 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
>*encoder,
>>  	return val & mask;
>>  }
>>
>> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
>> +				const struct intel_crtc_state *crtc_state,
>> +				unsigned int type,
>> +				const void *frame, ssize_t len)
>> +{
>> +	const u32 *data = frame;
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
>> +	int data_size;
>> +	int i;
>> +	u32 val = I915_READ(ctl_reg);
>> +
>> +	data_size = hsw_dip_data_size(dev_priv, type);
>> +
>> +	val &= ~hsw_infoframe_enable(type);
>> +	I915_WRITE(ctl_reg, val);
>> +
>> +	for (i = 0; i < len; i += 4) {
>> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
>> +					    type, i >> 2), *data);
>> +		data++;
>> +	}
>> +	/* Write every possible data byte to force correct ECC calculation. */
>> +	for (; i < data_size; i += 4)
>> +		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
>> +					    type, i >> 2), 0);
>> +
>> +	val |= hsw_infoframe_enable(type);
>> +	I915_WRITE(ctl_reg, val);
>> +	POSTING_READ(ctl_reg);
>> +}
>
>We already have that code.

Sure yeah, will reuse the same and remove this redundancy.

>> +
>>  static const u8 infoframe_type_to_idx[] = {
>>  	HDMI_PACKET_TYPE_GENERAL_CONTROL,
>>  	HDMI_PACKET_TYPE_GAMUT_METADATA,
>> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
>> b/drivers/gpu/drm/i915/display/intel_lspcon.c
>> index a1d0127b7f57..51ad5f02e700 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
>> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
>> @@ -460,27 +460,41 @@ void lspcon_write_infoframe(struct intel_encoder
>*encoder,
>>  			    unsigned int type,
>>  			    const void *frame, ssize_t len)  {
>> -	bool ret;
>> +	bool ret = true;
>>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>>  	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
>>
>> -	/* LSPCON only needs AVI IF */
>> -	if (type != HDMI_INFOFRAME_TYPE_AVI)
>> +	if (!(type == HDMI_INFOFRAME_TYPE_AVI ||
>> +	      type == HDMI_PACKET_TYPE_GAMUT_METADATA))
>>  		return;
>>
>> -	if (lspcon->vendor == LSPCON_VENDOR_MCA)
>> -		ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
>> -						      frame, len);
>> -	else
>> -		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
>> -							 frame, len);
>> +	/*
>> +	 * Supporting HDR on MCA LSPCON
>> +	 * Todo: Add support for Parade later
>> +	 */
>> +	if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
>> +	    lspcon->vendor != LSPCON_VENDOR_MCA)
>> +		return;
>> +
>> +	if (lspcon->vendor == LSPCON_VENDOR_MCA) {
>> +		if (type == HDMI_INFOFRAME_TYPE_AVI)
>> +			ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
>> +							      frame, len);
>> +		else if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
>> +			lspcon_drm_write_infoframe(encoder, crtc_state,
>> +
>HDMI_PACKET_TYPE_GAMUT_METADATA,
>> +						   frame, VIDEO_DIP_DATA_SIZE);
>> +	} else {
>> +		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, frame,
>> +							 len);
>> +	}
>>
>>  	if (!ret) {
>> -		DRM_ERROR("Failed to write AVI infoframes\n");
>> +		DRM_ERROR("Failed to write infoframes\n");
>>  		return;
>>  	}
>>
>> -	DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
>> +	DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
>>  }
>>
>>  void lspcon_read_infoframe(struct intel_encoder *encoder, diff --git
>> a/drivers/gpu/drm/i915/display/intel_lspcon.h
>> b/drivers/gpu/drm/i915/display/intel_lspcon.h
>> index 37cfddf8a9c5..65878904f672 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
>> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
>> @@ -35,4 +35,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder
>> *encoder,  void lspcon_ycbcr420_config(struct drm_connector *connector,
>>  			    struct intel_crtc_state *crtc_state);
>>
>> +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
>> +				const struct intel_crtc_state *crtc_state,
>> +				unsigned int type,
>> +				const void *frame, ssize_t len);
>>  #endif /* __INTEL_LSPCON_H__ */
>> --
>> 2.22.0
>
>--
>Ville Syrjälä
>Intel
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Re: [v1 0/6] Enable HDR on MCA LSPCON based Gen9 devices

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Sent: Wednesday, October 16, 2019 6:48 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
>gyeong.mun@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
>Subject: Re: [v1 0/6] Enable HDR on MCA LSPCON based Gen9 devices
>
>On Wed, Oct 16, 2019 at 04:02:43PM +0530, Uma Shankar wrote:
>> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
>> support for MCA LSPCON based GEN9 devices.
>
>Couple of general comments about the LSPCON stuff.
>
>a) we need infoframe readout support

We lack that in general for all the DP SDP stuff. Discussed with GG
and hopefully he has plans for DP state readout.

>b) we need to stop sending infoframes to DVI sinks

Sure, will work on this.

>c) we need to figure out how to disable the AVI infoframe
>   once enabled (if it doesn't get automagically disabled
>   when do a modeset), because otherwise when we switch
>   displays from HDMI to DVI we will still send the infoframe
>   to the DVI sink

Ok, will  work on to handle this.

>I think those should be fixed first before we add more infoframes to the mix.
>
>Also if we use the SDP stuff for the HDR infoframe we should just integrate it properly
>with the already existing DP HDR metadata stuff. And we need to add readout support
>for that.

Sure, will discuss with GG to get the state readout for DP SDP.

>--
>Ville Syrjälä
>Intel
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