[MODERATED] Re: [PATCH v5 08/11] TAAv5 8

[Pawan Gupta <pawan.kumar.gupta@linux.intel.com>]

On Fri, Oct 18, 2019 at 02:17:12AM +0100, speck for Ben Hutchings wrote:
> On Tue, 2019-10-15 at 18:12 -0500, speck for Josh Poimboeuf wrote:
> > On Tue, Oct 15, 2019 at 11:14:03PM +0200, speck for Jiri Kosina wrote:
> [...]
> > > OK, that piece of information finally made it to make sense again :)
> > > 
> > > So I believe distros still want the option (Michal's patch) to default to 
> > > 'auto', so that actual heavy users of TSX will get the right thing once 
> > > they update their CPUs to !TAA_BUG ones, but it's less urgent that I 
> > > originally thought.
> > 
> > So if I understand correctly, you're postulating that distros want:
> > 
> > a) TAA_BUG && MDS_NO=0 => TSX on
> > b) TAA_BUG && MDS_NO=1 => TSX off
> > c) !TAA_BUG            => TSX on
> [...]
> 
> I think this should be:
> 
> a) TAA_BUG && MD_CLEAR=1 => TSX on
> b) TAA_BUG && MD_CLEAR=0 => TSX off
> c) !TAA_BUG              => TSX on
> 
> As I understand it, with currently released microcode, no CPUs have
> both MDS_NO and MD_CLEAR set.  But with the pending microcode updates,
> CPUs with MDS_NO=1 will also get MD_CLEAR=1 and we can use VERW to
> mitigate against TAA.

Both with current and pending microcode update MDS_NO and MD_CLEAR could
be set at the same time. We should not rely on MD_CLEAR. There are other
means of finding out if VERW clears the CPU buffers, better described in
the matrix I shared in the other email.

In summary TSX_CTRL bit in ARCH_CAP_MSR is the true indicator if VERW
clears CPU buffers on MDS_NO=1 CPUs.

Thanks,
Pawan