[MODERATED] [PATCH v5 04/11] TAAv5 4

From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] [PATCH v5 04/11] TAAv5 4
Date: Fri, 4 Oct 2019 23:29:31 -0700	[thread overview]
Message-ID: <=?utf-8?q?=3Ce1936842f51256b93a57b52d53ec5d449775cc8a=2E157025?= =?utf-8?q?5065=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?=> (raw)
In-Reply-To: <cover.1570255065.git.pawan.kumar.gupta@linux.intel.com>

Add kernel cmdline parameter "tsx" to control the Transactional
Synchronization Extensions (TSX) feature.  On CPUs that support TSX
control, use "tsx=on|off" to enable or disable TSX.  Not specifying this
option is equivalent to "tsx=off".

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Reviewed-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
---
 .../admin-guide/kernel-parameters.txt         | 11 +++
 arch/x86/kernel/cpu/tsx.c                     | 97 ++++++++++++++++---
 2 files changed, 95 insertions(+), 13 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 4c1971960afa..832537d59562 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4813,6 +4813,17 @@
 			interruptions from clocksource watchdog are not
 			acceptable).
 
+	tsx=		[X86] Control Transactional Synchronization
+			Extensions (TSX) feature in Intel processors that
+			support TSX control.
+
+			This parameter controls the TSX feature. The options are:
+
+			on	- Enable TSX on the system.
+			off	- Disable TSX on the system.
+
+			Not specifying this option is equivalent to tsx=off.
+
 	turbografx.map[2|3]=	[HW,JOY]
 			TurboGraFX parallel port interface
 			Format:
diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
index c549750dd7c8..1c0cee7a7d46 100644
--- a/arch/x86/kernel/cpu/tsx.c
+++ b/arch/x86/kernel/cpu/tsx.c
@@ -19,6 +19,30 @@ static enum tsx_ctrl_states {
 	TSX_CTRL_NOT_SUPPORTED,
 } tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
 
+static enum tsx_user_cmds {
+	TSX_USER_CMD_NONE,
+	TSX_USER_CMD_ON,
+	TSX_USER_CMD_OFF,
+} tsx_user_cmd = TSX_USER_CMD_NONE;
+
+static int __init tsx_cmdline(char *str)
+{
+	if (!str)
+		return -EINVAL;
+
+	/*
+	 * tsx_en/disable() are only called when
+	 * X86_FEATURE_RTM and TSX_CTRL MSR are supported.
+	 */
+	if (!strcmp(str, "on"))
+		tsx_user_cmd = TSX_USER_CMD_ON;
+	else if (!strcmp(str, "off"))
+		tsx_user_cmd = TSX_USER_CMD_OFF;
+
+	return 0;
+}
+early_param("tsx", tsx_cmdline);
+
 static void tsx_disable(void)
 {
 	u64 tsx;
@@ -38,6 +62,24 @@ static void tsx_disable(void)
 	wrmsrl(MSR_IA32_TSX_CTRL, tsx);
 }
 
+static void tsx_enable(void)
+{
+	u64 tsx;
+
+	rdmsrl(MSR_IA32_TSX_CTRL, tsx);
+
+	/* Enable the RTM feature in the cpu */
+	tsx &= ~TSX_CTRL_RTM_DISABLE;
+	/*
+	 * Ensure TSX support is enumerated in CPUID.
+	 * This is visible to userspace and will ensure they
+	 * can enumerate and use the TSX feature.
+	 */
+	tsx &= ~TSX_CTRL_CPUID_CLEAR;
+
+	wrmsrl(MSR_IA32_TSX_CTRL, tsx);
+}
+
 static bool tsx_ctrl_is_supported(void)
 {
 	u64 ia32_cap = read_ia32_arch_cap();
@@ -55,18 +97,47 @@ void tsx_init(struct cpuinfo_x86 *c)
 	if (!tsx_ctrl_is_supported())
 		return;
 
-	/*
-	 * Default to TSX_CTRL_DISABLE. This is because on certain processors
-	 * TSX may be used as part of a speculative side channel attack.
-	 */
-	tsx_ctrl_state = TSX_CTRL_DISABLE;
+	switch (tsx_user_cmd) {
+	case TSX_USER_CMD_ON:
+		tsx_ctrl_state = TSX_CTRL_ENABLE;
+		break;
+	case TSX_USER_CMD_OFF:
+		tsx_ctrl_state = TSX_CTRL_DISABLE;
+		break;
+	case TSX_USER_CMD_NONE:
+	default:
+		/*
+		 * If user provided an invalid option or tsx= is not provided
+		 * on cmdline default to TSX_CTRL_DISABLE. This is because on
+		 * certain processors TSX may be used as part of a speculative
+		 * side channel attack.
+		 */
+		tsx_ctrl_state = TSX_CTRL_DISABLE;
+	}
 
-	tsx_disable();
-	/*
-	 * tsx_disable() will change the state of the
-	 * RTM CPUID bit.  Clear it here since it is now
-	 * expected to be not set.
-	 */
-	clear_cpu_cap(c, X86_FEATURE_RTM);
-	setup_clear_cpu_cap(X86_FEATURE_RTM);
+	if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
+		tsx_disable();
+		/*
+		 * tsx_disable() will change the state of the
+		 * RTM CPUID bit.  Clear it here since it is now
+		 * expected to be not set.
+		 */
+		clear_cpu_cap(c, X86_FEATURE_RTM);
+		setup_clear_cpu_cap(X86_FEATURE_RTM);
+	} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
+		/*
+		 * HW defaults TSX to be enabled at bootup.
+		 * We may still need the TSX enable support
+		 * during init for special cases like
+		 * kexec after TSX is disabled.
+		 */
+		tsx_enable();
+		/*
+		 * tsx_enable() will change the state of the
+		 * RTM CPUID bit.  Force it here since it is now
+		 * expected to be set.
+		 */
+		set_cpu_cap(c, X86_FEATURE_RTM);
+		setup_force_cpu_cap(X86_FEATURE_RTM);
+	}
 }
-- 
2.20.1
