* [PATCH] drm/i915/selftests: Add coverage of mocs registers
@ 2019-10-17 8:01 Chris Wilson
2019-10-17 8:34 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Chris Wilson @ 2019-10-17 8:01 UTC (permalink / raw)
To: intel-gfx
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 4 +
drivers/gpu/drm/i915/gt/selftest_mocs.c | 309 ++++++++++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 314 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 5bac3966906b..f5a239640553 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -490,3 +490,7 @@ void intel_mocs_init(struct intel_gt *gt)
if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
intel_mocs_init_global(gt);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..0aac3b1ab846
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,309 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+ struct drm_i915_mocs_table table;
+ struct i915_gem_context *ctx;
+ struct i915_vma *scratch;
+ void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+ int err = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (spin && !igt_wait_for_spinner(spin, rq))
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+ int err;
+
+ if (!get_mocs_settings(gt->i915, &arg->table))
+ return -EINVAL;
+
+ arg->ctx = kernel_context(gt->i915);
+ if (!arg->ctx)
+ return -ENOMEM;
+
+ arg->scratch = create_scratch(gt);
+ if (IS_ERR(arg->scratch)) {
+ err = PTR_ERR(arg->scratch);
+ goto err_ctx;
+ }
+
+ arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+ if (IS_ERR(arg->vaddr)) {
+ err = PTR_ERR(arg->vaddr);
+ goto err_scratch;
+ }
+
+ return 0;
+
+err_scratch:
+ i915_vma_put(arg->scratch);
+err_ctx:
+ kernel_context_close(arg->ctx);
+ return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+ i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+ kernel_context_close(arg->ctx);
+}
+
+static int read_mocs_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma)
+{
+ unsigned int i;
+ int err;
+ u32 *cs;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ return err;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ for (i = 0; i < table->n_entries; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ?
+ GEN12_GLOBAL_MOCS(i) :
+ mocs_register(rq->engine, i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32);
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr)
+{
+ unsigned int i;
+ u32 expect;
+
+ for (i = 0; i < table->size; i++) {
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[i].control_value;
+ else
+ expect = get_entry_control(table, i);
+
+ if (vaddr[i] != expect) {
+ pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[i], expect);
+ return -EINVAL;
+ }
+ }
+
+ /* All remaining entries are default */
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[0].control_value;
+ else
+ expect = table->table[I915_MOCS_PTE].control_value;
+ for (; i < table->n_entries; i++) {
+ if (vaddr[i] != expect) {
+ pr_err("%s: Invalid MOCS[%d*] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[i], expect);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+ struct intel_context *ce)
+{
+ struct i915_request *rq;
+ int err;
+
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE/sizeof(u32));
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ err = read_mocs_table(rq, &arg->table, arg->scratch);
+
+ err = request_add_sync(rq, err);
+ if(err)
+ return err;
+
+ return check_mocs_table(ce->engine, &arg->table, arg->vaddr);
+}
+
+static int live_mocs_clean(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ struct live_mocs mocs;
+ int err;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ /* XXX for_each_engine(gt) once we can create raw intel_context */
+ for_each_gem_engine(ce, i915_gem_context_engines(mocs.ctx), it) {
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+ }
+ i915_gem_context_unlock_engines(mocs.ctx);
+
+ live_mocs_fini(&mocs);
+
+ return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+ const char *reason)
+{
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err;
+
+ err = igt_spinner_init(&spin, ce->engine->gt);
+ if (err)
+ return err;
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ igt_spinner_fini(&spin);
+ return PTR_ERR(rq);
+ }
+
+ err = request_add_spin(rq, &spin);
+ if (err == 0)
+ err = intel_engine_reset(ce->engine, reason);
+
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+
+ return err;
+
+}
+static int live_mocs_reset(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ intel_wakeref_t wakeref;
+ struct live_mocs mocs;
+ int err = 0;
+
+ if (!intel_has_reset_engine(gt))
+ return 0;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ igt_global_reset_lock(gt);
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ for_each_gem_engine(ce, i915_gem_context_engines(mocs.ctx), it) {
+ err = intel_engine_reset(ce->engine, "mocs");
+ if (err)
+ break;
+
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+
+ err = active_engine_reset(ce, "mocs");
+ if (err)
+ break;
+
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+ }
+ i915_gem_context_unlock_engines(mocs.ctx);
+
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+ igt_global_reset_unlock(gt);
+
+ live_mocs_fini(&mocs);
+ return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_mocs_clean),
+ SUBTEST(live_mocs_reset),
+ };
+ struct drm_i915_mocs_table table;
+
+ if (!get_mocs_settings(i915, &table))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..1a6abcffce81 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
@ 2019-10-17 8:34 ` Patchwork
2019-10-17 9:06 ` ✗ Fi.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-17 8:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5fad9967a15 drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
-:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#33: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*
-:34: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#34: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT
-:217: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#217: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:185:
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE/sizeof(u32));
^
-:226: ERROR:SPACING: space required before the open parenthesis '('
#226: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:194:
+ if(err)
-:283: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#283: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:251:
+
+}
-:284: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#284: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:252:
+}
+static int live_mocs_reset(void *arg)
total: 1 errors, 3 warnings, 3 checks, 323 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/selftests: Add coverage of mocs registers
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-17 8:34 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-10-17 9:06 ` Patchwork
2019-10-17 9:27 ` [PATCH] " Chris Wilson
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-17 9:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14852
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14852 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14852, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14852:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u2/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-icl-u3: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@i915_selftest@live_execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u3/igt@i915_selftest@live_execlists.html
- fi-bxt-dsi: NOTRUN -> [DMESG-FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][6] -> [DMESG-FAIL][7] +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* {igt@i915_selftest@live_gt_mocs} (NEW):
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-8809g/igt@i915_selftest@live_gt_mocs.html
- fi-skl-guc: NOTRUN -> [DMESG-WARN][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-r: NOTRUN -> [DMESG-WARN][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-r/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-x1275: NOTRUN -> [DMESG-WARN][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-x1275/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-guc: NOTRUN -> [DMESG-WARN][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6260u: NOTRUN -> [DMESG-WARN][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-6260u/igt@i915_selftest@live_gt_mocs.html
- {fi-icl-u4}: NOTRUN -> [DMESG-WARN][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u4/igt@i915_selftest@live_gt_mocs.html
- fi-skl-lmem: NOTRUN -> [DMESG-WARN][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-lmem/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6770hq: NOTRUN -> [DMESG-WARN][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-6770hq/igt@i915_selftest@live_gt_mocs.html
- {fi-tgl-u2}: NOTRUN -> [DMESG-WARN][17]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-tgl-u2/igt@i915_selftest@live_gt_mocs.html
- fi-icl-u2: NOTRUN -> [DMESG-WARN][18]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u2/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][19]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cfl-8109u/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-7500u: NOTRUN -> [DMESG-WARN][20]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-7500u/igt@i915_selftest@live_gt_mocs.html
- fi-icl-u3: NOTRUN -> [DMESG-WARN][21]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u3/igt@i915_selftest@live_gt_mocs.html
- fi-cml-u: NOTRUN -> [DMESG-WARN][22]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cml-u/igt@i915_selftest@live_gt_mocs.html
- fi-glk-dsi: NOTRUN -> [DMESG-WARN][23]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-glk-dsi/igt@i915_selftest@live_gt_mocs.html
- {fi-cml-s}: NOTRUN -> [DMESG-WARN][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cml-s/igt@i915_selftest@live_gt_mocs.html
- {fi-icl-guc}: NOTRUN -> [DMESG-WARN][25]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-guc/igt@i915_selftest@live_gt_mocs.html
- {fi-kbl-soraka}: NOTRUN -> [DMESG-WARN][26]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-soraka/igt@i915_selftest@live_gt_mocs.html
- fi-skl-iommu: NOTRUN -> [DMESG-WARN][27]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-iommu/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-guc: NOTRUN -> [DMESG-WARN][28]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cfl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-cml-u2: NOTRUN -> [DMESG-WARN][29]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cml-u2/igt@i915_selftest@live_gt_mocs.html
- {fi-icl-dsi}: NOTRUN -> [DMESG-WARN][30]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-dsi/igt@i915_selftest@live_gt_mocs.html
- fi-whl-u: NOTRUN -> [DMESG-WARN][31]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-whl-u/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-8700k: NOTRUN -> [DMESG-WARN][32]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cfl-8700k/igt@i915_selftest@live_gt_mocs.html
- fi-bxt-dsi: NOTRUN -> [DMESG-WARN][33]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-bxt-dsi/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6600u: NOTRUN -> [DMESG-WARN][34]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-skl-6600u/igt@i915_selftest@live_gt_mocs.html
New tests
---------
New tests have been introduced between CI_DRM_7114 and Patchwork_14852:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_mocs:
- Statuses : 27 dmesg-warn(s) 18 pass(s)
- Exec time: [0.38, 1.89] s
Known issues
------------
Here are the changes found in Patchwork_14852 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@bad-pitch-256:
- fi-icl-u3: [PASS][35] -> [DMESG-WARN][36] ([fdo#107724])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@kms_addfb_basic@bad-pitch-256.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u3/igt@kms_addfb_basic@bad-pitch-256.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-bdw-gvtdvm: [DMESG-WARN][37] -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-bdw-gvtdvm/igt@gem_ctx_create@basic-files.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-bdw-gvtdvm/igt@gem_ctx_create@basic-files.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][39] ([fdo#107724]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* igt@i915_selftest@live_execlists:
- fi-cfl-guc: [DMESG-FAIL][41] -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-guc/igt@i915_selftest@live_execlists.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cfl-guc/igt@i915_selftest@live_execlists.html
- fi-cml-u: [DMESG-FAIL][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cml-u/igt@i915_selftest@live_execlists.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-cml-u/igt@i915_selftest@live_execlists.html
- fi-whl-u: [INCOMPLETE][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-whl-u/igt@i915_selftest@live_execlists.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-whl-u/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [DMESG-FAIL][47] -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-apl-guc/igt@i915_selftest@live_execlists.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gtt:
- {fi-icl-guc}: [INCOMPLETE][49] ([fdo#107713]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-guc/igt@i915_selftest@live_gtt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-icl-guc/igt@i915_selftest@live_gtt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][51] ([fdo#111407]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7114 -> Patchwork_14852
CI-20190529: 20190529
CI_DRM_7114: d9e909272a022597067d3ac2dfcedacd63c61af9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14852: e5fad9967a1552c896c8648e728df57748c6ad83 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e5fad9967a15 drm/i915/selftests: Add coverage of mocs registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14852/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] drm/i915/selftests: Add coverage of mocs registers
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-17 8:34 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-10-17 9:06 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-10-17 9:27 ` Chris Wilson
2019-10-17 15:02 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev2) Patchwork
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2019-10-17 9:27 UTC (permalink / raw)
To: intel-gfx
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
Helps to lock the engines.
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 4 +
drivers/gpu/drm/i915/gt/selftest_mocs.c | 309 ++++++++++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 314 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 5bac3966906b..f5a239640553 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -490,3 +490,7 @@ void intel_mocs_init(struct intel_gt *gt)
if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
intel_mocs_init_global(gt);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..46ae9976570f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,309 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+ struct drm_i915_mocs_table table;
+ struct i915_gem_context *ctx;
+ struct i915_vma *scratch;
+ void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+ int err = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (spin && !igt_wait_for_spinner(spin, rq))
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+ int err;
+
+ if (!get_mocs_settings(gt->i915, &arg->table))
+ return -EINVAL;
+
+ arg->ctx = kernel_context(gt->i915);
+ if (!arg->ctx)
+ return -ENOMEM;
+
+ arg->scratch = create_scratch(gt);
+ if (IS_ERR(arg->scratch)) {
+ err = PTR_ERR(arg->scratch);
+ goto err_ctx;
+ }
+
+ arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+ if (IS_ERR(arg->vaddr)) {
+ err = PTR_ERR(arg->vaddr);
+ goto err_scratch;
+ }
+
+ return 0;
+
+err_scratch:
+ i915_vma_unpin_and_release(&arg->scratch, 0);
+err_ctx:
+ kernel_context_close(arg->ctx);
+ return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+ i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+ kernel_context_close(arg->ctx);
+}
+
+static int read_mocs_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma)
+{
+ unsigned int i;
+ int err;
+ u32 *cs;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ return err;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ for (i = 0; i < table->n_entries; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ?
+ GEN12_GLOBAL_MOCS(i) :
+ mocs_register(rq->engine, i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32);
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr)
+{
+ unsigned int i;
+ u32 expect;
+
+ for (i = 0; i < table->size; i++) {
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[i].control_value;
+ else
+ expect = get_entry_control(table, i);
+
+ if (vaddr[i] != expect) {
+ pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[i], expect);
+ return -EINVAL;
+ }
+ }
+
+ /* All remaining entries are default */
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[0].control_value;
+ else
+ expect = table->table[I915_MOCS_PTE].control_value;
+ for (; i < table->n_entries; i++) {
+ if (vaddr[i] != expect) {
+ pr_err("%s: Invalid MOCS[%d*] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[i], expect);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+ struct intel_context *ce)
+{
+ struct i915_request *rq;
+ int err;
+
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE/sizeof(u32));
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ err = read_mocs_table(rq, &arg->table, arg->scratch);
+
+ err = request_add_sync(rq, err);
+ if(err)
+ return err;
+
+ return check_mocs_table(ce->engine, &arg->table, arg->vaddr);
+}
+
+static int live_mocs_clean(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ struct live_mocs mocs;
+ int err;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ /* XXX for_each_engine(gt) once we can create raw intel_context */
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(mocs.ctx), it) {
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+ }
+ i915_gem_context_unlock_engines(mocs.ctx);
+
+ live_mocs_fini(&mocs);
+
+ return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+ const char *reason)
+{
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err;
+
+ err = igt_spinner_init(&spin, ce->engine->gt);
+ if (err)
+ return err;
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ igt_spinner_fini(&spin);
+ return PTR_ERR(rq);
+ }
+
+ err = request_add_spin(rq, &spin);
+ if (err == 0)
+ err = intel_engine_reset(ce->engine, reason);
+
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+
+ return err;
+
+}
+static int live_mocs_reset(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ intel_wakeref_t wakeref;
+ struct live_mocs mocs;
+ int err = 0;
+
+ if (!intel_has_reset_engine(gt))
+ return 0;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ igt_global_reset_lock(gt);
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(mocs.ctx), it) {
+ err = intel_engine_reset(ce->engine, "mocs");
+ if (err)
+ break;
+
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+
+ err = active_engine_reset(ce, "mocs");
+ if (err)
+ break;
+
+ err = check_mocs_engine(&mocs, ce);
+ if (err)
+ break;
+ }
+ i915_gem_context_unlock_engines(mocs.ctx);
+
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+ igt_global_reset_unlock(gt);
+
+ live_mocs_fini(&mocs);
+ return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_mocs_clean),
+ SUBTEST(live_mocs_reset),
+ };
+ struct drm_i915_mocs_table table;
+
+ if (!get_mocs_settings(i915, &table))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..1a6abcffce81 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev2)
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (2 preceding siblings ...)
2019-10-17 9:27 ` [PATCH] " Chris Wilson
@ 2019-10-17 15:02 ` Patchwork
2019-10-17 15:36 ` ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-17 15:02 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
716eba73b16f drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
-:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#33: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*
-:34: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#34: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT
-:217: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#217: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:185:
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE/sizeof(u32));
^
-:226: ERROR:SPACING: space required before the open parenthesis '('
#226: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:194:
+ if(err)
-:283: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#283: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:251:
+
+}
-:284: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#284: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:252:
+}
+static int live_mocs_reset(void *arg)
total: 1 errors, 3 warnings, 3 checks, 323 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/selftests: Add coverage of mocs registers (rev2)
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (3 preceding siblings ...)
2019-10-17 15:02 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev2) Patchwork
@ 2019-10-17 15:36 ` Patchwork
2019-10-18 8:46 ` [PATCH v2] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-17 15:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7120 -> Patchwork_14855
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14855 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14855, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14855:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-icl-u2/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-apl-guc/igt@i915_selftest@live_execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-apl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-skl-6260u/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
New tests
---------
New tests have been introduced between CI_DRM_7120 and Patchwork_14855:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_mocs:
- Statuses : 44 pass(s)
- Exec time: [0.39, 2.47] s
Known issues
------------
Here are the changes found in Patchwork_14855 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-r: [PASS][9] -> [INCOMPLETE][10] ([fdo#112002])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-kbl-r/igt@gem_exec_suspend@basic-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-kbl-r/igt@gem_exec_suspend@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111045] / [fdo#111096])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][13] -> [DMESG-WARN][14] ([fdo#102614])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_sync@basic-many-each:
- {fi-tgl-u2}: [INCOMPLETE][15] ([fdo#111647]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u2/igt@gem_sync@basic-many-each.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-tgl-u2/igt@gem_sync@basic-many-each.html
- {fi-tgl-u}: [INCOMPLETE][17] ([fdo#111880]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u/igt@gem_sync@basic-many-each.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-tgl-u/igt@gem_sync@basic-many-each.html
* igt@i915_selftest@live_execlists:
- fi-whl-u: [DMESG-FAIL][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-whl-u/igt@i915_selftest@live_execlists.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-whl-u/igt@i915_selftest@live_execlists.html
- fi-skl-6600u: [DMESG-FAIL][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6600u/igt@i915_selftest@live_execlists.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-skl-6600u/igt@i915_selftest@live_execlists.html
- fi-bxt-dsi: [DMESG-FAIL][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_requests:
- {fi-icl-guc}: [INCOMPLETE][25] ([fdo#107713] / [fdo#109644] / [fdo#110464]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-icl-guc/igt@i915_selftest@live_requests.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-icl-guc/igt@i915_selftest@live_requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112002]: https://bugs.freedesktop.org/show_bug.cgi?id=112002
Participating hosts (53 -> 45)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7120 -> Patchwork_14855
CI-20190529: 20190529
CI_DRM_7120: 94ed5de2139e0636fa96adbdbb6ff6048619e343 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5231: e293051f8f99c72cb01d21e4b73a5928ea351eb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14855: 716eba73b16f8f319eeb87afc0b67a7025cfb490 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
716eba73b16f drm/i915/selftests: Add coverage of mocs registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2] drm/i915/selftests: Add coverage of mocs registers
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (4 preceding siblings ...)
2019-10-17 15:36 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-10-18 8:46 ` Chris Wilson
2019-10-18 8:57 ` Chris Wilson
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2019-10-18 8:46 UTC (permalink / raw)
To: intel-gfx
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 4 +
drivers/gpu/drm/i915/gt/selftest_mocs.c | 431 ++++++++++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 436 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 5bac3966906b..f5a239640553 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -490,3 +490,7 @@ void intel_mocs_init(struct intel_gt *gt)
if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
intel_mocs_init_global(gt);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..b3a211d162b5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,431 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+ struct drm_i915_mocs_table table;
+ struct i915_gem_context *ctx;
+ struct i915_vma *scratch;
+ void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+ int err = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (spin && !igt_wait_for_spinner(spin, rq))
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+ int err;
+
+ if (!get_mocs_settings(gt->i915, &arg->table))
+ return -EINVAL;
+
+ arg->ctx = kernel_context(gt->i915);
+ if (!arg->ctx)
+ return -ENOMEM;
+
+ arg->scratch = create_scratch(gt);
+ if (IS_ERR(arg->scratch)) {
+ err = PTR_ERR(arg->scratch);
+ goto err_ctx;
+ }
+
+ arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+ if (IS_ERR(arg->vaddr)) {
+ err = PTR_ERR(arg->vaddr);
+ goto err_scratch;
+ }
+
+ return 0;
+
+err_scratch:
+ i915_vma_unpin_and_release(&arg->scratch, 0);
+err_ctx:
+ kernel_context_close(arg->ctx);
+ return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+ i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+ kernel_context_close(arg->ctx);
+}
+
+static int read_mocs_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma, int *offset)
+{
+ unsigned int i;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ for (i = 0; i < table->n_entries; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ?
+ GEN12_GLOBAL_MOCS(i) :
+ mocs_register(rq->engine, i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32) + *offset;
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+ *offset += i * sizeof(u32);
+
+ return 0;
+}
+
+static int read_l3cc_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma, int *offset)
+{
+ unsigned int i;
+ u32 *cs;
+
+ if (1 /* can't read the MCR range 0xb00 directly */)
+ return 0;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries / 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ for (i = 0; i < table->n_entries / 2; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32) + *offset;
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+ *offset += i * sizeof(u32);
+
+ return 0;
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr, int *offset)
+{
+ unsigned int i;
+ u32 expect;
+
+ for (i = 0; i < table->size; i++) {
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[i].control_value;
+ else
+ expect = get_entry_control(table, i);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ /* All remaining entries are default */
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[0].control_value;
+ else
+ expect = table->table[I915_MOCS_PTE].control_value;
+ for (; i < table->n_entries; i++) {
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid MOCS[%d*] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ return 0;
+}
+
+static int check_l3cc_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr, int *offset)
+{
+ u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
+ unsigned int i;
+ u32 expect;
+
+ if (1 /* can't read the MCR range 0xb00 directly */)
+ return 0;
+
+ for (i = 0; i < table->size / 2; i++) {
+ u16 low = get_entry_l3cc(table, 2 * i);
+ u16 high = get_entry_l3cc(table, 2 * i + 1);
+
+ expect = l3cc_combine(table, low, high);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ /* Odd table size - 1 left over */
+ if (table->size & 1) {
+ u16 low = get_entry_l3cc(table, 2 * i);
+
+ expect = l3cc_combine(table, low, unused_value);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ i++;
+ }
+
+ /* All remaining entries are also unused */
+ for (; i < table->n_entries / 2; i++) {
+ expect = l3cc_combine(table, unused_value, unused_value);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+ struct intel_context *ce)
+{
+ struct i915_vma *vma = arg->scratch;
+ struct i915_request *rq;
+ int offset;
+ int err;
+
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+
+ offset = 0;
+ if (!err)
+ err = read_mocs_table(rq, &arg->table, vma, &offset);
+ if (!err && ce->engine->class == RENDER_CLASS)
+ err = read_l3cc_table(rq, &arg->table, vma, &offset);
+
+ err = request_add_sync(rq, err);
+ if (err)
+ return err;
+
+ offset = 0;
+ if (!err)
+ err = check_mocs_table(ce->engine, &arg->table,
+ arg->vaddr, &offset);
+ if (!err && ce->engine->class == RENDER_CLASS)
+ err = check_l3cc_table(ce->engine, &arg->table,
+ arg->vaddr, &offset);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int live_mocs_clean(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct live_mocs mocs;
+ int err;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ ce = intel_context_create(engine->kernel_context->gem_context,
+ engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ break;
+ }
+
+ err = check_mocs_engine(&mocs, ce);
+ intel_context_put(ce);
+ if (err)
+ break;
+ }
+
+ live_mocs_fini(&mocs);
+
+ return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+ const char *reason)
+{
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err;
+
+ err = igt_spinner_init(&spin, ce->engine->gt);
+ if (err)
+ return err;
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ igt_spinner_fini(&spin);
+ return PTR_ERR(rq);
+ }
+
+ err = request_add_spin(rq, &spin);
+ if (err == 0)
+ err = intel_engine_reset(ce->engine, reason);
+
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+
+ return err;
+}
+
+static int __live_mocs_reset(struct live_mocs *mocs,
+ struct intel_context *ce)
+{
+ int err;
+
+ err = intel_engine_reset(ce->engine, "mocs");
+ if (err)
+ return err;
+
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+
+ err = active_engine_reset(ce, "mocs");
+ if (err)
+ return err;
+
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int live_mocs_reset(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct live_mocs mocs;
+ int err = 0;
+
+ if (!intel_has_reset_engine(gt))
+ return 0;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ igt_global_reset_lock(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ ce = intel_context_create(engine->kernel_context->gem_context,
+ engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ break;
+ }
+
+ intel_engine_pm_get(engine);
+ err = __live_mocs_reset(&mocs, ce);
+ intel_engine_pm_get(engine);
+
+ intel_context_put(ce);
+ if (err)
+ break;
+ }
+ igt_global_reset_unlock(gt);
+
+ live_mocs_fini(&mocs);
+ return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_mocs_clean),
+ SUBTEST(live_mocs_reset),
+ };
+ struct drm_i915_mocs_table table;
+
+ if (!get_mocs_settings(i915, &table))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..1a6abcffce81 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2] drm/i915/selftests: Add coverage of mocs registers
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (5 preceding siblings ...)
2019-10-18 8:46 ` [PATCH v2] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
@ 2019-10-18 8:57 ` Chris Wilson
2019-10-18 9:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev4) Patchwork
2019-10-18 9:43 ` ✗ Fi.CI.BAT: failure " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2019-10-18 8:57 UTC (permalink / raw)
To: intel-gfx
Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 4 +
drivers/gpu/drm/i915/gt/selftest_mocs.c | 431 ++++++++++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 436 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 5bac3966906b..f5a239640553 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -490,3 +490,7 @@ void intel_mocs_init(struct intel_gt *gt)
if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
intel_mocs_init_global(gt);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..ebb3b879e450
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,431 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+ struct drm_i915_mocs_table table;
+ struct i915_gem_context *ctx;
+ struct i915_vma *scratch;
+ void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+ int err = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (spin && !igt_wait_for_spinner(spin, rq))
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+ int err;
+
+ if (!get_mocs_settings(gt->i915, &arg->table))
+ return -EINVAL;
+
+ arg->ctx = kernel_context(gt->i915);
+ if (!arg->ctx)
+ return -ENOMEM;
+
+ arg->scratch = create_scratch(gt);
+ if (IS_ERR(arg->scratch)) {
+ err = PTR_ERR(arg->scratch);
+ goto err_ctx;
+ }
+
+ arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+ if (IS_ERR(arg->vaddr)) {
+ err = PTR_ERR(arg->vaddr);
+ goto err_scratch;
+ }
+
+ return 0;
+
+err_scratch:
+ i915_vma_unpin_and_release(&arg->scratch, 0);
+err_ctx:
+ kernel_context_close(arg->ctx);
+ return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+ i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+ kernel_context_close(arg->ctx);
+}
+
+static int read_mocs_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma, int *offset)
+{
+ unsigned int i;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ for (i = 0; i < table->n_entries; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ?
+ GEN12_GLOBAL_MOCS(i) :
+ mocs_register(rq->engine, i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32) + *offset;
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+ *offset += i * sizeof(u32);
+
+ return 0;
+}
+
+static int read_l3cc_table(struct i915_request *rq,
+ const struct drm_i915_mocs_table *table,
+ struct i915_vma *vma, int *offset)
+{
+ unsigned int i;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * table->n_entries / 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /* XXX can't read the MCR range 0xb00 directly */
+ for (i = 0; i < table->n_entries / 2; i++) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
+ *cs++ = i915_ggtt_offset(vma) + i * sizeof(u32) + *offset;
+ *cs++ = 0;
+ }
+
+ intel_ring_advance(rq, cs);
+ *offset += i * sizeof(u32);
+
+ return 0;
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr, int *offset)
+{
+ unsigned int i;
+ u32 expect;
+
+ for (i = 0; i < table->size; i++) {
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[i].control_value;
+ else
+ expect = get_entry_control(table, i);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ /* All remaining entries are default */
+ if (HAS_GLOBAL_MOCS_REGISTERS(engine->i915))
+ expect = table->table[0].control_value;
+ else
+ expect = table->table[I915_MOCS_PTE].control_value;
+ for (; i < table->n_entries; i++) {
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid MOCS[%d*] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ return 0;
+}
+
+static int check_l3cc_table(struct intel_engine_cs *engine,
+ const struct drm_i915_mocs_table *table,
+ const u32 *vaddr, int *offset)
+{
+ u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
+ unsigned int i;
+ u32 expect;
+
+ if (1) { /* XXX skip MCR read back */
+ *offset += table->n_entries / 2;
+ return 0;
+ }
+
+ for (i = 0; i < table->size / 2; i++) {
+ u16 low = get_entry_l3cc(table, 2 * i);
+ u16 high = get_entry_l3cc(table, 2 * i + 1);
+
+ expect = l3cc_combine(table, low, high);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ /* Odd table size - 1 left over */
+ if (table->size & 1) {
+ u16 low = get_entry_l3cc(table, 2 * i);
+
+ expect = l3cc_combine(table, low, unused_value);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ i++;
+ }
+
+ /* All remaining entries are also unused */
+ for (; i < table->n_entries / 2; i++) {
+ expect = l3cc_combine(table, unused_value, unused_value);
+ if (vaddr[*offset] != expect) {
+ pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+ engine->name, i, vaddr[*offset], expect);
+ return -EINVAL;
+ }
+ ++*offset;
+ }
+
+ return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+ struct intel_context *ce)
+{
+ struct i915_vma *vma = arg->scratch;
+ struct i915_request *rq;
+ int offset;
+ int err;
+
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+
+ offset = 0;
+ if (!err)
+ err = read_mocs_table(rq, &arg->table, vma, &offset);
+ if (!err && ce->engine->class == RENDER_CLASS)
+ err = read_l3cc_table(rq, &arg->table, vma, &offset);
+
+ err = request_add_sync(rq, err);
+ if (err)
+ return err;
+
+ offset = 0;
+ if (!err)
+ err = check_mocs_table(ce->engine, &arg->table,
+ arg->vaddr, &offset);
+ if (!err && ce->engine->class == RENDER_CLASS)
+ err = check_l3cc_table(ce->engine, &arg->table,
+ arg->vaddr, &offset);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int live_mocs_clean(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct live_mocs mocs;
+ int err;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ ce = intel_context_create(engine->kernel_context->gem_context,
+ engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ break;
+ }
+
+ err = check_mocs_engine(&mocs, ce);
+ intel_context_put(ce);
+ if (err)
+ break;
+ }
+
+ live_mocs_fini(&mocs);
+
+ return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+ const char *reason)
+{
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err;
+
+ err = igt_spinner_init(&spin, ce->engine->gt);
+ if (err)
+ return err;
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ igt_spinner_fini(&spin);
+ return PTR_ERR(rq);
+ }
+
+ err = request_add_spin(rq, &spin);
+ if (err == 0)
+ err = intel_engine_reset(ce->engine, reason);
+
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+
+ return err;
+}
+
+static int __live_mocs_reset(struct live_mocs *mocs,
+ struct intel_context *ce)
+{
+ int err;
+
+ err = intel_engine_reset(ce->engine, "mocs");
+ if (err)
+ return err;
+
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+
+ err = active_engine_reset(ce, "mocs");
+ if (err)
+ return err;
+
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int live_mocs_reset(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct live_mocs mocs;
+ int err = 0;
+
+ if (!intel_has_reset_engine(gt))
+ return 0;
+
+ err = live_mocs_init(&mocs, gt);
+ if (err)
+ return err;
+
+ igt_global_reset_lock(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ ce = intel_context_create(engine->kernel_context->gem_context,
+ engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ break;
+ }
+
+ intel_engine_pm_get(engine);
+ err = __live_mocs_reset(&mocs, ce);
+ intel_engine_pm_get(engine);
+
+ intel_context_put(ce);
+ if (err)
+ break;
+ }
+ igt_global_reset_unlock(gt);
+
+ live_mocs_fini(&mocs);
+ return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_mocs_clean),
+ SUBTEST(live_mocs_reset),
+ };
+ struct drm_i915_mocs_table table;
+
+ if (!get_mocs_settings(i915, &table))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..1a6abcffce81 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev4)
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (6 preceding siblings ...)
2019-10-18 8:57 ` Chris Wilson
@ 2019-10-18 9:15 ` Patchwork
2019-10-18 9:43 ` ✗ Fi.CI.BAT: failure " Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-18 9:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev4)
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f7857122b69e drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
-:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#33: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*
-:34: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#34: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 3 warnings, 0 checks, 445 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/selftests: Add coverage of mocs registers (rev4)
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
` (7 preceding siblings ...)
2019-10-18 9:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev4) Patchwork
@ 2019-10-18 9:43 ` Patchwork
8 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-10-18 9:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev4)
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14875
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14875 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14875, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14875:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_selftest@live_gt_mocs} (NEW):
- fi-kbl-8809g: NOTRUN -> [TIMEOUT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-8809g/igt@i915_selftest@live_gt_mocs.html
- fi-skl-guc: NOTRUN -> [TIMEOUT][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-r: NOTRUN -> [TIMEOUT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-r/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-x1275: NOTRUN -> [TIMEOUT][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-x1275/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-guc: NOTRUN -> [TIMEOUT][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6260u: NOTRUN -> [TIMEOUT][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-6260u/igt@i915_selftest@live_gt_mocs.html
- fi-skl-lmem: NOTRUN -> [TIMEOUT][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-lmem/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6770hq: NOTRUN -> [TIMEOUT][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-6770hq/igt@i915_selftest@live_gt_mocs.html
- {fi-tgl-u}: NOTRUN -> [TIMEOUT][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-tgl-u/igt@i915_selftest@live_gt_mocs.html
- fi-icl-u2: NOTRUN -> [TIMEOUT][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-icl-u2/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-8109u: NOTRUN -> [TIMEOUT][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cfl-8109u/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-7500u: NOTRUN -> [TIMEOUT][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-7500u/igt@i915_selftest@live_gt_mocs.html
- fi-icl-u3: NOTRUN -> [TIMEOUT][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-icl-u3/igt@i915_selftest@live_gt_mocs.html
- fi-cml-u: NOTRUN -> [TIMEOUT][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cml-u/igt@i915_selftest@live_gt_mocs.html
- fi-glk-dsi: NOTRUN -> [TIMEOUT][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-glk-dsi/igt@i915_selftest@live_gt_mocs.html
- {fi-cml-s}: NOTRUN -> [TIMEOUT][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cml-s/igt@i915_selftest@live_gt_mocs.html
- {fi-icl-guc}: NOTRUN -> [TIMEOUT][17]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-icl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][18]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-soraka/igt@i915_selftest@live_gt_mocs.html
- fi-skl-iommu: NOTRUN -> [TIMEOUT][19]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-iommu/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-guc: NOTRUN -> [TIMEOUT][20]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cfl-guc/igt@i915_selftest@live_gt_mocs.html
- fi-cml-u2: NOTRUN -> [TIMEOUT][21]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cml-u2/igt@i915_selftest@live_gt_mocs.html
- fi-whl-u: NOTRUN -> [TIMEOUT][22]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-whl-u/igt@i915_selftest@live_gt_mocs.html
- fi-cfl-8700k: NOTRUN -> [TIMEOUT][23]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cfl-8700k/igt@i915_selftest@live_gt_mocs.html
- fi-bxt-dsi: NOTRUN -> [TIMEOUT][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-bxt-dsi/igt@i915_selftest@live_gt_mocs.html
- fi-skl-6600u: NOTRUN -> [TIMEOUT][25]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-skl-6600u/igt@i915_selftest@live_gt_mocs.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][26]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cfl-8109u/igt@runner@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][27]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-7500u/igt@runner@aborted.html
- fi-whl-u: NOTRUN -> [FAIL][28]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-whl-u/igt@runner@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][29]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-bxt-dsi/igt@runner@aborted.html
- fi-kbl-x1275: NOTRUN -> [FAIL][30]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-x1275/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][31]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-cfl-8700k/igt@runner@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][32]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-8809g/igt@runner@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][33]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-r/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-u}: NOTRUN -> [FAIL][34]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-tgl-u/igt@runner@aborted.html
New tests
---------
New tests have been introduced between CI_DRM_7125 and Patchwork_14875:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_mocs:
- Statuses : 1 incomplete(s) 17 pass(s) 24 timeout(s)
- Exec time: [0.0, 232.99] s
Known issues
------------
Here are the changes found in Patchwork_14875 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [PASS][35] -> [DMESG-WARN][36] ([fdo#107724]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][37] ([fdo#107724]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][39] ([fdo#111407]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (53 -> 44)
------------------------------
Missing (9): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7125 -> Patchwork_14875
CI-20190529: 20190529
CI_DRM_7125: f1ac92f5feb18678a3191a45be0ee4a4d255fc61 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14875: f7857122b69e68264933b2dc1b3e8be795f726c9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f7857122b69e drm/i915/selftests: Add coverage of mocs registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14875/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-10-18 9:43 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-17 8:01 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-17 8:34 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-10-17 9:06 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-17 9:27 ` [PATCH] " Chris Wilson
2019-10-17 15:02 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev2) Patchwork
2019-10-17 15:36 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-18 8:46 ` [PATCH v2] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-18 8:57 ` Chris Wilson
2019-10-18 9:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev4) Patchwork
2019-10-18 9:43 ` ✗ Fi.CI.BAT: failure " Patchwork
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