* [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2
@ 2019-10-21 2:47 Quan, Evan
[not found] ` <20191021024610.16569-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Quan, Evan @ 2019-10-21 2:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Grodzovsky, Andrey, Quan, Evan, Xu, Feifei
This is a quick and low risk fix. Those APIs which
are exposed to other IPs or to support sysfs/hwmon
interfaces or DAL will have lock protection. Meanwhile
no lock protection is enforced for swSMU internal used
APIs. Future optimization is needed.
V2: strip the lock protection for all swSMU internal APIs
Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 696 ++++++++++++++++--
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 -
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 163 ++--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 15 +-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 14 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 +-
12 files changed, 777 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 263265245e19..28d32725285b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
@@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 1c5c0fd76dbf..2cfb677272af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_get_current_power_state(adev) \
((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
-#define amdgpu_smu_get_current_power_state(adev) \
- ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
-
-#define amdgpu_smu_set_power_state(adev) \
- ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
-
#define amdgpu_dpm_get_pp_num_states(adev, data) \
((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c50d5f1e75e5..36f36b35000d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -211,7 +211,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
if (is_support_sw_smu(adev)) {
if (adev->smu.ppt_funcs->get_current_power_state)
- pm = amdgpu_smu_get_current_power_state(adev);
+ pm = smu_get_current_power_state(&adev->smu);
else
pm = adev->pm.dpm.user_state;
} else if (adev->powerplay.pp_funcs->get_current_power_state) {
@@ -957,7 +957,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -1004,7 +1004,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -1044,7 +1044,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
@@ -1084,7 +1084,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
@@ -1124,7 +1124,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
@@ -1164,7 +1164,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -1356,7 +1356,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
}
parameter[parameter_size] = profile_mode;
if (is_support_sw_smu(adev))
- ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
+ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
else if (adev->powerplay.pp_funcs->set_power_profile_mode)
ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
if (!ret)
@@ -2065,7 +2065,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, true);
+ smu_get_power_limit(&adev->smu, &limit, true, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
@@ -2083,7 +2083,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, false);
+ smu_get_power_limit(&adev->smu, &limit, false, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
@@ -3064,7 +3064,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
smu_handle_task(&adev->smu,
smu_dpm->dpm_level,
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ true);
} else {
if (adev->powerplay.pp_funcs->dispatch_tasks) {
if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 1352019648c0..ee9915d61cf1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -876,7 +876,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
if (!smu->funcs->get_max_sustainable_clocks_by_dc)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
+ if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
return PP_SMU_RESULT_OK;
return PP_SMU_RESULT_FAIL;
@@ -895,7 +895,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
if (!smu->ppt_funcs->get_uclk_dpm_states)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
+ if (!smu_get_uclk_dpm_states(smu,
clock_values_in_khz, num_states))
return PP_SMU_RESULT_OK;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 26cacc899dfe..0841d8c79e5b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
uint32_t sort_feature[SMU_FEATURE_COUNT];
uint64_t hw_feature_count = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
goto failed;
@@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
}
failed:
+ mutex_unlock(&smu->mutex);
+
return size;
}
@@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
uint64_t feature_2_disabled = 0;
uint64_t feature_enables = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
- return ret;
+ goto out;
feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
@@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
if (feature_2_enabled) {
ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
if (ret)
- return ret;
+ goto out;
}
if (feature_2_disabled) {
ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
if (ret)
- return ret;
+ goto out;
}
+out:
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
}
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max)
+ uint32_t *min, uint32_t *max, bool lock_needed)
{
uint32_t clock_limit;
int ret = 0;
@@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (!min && !max)
return -EINVAL;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
switch (clk_type) {
case SMU_MCLK:
@@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
*min = clock_limit / 100;
if (max)
*max = clock_limit / 100;
-
- return 0;
+ } else {
+ /*
+ * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
+ * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
+ */
+ ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
}
- /*
- * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
- * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
- */
- ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
{
int ret = 0;
+ mutex_lock(&smu->mutex);
+
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
ret = smu_dpm_set_uvd_enable(smu, gate);
@@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
break;
}
- return ret;
-}
+ mutex_unlock(&smu->mutex);
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
-{
- /* not support power state */
- return POWER_STATE_TYPE_DEFAULT;
+ return ret;
}
int smu_get_power_num_states(struct smu_context *smu,
@@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
int smu_sys_get_pp_table(struct smu_context *smu, void **table)
{
struct smu_table_context *smu_table = &smu->smu_table;
+ uint32_t powerplay_table_size;
if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
if (smu_table->hardcode_pptable)
*table = smu_table->hardcode_pptable;
else
*table = smu_table->power_play_table;
- return smu_table->power_play_table_size;
+ powerplay_table_size = smu_table->power_play_table_size;
+
+ mutex_unlock(&smu->mutex);
+
+ return powerplay_table_size;
}
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
@@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
memcpy(smu_table->hardcode_pptable, buf, size);
smu_table->power_play_table = smu_table->hardcode_pptable;
smu_table->power_play_table_size = size;
- mutex_unlock(&smu->mutex);
ret = smu_reset(smu);
if (ret)
pr_info("smu reset failed, ret = %d\n", ret);
- return ret;
-
failed:
mutex_unlock(&smu->mutex);
return ret;
@@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
if (!smu->pm_enabled)
return 0;
- mutex_lock(&smu->mutex);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
- AMD_PP_TASK_COMPLETE_INIT);
- mutex_unlock(&smu->mutex);
+ AMD_PP_TASK_COMPLETE_INIT,
+ false);
return 0;
}
@@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
if (ret)
return ret;
- ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
+ ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
if (ret)
return ret;
}
@@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct smu_context *smu)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->asic_type < CHIP_NAVI10) {
- ret = smu_load_microcode(smu);
- if (ret)
- return ret;
+ if (smu->funcs->load_microcode) {
+ ret = smu->funcs->load_microcode(smu);
+ if (ret)
+ return ret;
+ }
}
}
- ret = smu_check_fw_status(smu);
- if (ret)
- pr_err("SMC is not ready\n");
+ if (smu->funcs->check_fw_status) {
+ ret = smu->funcs->check_fw_status(smu);
+ if (ret)
+ pr_err("SMC is not ready\n");
+ }
return ret;
}
@@ -1334,8 +1354,6 @@ static int smu_resume(void *handle)
pr_info("SMU is resuming...\n");
- mutex_lock(&smu->mutex);
-
ret = smu_start_smc_engine(smu);
if (ret) {
pr_err("SMU is not ready yet!\n");
@@ -1350,13 +1368,11 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
- mutex_unlock(&smu->mutex);
-
pr_info("SMU is resumed successfully!\n");
return 0;
+
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1374,8 +1390,9 @@ int smu_display_configuration_change(struct smu_context *smu,
mutex_lock(&smu->mutex);
- smu_set_deep_sleep_dcefclk(smu,
- display_config->min_dcef_deep_sleep_set_clk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ smu->funcs->set_deep_sleep_dcefclk(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
for (index = 0; index < display_config->num_path_including_non_display; index++) {
if (display_config->displays[index].controller_id != 0)
@@ -1553,9 +1570,9 @@ static int smu_default_set_performance_level(struct smu_context *smu, enum amd_d
&soc_mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
+ smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
+ smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -1619,7 +1636,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
workload = smu->workload_setting[index];
if (smu->power_profile_mode != workload)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
}
return ret;
@@ -1627,18 +1644,22 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id)
+ enum amd_pp_task task_id,
+ bool lock_needed)
{
int ret = 0;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
ret = smu_pre_display_config_changed(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_set_cpu_power_state(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_adjust_power_state_dynamic(smu, level, false);
break;
case AMD_PP_TASK_COMPLETE_INIT:
@@ -1649,6 +1670,10 @@ int smu_handle_task(struct smu_context *smu,
break;
}
+out:
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1681,7 +1706,7 @@ int smu_switch_power_profile(struct smu_context *smu,
}
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
mutex_unlock(&smu->mutex);
@@ -1711,12 +1736,19 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
ret = smu_enable_umd_pstate(smu, &level);
- if (ret)
+ if (ret) {
+ mutex_unlock(&smu->mutex);
return ret;
+ }
ret = smu_handle_task(smu, level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
+
+ mutex_unlock(&smu->mutex);
return ret;
}
@@ -1734,7 +1766,8 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask)
+ uint32_t mask,
+ bool lock_needed)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -1744,9 +1777,15 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1764,6 +1803,8 @@ int smu_set_mp1_state(struct smu_context *smu,
if (!smu->pm_enabled)
return 0;
+ mutex_lock(&smu->mutex);
+
switch (mp1_state) {
case PP_MP1_STATE_SHUTDOWN:
msg = SMU_MSG_PrepareMp1ForShutdown;
@@ -1776,17 +1817,22 @@ int smu_set_mp1_state(struct smu_context *smu,
break;
case PP_MP1_STATE_NONE:
default:
+ mutex_unlock(&smu->mutex);
return 0;
}
/* some asics may not support those messages */
- if (smu_msg_get_index(smu, msg) < 0)
+ if (smu_msg_get_index(smu, msg) < 0) {
+ mutex_unlock(&smu->mutex);
return 0;
+ }
ret = smu_send_smc_msg(smu, msg);
if (ret)
pr_err("[PrepareMp1] Failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1806,10 +1852,14 @@ int smu_set_df_cstate(struct smu_context *smu,
if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
return 0;
+ mutex_lock(&smu->mutex);
+
ret = smu->ppt_funcs->set_df_cstate(smu, state);
if (ret)
pr_err("[SetDfCstate] failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1849,3 +1899,549 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
.rev = 0,
.funcs = &smu_ip_funcs,
};
+
+int smu_load_microcode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->load_microcode)
+ ret = smu->funcs->load_microcode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_check_fw_status(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->check_fw_status)
+ ret = smu->funcs->check_fw_status(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_gfx_cgpg)
+ ret = smu->funcs->set_gfx_cgpg(smu, enabled);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_rpm)
+ ret = smu->funcs->set_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_limit)
+ ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_power_limit)
+ ret = smu->funcs->set_power_limit(smu, limit);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->print_clk_levels)
+ ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_od_percentage)
+ ret = smu->ppt_funcs->get_od_percentage(smu, type);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_od_percentage)
+ ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->od_edit_dpm_table)
+ ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->read_sensor)
+ ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_profile_mode)
+ ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_power_profile_mode)
+ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_get_fan_control_mode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_fan_control_mode)
+ ret = smu->funcs->get_fan_control_mode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_control_mode(struct smu_context *smu, int value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_control_mode)
+ ret = smu->funcs->set_fan_control_mode(smu, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_percent)
+ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_percent)
+ ret = smu->funcs->set_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_rpm)
+ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_active_display_count)
+ ret = smu->funcs->set_active_display_count(smu, count);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_clock_by_type)
+ ret = smu->funcs->get_clock_by_type(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_high_clocks)
+ ret = smu->funcs->get_max_high_clocks(smu, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_latency)
+ ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_voltage)
+ ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
+{
+ int ret = -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->display_disable_memory_clock_switch)
+ ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_notify_smu_enable_pwe(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->notify_smu_enable_pwe)
+ ret = smu->funcs->notify_smu_enable_pwe(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_watermarks_for_clock_ranges)
+ ret = smu->funcs->set_watermarks_for_clock_ranges(smu, clock_ranges);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_xgmi_pstate)
+ ret = smu->funcs->set_xgmi_pstate(smu, pstate);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_azalia_d3_pme(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_azalia_d3_pme)
+ ret = smu->funcs->set_azalia_d3_pme(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+bool smu_baco_is_support(struct smu_context *smu)
+{
+ bool ret = false;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_is_support)
+ ret = smu->funcs->baco_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+{
+ if (smu->funcs->baco_get_state)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+ *state = smu->funcs->baco_get_state(smu);
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
+
+int smu_baco_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_reset)
+ ret = smu->funcs->baco_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_mode2_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->mode2_reset)
+ ret = smu->funcs->mode2_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_sustainable_clocks_by_dc)
+ ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_uclk_dpm_states)
+ ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+{
+ enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_current_power_state)
+ pm_state = smu->ppt_funcs->get_current_power_state(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return pm_state;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 6731fed5458e..141e48cd1c5d 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -772,8 +772,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -892,7 +890,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index cdb845f5f23e..3e3464fa2ff5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -565,18 +565,17 @@ struct smu_funcs
((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_fini_power(smu) \
((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
-#define smu_load_microcode(smu) \
- ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
-#define smu_check_fw_status(smu) \
- ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
+int smu_load_microcode(struct smu_context *smu);
+
+int smu_check_fw_status(struct smu_context *smu);
+
#define smu_setup_pptable(smu) \
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
#define smu_powergate_sdma(smu, gate) \
((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
-#define smu_set_gfx_cgpg(smu, enabled) \
- ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
@@ -610,8 +609,8 @@ struct smu_funcs
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
-#define smu_set_fan_speed_rpm(smu, speed) \
- ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
@@ -642,20 +641,22 @@ struct smu_funcs
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_set_default_od8_settings(smu) \
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
-#define smu_get_power_limit(smu, limit, def) \
- ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
-#define smu_set_power_limit(smu, limit) \
- ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed);
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
#define smu_get_current_clk_freq(smu, clk_id, value) \
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
-#define smu_print_clk_levels(smu, clk_type, buf) \
- ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
-#define smu_get_od_percentage(smu, type) \
- ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
-#define smu_set_od_percentage(smu, type, value) \
- ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
-#define smu_od_edit_dpm_table(smu, type, input, size) \
- ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
#define smu_tables_init(smu, tab) \
((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
#define smu_set_thermal_fan_table(smu) \
@@ -664,14 +665,18 @@ struct smu_funcs
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_stop_thermal_control(smu) \
((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
-#define smu_read_sensor(smu, sensor, data, size) \
- ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
#define smu_smc_read_sensor(smu, sensor, data, size) \
((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
-#define smu_get_power_profile_mode(smu, buf) \
- ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
-#define smu_set_power_profile_mode(smu, param, param_size) \
- ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed);
#define smu_pre_display_config_changed(smu) \
((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
#define smu_display_config_changed(smu) \
@@ -688,16 +693,11 @@ struct smu_funcs
((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
#define smu_set_cpu_power_state(smu) \
((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
-#define smu_get_fan_control_mode(smu) \
- ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
-#define smu_set_fan_control_mode(smu, value) \
- ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
-#define smu_get_fan_speed_percent(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
-#define smu_set_fan_speed_percent(smu, speed) \
- ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
-#define smu_get_fan_speed_rpm(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
+int smu_get_fan_control_mode(struct smu_context *smu);
+int smu_set_fan_control_mode(struct smu_context *smu, int value);
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
@@ -715,40 +715,46 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
-#define smu_set_deep_sleep_dcefclk(smu, clk) \
- ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
-#define smu_set_active_display_count(smu, count) \
- ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
-#define smu_get_clock_by_type(smu, type, clocks) \
- ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
-#define smu_get_max_high_clocks(smu, clocks) \
- ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
-#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
-#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
-#define smu_display_clock_voltage_request(smu, clock_req) \
- ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
-#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
- ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks);
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks);
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req);
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
-#define smu_notify_smu_enable_pwe(smu) \
- ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
- ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+int smu_notify_smu_enable_pwe(struct smu_context *smu);
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
#define smu_dpm_set_uvd_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
#define smu_dpm_set_vce_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
-#define smu_set_xgmi_pstate(smu, pstate) \
- ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate);
#define smu_set_watermarks_table(smu, tab, clock_ranges) \
((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -759,22 +765,18 @@ struct smu_funcs
((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
#define smu_register_irq_handler(smu) \
((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
-#define smu_set_azalia_d3_pme(smu) \
- ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+
+int smu_set_azalia_d3_pme(struct smu_context *smu);
#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
- ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
-#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
- ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
-#define smu_baco_is_support(smu) \
- ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
-#define smu_baco_get_state(smu, state) \
- ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
-#define smu_baco_reset(smu) \
- ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
-#define smu_mode2_reset(smu) \
- ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
+
+bool smu_baco_is_support(struct smu_context *smu);
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+
+int smu_baco_reset(struct smu_context *smu);
+
+int smu_mode2_reset(struct smu_context *smu);
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
#define smu_dump_pptable(smu) \
@@ -833,7 +835,8 @@ extern int smu_get_current_clocks(struct smu_context *smu,
extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id);
+ enum amd_pp_task task_id,
+ bool lock_needed);
int smu_switch_power_profile(struct smu_context *smu,
enum PP_SMC_POWER_PROFILE type,
bool en);
@@ -843,7 +846,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *value);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max);
+ uint32_t *min, uint32_t *max, bool lock_needed);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
@@ -858,10 +861,20 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask);
+ uint32_t mask,
+ bool lock_needed);
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
int smu_set_df_cstate(struct smu_context *smu,
enum pp_df_cstate state);
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks);
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states);
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b88aae9bb242..ead40b2840f9 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
int ret = 0;
uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
if (ret)
return ret;
smu->pstate_sclk = min_sclk_freq * 100;
- ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
if (ret)
return ret;
@@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
return ret;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
if (ret)
return ret;
ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
@@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
- if (!smu_display_clock_voltage_request(smu, &clock_req)) {
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
+ if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 6aedffd739db..6036f682e6f9 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
case SMU_SCLK:
/* retirve table returned paramters unit is MHz */
cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
if (!ret) {
/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
if (cur_value == max)
@@ -251,7 +251,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -269,7 +268,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
clk_type = clk_feature_map[i].clk_type;
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -435,7 +433,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
if (ret)
return ret;
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -511,7 +509,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
if (ret)
return ret;
@@ -519,7 +517,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
if (ret)
return ret;
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b68cb8badc75..caf8a3728541 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -809,8 +809,11 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
if (!table_context)
return -EINVAL;
- return smu_set_deep_sleep_dcefclk(smu,
- table_context->boot_values.dcefclk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ return smu->funcs->set_deep_sleep_dcefclk(smu,
+ table_context->boot_values.dcefclk / 100);
+
+ return 0;
}
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
@@ -1325,9 +1328,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
return 0;
- mutex_lock(&smu->mutex);
ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
- mutex_unlock(&smu->mutex);
if(clk_select == SMU_UCLK)
smu->hard_min_uclk_req_from_dal = clk_freq;
@@ -1370,12 +1371,10 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
case CHIP_NAVI12:
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
- mutex_lock(&smu->mutex);
if (enable)
ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
else
ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
- mutex_unlock(&smu->mutex);
break;
default:
break;
@@ -1491,10 +1490,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
if (!speed)
return -EINVAL;
- mutex_lock(&(smu->mutex));
ret = smu_v11_0_auto_fan_control(smu, 0);
if (ret)
- goto set_fan_speed_rpm_failed;
+ return ret;
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
@@ -1505,8 +1503,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
-set_fan_speed_rpm_failed:
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1517,11 +1513,9 @@ static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate)
{
int ret = 0;
- mutex_lock(&(smu->mutex));
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetXgmiMode,
pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1633,9 +1627,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
int ret = 0;
- mutex_lock(&smu->mutex);
ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1767,7 +1759,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0, clk_id = 0;
uint32_t param = 0;
- mutex_lock(&smu->mutex);
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) {
ret = -EINVAL;
@@ -1794,7 +1785,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index c9691d0fb523..6bf942d3ceca 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -325,8 +325,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0;
uint32_t mclk_mask, soc_mask;
- mutex_lock(&smu->mutex);
-
if (max) {
ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
NULL,
@@ -396,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index a76ffd58404e..c249df9256c7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -635,7 +635,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -653,7 +652,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level, hard_min_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1446,8 +1441,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
dpm_table = smu_dpm->dpm_context;
- mutex_lock(&smu->mutex);
-
switch (clk_type) {
case SMU_GFXCLK:
single_dpm_table = &(dpm_table->gfx_table);
@@ -1469,7 +1462,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
ret = -EINVAL;
}
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct smu_context *smu,
int feature_enabled;
PPCLK_e clk_id;
- mutex_lock(&(smu->mutex));
-
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
@@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct smu_context *smu,
}
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
set_od_failed:
- mutex_unlock(&(smu->mutex));
-
return ret;
}
@@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
}
if (type == PP_OD_COMMIT_DPM_TABLE) {
- mutex_lock(&(smu->mutex));
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
- mutex_unlock(&(smu->mutex));
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
}
return ret;
--
2.23.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/amd/powerplay: split out those internal used swSMU APIs V2
[not found] ` <20191021024610.16569-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-10-21 2:47 ` Quan, Evan
[not found] ` <20191021024610.16569-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-21 2:47 ` [PATCH 3/3] drm/amd/powerplay: clear the swSMU code layer Quan, Evan
2019-10-21 13:42 ` [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2 Deucher, Alexander
2 siblings, 1 reply; 7+ messages in thread
From: Quan, Evan @ 2019-10-21 2:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Grodzovsky, Andrey, Quan, Evan, Xu, Feifei
Those swSMU APIs used internally are moved to smu_internal.h while
others are kept in amdgpu_smu.h.
V2: give a better name smu_internal.h for the place to hold
those internal APIs
Change-Id: Ib726ef7f65dee46e47a07680b71e6e043e459f42
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 +
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 164 +-------------
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 +
drivers/gpu/drm/amd/powerplay/smu_internal.h | 206 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 1 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 +
9 files changed, 214 insertions(+), 163 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/smu_internal.h
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 0841d8c79e5b..1646581dcf66 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -25,6 +25,7 @@
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "soc15_common.h"
#include "smu_v11_0.h"
#include "smu_v12_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 141e48cd1c5d..a5e86375fa76 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -25,6 +25,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 3e3464fa2ff5..d01e40184fe0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -555,92 +555,13 @@ struct smu_funcs
int (*override_pcie_parameters)(struct smu_context *smu);
};
-#define smu_init_microcode(smu) \
- ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
-#define smu_init_smc_tables(smu) \
- ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
-#define smu_fini_smc_tables(smu) \
- ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
-#define smu_init_power(smu) \
- ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
-#define smu_fini_power(smu) \
- ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
int smu_load_microcode(struct smu_context *smu);
int smu_check_fw_status(struct smu_context *smu);
-#define smu_setup_pptable(smu) \
- ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
-#define smu_powergate_sdma(smu, gate) \
- ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
-#define smu_powergate_vcn(smu, gate) \
- ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
-#define smu_get_vbios_bootup_values(smu) \
- ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
-#define smu_get_clk_info_from_vbios(smu) \
- ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
-#define smu_check_pptable(smu) \
- ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
-#define smu_parse_pptable(smu) \
- ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
-#define smu_populate_smc_tables(smu) \
- ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
-#define smu_check_fw_version(smu) \
- ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
-#define smu_write_pptable(smu) \
- ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
-#define smu_set_min_dcef_deep_sleep(smu) \
- ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
-#define smu_set_tool_table_location(smu) \
- ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
-#define smu_notify_memory_pool_location(smu) \
- ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
-#define smu_gfx_off_control(smu, enable) \
- ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
-
-#define smu_write_watermarks_table(smu) \
- ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
-#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
- ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
-#define smu_system_features_control(smu, en) \
- ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
-#define smu_init_max_sustainable_clocks(smu) \
- ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
-#define smu_set_default_od_settings(smu, initialize) \
- ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
-int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
-#define smu_send_smc_msg(smu, msg) \
- ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
-#define smu_send_smc_msg_with_param(smu, msg, param) \
- ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
-#define smu_read_smc_arg(smu, arg) \
- ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
-#define smu_alloc_dpm_context(smu) \
- ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
-#define smu_init_display_count(smu, count) \
- ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
-#define smu_feature_set_allowed_mask(smu) \
- ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
-#define smu_feature_get_enabled_mask(smu, mask, num) \
- ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
-#define smu_is_dpm_running(smu) \
- ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_notify_display_change(smu) \
- ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
-#define smu_store_powerplay_table(smu) \
- ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
-#define smu_check_powerplay_table(smu) \
- ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
-#define smu_append_powerplay_table(smu) \
- ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
-#define smu_set_default_dpm_table(smu) \
- ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
-#define smu_populate_umd_state_clk(smu) \
- ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
-#define smu_set_default_od8_settings(smu) \
- ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
@@ -648,8 +569,6 @@ int smu_get_power_limit(struct smu_context *smu,
bool lock_needed);
int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
-#define smu_get_current_clk_freq(smu, clk_id, value) \
- ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
@@ -657,68 +576,24 @@ int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint3
int smu_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
-#define smu_tables_init(smu, tab) \
- ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
-#define smu_set_thermal_fan_table(smu) \
- ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
-#define smu_start_thermal_control(smu) \
- ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
-#define smu_stop_thermal_control(smu) \
- ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
int smu_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size);
-#define smu_smc_read_sensor(smu, sensor, data, size) \
- ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
int smu_set_power_profile_mode(struct smu_context *smu,
long *param,
uint32_t param_size,
bool lock_needed);
-#define smu_pre_display_config_changed(smu) \
- ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
-#define smu_display_config_changed(smu) \
- ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
-#define smu_apply_clocks_adjust_rules(smu) \
- ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
-#define smu_notify_smc_dispaly_config(smu) \
- ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
-#define smu_force_dpm_limit_value(smu, highest) \
- ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
-#define smu_unforce_dpm_levels(smu) \
- ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
-#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
- ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
-#define smu_set_cpu_power_state(smu) \
- ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
int smu_get_fan_control_mode(struct smu_context *smu);
int smu_set_fan_control_mode(struct smu_context *smu, int value);
int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
-#define smu_msg_get_index(smu, msg) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
-#define smu_clk_get_index(smu, msg) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
-#define smu_feature_get_index(smu, msg) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
-#define smu_table_get_index(smu, tab) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
-#define smu_power_get_index(smu, src) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
-#define smu_workload_get_type(smu, profile) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
-#define smu_run_btc(smu) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
-#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
-#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
- ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
int smu_get_clock_by_type(struct smu_context *smu,
enum amd_pp_clock_type type,
@@ -738,37 +613,15 @@ int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
int smu_display_clock_voltage_request(struct smu_context *smu,
struct pp_display_clock_request *clock_req);
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
-#define smu_get_dal_power_level(smu, clocks) \
- ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
-#define smu_get_perf_level(smu, designation, level) \
- ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
-#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
- ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
int smu_notify_smu_enable_pwe(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
-#define smu_dpm_set_uvd_enable(smu, enable) \
- ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
-#define smu_dpm_set_vce_enable(smu, enable) \
- ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
int smu_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
-#define smu_set_watermarks_table(smu, tab, clock_ranges) \
- ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
-#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
- ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
-#define smu_thermal_temperature_range_update(smu, range, rw) \
- ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
-#define smu_get_thermal_temperature_range(smu, range) \
- ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
-#define smu_register_irq_handler(smu) \
- ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
int smu_set_azalia_d3_pme(struct smu_context *smu);
-#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
- ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
bool smu_baco_is_support(struct smu_context *smu);
@@ -777,21 +630,6 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
int smu_baco_reset(struct smu_context *smu);
int smu_mode2_reset(struct smu_context *smu);
-#define smu_asic_set_performance_level(smu, level) \
- ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
-#define smu_dump_pptable(smu) \
- ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
-#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
- ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
-
-#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
- ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
-
-#define smu_override_pcie_parameters(smu) \
- ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
-
-#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
- ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index ead40b2840f9..54d5c91dda23 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -25,6 +25,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 6036f682e6f9..5e37a01df4a1 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -23,6 +23,7 @@
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "soc15_common.h"
#include "smu_v12_0_ppsmc.h"
#include "smu12_driver_if.h"
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
new file mode 100644
index 000000000000..0c1673a822c0
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __SMU_INTERNAL_H__
+#define __SMU_INTERNAL_H__
+
+#include "amdgpu_smu.h"
+
+#define smu_init_microcode(smu) \
+ ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+#define smu_init_smc_tables(smu) \
+ ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+#define smu_fini_smc_tables(smu) \
+ ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
+#define smu_init_power(smu) \
+ ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+#define smu_fini_power(smu) \
+ ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+
+#define smu_setup_pptable(smu) \
+ ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+#define smu_powergate_sdma(smu, gate) \
+ ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+#define smu_powergate_vcn(smu, gate) \
+ ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+
+#define smu_get_vbios_bootup_values(smu) \
+ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+#define smu_get_clk_info_from_vbios(smu) \
+ ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
+#define smu_check_pptable(smu) \
+ ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+#define smu_parse_pptable(smu) \
+ ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+#define smu_populate_smc_tables(smu) \
+ ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+#define smu_check_fw_version(smu) \
+ ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+#define smu_write_pptable(smu) \
+ ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+#define smu_set_min_dcef_deep_sleep(smu) \
+ ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+#define smu_set_tool_table_location(smu) \
+ ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+#define smu_notify_memory_pool_location(smu) \
+ ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+#define smu_gfx_off_control(smu, enable) \
+ ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+
+#define smu_write_watermarks_table(smu) \
+ ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
+#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+ ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+#define smu_system_features_control(smu, en) \
+ ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+#define smu_init_max_sustainable_clocks(smu) \
+ ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+#define smu_set_default_od_settings(smu, initialize) \
+ ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+
+#define smu_send_smc_msg(smu, msg) \
+ ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+#define smu_send_smc_msg_with_param(smu, msg, param) \
+ ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+#define smu_read_smc_arg(smu, arg) \
+ ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+#define smu_alloc_dpm_context(smu) \
+ ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+#define smu_init_display_count(smu, count) \
+ ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
+#define smu_feature_set_allowed_mask(smu) \
+ ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+#define smu_feature_get_enabled_mask(smu, mask, num) \
+ ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+#define smu_is_dpm_running(smu) \
+ ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+#define smu_notify_display_change(smu) \
+ ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+#define smu_store_powerplay_table(smu) \
+ ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+#define smu_check_powerplay_table(smu) \
+ ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
+#define smu_append_powerplay_table(smu) \
+ ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
+#define smu_set_default_dpm_table(smu) \
+ ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
+#define smu_populate_umd_state_clk(smu) \
+ ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+#define smu_set_default_od8_settings(smu) \
+ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+
+#define smu_get_current_clk_freq(smu, clk_id, value) \
+ ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+
+#define smu_tables_init(smu, tab) \
+ ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+#define smu_set_thermal_fan_table(smu) \
+ ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+#define smu_start_thermal_control(smu) \
+ ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+#define smu_stop_thermal_control(smu) \
+ ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+ ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+
+#define smu_pre_display_config_changed(smu) \
+ ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+#define smu_display_config_changed(smu) \
+ ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
+#define smu_apply_clocks_adjust_rules(smu) \
+ ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
+#define smu_notify_smc_dispaly_config(smu) \
+ ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
+#define smu_force_dpm_limit_value(smu, highest) \
+ ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
+#define smu_unforce_dpm_levels(smu) \
+ ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
+#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
+ ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+#define smu_set_cpu_power_state(smu) \
+ ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+
+#define smu_msg_get_index(smu, msg) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+#define smu_clk_get_index(smu, msg) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
+#define smu_feature_get_index(smu, msg) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
+#define smu_table_get_index(smu, tab) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
+#define smu_power_get_index(smu, src) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
+#define smu_workload_get_type(smu, profile) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
+#define smu_run_btc(smu) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+
+
+#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+ ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+
+#define smu_get_dal_power_level(smu, clocks) \
+ ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+#define smu_get_perf_level(smu, designation, level) \
+ ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+ ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+
+#define smu_dpm_set_uvd_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+#define smu_dpm_set_vce_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+
+#define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+ ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
+#define smu_thermal_temperature_range_update(smu, range, rw) \
+ ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
+#define smu_get_thermal_temperature_range(smu, range) \
+ ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+#define smu_register_irq_handler(smu) \
+ ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+
+#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+ ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+
+#define smu_asic_set_performance_level(smu, level) \
+ ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+#define smu_dump_pptable(smu) \
+ ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+ ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+
+#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+
+#define smu_override_pcie_parameters(smu) \
+ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+
+#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+ ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index caf8a3728541..9ab319912748 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -24,6 +24,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 6bf942d3ceca..ea67380cd9f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -24,6 +24,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v12_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c249df9256c7..4039efcdcb1f 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -25,6 +25,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
--
2.23.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/amd/powerplay: clear the swSMU code layer
[not found] ` <20191021024610.16569-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-21 2:47 ` [PATCH 2/3] drm/amd/powerplay: split out those internal used " Quan, Evan
@ 2019-10-21 2:47 ` Quan, Evan
2019-10-21 13:42 ` [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2 Deucher, Alexander
2 siblings, 0 replies; 7+ messages in thread
From: Quan, Evan @ 2019-10-21 2:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Grodzovsky, Andrey, Quan, Evan, Xu, Feifei
With this cleanup, the APIs from amdgpu_smu.c will map to
ASIC specific ones directly. Those can be shared around
all SMU V11/V12 ASICs will be put in smu_v11_0.c and
smu_v12_0.c respectively.
Change-Id: I9b98eb5ace5df19896de4b05c37255a38d1079ce
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 48 ++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 119 +++++------
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 53 ++++-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 127 +++++++++++-
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 41 +++-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 +++++-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 15 ++
drivers/gpu/drm/amd/powerplay/smu_internal.h | 84 ++++----
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 189 +++++-------------
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 70 ++-----
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 57 +++++-
13 files changed, 542 insertions(+), 330 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index fcae935bdc1b..a2c46e09e3e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -511,7 +511,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
return -EIO;
} else {
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return -ENOENT;
if (smu_baco_reset(smu))
@@ -568,7 +568,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
}
break;
case CHIP_ARCTURUS:
- if (smu->funcs && smu_baco_is_support(smu))
+ if (smu->ppt_funcs && smu_baco_is_support(smu))
baco_reset = true;
else
baco_reset = false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index ee9915d61cf1..5df9e6de7c75 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -346,7 +346,7 @@ bool dm_pp_get_clock_levels_by_type(
/* Error in pplib. Provide default values. */
return true;
}
- } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
+ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
if (smu_get_clock_by_type(&adev->smu,
dc_to_pp_clock_type(clk_type),
&pp_clks)) {
@@ -366,7 +366,7 @@ bool dm_pp_get_clock_levels_by_type(
validation_clks.memory_max_clock = 80000;
validation_clks.level = 0;
}
- } else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
+ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
validation_clks.engine_max_clock = 72000;
@@ -507,8 +507,8 @@ bool dm_pp_apply_clock_for_voltage_request(
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
adev->powerplay.pp_handle,
&pp_clock_request);
- else if (adev->smu.funcs &&
- adev->smu.funcs->display_clock_voltage_request)
+ else if (adev->smu.ppt_funcs &&
+ adev->smu.ppt_funcs->display_clock_voltage_request)
ret = smu_display_clock_voltage_request(&adev->smu,
&pp_clock_request);
if (ret)
@@ -528,7 +528,7 @@ bool dm_pp_get_static_clocks(
ret = adev->powerplay.pp_funcs->get_current_clocks(
adev->powerplay.pp_handle,
&pp_clk_info);
- else if (adev->smu.funcs)
+ else if (adev->smu.ppt_funcs)
ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
if (ret)
return false;
@@ -590,8 +590,8 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
&wm_with_clock_ranges);
- else if (adev->smu.funcs &&
- adev->smu.funcs->set_watermarks_for_clock_ranges)
+ else if (adev->smu.ppt_funcs &&
+ adev->smu.ppt_funcs->set_watermarks_for_clock_ranges)
smu_set_watermarks_for_clock_ranges(&adev->smu,
&wm_with_clock_ranges);
}
@@ -605,7 +605,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
pp_funcs->notify_smu_enable_pwe(pp_handle);
- else if (adev->smu.funcs)
+ else if (adev->smu.ppt_funcs)
smu_notify_smu_enable_pwe(&adev->smu);
}
@@ -709,10 +709,10 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
+ /* 0: successful or smu.ppt_funcs->set_watermarks_for_clock_ranges = NULL;
* 1: fail
*/
if (smu_set_watermarks_for_clock_ranges(&adev->smu,
@@ -728,10 +728,10 @@ enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
struct amdgpu_device *adev = ctx->driver_context;
struct smu_context *smu = &adev->smu;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
- /* 0: successful or smu.funcs->set_azalia_d3_pme = NULL; 1: fail */
+ /* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL; 1: fail */
if (smu_set_azalia_d3_pme(smu))
return PP_SMU_RESULT_FAIL;
@@ -744,10 +744,10 @@ enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
struct amdgpu_device *adev = ctx->driver_context;
struct smu_context *smu = &adev->smu;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
- /* 0: successful or smu.funcs->set_display_count = NULL; 1: fail */
+ /* 0: successful or smu.ppt_funcs->set_display_count = NULL; 1: fail */
if (smu_set_display_count(smu, count))
return PP_SMU_RESULT_FAIL;
@@ -760,10 +760,10 @@ enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
struct amdgpu_device *adev = ctx->driver_context;
struct smu_context *smu = &adev->smu;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
- /* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */
+ /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
if (smu_set_deep_sleep_dcefclk(smu, mhz))
return PP_SMU_RESULT_FAIL;
@@ -778,13 +778,13 @@ enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
struct smu_context *smu = &adev->smu;
struct pp_display_clock_request clock_req;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = mhz * 1000;
- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
* 1: fail
*/
if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -800,13 +800,13 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
struct smu_context *smu = &adev->smu;
struct pp_display_clock_request clock_req;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
clock_req.clock_type = amd_pp_mem_clock;
clock_req.clock_freq_in_khz = mhz * 1000;
- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
* 1: fail
*/
if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -836,7 +836,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
struct smu_context *smu = &adev->smu;
struct pp_display_clock_request clock_req;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
switch (clock_id) {
@@ -854,7 +854,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
}
clock_req.clock_freq_in_khz = mhz * 1000;
- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
+ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
* 1: fail
*/
if (smu_display_clock_voltage_request(smu, &clock_req))
@@ -870,10 +870,10 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
struct amdgpu_device *adev = ctx->driver_context;
struct smu_context *smu = &adev->smu;
- if (!smu->funcs)
+ if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->funcs->get_max_sustainable_clocks_by_dc)
+ if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
return PP_SMU_RESULT_UNSUPPORTED;
if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 1646581dcf66..ad30f17dae0d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -31,6 +31,10 @@
#include "smu_v12_0.h"
#include "atom.h"
#include "amd_pcie.h"
+#include "vega20_ppt.h"
+#include "arcturus_ppt.h"
+#include "navi10_ppt.h"
+#include "renoir_ppt.h"
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) #type
@@ -703,23 +707,26 @@ static int smu_set_funcs(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA20:
+ vega20_set_ppt_funcs(smu);
+ break;
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ navi10_set_ppt_funcs(smu);
+ break;
case CHIP_ARCTURUS:
- if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
- smu->od_enabled = true;
- smu_v11_0_set_smu_funcs(smu);
+ arcturus_set_ppt_funcs(smu);
break;
case CHIP_RENOIR:
- if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
- smu->od_enabled = true;
- smu_v12_0_set_smu_funcs(smu);
+ renoir_set_ppt_funcs(smu);
break;
default:
return -EINVAL;
}
+ if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+ smu->od_enabled = true;
+
return 0;
}
@@ -1177,16 +1184,16 @@ static int smu_start_smc_engine(struct smu_context *smu)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->asic_type < CHIP_NAVI10) {
- if (smu->funcs->load_microcode) {
- ret = smu->funcs->load_microcode(smu);
+ if (smu->ppt_funcs->load_microcode) {
+ ret = smu->ppt_funcs->load_microcode(smu);
if (ret)
return ret;
}
}
}
- if (smu->funcs->check_fw_status) {
- ret = smu->funcs->check_fw_status(smu);
+ if (smu->ppt_funcs->check_fw_status) {
+ ret = smu->ppt_funcs->check_fw_status(smu);
if (ret)
pr_err("SMC is not ready\n");
}
@@ -1391,8 +1398,8 @@ int smu_display_configuration_change(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->set_deep_sleep_dcefclk)
- smu->funcs->set_deep_sleep_dcefclk(smu,
+ if (smu->ppt_funcs->set_deep_sleep_dcefclk)
+ smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
display_config->min_dcef_deep_sleep_set_clk / 100);
for (index = 0; index < display_config->num_path_including_non_display; index++) {
@@ -1907,8 +1914,8 @@ int smu_load_microcode(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->load_microcode)
- ret = smu->funcs->load_microcode(smu);
+ if (smu->ppt_funcs->load_microcode)
+ ret = smu->ppt_funcs->load_microcode(smu);
mutex_unlock(&smu->mutex);
@@ -1921,8 +1928,8 @@ int smu_check_fw_status(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->check_fw_status)
- ret = smu->funcs->check_fw_status(smu);
+ if (smu->ppt_funcs->check_fw_status)
+ ret = smu->ppt_funcs->check_fw_status(smu);
mutex_unlock(&smu->mutex);
@@ -1935,8 +1942,8 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_gfx_cgpg)
- ret = smu->funcs->set_gfx_cgpg(smu, enabled);
+ if (smu->ppt_funcs->set_gfx_cgpg)
+ ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
mutex_unlock(&smu->mutex);
@@ -1949,8 +1956,8 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_fan_speed_rpm)
- ret = smu->funcs->set_fan_speed_rpm(smu, speed);
+ if (smu->ppt_funcs->set_fan_speed_rpm)
+ ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
mutex_unlock(&smu->mutex);
@@ -1982,8 +1989,8 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_power_limit)
- ret = smu->funcs->set_power_limit(smu, limit);
+ if (smu->ppt_funcs->set_power_limit)
+ ret = smu->ppt_funcs->set_power_limit(smu, limit);
mutex_unlock(&smu->mutex);
@@ -2104,8 +2111,8 @@ int smu_get_fan_control_mode(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->get_fan_control_mode)
- ret = smu->funcs->get_fan_control_mode(smu);
+ if (smu->ppt_funcs->get_fan_control_mode)
+ ret = smu->ppt_funcs->get_fan_control_mode(smu);
mutex_unlock(&smu->mutex);
@@ -2118,8 +2125,8 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_fan_control_mode)
- ret = smu->funcs->set_fan_control_mode(smu, value);
+ if (smu->ppt_funcs->set_fan_control_mode)
+ ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
mutex_unlock(&smu->mutex);
@@ -2146,8 +2153,8 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_fan_speed_percent)
- ret = smu->funcs->set_fan_speed_percent(smu, speed);
+ if (smu->ppt_funcs->set_fan_speed_percent)
+ ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
mutex_unlock(&smu->mutex);
@@ -2174,8 +2181,8 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_deep_sleep_dcefclk)
- ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
+ if (smu->ppt_funcs->set_deep_sleep_dcefclk)
+ ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
mutex_unlock(&smu->mutex);
@@ -2188,8 +2195,8 @@ int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_active_display_count)
- ret = smu->funcs->set_active_display_count(smu, count);
+ if (smu->ppt_funcs->set_active_display_count)
+ ret = smu->ppt_funcs->set_active_display_count(smu, count);
mutex_unlock(&smu->mutex);
@@ -2204,8 +2211,8 @@ int smu_get_clock_by_type(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->get_clock_by_type)
- ret = smu->funcs->get_clock_by_type(smu, type, clocks);
+ if (smu->ppt_funcs->get_clock_by_type)
+ ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
mutex_unlock(&smu->mutex);
@@ -2219,8 +2226,8 @@ int smu_get_max_high_clocks(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->get_max_high_clocks)
- ret = smu->funcs->get_max_high_clocks(smu, clocks);
+ if (smu->ppt_funcs->get_max_high_clocks)
+ ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
mutex_unlock(&smu->mutex);
@@ -2267,8 +2274,8 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->display_clock_voltage_request)
- ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
+ if (smu->ppt_funcs->display_clock_voltage_request)
+ ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
mutex_unlock(&smu->mutex);
@@ -2296,8 +2303,8 @@ int smu_notify_smu_enable_pwe(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->notify_smu_enable_pwe)
- ret = smu->funcs->notify_smu_enable_pwe(smu);
+ if (smu->ppt_funcs->notify_smu_enable_pwe)
+ ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
mutex_unlock(&smu->mutex);
@@ -2311,8 +2318,8 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->set_watermarks_for_clock_ranges)
- ret = smu->funcs->set_watermarks_for_clock_ranges(smu, clock_ranges);
+ if (smu->ppt_funcs->set_watermarks_for_clock_ranges)
+ ret = smu->ppt_funcs->set_watermarks_for_clock_ranges(smu, clock_ranges);
mutex_unlock(&smu->mutex);
@@ -2326,8 +2333,8 @@ int smu_set_xgmi_pstate(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->set_xgmi_pstate)
- ret = smu->funcs->set_xgmi_pstate(smu, pstate);
+ if (smu->ppt_funcs->set_xgmi_pstate)
+ ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
mutex_unlock(&smu->mutex);
@@ -2340,8 +2347,8 @@ int smu_set_azalia_d3_pme(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->set_azalia_d3_pme)
- ret = smu->funcs->set_azalia_d3_pme(smu);
+ if (smu->ppt_funcs->set_azalia_d3_pme)
+ ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
mutex_unlock(&smu->mutex);
@@ -2354,8 +2361,8 @@ bool smu_baco_is_support(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->baco_is_support)
- ret = smu->funcs->baco_is_support(smu);
+ if (smu->ppt_funcs->baco_is_support)
+ ret = smu->ppt_funcs->baco_is_support(smu);
mutex_unlock(&smu->mutex);
@@ -2364,11 +2371,11 @@ bool smu_baco_is_support(struct smu_context *smu)
int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
{
- if (smu->funcs->baco_get_state)
+ if (smu->ppt_funcs->baco_get_state)
return -EINVAL;
mutex_lock(&smu->mutex);
- *state = smu->funcs->baco_get_state(smu);
+ *state = smu->ppt_funcs->baco_get_state(smu);
mutex_unlock(&smu->mutex);
return 0;
@@ -2380,8 +2387,8 @@ int smu_baco_reset(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->baco_reset)
- ret = smu->funcs->baco_reset(smu);
+ if (smu->ppt_funcs->baco_reset)
+ ret = smu->ppt_funcs->baco_reset(smu);
mutex_unlock(&smu->mutex);
@@ -2394,8 +2401,8 @@ int smu_mode2_reset(struct smu_context *smu)
mutex_lock(&smu->mutex);
- if (smu->funcs->mode2_reset)
- ret = smu->funcs->mode2_reset(smu);
+ if (smu->ppt_funcs->mode2_reset)
+ ret = smu->ppt_funcs->mode2_reset(smu);
mutex_unlock(&smu->mutex);
@@ -2409,8 +2416,8 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
mutex_lock(&smu->mutex);
- if (smu->funcs->get_max_sustainable_clocks_by_dc)
- ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+ if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
+ ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
mutex_unlock(&smu->mutex);
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a5e86375fa76..ae1cdb454f8f 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1057,7 +1057,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
- ret = smu_smc_read_sensor(smu, sensor, data, size);
+ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
}
mutex_unlock(&smu->sensor_lock);
@@ -1973,6 +1973,57 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_power_limit = arcturus_get_power_limit,
.is_dpm_running = arcturus_is_dpm_running,
.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
+ .check_fw_status = smu_v11_0_check_fw_status,
+ .setup_pptable = smu_v11_0_setup_pptable,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+ .check_pptable = smu_v11_0_check_pptable,
+ .parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ .check_fw_version = smu_v11_0_check_fw_version,
+ .write_pptable = smu_v11_0_write_pptable,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .write_watermarks_table = smu_v11_0_write_watermarks_table,
+ .system_features_control = smu_v11_0_system_features_control,
+ .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+ .set_allowed_mask = smu_v11_0_set_allowed_mask,
+ .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .notify_display_change = smu_v11_0_notify_display_change,
+ .set_power_limit = smu_v11_0_set_power_limit,
+ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ .start_thermal_control = smu_v11_0_start_thermal_control,
+ .stop_thermal_control = smu_v11_0_stop_thermal_control,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+ .gfx_off_control = smu_v11_0_gfx_off_control,
+ .register_irq_handler = smu_v11_0_register_irq_handler,
+ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+ .baco_reset = smu_v11_0_baco_reset,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index d01e40184fe0..9c836e415986 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -347,7 +347,6 @@ struct smu_context
struct amdgpu_device *adev;
struct amdgpu_irq_src *irq_source;
- const struct smu_funcs *funcs;
const struct pptable_funcs *ppt_funcs;
struct mutex mutex;
struct mutex sensor_lock;
@@ -470,16 +469,12 @@ struct pptable_funcs {
uint32_t dpm_level, uint32_t *freq);
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
-};
-
-struct smu_funcs
-{
int (*init_microcode)(struct smu_context *smu);
+ int (*load_microcode)(struct smu_context *smu);
int (*init_smc_tables)(struct smu_context *smu);
int (*fini_smc_tables)(struct smu_context *smu);
int (*init_power)(struct smu_context *smu);
int (*fini_power)(struct smu_context *smu);
- int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
int (*setup_pptable)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
@@ -510,8 +505,6 @@ struct smu_funcs
int (*init_max_sustainable_clocks)(struct smu_context *smu);
int (*start_thermal_control)(struct smu_context *smu);
int (*stop_thermal_control)(struct smu_context *smu);
- int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
- void *data, uint32_t *size);
int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index e71f6fedf3c6..46214f53386d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -131,6 +131,131 @@ enum smu_v11_0_baco_seq {
BACO_SEQ_COUNT,
};
-void smu_v11_0_set_smu_funcs(struct smu_context *smu);
+int smu_v11_0_init_microcode(struct smu_context *smu);
+
+int smu_v11_0_load_microcode(struct smu_context *smu);
+
+int smu_v11_0_init_smc_tables(struct smu_context *smu);
+
+int smu_v11_0_fini_smc_tables(struct smu_context *smu);
+
+int smu_v11_0_init_power(struct smu_context *smu);
+
+int smu_v11_0_fini_power(struct smu_context *smu);
+
+int smu_v11_0_check_fw_status(struct smu_context *smu);
+
+int smu_v11_0_setup_pptable(struct smu_context *smu);
+
+int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
+
+int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
+
+int smu_v11_0_check_pptable(struct smu_context *smu);
+
+int smu_v11_0_parse_pptable(struct smu_context *smu);
+
+int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
+
+int smu_v11_0_check_fw_version(struct smu_context *smu);
+
+int smu_v11_0_write_pptable(struct smu_context *smu);
+
+int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
+
+int smu_v11_0_set_tool_table_location(struct smu_context *smu);
+
+int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
+
+int smu_v11_0_write_watermarks_table(struct smu_context *smu);
+
+int smu_v11_0_system_features_control(struct smu_context *smu,
+ bool en);
+
+int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
+
+int
+smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param);
+
+int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
+
+int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
+
+int smu_v11_0_set_allowed_mask(struct smu_context *smu);
+
+int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num);
+
+int smu_v11_0_notify_display_change(struct smu_context *smu);
+
+int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
+
+int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_id,
+ uint32_t *value);
+
+int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
+
+int smu_v11_0_start_thermal_control(struct smu_context *smu);
+
+int smu_v11_0_stop_thermal_control(struct smu_context *smu);
+
+int smu_v11_0_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
+
+int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
+
+int
+smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request
+ *clock_req);
+
+int
+smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
+ dm_pp_wm_sets_with_clock_ranges_soc15
+ *clock_ranges);
+
+uint32_t
+smu_v11_0_get_fan_control_mode(struct smu_context *smu);
+
+int
+smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ uint32_t mode);
+
+int
+smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ uint32_t speed);
+
+int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate);
+
+int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
+
+int smu_v11_0_register_irq_handler(struct smu_context *smu);
+
+int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
+
+int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks);
+
+bool smu_v11_0_baco_is_support(struct smu_context *smu);
+
+enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
+
+int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
+
+int smu_v11_0_baco_reset(struct smu_context *smu);
+
+int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max);
+
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t min, uint32_t max);
+
+int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index acf3db12f59f..9b9f5df0911c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -37,6 +37,45 @@ struct smu_12_0_cmn2aisc_mapping {
int map_to;
};
-void smu_v12_0_set_smu_funcs(struct smu_context *smu);
+int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ uint16_t msg);
+
+int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
+
+int smu_v12_0_wait_for_response(struct smu_context *smu);
+
+int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
+
+int
+smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param);
+
+int smu_v12_0_check_fw_status(struct smu_context *smu);
+
+int smu_v12_0_check_fw_version(struct smu_context *smu);
+
+int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
+
+int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
+
+int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
+uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+
+int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+
+int smu_v12_0_init_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+
+int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max);
+
+int smu_v12_0_mode2_reset(struct smu_context *smu);
+
+int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t min, uint32_t max);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 54d5c91dda23..9b8c20347183 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1268,8 +1268,7 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
- if (smu->funcs->display_clock_voltage_request)
- ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
+ ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
@@ -1424,7 +1423,7 @@ static int navi10_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
- ret = smu_smc_read_sensor(smu, sensor, data, size);
+ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
}
mutex_unlock(&smu->sensor_lock);
@@ -1693,6 +1692,57 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
.get_power_limit = navi10_get_power_limit,
.update_pcie_parameters = navi10_update_pcie_parameters,
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
+ .check_fw_status = smu_v11_0_check_fw_status,
+ .setup_pptable = smu_v11_0_setup_pptable,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+ .check_pptable = smu_v11_0_check_pptable,
+ .parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ .check_fw_version = smu_v11_0_check_fw_version,
+ .write_pptable = smu_v11_0_write_pptable,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .write_watermarks_table = smu_v11_0_write_watermarks_table,
+ .system_features_control = smu_v11_0_system_features_control,
+ .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+ .set_allowed_mask = smu_v11_0_set_allowed_mask,
+ .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .notify_display_change = smu_v11_0_notify_display_change,
+ .set_power_limit = smu_v11_0_set_power_limit,
+ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ .start_thermal_control = smu_v11_0_start_thermal_control,
+ .stop_thermal_control = smu_v11_0_stop_thermal_control,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+ .gfx_off_control = smu_v11_0_gfx_off_control,
+ .register_irq_handler = smu_v11_0_register_irq_handler,
+ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+ .baco_reset = smu_v11_0_baco_reset,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 5e37a01df4a1..06525d4ff08b 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -561,6 +561,21 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.force_clk_levels = renoir_force_clk_levels,
.set_power_profile_mode = renoir_set_power_profile_mode,
.set_performance_level = renoir_set_performance_level,
+ .check_fw_status = smu_v12_0_check_fw_status,
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+ .powergate_vcn = smu_v12_0_powergate_vcn,
+ .send_smc_msg = smu_v12_0_send_msg,
+ .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ .read_smc_arg = smu_v12_0_read_arg,
+ .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+ .gfx_off_control = smu_v12_0_gfx_off_control,
+ .init_smc_tables = smu_v12_0_init_smc_tables,
+ .fini_smc_tables = smu_v12_0_fini_smc_tables,
+ .populate_smc_tables = smu_v12_0_populate_smc_tables,
+ .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ .mode2_reset = smu_v12_0_mode2_reset,
+ .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
};
void renoir_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 0c1673a822c0..0a28417d1a2f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -26,75 +26,75 @@
#include "amdgpu_smu.h"
#define smu_init_microcode(smu) \
- ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+ ((smu)->ppt_funcs->init_microcode ? (smu)->ppt_funcs->init_microcode((smu)) : 0)
#define smu_init_smc_tables(smu) \
- ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+ ((smu)->ppt_funcs->init_smc_tables ? (smu)->ppt_funcs->init_smc_tables((smu)) : 0)
#define smu_fini_smc_tables(smu) \
- ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
+ ((smu)->ppt_funcs->fini_smc_tables ? (smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
#define smu_init_power(smu) \
- ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+ ((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
#define smu_fini_power(smu) \
- ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+ ((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
#define smu_setup_pptable(smu) \
- ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+ ((smu)->ppt_funcs->setup_pptable ? (smu)->ppt_funcs->setup_pptable((smu)) : 0)
#define smu_powergate_sdma(smu, gate) \
- ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+ ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
- ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+ ((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
#define smu_get_vbios_bootup_values(smu) \
- ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
- ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
+ ((smu)->ppt_funcs->get_clk_info_from_vbios ? (smu)->ppt_funcs->get_clk_info_from_vbios((smu)) : 0)
#define smu_check_pptable(smu) \
- ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+ ((smu)->ppt_funcs->check_pptable ? (smu)->ppt_funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
- ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+ ((smu)->ppt_funcs->parse_pptable ? (smu)->ppt_funcs->parse_pptable((smu)) : 0)
#define smu_populate_smc_tables(smu) \
- ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+ ((smu)->ppt_funcs->populate_smc_tables ? (smu)->ppt_funcs->populate_smc_tables((smu)) : 0)
#define smu_check_fw_version(smu) \
- ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+ ((smu)->ppt_funcs->check_fw_version ? (smu)->ppt_funcs->check_fw_version((smu)) : 0)
#define smu_write_pptable(smu) \
- ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+ ((smu)->ppt_funcs->write_pptable ? (smu)->ppt_funcs->write_pptable((smu)) : 0)
#define smu_set_min_dcef_deep_sleep(smu) \
- ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+ ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep((smu)) : 0)
#define smu_set_tool_table_location(smu) \
- ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+ ((smu)->ppt_funcs->set_tool_table_location ? (smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
#define smu_notify_memory_pool_location(smu) \
- ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+ ((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
#define smu_gfx_off_control(smu, enable) \
- ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+ ((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
#define smu_write_watermarks_table(smu) \
- ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
+ ((smu)->ppt_funcs->write_watermarks_table ? (smu)->ppt_funcs->write_watermarks_table((smu)) : 0)
#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
- ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+ ((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
#define smu_system_features_control(smu, en) \
- ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+ ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
#define smu_init_max_sustainable_clocks(smu) \
- ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+ ((smu)->ppt_funcs->init_max_sustainable_clocks ? (smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
#define smu_send_smc_msg(smu, msg) \
- ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+ ((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
- ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+ ((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
#define smu_read_smc_arg(smu, arg) \
- ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+ ((smu)->ppt_funcs->read_smc_arg? (smu)->ppt_funcs->read_smc_arg((smu), (arg)) : 0)
#define smu_alloc_dpm_context(smu) \
((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
#define smu_init_display_count(smu, count) \
- ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
+ ((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
#define smu_feature_set_allowed_mask(smu) \
- ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+ ((smu)->ppt_funcs->set_allowed_mask? (smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
#define smu_feature_get_enabled_mask(smu, mask, num) \
- ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+ ((smu)->ppt_funcs->get_enabled_mask? (smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
#define smu_is_dpm_running(smu) \
((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
#define smu_notify_display_change(smu) \
- ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+ ((smu)->ppt_funcs->notify_display_change? (smu)->ppt_funcs->notify_display_change((smu)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
@@ -109,19 +109,19 @@
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
- ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ ((smu)->ppt_funcs->get_current_clk_freq? (smu)->ppt_funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_tables_init(smu, tab) \
((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
#define smu_set_thermal_fan_table(smu) \
((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
#define smu_start_thermal_control(smu) \
- ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+ ((smu)->ppt_funcs->start_thermal_control? (smu)->ppt_funcs->start_thermal_control((smu)) : 0)
#define smu_stop_thermal_control(smu) \
- ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+ ((smu)->ppt_funcs->stop_thermal_control? (smu)->ppt_funcs->stop_thermal_control((smu)) : 0)
#define smu_smc_read_sensor(smu, sensor, data, size) \
- ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+ ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
#define smu_pre_display_config_changed(smu) \
((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
@@ -159,14 +159,14 @@
#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
- ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+ ((smu)->ppt_funcs->store_cc6_data ? (smu)->ppt_funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
#define smu_get_dal_power_level(smu, clocks) \
- ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+ ((smu)->ppt_funcs->get_dal_power_level ? (smu)->ppt_funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
- ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+ ((smu)->ppt_funcs->get_perf_level ? (smu)->ppt_funcs->get_perf_level((smu), (designation), (level)) : 0)
#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
- ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ ((smu)->ppt_funcs->get_current_shallow_sleep_clocks ? (smu)->ppt_funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
#define smu_dpm_set_uvd_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
@@ -182,10 +182,10 @@
#define smu_get_thermal_temperature_range(smu, range) \
((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
#define smu_register_irq_handler(smu) \
- ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+ ((smu)->ppt_funcs->register_irq_handler ? (smu)->ppt_funcs->register_irq_handler(smu) : 0)
#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
- ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+ ((smu)->ppt_funcs->get_dpm_ultimate_freq ? (smu)->ppt_funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
@@ -195,10 +195,10 @@
((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
- ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+ ((smu)->ppt_funcs->set_soft_freq_limited_range ? (smu)->ppt_funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
#define smu_override_pcie_parameters(smu) \
- ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+ ((smu)->ppt_funcs->override_pcie_parameters ? (smu)->ppt_funcs->override_pcie_parameters((smu)) : 0)
#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9ab319912748..1f9766c48674 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -30,9 +30,6 @@
#include "smu_v11_0.h"
#include "soc15_common.h"
#include "atom.h"
-#include "vega20_ppt.h"
-#include "arcturus_ppt.h"
-#include "navi10_ppt.h"
#include "amd_pcie.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
@@ -60,7 +57,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
return 0;
}
-static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
+int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
{
struct amdgpu_device *adev = smu->adev;
@@ -87,7 +84,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
}
-static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0, index = 0;
@@ -112,7 +109,7 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
}
-static int
+int
smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
uint32_t param)
{
@@ -143,7 +140,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
return ret;
}
-static int smu_v11_0_init_microcode(struct smu_context *smu)
+int smu_v11_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
const char *chip_name;
@@ -205,7 +202,7 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
return err;
}
-static int smu_v11_0_load_microcode(struct smu_context *smu)
+int smu_v11_0_load_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
const uint32_t *src;
@@ -243,7 +240,7 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_check_fw_status(struct smu_context *smu)
+int smu_v11_0_check_fw_status(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;
@@ -258,7 +255,7 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
return -EIO;
}
-static int smu_v11_0_check_fw_version(struct smu_context *smu)
+int smu_v11_0_check_fw_version(struct smu_context *smu)
{
uint32_t if_version = 0xff, smu_version = 0xff;
uint16_t smu_major;
@@ -356,7 +353,7 @@ static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
return 0;
}
-static int smu_v11_0_setup_pptable(struct smu_context *smu)
+int smu_v11_0_setup_pptable(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
const struct smc_firmware_header_v1_0 *hdr;
@@ -435,7 +432,7 @@ static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+int smu_v11_0_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = NULL;
@@ -462,7 +459,7 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+int smu_v11_0_fini_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
int ret = 0;
@@ -482,7 +479,7 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_init_power(struct smu_context *smu)
+int smu_v11_0_init_power(struct smu_context *smu)
{
struct smu_power_context *smu_power = &smu->smu_power;
@@ -500,7 +497,7 @@ static int smu_v11_0_init_power(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_fini_power(struct smu_context *smu)
+int smu_v11_0_fini_power(struct smu_context *smu)
{
struct smu_power_context *smu_power = &smu->smu_power;
@@ -577,7 +574,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
{
int ret, index;
struct amdgpu_device *adev = smu->adev;
@@ -674,7 +671,7 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *memory_pool = &smu_table->memory_pool;
@@ -720,7 +717,7 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_check_pptable(struct smu_context *smu)
+int smu_v11_0_check_pptable(struct smu_context *smu)
{
int ret;
@@ -728,7 +725,7 @@ static int smu_v11_0_check_pptable(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_parse_pptable(struct smu_context *smu)
+int smu_v11_0_parse_pptable(struct smu_context *smu)
{
int ret;
@@ -752,7 +749,7 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
{
int ret;
@@ -761,7 +758,7 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_write_pptable(struct smu_context *smu)
+int smu_v11_0_write_pptable(struct smu_context *smu)
{
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
@@ -772,7 +769,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+int smu_v11_0_write_watermarks_table(struct smu_context *smu)
{
int ret = 0;
struct smu_table_context *smu_table = &smu->smu_table;
@@ -789,7 +786,7 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
{
int ret;
@@ -801,7 +798,7 @@ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t cl
return ret;
}
-static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
{
struct smu_table_context *table_context = &smu->smu_table;
@@ -810,14 +807,10 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
if (!table_context)
return -EINVAL;
- if (smu->funcs->set_deep_sleep_dcefclk)
- return smu->funcs->set_deep_sleep_dcefclk(smu,
- table_context->boot_values.dcefclk / 100);
-
- return 0;
+ return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
}
-static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+int smu_v11_0_set_tool_table_location(struct smu_context *smu)
{
int ret = 0;
struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
@@ -835,7 +828,7 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
{
int ret = 0;
@@ -847,7 +840,7 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
}
-static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+int smu_v11_0_set_allowed_mask(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
int ret = 0;
@@ -874,7 +867,7 @@ static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+int smu_v11_0_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
{
uint32_t feature_mask_high = 0, feature_mask_low = 0;
@@ -903,7 +896,7 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
return ret;
}
-static int smu_v11_0_system_features_control(struct smu_context *smu,
+int smu_v11_0_system_features_control(struct smu_context *smu,
bool en)
{
struct smu_feature *feature = &smu->smu_feature;
@@ -929,7 +922,7 @@ static int smu_v11_0_system_features_control(struct smu_context *smu,
return ret;
}
-static int smu_v11_0_notify_display_change(struct smu_context *smu)
+int smu_v11_0_notify_display_change(struct smu_context *smu)
{
int ret = 0;
@@ -987,7 +980,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
return ret;
}
-static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
{
struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
int ret = 0;
@@ -1067,7 +1060,7 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
{
int ret = 0;
@@ -1095,7 +1088,7 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
return 0;
}
-static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
enum smu_clk_type clk_id,
uint32_t *value)
{
@@ -1174,7 +1167,7 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
return 0;
}
-static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+int smu_v11_0_start_thermal_control(struct smu_context *smu)
{
int ret = 0;
struct smu_temperature_range range;
@@ -1216,7 +1209,7 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
+int smu_v11_0_stop_thermal_control(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -1249,7 +1242,7 @@ static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
}
-static int smu_v11_0_read_sensor(struct smu_context *smu,
+int smu_v11_0_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
@@ -1286,7 +1279,7 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
return ret;
}
-static int
+int
smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
struct pp_display_clock_request
*clock_req)
@@ -1339,7 +1332,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
return ret;
}
-static int
+int
smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
dm_pp_wm_sets_with_clock_ranges_soc15
*clock_ranges)
@@ -1359,7 +1352,7 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
return ret;
}
-static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
{
int ret = 0;
struct amdgpu_device *adev = smu->adev;
@@ -1384,7 +1377,7 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
return ret;
}
-static uint32_t
+uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context *smu)
{
if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
@@ -1424,7 +1417,7 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
return 0;
}
-static int
+int
smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
{
struct amdgpu_device *adev = smu->adev;
@@ -1453,7 +1446,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
}
-static int
+int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
{
@@ -1481,7 +1474,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
return ret;
}
-static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
uint32_t speed)
{
struct amdgpu_device *adev = smu->adev;
@@ -1510,7 +1503,7 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
#define XGMI_STATE_D0 1
#define XGMI_STATE_D3 0
-static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate)
{
int ret = 0;
@@ -1562,7 +1555,7 @@ static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs= {
.process = smu_v11_0_irq_process,
};
-static int smu_v11_0_register_irq_handler(struct smu_context *smu)
+int smu_v11_0_register_irq_handler(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct amdgpu_irq_src *irq_src = smu->irq_source;
@@ -1594,7 +1587,7 @@ static int smu_v11_0_register_irq_handler(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
struct pp_smu_nv_clock_table *max_clocks)
{
struct smu_table_context *table_context = &smu->smu_table;
@@ -1624,7 +1617,7 @@ static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
return 0;
}
-static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
int ret = 0;
@@ -1638,7 +1631,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v
return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
}
-static bool smu_v11_0_baco_is_support(struct smu_context *smu)
+bool smu_v11_0_baco_is_support(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_baco_context *smu_baco = &smu->smu_baco;
@@ -1671,7 +1664,7 @@ static bool smu_v11_0_baco_is_support(struct smu_context *smu)
return false;
}
-static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
{
struct smu_baco_context *smu_baco = &smu->smu_baco;
enum smu_baco_state baco_state;
@@ -1683,7 +1676,7 @@ static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
return baco_state;
}
-static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
{
struct smu_baco_context *smu_baco = &smu->smu_baco;
struct amdgpu_device *adev = smu->adev;
@@ -1725,7 +1718,7 @@ static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state
return ret;
}
-static int smu_v11_0_baco_reset(struct smu_context *smu)
+int smu_v11_0_baco_reset(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
@@ -1754,7 +1747,7 @@ static int smu_v11_0_baco_reset(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max)
{
int ret = 0, clk_id = 0;
@@ -1789,7 +1782,7 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
return ret;
}
-static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max)
{
int ret = 0, clk_id = 0;
@@ -1818,7 +1811,7 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
return ret;
}
-static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t pcie_gen = 0, pcie_width = 0;
@@ -1858,81 +1851,3 @@ static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
return ret;
}
-
-
-static const struct smu_funcs smu_v11_0_funcs = {
- .init_microcode = smu_v11_0_init_microcode,
- .load_microcode = smu_v11_0_load_microcode,
- .check_fw_status = smu_v11_0_check_fw_status,
- .check_fw_version = smu_v11_0_check_fw_version,
- .send_smc_msg = smu_v11_0_send_msg,
- .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
- .read_smc_arg = smu_v11_0_read_arg,
- .setup_pptable = smu_v11_0_setup_pptable,
- .init_smc_tables = smu_v11_0_init_smc_tables,
- .fini_smc_tables = smu_v11_0_fini_smc_tables,
- .init_power = smu_v11_0_init_power,
- .fini_power = smu_v11_0_fini_power,
- .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
- .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
- .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
- .check_pptable = smu_v11_0_check_pptable,
- .parse_pptable = smu_v11_0_parse_pptable,
- .populate_smc_tables = smu_v11_0_populate_smc_pptable,
- .write_pptable = smu_v11_0_write_pptable,
- .write_watermarks_table = smu_v11_0_write_watermarks_table,
- .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
- .set_tool_table_location = smu_v11_0_set_tool_table_location,
- .init_display_count = smu_v11_0_init_display_count,
- .set_allowed_mask = smu_v11_0_set_allowed_mask,
- .get_enabled_mask = smu_v11_0_get_enabled_mask,
- .system_features_control = smu_v11_0_system_features_control,
- .notify_display_change = smu_v11_0_notify_display_change,
- .set_power_limit = smu_v11_0_set_power_limit,
- .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
- .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
- .start_thermal_control = smu_v11_0_start_thermal_control,
- .stop_thermal_control = smu_v11_0_stop_thermal_control,
- .read_sensor = smu_v11_0_read_sensor,
- .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
- .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
- .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
- .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
- .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
- .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
- .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
- .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
- .gfx_off_control = smu_v11_0_gfx_off_control,
- .register_irq_handler = smu_v11_0_register_irq_handler,
- .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
- .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
- .baco_is_support= smu_v11_0_baco_is_support,
- .baco_get_state = smu_v11_0_baco_get_state,
- .baco_set_state = smu_v11_0_baco_set_state,
- .baco_reset = smu_v11_0_baco_reset,
- .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
- .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
- .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
-};
-
-void smu_v11_0_set_smu_funcs(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
-
- smu->funcs = &smu_v11_0_funcs;
- switch (adev->asic_type) {
- case CHIP_VEGA20:
- vega20_set_ppt_funcs(smu);
- break;
- case CHIP_ARCTURUS:
- arcturus_set_ppt_funcs(smu);
- break;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- navi10_set_ppt_funcs(smu);
- break;
- default:
- pr_warn("Unknown asic for smu11\n");
- }
-}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index ea67380cd9f0..4b617d2164bd 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -30,7 +30,6 @@
#include "smu_v12_0.h"
#include "soc15_common.h"
#include "atom.h"
-#include "renoir_ppt.h"
#include "asic_reg/mp/mp_12_0_0_offset.h"
#include "asic_reg/mp/mp_12_0_0_sh_mask.h"
@@ -42,7 +41,7 @@
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
-static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
{
struct amdgpu_device *adev = smu->adev;
@@ -51,7 +50,7 @@ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
return 0;
}
-static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
{
struct amdgpu_device *adev = smu->adev;
@@ -59,7 +58,7 @@ static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
return 0;
}
-static int smu_v12_0_wait_for_response(struct smu_context *smu)
+int smu_v12_0_wait_for_response(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t cur_value, i;
@@ -78,7 +77,7 @@ static int smu_v12_0_wait_for_response(struct smu_context *smu)
return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
}
-static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0, index = 0;
@@ -103,7 +102,7 @@ static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
}
-static int
+int
smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
uint32_t param)
{
@@ -133,7 +132,7 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
return ret;
}
-static int smu_v12_0_check_fw_status(struct smu_context *smu)
+int smu_v12_0_check_fw_status(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;
@@ -148,7 +147,7 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
return -EIO;
}
-static int smu_v12_0_check_fw_version(struct smu_context *smu)
+int smu_v12_0_check_fw_version(struct smu_context *smu)
{
uint32_t if_version = 0xff, smu_version = 0xff;
uint16_t smu_major;
@@ -182,7 +181,7 @@ static int smu_v12_0_check_fw_version(struct smu_context *smu)
return ret;
}
-static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
{
if (!(smu->adev->flags & AMD_IS_APU))
return 0;
@@ -193,7 +192,7 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
}
-static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
{
if (!(smu->adev->flags & AMD_IS_APU))
return 0;
@@ -204,7 +203,7 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
}
-static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
{
if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
return 0;
@@ -225,7 +224,7 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
* Returns 2=Not in GFXOFF.
* Returns 3=Transition into GFXOFF.
*/
-static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
{
uint32_t reg;
uint32_t gfxOff_Status = 0;
@@ -238,7 +237,7 @@ static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
return gfxOff_Status;
}
-static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
{
int ret = 0, timeout = 500;
@@ -271,7 +270,7 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
return ret;
}
-static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+int smu_v12_0_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = NULL;
@@ -289,7 +288,7 @@ static int smu_v12_0_init_smc_tables(struct smu_context *smu)
return smu_tables_init(smu, tables);
}
-static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+int smu_v12_0_fini_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
@@ -305,7 +304,7 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
return 0;
}
-static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+int smu_v12_0_populate_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *table = NULL;
@@ -320,7 +319,7 @@ static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
}
-static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max)
{
int ret = 0;
@@ -398,11 +397,11 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
return ret;
}
-static int smu_v12_0_mode2_reset(struct smu_context *smu){
+int smu_v12_0_mode2_reset(struct smu_context *smu){
return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
}
-static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max)
{
int ret = 0;
@@ -455,36 +454,3 @@ static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
return ret;
}
-
-static const struct smu_funcs smu_v12_0_funcs = {
- .check_fw_status = smu_v12_0_check_fw_status,
- .check_fw_version = smu_v12_0_check_fw_version,
- .powergate_sdma = smu_v12_0_powergate_sdma,
- .powergate_vcn = smu_v12_0_powergate_vcn,
- .send_smc_msg = smu_v12_0_send_msg,
- .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
- .read_smc_arg = smu_v12_0_read_arg,
- .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
- .gfx_off_control = smu_v12_0_gfx_off_control,
- .init_smc_tables = smu_v12_0_init_smc_tables,
- .fini_smc_tables = smu_v12_0_fini_smc_tables,
- .populate_smc_tables = smu_v12_0_populate_smc_tables,
- .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
- .mode2_reset = smu_v12_0_mode2_reset,
- .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
-};
-
-void smu_v12_0_set_smu_funcs(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
-
- smu->funcs = &smu_v12_0_funcs;
-
- switch (adev->asic_type) {
- case CHIP_RENOIR:
- renoir_set_ppt_funcs(smu);
- break;
- default:
- pr_warn("Unknown asic for smu12\n");
- }
-}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 4039efcdcb1f..d64e997ae36b 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2248,7 +2248,7 @@ vega20_notify_smc_dispaly_config(struct smu_context *smu)
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
- if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
+ if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
@@ -3031,7 +3031,7 @@ static int vega20_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
- ret = smu_smc_read_sensor(smu, sensor, data, size);
+ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
}
mutex_unlock(&smu->sensor_lock);
@@ -3212,7 +3212,58 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.set_watermarks_table = vega20_set_watermarks_table,
.get_thermal_temperature_range = vega20_get_thermal_temperature_range,
.set_df_cstate = vega20_set_df_cstate,
- .update_pcie_parameters = vega20_update_pcie_parameters
+ .update_pcie_parameters = vega20_update_pcie_parameters,
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
+ .check_fw_status = smu_v11_0_check_fw_status,
+ .setup_pptable = smu_v11_0_setup_pptable,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+ .check_pptable = smu_v11_0_check_pptable,
+ .parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ .check_fw_version = smu_v11_0_check_fw_version,
+ .write_pptable = smu_v11_0_write_pptable,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .write_watermarks_table = smu_v11_0_write_watermarks_table,
+ .system_features_control = smu_v11_0_system_features_control,
+ .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+ .set_allowed_mask = smu_v11_0_set_allowed_mask,
+ .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .notify_display_change = smu_v11_0_notify_display_change,
+ .set_power_limit = smu_v11_0_set_power_limit,
+ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ .start_thermal_control = smu_v11_0_start_thermal_control,
+ .stop_thermal_control = smu_v11_0_stop_thermal_control,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+ .gfx_off_control = smu_v11_0_gfx_off_control,
+ .register_irq_handler = smu_v11_0_register_irq_handler,
+ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+ .baco_reset = smu_v11_0_baco_reset,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.23.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2
[not found] ` <20191021024610.16569-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-21 2:47 ` [PATCH 2/3] drm/amd/powerplay: split out those internal used " Quan, Evan
2019-10-21 2:47 ` [PATCH 3/3] drm/amd/powerplay: clear the swSMU code layer Quan, Evan
@ 2019-10-21 13:42 ` Deucher, Alexander
2 siblings, 0 replies; 7+ messages in thread
From: Deucher, Alexander @ 2019-10-21 13:42 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Grodzovsky, Andrey, Xu, Feifei
> -----Original Message-----
> From: Quan, Evan <Evan.Quan@amd.com>
> Sent: Sunday, October 20, 2019 10:48 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky,
> Andrey <Andrey.Grodzovsky@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>;
> Quan, Evan <Evan.Quan@amd.com>; Grodzovsky, Andrey
> <Andrey.Grodzovsky@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>
> Subject: [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU
> APIs V2
>
> This is a quick and low risk fix. Those APIs which
> are exposed to other IPs or to support sysfs/hwmon
> interfaces or DAL will have lock protection. Meanwhile
> no lock protection is enforced for swSMU internal used
> APIs. Future optimization is needed.
>
> V2: strip the lock protection for all swSMU internal APIs
>
> Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> Acked-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +-
> .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 +-
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 696
> ++++++++++++++++--
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 -
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 163 ++--
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 15 +-
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 14 +-
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +-
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 -
> drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 +-
> 12 files changed, 777 insertions(+), 198 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
> index 263265245e19..28d32725285b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
> @@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device
> *adev, bool low)
> if (is_support_sw_smu(adev)) {
> ret = smu_get_dpm_freq_range(&adev->smu,
> SMU_GFXCLK,
> low ? &clk_freq : NULL,
> - !low ? &clk_freq : NULL);
> + !low ? &clk_freq : NULL,
> + true);
> if (ret)
> return 0;
> return clk_freq * 100;
> @@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device
> *adev, bool low)
> if (is_support_sw_smu(adev)) {
> ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
> low ? &clk_freq : NULL,
> - !low ? &clk_freq : NULL);
> + !low ? &clk_freq : NULL,
> + true);
> if (ret)
> return 0;
> return clk_freq * 100;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 1c5c0fd76dbf..2cfb677272af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
> #define amdgpu_dpm_get_current_power_state(adev) \
> ((adev)->powerplay.pp_funcs-
> >get_current_power_state((adev)->powerplay.pp_handle))
>
> -#define amdgpu_smu_get_current_power_state(adev) \
> - ((adev)->smu.ppt_funcs-
> >get_current_power_state(&((adev)->smu)))
> -
> -#define amdgpu_smu_set_power_state(adev) \
> - ((adev)->smu.ppt_funcs->set_power_state(&((adev)-
> >smu)))
> -
> #define amdgpu_dpm_get_pp_num_states(adev, data) \
> ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)-
> >powerplay.pp_handle, data))
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index c50d5f1e75e5..36f36b35000d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -211,7 +211,7 @@ static ssize_t amdgpu_get_dpm_state(struct device
> *dev,
>
> if (is_support_sw_smu(adev)) {
> if (adev->smu.ppt_funcs->get_current_power_state)
> - pm =
> amdgpu_smu_get_current_power_state(adev);
> + pm = smu_get_current_power_state(&adev->smu);
> else
> pm = adev->pm.dpm.user_state;
> } else if (adev->powerplay.pp_funcs->get_current_power_state) {
> @@ -957,7 +957,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask,
> true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK,
> mask);
>
> @@ -1004,7 +1004,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_MCLK,
> mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask,
> true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK,
> mask);
>
> @@ -1044,7 +1044,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK,
> mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK,
> mask, true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK,
> mask);
>
> @@ -1084,7 +1084,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask,
> true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK,
> mask);
>
> @@ -1124,7 +1124,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK,
> mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK,
> mask, true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK,
> mask);
>
> @@ -1164,7 +1164,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct
> device *dev,
> return ret;
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
> + ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask,
> true);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
>
> @@ -1356,7 +1356,7 @@ static ssize_t
> amdgpu_set_pp_power_profile_mode(struct device *dev,
> }
> parameter[parameter_size] = profile_mode;
> if (is_support_sw_smu(adev))
> - ret = smu_set_power_profile_mode(&adev->smu,
> parameter, parameter_size);
> + ret = smu_set_power_profile_mode(&adev->smu,
> parameter, parameter_size, true);
> else if (adev->powerplay.pp_funcs->set_power_profile_mode)
> ret = amdgpu_dpm_set_power_profile_mode(adev,
> parameter, parameter_size);
> if (!ret)
> @@ -2065,7 +2065,7 @@ static ssize_t
> amdgpu_hwmon_show_power_cap_max(struct device *dev,
> uint32_t limit = 0;
>
> if (is_support_sw_smu(adev)) {
> - smu_get_power_limit(&adev->smu, &limit, true);
> + smu_get_power_limit(&adev->smu, &limit, true, true);
> return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >get_power_limit) {
> adev->powerplay.pp_funcs->get_power_limit(adev-
> >powerplay.pp_handle, &limit, true);
> @@ -2083,7 +2083,7 @@ static ssize_t
> amdgpu_hwmon_show_power_cap(struct device *dev,
> uint32_t limit = 0;
>
> if (is_support_sw_smu(adev)) {
> - smu_get_power_limit(&adev->smu, &limit, false);
> + smu_get_power_limit(&adev->smu, &limit, false, true);
> return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >get_power_limit) {
> adev->powerplay.pp_funcs->get_power_limit(adev-
> >powerplay.pp_handle, &limit, false);
> @@ -3064,7 +3064,8 @@ void amdgpu_pm_compute_clocks(struct
> amdgpu_device *adev)
> struct smu_dpm_context *smu_dpm = &adev-
> >smu.smu_dpm;
> smu_handle_task(&adev->smu,
> smu_dpm->dpm_level,
> -
> AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
> + AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
> + true);
> } else {
> if (adev->powerplay.pp_funcs->dispatch_tasks) {
> if (!amdgpu_device_has_dc_support(adev)) {
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 1352019648c0..ee9915d61cf1 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -876,7 +876,7 @@ enum pp_smu_status
> pp_nv_get_maximum_sustainable_clocks(
> if (!smu->funcs->get_max_sustainable_clocks_by_dc)
> return PP_SMU_RESULT_UNSUPPORTED;
>
> - if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu,
> max_clocks))
> + if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
> return PP_SMU_RESULT_OK;
>
> return PP_SMU_RESULT_FAIL;
> @@ -895,7 +895,7 @@ enum pp_smu_status
> pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
> if (!smu->ppt_funcs->get_uclk_dpm_states)
> return PP_SMU_RESULT_UNSUPPORTED;
>
> - if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
> + if (!smu_get_uclk_dpm_states(smu,
> clock_values_in_khz, num_states))
> return PP_SMU_RESULT_OK;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 26cacc899dfe..0841d8c79e5b 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct
> smu_context *smu, char *buf)
> uint32_t sort_feature[SMU_FEATURE_COUNT];
> uint64_t hw_feature_count = 0;
>
> + mutex_lock(&smu->mutex);
> +
> ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> if (ret)
> goto failed;
> @@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct
> smu_context *smu, char *buf)
> }
>
> failed:
> + mutex_unlock(&smu->mutex);
> +
> return size;
> }
>
> @@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct
> smu_context *smu, uint64_t new_mask)
> uint64_t feature_2_disabled = 0;
> uint64_t feature_enables = 0;
>
> + mutex_lock(&smu->mutex);
> +
> ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> if (ret)
> - return ret;
> + goto out;
>
> feature_enables = ((uint64_t)feature_mask[1] << 32 |
> (uint64_t)feature_mask[0]);
>
> @@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct
> smu_context *smu, uint64_t new_mask)
> if (feature_2_enabled) {
> ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> if (ret)
> - return ret;
> + goto out;
> }
> if (feature_2_disabled) {
> ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> if (ret)
> - return ret;
> + goto out;
> }
>
> +out:
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
> }
>
> int smu_get_dpm_freq_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> - uint32_t *min, uint32_t *max)
> + uint32_t *min, uint32_t *max, bool lock_needed)
> {
> uint32_t clock_limit;
> int ret = 0;
> @@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
> if (!min && !max)
> return -EINVAL;
>
> + if (lock_needed)
> + mutex_lock(&smu->mutex);
> +
> if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
> switch (clk_type) {
> case SMU_MCLK:
> @@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
> *min = clock_limit / 100;
> if (max)
> *max = clock_limit / 100;
> -
> - return 0;
> + } else {
> + /*
> + * Todo: Use each asic(ASIC_ppt funcs) control the callbacks
> exposed to the
> + * core driver and then have helpers for stuff that is
> common(SMU_v11_x | SMU_v12_x funcs).
> + */
> + ret = smu_get_dpm_ultimate_freq(smu, clk_type, min,
> max);
> }
> - /*
> - * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed
> to the
> - * core driver and then have helpers for stuff that is
> common(SMU_v11_x | SMU_v12_x funcs).
> - */
> - ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
> +
> + if (lock_needed)
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context
> *smu, uint32_t block_type,
> {
> int ret = 0;
>
> + mutex_lock(&smu->mutex);
> +
> switch (block_type) {
> case AMD_IP_BLOCK_TYPE_UVD:
> ret = smu_dpm_set_uvd_enable(smu, gate);
> @@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context
> *smu, uint32_t block_type,
> break;
> }
>
> - return ret;
> -}
> + mutex_unlock(&smu->mutex);
>
> -enum amd_pm_state_type smu_get_current_power_state(struct
> smu_context *smu)
> -{
> - /* not support power state */
> - return POWER_STATE_TYPE_DEFAULT;
> + return ret;
> }
>
> int smu_get_power_num_states(struct smu_context *smu,
> @@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct
> amdgpu_device *adev)
> int smu_sys_get_pp_table(struct smu_context *smu, void **table)
> {
> struct smu_table_context *smu_table = &smu->smu_table;
> + uint32_t powerplay_table_size;
>
> if (!smu_table->power_play_table && !smu_table-
> >hardcode_pptable)
> return -EINVAL;
>
> + mutex_lock(&smu->mutex);
> +
> if (smu_table->hardcode_pptable)
> *table = smu_table->hardcode_pptable;
> else
> *table = smu_table->power_play_table;
>
> - return smu_table->power_play_table_size;
> + powerplay_table_size = smu_table->power_play_table_size;
> +
> + mutex_unlock(&smu->mutex);
> +
> + return powerplay_table_size;
> }
>
> int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
> @@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context
> *smu, void *buf, size_t size)
> memcpy(smu_table->hardcode_pptable, buf, size);
> smu_table->power_play_table = smu_table->hardcode_pptable;
> smu_table->power_play_table_size = size;
> - mutex_unlock(&smu->mutex);
>
> ret = smu_reset(smu);
> if (ret)
> pr_info("smu reset failed, ret = %d\n", ret);
>
> - return ret;
> -
> failed:
> mutex_unlock(&smu->mutex);
> return ret;
> @@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
> if (!smu->pm_enabled)
> return 0;
>
> - mutex_lock(&smu->mutex);
> smu_handle_task(&adev->smu,
> smu->smu_dpm.dpm_level,
> - AMD_PP_TASK_COMPLETE_INIT);
> - mutex_unlock(&smu->mutex);
> + AMD_PP_TASK_COMPLETE_INIT,
> + false);
>
> return 0;
> }
> @@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> if (ret)
> return ret;
>
> - ret = smu_get_power_limit(smu, &smu-
> >default_power_limit, true);
> + ret = smu_get_power_limit(smu, &smu-
> >default_power_limit, true, false);
> if (ret)
> return ret;
> }
> @@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct
> smu_context *smu)
>
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> if (adev->asic_type < CHIP_NAVI10) {
> - ret = smu_load_microcode(smu);
> - if (ret)
> - return ret;
> + if (smu->funcs->load_microcode) {
> + ret = smu->funcs->load_microcode(smu);
> + if (ret)
> + return ret;
> + }
> }
> }
>
> - ret = smu_check_fw_status(smu);
> - if (ret)
> - pr_err("SMC is not ready\n");
> + if (smu->funcs->check_fw_status) {
> + ret = smu->funcs->check_fw_status(smu);
> + if (ret)
> + pr_err("SMC is not ready\n");
> + }
>
> return ret;
> }
> @@ -1334,8 +1354,6 @@ static int smu_resume(void *handle)
>
> pr_info("SMU is resuming...\n");
>
> - mutex_lock(&smu->mutex);
> -
> ret = smu_start_smc_engine(smu);
> if (ret) {
> pr_err("SMU is not ready yet!\n");
> @@ -1350,13 +1368,11 @@ static int smu_resume(void *handle)
> if (ret)
> goto failed;
>
> - mutex_unlock(&smu->mutex);
> -
> pr_info("SMU is resumed successfully!\n");
>
> return 0;
> +
> failed:
> - mutex_unlock(&smu->mutex);
> return ret;
> }
>
> @@ -1374,8 +1390,9 @@ int smu_display_configuration_change(struct
> smu_context *smu,
>
> mutex_lock(&smu->mutex);
>
> - smu_set_deep_sleep_dcefclk(smu,
> - display_config-
> >min_dcef_deep_sleep_set_clk / 100);
> + if (smu->funcs->set_deep_sleep_dcefclk)
> + smu->funcs->set_deep_sleep_dcefclk(smu,
> + display_config-
> >min_dcef_deep_sleep_set_clk / 100);
>
> for (index = 0; index < display_config-
> >num_path_including_non_display; index++) {
> if (display_config->displays[index].controller_id != 0)
> @@ -1553,9 +1570,9 @@ static int
> smu_default_set_performance_level(struct smu_context *smu, enum
> amd_d
> &soc_mask);
> if (ret)
> return ret;
> - smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
> - smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
> - smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
> + smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask,
> false);
> + smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask,
> false);
> + smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask,
> false);
> break;
> case AMD_DPM_FORCED_LEVEL_MANUAL:
> case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> @@ -1619,7 +1636,7 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
> workload = smu->workload_setting[index];
>
> if (smu->power_profile_mode != workload)
> - smu_set_power_profile_mode(smu, &workload, 0);
> + smu_set_power_profile_mode(smu, &workload, 0,
> false);
> }
>
> return ret;
> @@ -1627,18 +1644,22 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
>
> int smu_handle_task(struct smu_context *smu,
> enum amd_dpm_forced_level level,
> - enum amd_pp_task task_id)
> + enum amd_pp_task task_id,
> + bool lock_needed)
> {
> int ret = 0;
>
> + if (lock_needed)
> + mutex_lock(&smu->mutex);
> +
> switch (task_id) {
> case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
> ret = smu_pre_display_config_changed(smu);
> if (ret)
> - return ret;
> + goto out;
> ret = smu_set_cpu_power_state(smu);
> if (ret)
> - return ret;
> + goto out;
> ret = smu_adjust_power_state_dynamic(smu, level, false);
> break;
> case AMD_PP_TASK_COMPLETE_INIT:
> @@ -1649,6 +1670,10 @@ int smu_handle_task(struct smu_context *smu,
> break;
> }
>
> +out:
> + if (lock_needed)
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -1681,7 +1706,7 @@ int smu_switch_power_profile(struct smu_context
> *smu,
> }
>
> if (smu_dpm_ctx->dpm_level !=
> AMD_DPM_FORCED_LEVEL_MANUAL)
> - smu_set_power_profile_mode(smu, &workload, 0);
> + smu_set_power_profile_mode(smu, &workload, 0, false);
>
> mutex_unlock(&smu->mutex);
>
> @@ -1711,12 +1736,19 @@ int smu_force_performance_level(struct
> smu_context *smu, enum amd_dpm_forced_lev
> if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
> return -EINVAL;
>
> + mutex_lock(&smu->mutex);
> +
> ret = smu_enable_umd_pstate(smu, &level);
> - if (ret)
> + if (ret) {
> + mutex_unlock(&smu->mutex);
> return ret;
> + }
>
> ret = smu_handle_task(smu, level,
> - AMD_PP_TASK_READJUST_POWER_STATE);
> + AMD_PP_TASK_READJUST_POWER_STATE,
> + false);
> +
> + mutex_unlock(&smu->mutex);
>
> return ret;
> }
> @@ -1734,7 +1766,8 @@ int smu_set_display_count(struct smu_context
> *smu, uint32_t count)
>
> int smu_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type clk_type,
> - uint32_t mask)
> + uint32_t mask,
> + bool lock_needed)
> {
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> int ret = 0;
> @@ -1744,9 +1777,15 @@ int smu_force_clk_levels(struct smu_context
> *smu,
> return -EINVAL;
> }
>
> + if (lock_needed)
> + mutex_lock(&smu->mutex);
> +
> if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
> ret = smu->ppt_funcs->force_clk_levels(smu, clk_type,
> mask);
>
> + if (lock_needed)
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -1764,6 +1803,8 @@ int smu_set_mp1_state(struct smu_context *smu,
> if (!smu->pm_enabled)
> return 0;
>
> + mutex_lock(&smu->mutex);
> +
> switch (mp1_state) {
> case PP_MP1_STATE_SHUTDOWN:
> msg = SMU_MSG_PrepareMp1ForShutdown;
> @@ -1776,17 +1817,22 @@ int smu_set_mp1_state(struct smu_context
> *smu,
> break;
> case PP_MP1_STATE_NONE:
> default:
> + mutex_unlock(&smu->mutex);
> return 0;
> }
>
> /* some asics may not support those messages */
> - if (smu_msg_get_index(smu, msg) < 0)
> + if (smu_msg_get_index(smu, msg) < 0) {
> + mutex_unlock(&smu->mutex);
> return 0;
> + }
>
> ret = smu_send_smc_msg(smu, msg);
> if (ret)
> pr_err("[PrepareMp1] Failed!\n");
>
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -1806,10 +1852,14 @@ int smu_set_df_cstate(struct smu_context
> *smu,
> if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
> return 0;
>
> + mutex_lock(&smu->mutex);
> +
> ret = smu->ppt_funcs->set_df_cstate(smu, state);
> if (ret)
> pr_err("[SetDfCstate] failed!\n");
>
> + mutex_unlock(&smu->mutex);
> +
> return ret;
> }
>
> @@ -1849,3 +1899,549 @@ const struct amdgpu_ip_block_version
> smu_v12_0_ip_block =
> .rev = 0,
> .funcs = &smu_ip_funcs,
> };
> +
> +int smu_load_microcode(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->load_microcode)
> + ret = smu->funcs->load_microcode(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_check_fw_status(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->check_fw_status)
> + ret = smu->funcs->check_fw_status(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_gfx_cgpg)
> + ret = smu->funcs->set_gfx_cgpg(smu, enabled);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_fan_speed_rpm)
> + ret = smu->funcs->set_fan_speed_rpm(smu, speed);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_power_limit(struct smu_context *smu,
> + uint32_t *limit,
> + bool def,
> + bool lock_needed)
> +{
> + int ret = 0;
> +
> + if (lock_needed)
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_power_limit)
> + ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
> +
> + if (lock_needed)
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_power_limit)
> + ret = smu->funcs->set_power_limit(smu, limit);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type
> clk_type, char *buf)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->print_clk_levels)
> + ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_od_percentage(struct smu_context *smu, enum
> smu_clk_type type)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_od_percentage)
> + ret = smu->ppt_funcs->get_od_percentage(smu, type);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_od_percentage(struct smu_context *smu, enum
> smu_clk_type type, uint32_t value)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->set_od_percentage)
> + ret = smu->ppt_funcs->set_od_percentage(smu, type,
> value);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_od_edit_dpm_table(struct smu_context *smu,
> + enum PP_OD_DPM_TABLE_COMMAND type,
> + long *input, uint32_t size)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->od_edit_dpm_table)
> + ret = smu->ppt_funcs->od_edit_dpm_table(smu, type,
> input, size);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_read_sensor(struct smu_context *smu,
> + enum amd_pp_sensors sensor,
> + void *data, uint32_t *size)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->read_sensor)
> + ret = smu->ppt_funcs->read_sensor(smu, sensor, data,
> size);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_power_profile_mode)
> + ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_power_profile_mode(struct smu_context *smu,
> + long *param,
> + uint32_t param_size,
> + bool lock_needed)
> +{
> + int ret = 0;
> +
> + if (lock_needed)
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->set_power_profile_mode)
> + ret = smu->ppt_funcs->set_power_profile_mode(smu,
> param, param_size);
> +
> + if (lock_needed)
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +
> +int smu_get_fan_control_mode(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->get_fan_control_mode)
> + ret = smu->funcs->get_fan_control_mode(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_fan_control_mode(struct smu_context *smu, int value)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_fan_control_mode)
> + ret = smu->funcs->set_fan_control_mode(smu, value);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t
> *speed)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_fan_speed_percent)
> + ret = smu->ppt_funcs->get_fan_speed_percent(smu,
> speed);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t
> speed)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_fan_speed_percent)
> + ret = smu->funcs->set_fan_speed_percent(smu, speed);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_fan_speed_rpm)
> + ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_deep_sleep_dcefclk)
> + ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_active_display_count(struct smu_context *smu, uint32_t
> count)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_active_display_count)
> + ret = smu->funcs->set_active_display_count(smu, count);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_clock_by_type(struct smu_context *smu,
> + enum amd_pp_clock_type type,
> + struct amd_pp_clocks *clocks)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->get_clock_by_type)
> + ret = smu->funcs->get_clock_by_type(smu, type, clocks);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_max_high_clocks(struct smu_context *smu,
> + struct amd_pp_simple_clock_info *clocks)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->get_max_high_clocks)
> + ret = smu->funcs->get_max_high_clocks(smu, clocks);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_clock_by_type_with_latency(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + struct pp_clock_levels_with_latency
> *clocks)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_clock_by_type_with_latency)
> + ret = smu->ppt_funcs-
> >get_clock_by_type_with_latency(smu, clk_type, clocks);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_voltage
> *clocks)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_clock_by_type_with_voltage)
> + ret = smu->ppt_funcs-
> >get_clock_by_type_with_voltage(smu, type, clocks);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +
> +int smu_display_clock_voltage_request(struct smu_context *smu,
> + struct pp_display_clock_request
> *clock_req)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->display_clock_voltage_request)
> + ret = smu->funcs->display_clock_voltage_request(smu,
> clock_req);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +
> +int smu_display_disable_memory_clock_switch(struct smu_context *smu,
> bool disable_memory_clock_switch)
> +{
> + int ret = -EINVAL;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->display_disable_memory_clock_switch)
> + ret = smu->ppt_funcs-
> >display_disable_memory_clock_switch(smu,
> disable_memory_clock_switch);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_notify_smu_enable_pwe(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->notify_smu_enable_pwe)
> + ret = smu->funcs->notify_smu_enable_pwe(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
> + struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_watermarks_for_clock_ranges)
> + ret = smu->funcs->set_watermarks_for_clock_ranges(smu,
> clock_ranges);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_xgmi_pstate(struct smu_context *smu,
> + uint32_t pstate)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_xgmi_pstate)
> + ret = smu->funcs->set_xgmi_pstate(smu, pstate);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_set_azalia_d3_pme(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->set_azalia_d3_pme)
> + ret = smu->funcs->set_azalia_d3_pme(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +bool smu_baco_is_support(struct smu_context *smu)
> +{
> + bool ret = false;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->baco_is_support)
> + ret = smu->funcs->baco_is_support(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state
> *state)
> +{
> + if (smu->funcs->baco_get_state)
> + return -EINVAL;
> +
> + mutex_lock(&smu->mutex);
> + *state = smu->funcs->baco_get_state(smu);
> + mutex_unlock(&smu->mutex);
> +
> + return 0;
> +}
> +
> +int smu_baco_reset(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->baco_reset)
> + ret = smu->funcs->baco_reset(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_mode2_reset(struct smu_context *smu)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->mode2_reset)
> + ret = smu->funcs->mode2_reset(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
> + struct pp_smu_nv_clock_table
> *max_clocks)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->funcs->get_max_sustainable_clocks_by_dc)
> + ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu,
> max_clocks);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +int smu_get_uclk_dpm_states(struct smu_context *smu,
> + unsigned int *clock_values_in_khz,
> + unsigned int *num_states)
> +{
> + int ret = 0;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_uclk_dpm_states)
> + ret = smu->ppt_funcs->get_uclk_dpm_states(smu,
> clock_values_in_khz, num_states);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return ret;
> +}
> +
> +enum amd_pm_state_type smu_get_current_power_state(struct
> smu_context *smu)
> +{
> + enum amd_pm_state_type pm_state =
> POWER_STATE_TYPE_DEFAULT;
> +
> + mutex_lock(&smu->mutex);
> +
> + if (smu->ppt_funcs->get_current_power_state)
> + pm_state = smu->ppt_funcs-
> >get_current_power_state(smu);
> +
> + mutex_unlock(&smu->mutex);
> +
> + return pm_state;
> +}
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 6731fed5458e..141e48cd1c5d 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -772,8 +772,6 @@ static int arcturus_force_clk_levels(struct
> smu_context *smu,
> uint32_t soft_min_level, soft_max_level;
> int ret = 0;
>
> - mutex_lock(&(smu->mutex));
> -
> soft_min_level = mask ? (ffs(mask) - 1) : 0;
> soft_max_level = mask ? (fls(mask) - 1) : 0;
>
> @@ -892,7 +890,6 @@ static int arcturus_force_clk_levels(struct
> smu_context *smu,
> break;
> }
>
> - mutex_unlock(&(smu->mutex));
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index cdb845f5f23e..3e3464fa2ff5 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -565,18 +565,17 @@ struct smu_funcs
> ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
> #define smu_fini_power(smu) \
> ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
> -#define smu_load_microcode(smu) \
> - ((smu)->funcs->load_microcode ? (smu)->funcs-
> >load_microcode((smu)) : 0)
> -#define smu_check_fw_status(smu) \
> - ((smu)->funcs->check_fw_status ? (smu)->funcs-
> >check_fw_status((smu)) : 0)
> +int smu_load_microcode(struct smu_context *smu);
> +
> +int smu_check_fw_status(struct smu_context *smu);
> +
> #define smu_setup_pptable(smu) \
> ((smu)->funcs->setup_pptable ? (smu)->funcs-
> >setup_pptable((smu)) : 0)
> #define smu_powergate_sdma(smu, gate) \
> ((smu)->funcs->powergate_sdma ? (smu)->funcs-
> >powergate_sdma((smu), (gate)) : 0)
> #define smu_powergate_vcn(smu, gate) \
> ((smu)->funcs->powergate_vcn ? (smu)->funcs-
> >powergate_vcn((smu), (gate)) : 0)
> -#define smu_set_gfx_cgpg(smu, enabled) \
> - ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu),
> (enabled)) : 0)
> +int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
> #define smu_get_vbios_bootup_values(smu) \
> ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs-
> >get_vbios_bootup_values((smu)) : 0)
> #define smu_get_clk_info_from_vbios(smu) \
> @@ -610,8 +609,8 @@ struct smu_funcs
> ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs-
> >init_max_sustainable_clocks((smu)) : 0)
> #define smu_set_default_od_settings(smu, initialize) \
> ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs-
> >set_default_od_settings((smu), (initialize)) : 0)
> -#define smu_set_fan_speed_rpm(smu, speed) \
> - ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs-
> >set_fan_speed_rpm((smu), (speed)) : 0)
> +int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
> +
> #define smu_send_smc_msg(smu, msg) \
> ((smu)->funcs->send_smc_msg? (smu)->funcs-
> >send_smc_msg((smu), (msg)) : 0)
> #define smu_send_smc_msg_with_param(smu, msg, param) \
> @@ -642,20 +641,22 @@ struct smu_funcs
> ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs-
> >populate_umd_state_clk((smu)) : 0)
> #define smu_set_default_od8_settings(smu) \
> ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs-
> >set_default_od8_settings((smu)) : 0)
> -#define smu_get_power_limit(smu, limit, def) \
> - ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs-
> >get_power_limit((smu), (limit), (def)) : 0)
> -#define smu_set_power_limit(smu, limit) \
> - ((smu)->funcs->set_power_limit ? (smu)->funcs-
> >set_power_limit((smu), (limit)) : 0)
> +
> +int smu_get_power_limit(struct smu_context *smu,
> + uint32_t *limit,
> + bool def,
> + bool lock_needed);
> +
> +int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
> #define smu_get_current_clk_freq(smu, clk_id, value) \
> ((smu)->funcs->get_current_clk_freq? (smu)->funcs-
> >get_current_clk_freq((smu), (clk_id), (value)) : 0)
> -#define smu_print_clk_levels(smu, clk_type, buf) \
> - ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs-
> >print_clk_levels((smu), (clk_type), (buf)) : 0)
> -#define smu_get_od_percentage(smu, type) \
> - ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs-
> >get_od_percentage((smu), (type)) : 0)
> -#define smu_set_od_percentage(smu, type, value) \
> - ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs-
> >set_od_percentage((smu), (type), (value)) : 0)
> -#define smu_od_edit_dpm_table(smu, type, input, size) \
> - ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs-
> >od_edit_dpm_table((smu), (type), (input), (size)) : 0)
> +int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type
> clk_type, char *buf);
> +int smu_get_od_percentage(struct smu_context *smu, enum
> smu_clk_type type);
> +int smu_set_od_percentage(struct smu_context *smu, enum
> smu_clk_type type, uint32_t value);
> +
> +int smu_od_edit_dpm_table(struct smu_context *smu,
> + enum PP_OD_DPM_TABLE_COMMAND type,
> + long *input, uint32_t size);
> #define smu_tables_init(smu, tab) \
> ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs-
> >tables_init((smu), (tab)) : 0)
> #define smu_set_thermal_fan_table(smu) \
> @@ -664,14 +665,18 @@ struct smu_funcs
> ((smu)->funcs->start_thermal_control? (smu)->funcs-
> >start_thermal_control((smu)) : 0)
> #define smu_stop_thermal_control(smu) \
> ((smu)->funcs->stop_thermal_control? (smu)->funcs-
> >stop_thermal_control((smu)) : 0)
> -#define smu_read_sensor(smu, sensor, data, size) \
> - ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs-
> >read_sensor((smu), (sensor), (data), (size)) : 0)
> +
> +int smu_read_sensor(struct smu_context *smu,
> + enum amd_pp_sensors sensor,
> + void *data, uint32_t *size);
> #define smu_smc_read_sensor(smu, sensor, data, size) \
> ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu),
> (sensor), (data), (size)) : -EINVAL)
> -#define smu_get_power_profile_mode(smu, buf) \
> - ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs-
> >get_power_profile_mode((smu), buf) : 0)
> -#define smu_set_power_profile_mode(smu, param, param_size) \
> - ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs-
> >set_power_profile_mode((smu), (param), (param_size)) : 0)
> +int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
> +
> +int smu_set_power_profile_mode(struct smu_context *smu,
> + long *param,
> + uint32_t param_size,
> + bool lock_needed);
> #define smu_pre_display_config_changed(smu) \
> ((smu)->ppt_funcs->pre_display_config_changed ? (smu)-
> >ppt_funcs->pre_display_config_changed((smu)) : 0)
> #define smu_display_config_changed(smu) \
> @@ -688,16 +693,11 @@ struct smu_funcs
> ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs-
> >get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask),
> (soc_mask)) : 0)
> #define smu_set_cpu_power_state(smu) \
> ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs-
> >set_cpu_power_state((smu)) : 0)
> -#define smu_get_fan_control_mode(smu) \
> - ((smu)->funcs->get_fan_control_mode ? (smu)->funcs-
> >get_fan_control_mode((smu)) : 0)
> -#define smu_set_fan_control_mode(smu, value) \
> - ((smu)->funcs->set_fan_control_mode ? (smu)->funcs-
> >set_fan_control_mode((smu), (value)) : 0)
> -#define smu_get_fan_speed_percent(smu, speed) \
> - ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs-
> >get_fan_speed_percent((smu), (speed)) : 0)
> -#define smu_set_fan_speed_percent(smu, speed) \
> - ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs-
> >set_fan_speed_percent((smu), (speed)) : 0)
> -#define smu_get_fan_speed_rpm(smu, speed) \
> - ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs-
> >get_fan_speed_rpm((smu), (speed)) : 0)
> +int smu_get_fan_control_mode(struct smu_context *smu);
> +int smu_set_fan_control_mode(struct smu_context *smu, int value);
> +int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t
> *speed);
> +int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t
> speed);
> +int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
>
> #define smu_msg_get_index(smu, msg) \
> ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index?
> (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -
> EINVAL)
> @@ -715,40 +715,46 @@ struct smu_funcs
> ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)-
> >ppt_funcs->run_btc((smu)) : 0) : 0)
> #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
> ((smu)->ppt_funcs? ((smu)->ppt_funcs-
> >get_allowed_feature_mask? (smu)->ppt_funcs-
> >get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
> -#define smu_set_deep_sleep_dcefclk(smu, clk) \
> - ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs-
> >set_deep_sleep_dcefclk((smu), (clk)) : 0)
> -#define smu_set_active_display_count(smu, count) \
> - ((smu)->funcs->set_active_display_count ? (smu)->funcs-
> >set_active_display_count((smu), (count)) : 0)
> +int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
> +int smu_set_active_display_count(struct smu_context *smu, uint32_t
> count);
> #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
> ((smu)->funcs->store_cc6_data ? (smu)->funcs-
> >store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
> -#define smu_get_clock_by_type(smu, type, clocks) \
> - ((smu)->funcs->get_clock_by_type ? (smu)->funcs-
> >get_clock_by_type((smu), (type), (clocks)) : 0)
> -#define smu_get_max_high_clocks(smu, clocks) \
> - ((smu)->funcs->get_max_high_clocks ? (smu)->funcs-
> >get_max_high_clocks((smu), (clocks)) : 0)
> -#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
> - ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)-
> >ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) :
> 0)
> -#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
> - ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)-
> >ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
> -#define smu_display_clock_voltage_request(smu, clock_req) \
> - ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs-
> >display_clock_voltage_request((smu), (clock_req)) : 0)
> -#define smu_display_disable_memory_clock_switch(smu,
> disable_memory_clock_switch) \
> - ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)-
> >ppt_funcs->display_disable_memory_clock_switch((smu),
> (disable_memory_clock_switch)) : -EINVAL)
> +
> +int smu_get_clock_by_type(struct smu_context *smu,
> + enum amd_pp_clock_type type,
> + struct amd_pp_clocks *clocks);
> +
> +int smu_get_max_high_clocks(struct smu_context *smu,
> + struct amd_pp_simple_clock_info *clocks);
> +
> +int smu_get_clock_by_type_with_latency(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + struct pp_clock_levels_with_latency
> *clocks);
> +
> +int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_voltage
> *clocks);
> +
> +int smu_display_clock_voltage_request(struct smu_context *smu,
> + struct pp_display_clock_request
> *clock_req);
> +int smu_display_disable_memory_clock_switch(struct smu_context *smu,
> bool disable_memory_clock_switch);
> #define smu_get_dal_power_level(smu, clocks) \
> ((smu)->funcs->get_dal_power_level ? (smu)->funcs-
> >get_dal_power_level((smu), (clocks)) : 0)
> #define smu_get_perf_level(smu, designation, level) \
> ((smu)->funcs->get_perf_level ? (smu)->funcs-
> >get_perf_level((smu), (designation), (level)) : 0)
> #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
> ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs-
> >get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
> -#define smu_notify_smu_enable_pwe(smu) \
> - ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs-
> >notify_smu_enable_pwe((smu)) : 0)
> -#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
> - ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs-
> >set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
> +int smu_notify_smu_enable_pwe(struct smu_context *smu);
> +
> +int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
> + struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
> #define smu_dpm_set_uvd_enable(smu, enable) \
> ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs-
> >dpm_set_uvd_enable((smu), (enable)) : 0)
> #define smu_dpm_set_vce_enable(smu, enable) \
> ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs-
> >dpm_set_vce_enable((smu), (enable)) : 0)
> -#define smu_set_xgmi_pstate(smu, pstate) \
> - ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs-
> >set_xgmi_pstate((smu), (pstate)) : 0)
> +
> +int smu_set_xgmi_pstate(struct smu_context *smu,
> + uint32_t pstate);
> #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs-
> >set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
> #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> @@ -759,22 +765,18 @@ struct smu_funcs
> ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)-
> >ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
> #define smu_register_irq_handler(smu) \
> ((smu)->funcs->register_irq_handler ? (smu)->funcs-
> >register_irq_handler(smu) : 0)
> -#define smu_set_azalia_d3_pme(smu) \
> - ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs-
> >set_azalia_d3_pme((smu)) : 0)
> +
> +int smu_set_azalia_d3_pme(struct smu_context *smu);
> #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
> ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs-
> >get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
> -#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
> - ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs-
> >get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
> -#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
> - ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs-
> >get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
> -#define smu_baco_is_support(smu) \
> - ((smu)->funcs->baco_is_support? (smu)->funcs-
> >baco_is_support((smu)) : false)
> -#define smu_baco_get_state(smu, state) \
> - ((smu)->funcs->baco_get_state? (smu)->funcs-
> >baco_get_state((smu), (state)) : 0)
> -#define smu_baco_reset(smu) \
> - ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
> -#define smu_mode2_reset(smu) \
> - ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu))
> : 0)
> +
> +bool smu_baco_is_support(struct smu_context *smu);
> +
> +int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state
> *state);
> +
> +int smu_baco_reset(struct smu_context *smu);
> +
> +int smu_mode2_reset(struct smu_context *smu);
> #define smu_asic_set_performance_level(smu, level) \
> ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs-
> >set_performance_level((smu), (level)) : -EINVAL);
> #define smu_dump_pptable(smu) \
> @@ -833,7 +835,8 @@ extern int smu_get_current_clocks(struct
> smu_context *smu,
> extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t
> block_type, bool gate);
> extern int smu_handle_task(struct smu_context *smu,
> enum amd_dpm_forced_level level,
> - enum amd_pp_task task_id);
> + enum amd_pp_task task_id,
> + bool lock_needed);
> int smu_switch_power_profile(struct smu_context *smu,
> enum PP_SMC_POWER_PROFILE type,
> bool en);
> @@ -843,7 +846,7 @@ int smu_get_dpm_freq_by_index(struct
> smu_context *smu, enum smu_clk_type clk_typ
> int smu_get_dpm_level_count(struct smu_context *smu, enum
> smu_clk_type clk_type,
> uint32_t *value);
> int smu_get_dpm_freq_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> - uint32_t *min, uint32_t *max);
> + uint32_t *min, uint32_t *max, bool lock_needed);
> int smu_set_soft_freq_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> uint32_t min, uint32_t max);
> int smu_set_hard_freq_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> @@ -858,10 +861,20 @@ size_t smu_sys_get_pp_feature_mask(struct
> smu_context *smu, char *buf);
> int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask);
> int smu_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type clk_type,
> - uint32_t mask);
> + uint32_t mask,
> + bool lock_needed);
> int smu_set_mp1_state(struct smu_context *smu,
> enum pp_mp1_state mp1_state);
> int smu_set_df_cstate(struct smu_context *smu,
> enum pp_df_cstate state);
>
> +int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
> + struct pp_smu_nv_clock_table
> *max_clocks);
> +
> +int smu_get_uclk_dpm_states(struct smu_context *smu,
> + unsigned int *clock_values_in_khz,
> + unsigned int *num_states);
> +
> +enum amd_pm_state_type smu_get_current_power_state(struct
> smu_context *smu);
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index b88aae9bb242..ead40b2840f9 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct
> smu_context *smu)
> int ret = 0;
> uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
>
> - ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq,
> NULL);
> + ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq,
> NULL, false);
> if (ret)
> return ret;
>
> smu->pstate_sclk = min_sclk_freq * 100;
>
> - ret = smu_get_dpm_freq_range(smu, SMU_MCLK,
> &min_mclk_freq, NULL);
> + ret = smu_get_dpm_freq_range(smu, SMU_MCLK,
> &min_mclk_freq, NULL, false);
> if (ret)
> return ret;
>
> @@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct
> smu_context *smu)
> return ret;
>
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
> {
> - ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL,
> &max_freq);
> + ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL,
> &max_freq, false);
> if (ret)
> return ret;
> ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0,
> max_freq);
> @@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct
> smu_context *smu, bool highest)
>
> for (i = 0; i < ARRAY_SIZE(clks); i++) {
> clk_type = clks[i];
> - ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq);
> + ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq, false);
> if (ret)
> return ret;
>
> @@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct
> smu_context *smu)
>
> for (i = 0; i < ARRAY_SIZE(clks); i++) {
> clk_type = clks[i];
> - ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq);
> + ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq, false);
> if (ret)
> return ret;
>
> @@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct
> smu_context *smu)
> if (smu_feature_is_supported(smu,
> SMU_FEATURE_DPM_DCEFCLK_BIT)) {
> clock_req.clock_type = amd_pp_dcef_clock;
> clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
> - if (!smu_display_clock_voltage_request(smu, &clock_req)) {
> +
> + if (smu->funcs->display_clock_voltage_request)
> + ret = smu->funcs-
> >display_clock_voltage_request(smu, &clock_req);
> + if (!ret) {
> if (smu_feature_is_supported(smu,
> SMU_FEATURE_DS_DCEFCLK_BIT)) {
> ret = smu_send_smc_msg_with_param(smu,
>
> SMU_MSG_SetMinDeepSleepDcefclk,
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 6aedffd739db..6036f682e6f9 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context
> *smu,
> case SMU_SCLK:
> /* retirve table returned paramters unit is MHz */
> cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
> - ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min,
> &max);
> + ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min,
> &max, false);
> if (!ret) {
> /* driver only know min/max gfx_clk, Add level 1 for
> all other gfx clks */
> if (cur_value == max)
> @@ -251,7 +251,6 @@ static enum amd_pm_state_type
> renoir_get_current_power_state(struct smu_context
> !smu_dpm_ctx->dpm_current_power_state)
> return -EINVAL;
>
> - mutex_lock(&(smu->mutex));
> switch (smu_dpm_ctx->dpm_current_power_state-
> >classification.ui_label) {
> case SMU_STATE_UI_LABEL_BATTERY:
> pm_type = POWER_STATE_TYPE_BATTERY;
> @@ -269,7 +268,6 @@ static enum amd_pm_state_type
> renoir_get_current_power_state(struct smu_context
> pm_type = POWER_STATE_TYPE_DEFAULT;
> break;
> }
> - mutex_unlock(&(smu->mutex));
>
> return pm_type;
> }
> @@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct
> smu_context *smu, bool highest)
>
> for (i = 0; i < ARRAY_SIZE(clks); i++) {
> clk_type = clks[i];
> - ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq);
> + ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq, false);
> if (ret)
> return ret;
>
> @@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct
> smu_context *smu) {
>
> clk_type = clk_feature_map[i].clk_type;
>
> - ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq);
> + ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq, false);
> if (ret)
> return ret;
>
> @@ -435,7 +433,7 @@ static int renoir_force_clk_levels(struct smu_context
> *smu,
> return -EINVAL;
> }
>
> - ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
> &min_freq, &max_freq);
> + ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
> &min_freq, &max_freq, false);
> if (ret)
> return ret;
> ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_SetSoftMaxGfxClk,
> @@ -511,7 +509,7 @@ static int renoir_set_peak_clock_by_device(struct
> smu_context *smu)
> int ret = 0;
> uint32_t sclk_freq = 0, uclk_freq = 0;
>
> - ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL,
> &sclk_freq);
> + ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq,
> false);
> if (ret)
> return ret;
>
> @@ -519,7 +517,7 @@ static int renoir_set_peak_clock_by_device(struct
> smu_context *smu)
> if (ret)
> return ret;
>
> - ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL,
> &uclk_freq);
> + ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL,
> &uclk_freq, false);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index b68cb8badc75..caf8a3728541 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -809,8 +809,11 @@ static int
> smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
> if (!table_context)
> return -EINVAL;
>
> - return smu_set_deep_sleep_dcefclk(smu,
> - table_context->boot_values.dcefclk
> / 100);
> + if (smu->funcs->set_deep_sleep_dcefclk)
> + return smu->funcs->set_deep_sleep_dcefclk(smu,
> + table_context->boot_values.dcefclk / 100);
> +
> + return 0;
> }
>
> static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
> @@ -1325,9 +1328,7 @@ smu_v11_0_display_clock_voltage_request(struct
> smu_context *smu,
> if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
> return 0;
>
> - mutex_lock(&smu->mutex);
> ret = smu_set_hard_freq_range(smu, clk_select, clk_freq,
> 0);
> - mutex_unlock(&smu->mutex);
>
> if(clk_select == SMU_UCLK)
> smu->hard_min_uclk_req_from_dal = clk_freq;
> @@ -1370,12 +1371,10 @@ static int smu_v11_0_gfx_off_control(struct
> smu_context *smu, bool enable)
> case CHIP_NAVI12:
> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> return 0;
> - mutex_lock(&smu->mutex);
> if (enable)
> ret = smu_send_smc_msg(smu,
> SMU_MSG_AllowGfxOff);
> else
> ret = smu_send_smc_msg(smu,
> SMU_MSG_DisallowGfxOff);
> - mutex_unlock(&smu->mutex);
> break;
> default:
> break;
> @@ -1491,10 +1490,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct
> smu_context *smu,
> if (!speed)
> return -EINVAL;
>
> - mutex_lock(&(smu->mutex));
> ret = smu_v11_0_auto_fan_control(smu, 0);
> if (ret)
> - goto set_fan_speed_rpm_failed;
> + return ret;
>
> crystal_clock_freq = amdgpu_asic_get_xclk(adev);
> tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
> @@ -1505,8 +1503,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct
> smu_context *smu,
>
> ret = smu_v11_0_set_fan_static_mode(smu,
> FDO_PWM_MODE_STATIC_RPM);
>
> -set_fan_speed_rpm_failed:
> - mutex_unlock(&(smu->mutex));
> return ret;
> }
>
> @@ -1517,11 +1513,9 @@ static int smu_v11_0_set_xgmi_pstate(struct
> smu_context *smu,
> uint32_t pstate)
> {
> int ret = 0;
> - mutex_lock(&(smu->mutex));
> ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_SetXgmiMode,
> pstate ? XGMI_STATE_D0 :
> XGMI_STATE_D3);
> - mutex_unlock(&(smu->mutex));
> return ret;
> }
>
> @@ -1633,9 +1627,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct
> smu_context *smu)
> {
> int ret = 0;
>
> - mutex_lock(&smu->mutex);
> ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
> - mutex_unlock(&smu->mutex);
>
> return ret;
> }
> @@ -1767,7 +1759,6 @@ static int
> smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum
> smu_clk
> int ret = 0, clk_id = 0;
> uint32_t param = 0;
>
> - mutex_lock(&smu->mutex);
> clk_id = smu_clk_get_index(smu, clk_type);
> if (clk_id < 0) {
> ret = -EINVAL;
> @@ -1794,7 +1785,6 @@ static int
> smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum
> smu_clk
> }
>
> failed:
> - mutex_unlock(&smu->mutex);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index c9691d0fb523..6bf942d3ceca 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -325,8 +325,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
> smu_context *smu, enum smu_clk
> int ret = 0;
> uint32_t mclk_mask, soc_mask;
>
> - mutex_lock(&smu->mutex);
> -
> if (max) {
> ret = smu_get_profiling_clk_mask(smu,
> AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
> NULL,
> @@ -396,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
> smu_context *smu, enum smu_clk
> }
> }
> failed:
> - mutex_unlock(&smu->mutex);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index a76ffd58404e..c249df9256c7 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -635,7 +635,6 @@ amd_pm_state_type
> vega20_get_current_power_state(struct smu_context *smu)
> !smu_dpm_ctx->dpm_current_power_state)
> return -EINVAL;
>
> - mutex_lock(&(smu->mutex));
> switch (smu_dpm_ctx->dpm_current_power_state-
> >classification.ui_label) {
> case SMU_STATE_UI_LABEL_BATTERY:
> pm_type = POWER_STATE_TYPE_BATTERY;
> @@ -653,7 +652,6 @@ amd_pm_state_type
> vega20_get_current_power_state(struct smu_context *smu)
> pm_type = POWER_STATE_TYPE_DEFAULT;
> break;
> }
> - mutex_unlock(&(smu->mutex));
>
> return pm_type;
> }
> @@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct
> smu_context *smu,
> uint32_t soft_min_level, soft_max_level, hard_min_level;
> int ret = 0;
>
> - mutex_lock(&(smu->mutex));
> -
> soft_min_level = mask ? (ffs(mask) - 1) : 0;
> soft_max_level = mask ? (fls(mask) - 1) : 0;
>
> @@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct
> smu_context *smu,
> break;
> }
>
> - mutex_unlock(&(smu->mutex));
> return ret;
> }
>
> @@ -1446,8 +1441,6 @@ static int
> vega20_get_clock_by_type_with_latency(struct smu_context *smu,
>
> dpm_table = smu_dpm->dpm_context;
>
> - mutex_lock(&smu->mutex);
> -
> switch (clk_type) {
> case SMU_GFXCLK:
> single_dpm_table = &(dpm_table->gfx_table);
> @@ -1469,7 +1462,6 @@ static int
> vega20_get_clock_by_type_with_latency(struct smu_context *smu,
> ret = -EINVAL;
> }
>
> - mutex_unlock(&smu->mutex);
> return ret;
> }
>
> @@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct
> smu_context *smu,
> int feature_enabled;
> PPCLK_e clk_id;
>
> - mutex_lock(&(smu->mutex));
> -
> dpm_table = smu_dpm->dpm_context;
> golden_table = smu_dpm->golden_dpm_context;
>
> @@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct
> smu_context *smu,
> }
>
> ret = smu_handle_task(smu, smu_dpm->dpm_level,
> - AMD_PP_TASK_READJUST_POWER_STATE);
> + AMD_PP_TASK_READJUST_POWER_STATE,
> + false);
>
> set_od_failed:
> - mutex_unlock(&(smu->mutex));
> -
> return ret;
> }
>
> @@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct
> smu_context *smu,
> }
>
> if (type == PP_OD_COMMIT_DPM_TABLE) {
> - mutex_lock(&(smu->mutex));
> ret = smu_handle_task(smu, smu_dpm->dpm_level,
> -
> AMD_PP_TASK_READJUST_POWER_STATE);
> - mutex_unlock(&(smu->mutex));
> +
> AMD_PP_TASK_READJUST_POWER_STATE,
> + false);
> }
>
> return ret;
> --
> 2.23.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 2/3] drm/amd/powerplay: split out those internal used swSMU APIs V2
[not found] ` <20191021024610.16569-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-10-21 13:42 ` Deucher, Alexander
0 siblings, 0 replies; 7+ messages in thread
From: Deucher, Alexander @ 2019-10-21 13:42 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Grodzovsky, Andrey, Xu, Feifei
> -----Original Message-----
> From: Quan, Evan <Evan.Quan@amd.com>
> Sent: Sunday, October 20, 2019 10:48 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky,
> Andrey <Andrey.Grodzovsky@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>;
> Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 2/3] drm/amd/powerplay: split out those internal used
> swSMU APIs V2
>
> Those swSMU APIs used internally are moved to smu_internal.h while others
> are kept in amdgpu_smu.h.
>
> V2: give a better name smu_internal.h for the place to hold
> those internal APIs
>
> Change-Id: Ib726ef7f65dee46e47a07680b71e6e043e459f42
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 +
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 164 +-------------
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 +
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 206
> ++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 1 +
> drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 +
> 9 files changed, 214 insertions(+), 163 deletions(-) create mode 100644
> drivers/gpu/drm/amd/powerplay/smu_internal.h
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 0841d8c79e5b..1646581dcf66 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -25,6 +25,7 @@
> #include <drm/drmP.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "soc15_common.h"
> #include "smu_v11_0.h"
> #include "smu_v12_0.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 141e48cd1c5d..a5e86375fa76 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -25,6 +25,7 @@
> #include <linux/firmware.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "atomfirmware.h"
> #include "amdgpu_atomfirmware.h"
> #include "smu_v11_0.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 3e3464fa2ff5..d01e40184fe0 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -555,92 +555,13 @@ struct smu_funcs
> int (*override_pcie_parameters)(struct smu_context *smu); };
>
> -#define smu_init_microcode(smu) \
> - ((smu)->funcs->init_microcode ? (smu)->funcs-
> >init_microcode((smu)) : 0)
> -#define smu_init_smc_tables(smu) \
> - ((smu)->funcs->init_smc_tables ? (smu)->funcs-
> >init_smc_tables((smu)) : 0)
> -#define smu_fini_smc_tables(smu) \
> - ((smu)->funcs->fini_smc_tables ? (smu)->funcs-
> >fini_smc_tables((smu)) : 0)
> -#define smu_init_power(smu) \
> - ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
> -#define smu_fini_power(smu) \
> - ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
> int smu_load_microcode(struct smu_context *smu);
>
> int smu_check_fw_status(struct smu_context *smu);
>
> -#define smu_setup_pptable(smu) \
> - ((smu)->funcs->setup_pptable ? (smu)->funcs-
> >setup_pptable((smu)) : 0)
> -#define smu_powergate_sdma(smu, gate) \
> - ((smu)->funcs->powergate_sdma ? (smu)->funcs-
> >powergate_sdma((smu), (gate)) : 0)
> -#define smu_powergate_vcn(smu, gate) \
> - ((smu)->funcs->powergate_vcn ? (smu)->funcs-
> >powergate_vcn((smu), (gate)) : 0)
> int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); -#define
> smu_get_vbios_bootup_values(smu) \
> - ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs-
> >get_vbios_bootup_values((smu)) : 0)
> -#define smu_get_clk_info_from_vbios(smu) \
> - ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs-
> >get_clk_info_from_vbios((smu)) : 0)
> -#define smu_check_pptable(smu) \
> - ((smu)->funcs->check_pptable ? (smu)->funcs-
> >check_pptable((smu)) : 0)
> -#define smu_parse_pptable(smu) \
> - ((smu)->funcs->parse_pptable ? (smu)->funcs-
> >parse_pptable((smu)) : 0)
> -#define smu_populate_smc_tables(smu) \
> - ((smu)->funcs->populate_smc_tables ? (smu)->funcs-
> >populate_smc_tables((smu)) : 0)
> -#define smu_check_fw_version(smu) \
> - ((smu)->funcs->check_fw_version ? (smu)->funcs-
> >check_fw_version((smu)) : 0)
> -#define smu_write_pptable(smu) \
> - ((smu)->funcs->write_pptable ? (smu)->funcs-
> >write_pptable((smu)) : 0)
> -#define smu_set_min_dcef_deep_sleep(smu) \
> - ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs-
> >set_min_dcef_deep_sleep((smu)) : 0)
> -#define smu_set_tool_table_location(smu) \
> - ((smu)->funcs->set_tool_table_location ? (smu)->funcs-
> >set_tool_table_location((smu)) : 0)
> -#define smu_notify_memory_pool_location(smu) \
> - ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs-
> >notify_memory_pool_location((smu)) : 0)
> -#define smu_gfx_off_control(smu, enable) \
> - ((smu)->funcs->gfx_off_control ? (smu)->funcs-
> >gfx_off_control((smu), (enable)) : 0)
> -
> -#define smu_write_watermarks_table(smu) \
> - ((smu)->funcs->write_watermarks_table ? (smu)->funcs-
> >write_watermarks_table((smu)) : 0)
> -#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
> - ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs-
> >set_last_dcef_min_deep_sleep_clk((smu)) : 0)
> -#define smu_system_features_control(smu, en) \
> - ((smu)->funcs->system_features_control ? (smu)->funcs-
> >system_features_control((smu), (en)) : 0)
> -#define smu_init_max_sustainable_clocks(smu) \
> - ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs-
> >init_max_sustainable_clocks((smu)) : 0)
> -#define smu_set_default_od_settings(smu, initialize) \
> - ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs-
> >set_default_od_settings((smu), (initialize)) : 0)
> -int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
>
> -#define smu_send_smc_msg(smu, msg) \
> - ((smu)->funcs->send_smc_msg? (smu)->funcs-
> >send_smc_msg((smu), (msg)) : 0)
> -#define smu_send_smc_msg_with_param(smu, msg, param) \
> - ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs-
> >send_smc_msg_with_param((smu), (msg), (param)) : 0)
> -#define smu_read_smc_arg(smu, arg) \
> - ((smu)->funcs->read_smc_arg? (smu)->funcs-
> >read_smc_arg((smu), (arg)) : 0)
> -#define smu_alloc_dpm_context(smu) \
> - ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs-
> >alloc_dpm_context((smu)) : 0)
> -#define smu_init_display_count(smu, count) \
> - ((smu)->funcs->init_display_count ? (smu)->funcs-
> >init_display_count((smu), (count)) : 0)
> -#define smu_feature_set_allowed_mask(smu) \
> - ((smu)->funcs->set_allowed_mask? (smu)->funcs-
> >set_allowed_mask((smu)) : 0)
> -#define smu_feature_get_enabled_mask(smu, mask, num) \
> - ((smu)->funcs->get_enabled_mask? (smu)->funcs-
> >get_enabled_mask((smu), (mask), (num)) : 0)
> -#define smu_is_dpm_running(smu) \
> - ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs-
> >is_dpm_running((smu)) : 0)
> -#define smu_notify_display_change(smu) \
> - ((smu)->funcs->notify_display_change? (smu)->funcs-
> >notify_display_change((smu)) : 0)
> -#define smu_store_powerplay_table(smu) \
> - ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs-
> >store_powerplay_table((smu)) : 0)
> -#define smu_check_powerplay_table(smu) \
> - ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs-
> >check_powerplay_table((smu)) : 0)
> -#define smu_append_powerplay_table(smu) \
> - ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs-
> >append_powerplay_table((smu)) : 0)
> -#define smu_set_default_dpm_table(smu) \
> - ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs-
> >set_default_dpm_table((smu)) : 0)
> -#define smu_populate_umd_state_clk(smu) \
> - ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs-
> >populate_umd_state_clk((smu)) : 0)
> -#define smu_set_default_od8_settings(smu) \
> - ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs-
> >set_default_od8_settings((smu)) : 0)
> +int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
>
> int smu_get_power_limit(struct smu_context *smu,
> uint32_t *limit,
> @@ -648,8 +569,6 @@ int smu_get_power_limit(struct smu_context *smu,
> bool lock_needed);
>
> int smu_set_power_limit(struct smu_context *smu, uint32_t limit); -#define
> smu_get_current_clk_freq(smu, clk_id, value) \
> - ((smu)->funcs->get_current_clk_freq? (smu)->funcs-
> >get_current_clk_freq((smu), (clk_id), (value)) : 0)
> int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type
> clk_type, char *buf); int smu_get_od_percentage(struct smu_context
> *smu, enum smu_clk_type type); int smu_set_od_percentage(struct
> smu_context *smu, enum smu_clk_type type, uint32_t value); @@ -657,68
> +576,24 @@ int smu_set_od_percentage(struct smu_context *smu, enum
> smu_clk_type type, uint3 int smu_od_edit_dpm_table(struct smu_context
> *smu,
> enum PP_OD_DPM_TABLE_COMMAND type,
> long *input, uint32_t size);
> -#define smu_tables_init(smu, tab) \
> - ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs-
> >tables_init((smu), (tab)) : 0)
> -#define smu_set_thermal_fan_table(smu) \
> - ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs-
> >set_thermal_fan_table((smu)) : 0)
> -#define smu_start_thermal_control(smu) \
> - ((smu)->funcs->start_thermal_control? (smu)->funcs-
> >start_thermal_control((smu)) : 0)
> -#define smu_stop_thermal_control(smu) \
> - ((smu)->funcs->stop_thermal_control? (smu)->funcs-
> >stop_thermal_control((smu)) : 0)
>
> int smu_read_sensor(struct smu_context *smu,
> enum amd_pp_sensors sensor,
> void *data, uint32_t *size);
> -#define smu_smc_read_sensor(smu, sensor, data, size) \
> - ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu),
> (sensor), (data), (size)) : -EINVAL)
> int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
>
> int smu_set_power_profile_mode(struct smu_context *smu,
> long *param,
> uint32_t param_size,
> bool lock_needed);
> -#define smu_pre_display_config_changed(smu) \
> - ((smu)->ppt_funcs->pre_display_config_changed ? (smu)-
> >ppt_funcs->pre_display_config_changed((smu)) : 0)
> -#define smu_display_config_changed(smu) \
> - ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs-
> >display_config_changed((smu)) : 0)
> -#define smu_apply_clocks_adjust_rules(smu) \
> - ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs-
> >apply_clocks_adjust_rules((smu)) : 0)
> -#define smu_notify_smc_dispaly_config(smu) \
> - ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs-
> >notify_smc_dispaly_config((smu)) : 0)
> -#define smu_force_dpm_limit_value(smu, highest) \
> - ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs-
> >force_dpm_limit_value((smu), (highest)) : 0)
> -#define smu_unforce_dpm_levels(smu) \
> - ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs-
> >unforce_dpm_levels((smu)) : 0)
> -#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask,
> soc_mask) \
> - ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs-
> >get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask),
> (soc_mask)) : 0)
> -#define smu_set_cpu_power_state(smu) \
> - ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs-
> >set_cpu_power_state((smu)) : 0)
> int smu_get_fan_control_mode(struct smu_context *smu); int
> smu_set_fan_control_mode(struct smu_context *smu, int value); int
> smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
> int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t
> speed); int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t
> *speed);
>
> -#define smu_msg_get_index(smu, msg) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index?
> (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -
> EINVAL)
> -#define smu_clk_get_index(smu, msg) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index?
> (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
> -#define smu_feature_get_index(smu, msg) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index?
> (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -
> EINVAL)
> -#define smu_table_get_index(smu, tab) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index?
> (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -
> EINVAL)
> -#define smu_power_get_index(smu, src) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index?
> (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -
> EINVAL)
> -#define smu_workload_get_type(smu, profile) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type?
> (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -
> EINVAL)
> -#define smu_run_btc(smu) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)-
> >ppt_funcs->run_btc((smu)) : 0) : 0)
> -#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
> - ((smu)->ppt_funcs? ((smu)->ppt_funcs-
> >get_allowed_feature_mask? (smu)->ppt_funcs-
> >get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
> int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk); int
> smu_set_active_display_count(struct smu_context *smu, uint32_t count); -
> #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
> - ((smu)->funcs->store_cc6_data ? (smu)->funcs-
> >store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
>
> int smu_get_clock_by_type(struct smu_context *smu,
> enum amd_pp_clock_type type,
> @@ -738,37 +613,15 @@ int smu_get_clock_by_type_with_voltage(struct
> smu_context *smu, int smu_display_clock_voltage_request(struct
> smu_context *smu,
> struct pp_display_clock_request
> *clock_req); int smu_display_disable_memory_clock_switch(struct
> smu_context *smu, bool disable_memory_clock_switch); -#define
> smu_get_dal_power_level(smu, clocks) \
> - ((smu)->funcs->get_dal_power_level ? (smu)->funcs-
> >get_dal_power_level((smu), (clocks)) : 0)
> -#define smu_get_perf_level(smu, designation, level) \
> - ((smu)->funcs->get_perf_level ? (smu)->funcs-
> >get_perf_level((smu), (designation), (level)) : 0)
> -#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
> - ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs-
> >get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
> int smu_notify_smu_enable_pwe(struct smu_context *smu);
>
> int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
> struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); -#define
> smu_dpm_set_uvd_enable(smu, enable) \
> - ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs-
> >dpm_set_uvd_enable((smu), (enable)) : 0)
> -#define smu_dpm_set_vce_enable(smu, enable) \
> - ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs-
> >dpm_set_vce_enable((smu), (enable)) : 0)
>
> int smu_set_xgmi_pstate(struct smu_context *smu,
> uint32_t pstate);
> -#define smu_set_watermarks_table(smu, tab, clock_ranges) \
> - ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs-
> >set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
> -#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> - ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)-
> >ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
> -#define smu_thermal_temperature_range_update(smu, range, rw) \
> - ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)-
> >ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
> -#define smu_get_thermal_temperature_range(smu, range) \
> - ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)-
> >ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
> -#define smu_register_irq_handler(smu) \
> - ((smu)->funcs->register_irq_handler ? (smu)->funcs-
> >register_irq_handler(smu) : 0)
>
> int smu_set_azalia_d3_pme(struct smu_context *smu); -#define
> smu_get_dpm_ultimate_freq(smu, param, min, max) \
> - ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs-
> >get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
>
> bool smu_baco_is_support(struct smu_context *smu);
>
> @@ -777,21 +630,6 @@ int smu_baco_get_state(struct smu_context *smu,
> enum smu_baco_state *state); int smu_baco_reset(struct smu_context
> *smu);
>
> int smu_mode2_reset(struct smu_context *smu); -#define
> smu_asic_set_performance_level(smu, level) \
> - ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs-
> >set_performance_level((smu), (level)) : -EINVAL);
> -#define smu_dump_pptable(smu) \
> - ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs-
> >dump_pptable((smu)) : 0)
> -#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
> - ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)-
> >ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -
> EINVAL)
> -
> -#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
> - ((smu)->funcs->set_soft_freq_limited_range ? (smu)-
> >funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -
> EINVAL)
> -
> -#define smu_override_pcie_parameters(smu) \
> - ((smu)->funcs->override_pcie_parameters ? (smu)->funcs-
> >override_pcie_parameters((smu)) : 0)
> -
> -#define smu_update_pcie_parameters(smu, pcie_gen_cap,
> pcie_width_cap) \
> - ((smu)->ppt_funcs->update_pcie_parameters ? (smu)-
> >ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap),
> (pcie_width_cap)) : 0)
>
> extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t
> table,
> uint16_t *size, uint8_t *frev, uint8_t *crev,
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index ead40b2840f9..54d5c91dda23 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -25,6 +25,7 @@
> #include <linux/firmware.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "atomfirmware.h"
> #include "amdgpu_atomfirmware.h"
> #include "smu_v11_0.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 6036f682e6f9..5e37a01df4a1 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -23,6 +23,7 @@
>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "soc15_common.h"
> #include "smu_v12_0_ppsmc.h"
> #include "smu12_driver_if.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> new file mode 100644
> index 000000000000..0c1673a822c0
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> +included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> +SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> +DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> +OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE
> +OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __SMU_INTERNAL_H__
> +#define __SMU_INTERNAL_H__
> +
> +#include "amdgpu_smu.h"
> +
> +#define smu_init_microcode(smu) \
> + ((smu)->funcs->init_microcode ? (smu)->funcs-
> >init_microcode((smu)) :
> +0) #define smu_init_smc_tables(smu) \
> + ((smu)->funcs->init_smc_tables ? (smu)->funcs-
> >init_smc_tables((smu))
> +: 0) #define smu_fini_smc_tables(smu) \
> + ((smu)->funcs->fini_smc_tables ? (smu)->funcs-
> >fini_smc_tables((smu))
> +: 0) #define smu_init_power(smu) \
> + ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
> +#define smu_fini_power(smu) \
> + ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
> +
> +#define smu_setup_pptable(smu) \
> + ((smu)->funcs->setup_pptable ? (smu)->funcs-
> >setup_pptable((smu)) : 0)
> +#define smu_powergate_sdma(smu, gate) \
> + ((smu)->funcs->powergate_sdma ? (smu)->funcs-
> >powergate_sdma((smu),
> +(gate)) : 0) #define smu_powergate_vcn(smu, gate) \
> + ((smu)->funcs->powergate_vcn ? (smu)->funcs-
> >powergate_vcn((smu),
> +(gate)) : 0)
> +
> +#define smu_get_vbios_bootup_values(smu) \
> + ((smu)->funcs->get_vbios_bootup_values ?
> +(smu)->funcs->get_vbios_bootup_values((smu)) : 0) #define
> smu_get_clk_info_from_vbios(smu) \
> + ((smu)->funcs->get_clk_info_from_vbios ?
> +(smu)->funcs->get_clk_info_from_vbios((smu)) : 0) #define
> smu_check_pptable(smu) \
> + ((smu)->funcs->check_pptable ? (smu)->funcs-
> >check_pptable((smu)) : 0)
> +#define smu_parse_pptable(smu) \
> + ((smu)->funcs->parse_pptable ? (smu)->funcs-
> >parse_pptable((smu)) : 0)
> +#define smu_populate_smc_tables(smu) \
> + ((smu)->funcs->populate_smc_tables ?
> +(smu)->funcs->populate_smc_tables((smu)) : 0) #define
> smu_check_fw_version(smu) \
> + ((smu)->funcs->check_fw_version ?
> +(smu)->funcs->check_fw_version((smu)) : 0) #define
> smu_write_pptable(smu) \
> + ((smu)->funcs->write_pptable ? (smu)->funcs-
> >write_pptable((smu)) : 0)
> +#define smu_set_min_dcef_deep_sleep(smu) \
> + ((smu)->funcs->set_min_dcef_deep_sleep ?
> +(smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0) #define
> smu_set_tool_table_location(smu) \
> + ((smu)->funcs->set_tool_table_location ?
> +(smu)->funcs->set_tool_table_location((smu)) : 0) #define
> smu_notify_memory_pool_location(smu) \
> + ((smu)->funcs->notify_memory_pool_location ?
> +(smu)->funcs->notify_memory_pool_location((smu)) : 0) #define
> smu_gfx_off_control(smu, enable) \
> + ((smu)->funcs->gfx_off_control ? (smu)->funcs-
> >gfx_off_control((smu),
> +(enable)) : 0)
> +
> +#define smu_write_watermarks_table(smu) \
> + ((smu)->funcs->write_watermarks_table ?
> +(smu)->funcs->write_watermarks_table((smu)) : 0) #define
> smu_set_last_dcef_min_deep_sleep_clk(smu) \
> + ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ?
> +(smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0) #define
> smu_system_features_control(smu, en) \
> + ((smu)->funcs->system_features_control ?
> +(smu)->funcs->system_features_control((smu), (en)) : 0) #define
> smu_init_max_sustainable_clocks(smu) \
> + ((smu)->funcs->init_max_sustainable_clocks ?
> +(smu)->funcs->init_max_sustainable_clocks((smu)) : 0) #define
> smu_set_default_od_settings(smu, initialize) \
> + ((smu)->ppt_funcs->set_default_od_settings ?
> +(smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
> +
> +#define smu_send_smc_msg(smu, msg) \
> + ((smu)->funcs->send_smc_msg? (smu)->funcs-
> >send_smc_msg((smu), (msg))
> +: 0) #define smu_send_smc_msg_with_param(smu, msg, param) \
> + ((smu)->funcs->send_smc_msg_with_param?
> +(smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
> #define smu_read_smc_arg(smu, arg) \
> + ((smu)->funcs->read_smc_arg? (smu)->funcs-
> >read_smc_arg((smu), (arg))
> +: 0) #define smu_alloc_dpm_context(smu) \
> + ((smu)->ppt_funcs->alloc_dpm_context ?
> +(smu)->ppt_funcs->alloc_dpm_context((smu)) : 0) #define
> smu_init_display_count(smu, count) \
> + ((smu)->funcs->init_display_count ?
> +(smu)->funcs->init_display_count((smu), (count)) : 0) #define
> smu_feature_set_allowed_mask(smu) \
> + ((smu)->funcs->set_allowed_mask? (smu)->funcs-
> >set_allowed_mask((smu))
> +: 0) #define smu_feature_get_enabled_mask(smu, mask, num) \
> + ((smu)->funcs->get_enabled_mask? (smu)->funcs-
> >get_enabled_mask((smu),
> +(mask), (num)) : 0) #define smu_is_dpm_running(smu) \
> + ((smu)->ppt_funcs->is_dpm_running ?
> +(smu)->ppt_funcs->is_dpm_running((smu)) : 0) #define
> smu_notify_display_change(smu) \
> + ((smu)->funcs->notify_display_change?
> +(smu)->funcs->notify_display_change((smu)) : 0) #define
> smu_store_powerplay_table(smu) \
> + ((smu)->ppt_funcs->store_powerplay_table ?
> +(smu)->ppt_funcs->store_powerplay_table((smu)) : 0) #define
> smu_check_powerplay_table(smu) \
> + ((smu)->ppt_funcs->check_powerplay_table ?
> +(smu)->ppt_funcs->check_powerplay_table((smu)) : 0) #define
> smu_append_powerplay_table(smu) \
> + ((smu)->ppt_funcs->append_powerplay_table ?
> +(smu)->ppt_funcs->append_powerplay_table((smu)) : 0) #define
> smu_set_default_dpm_table(smu) \
> + ((smu)->ppt_funcs->set_default_dpm_table ?
> +(smu)->ppt_funcs->set_default_dpm_table((smu)) : 0) #define
> smu_populate_umd_state_clk(smu) \
> + ((smu)->ppt_funcs->populate_umd_state_clk ?
> +(smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0) #define
> smu_set_default_od8_settings(smu) \
> + ((smu)->ppt_funcs->set_default_od8_settings ?
> +(smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
> +
> +#define smu_get_current_clk_freq(smu, clk_id, value) \
> + ((smu)->funcs->get_current_clk_freq?
> +(smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
> +
> +#define smu_tables_init(smu, tab) \
> + ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs-
> >tables_init((smu),
> +(tab)) : 0) #define smu_set_thermal_fan_table(smu) \
> + ((smu)->ppt_funcs->set_thermal_fan_table ?
> +(smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0) #define
> smu_start_thermal_control(smu) \
> + ((smu)->funcs->start_thermal_control?
> +(smu)->funcs->start_thermal_control((smu)) : 0) #define
> smu_stop_thermal_control(smu) \
> + ((smu)->funcs->stop_thermal_control?
> +(smu)->funcs->stop_thermal_control((smu)) : 0)
> +
> +#define smu_smc_read_sensor(smu, sensor, data, size) \
> + ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu),
> (sensor),
> +(data), (size)) : -EINVAL)
> +
> +#define smu_pre_display_config_changed(smu) \
> + ((smu)->ppt_funcs->pre_display_config_changed ?
> +(smu)->ppt_funcs->pre_display_config_changed((smu)) : 0) #define
> smu_display_config_changed(smu) \
> + ((smu)->ppt_funcs->display_config_changed ?
> +(smu)->ppt_funcs->display_config_changed((smu)) : 0) #define
> smu_apply_clocks_adjust_rules(smu) \
> + ((smu)->ppt_funcs->apply_clocks_adjust_rules ?
> +(smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0) #define
> smu_notify_smc_dispaly_config(smu) \
> + ((smu)->ppt_funcs->notify_smc_dispaly_config ?
> +(smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0) #define
> smu_force_dpm_limit_value(smu, highest) \
> + ((smu)->ppt_funcs->force_dpm_limit_value ?
> +(smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0) #define
> smu_unforce_dpm_levels(smu) \
> + ((smu)->ppt_funcs->unforce_dpm_levels ?
> +(smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0) #define
> smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
> + ((smu)->ppt_funcs->get_profiling_clk_mask ?
> +(smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask),
> (mclk_mask), (soc_mask)) : 0) #define smu_set_cpu_power_state(smu) \
> + ((smu)->ppt_funcs->set_cpu_power_state ?
> +(smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
> +
> +#define smu_msg_get_index(smu, msg) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index?
> +(smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -
> EINVAL) #define smu_clk_get_index(smu, msg) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index?
> +(smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
> #define smu_feature_get_index(smu, msg) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index?
> +(smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -
> EINVAL) #define smu_table_get_index(smu, tab) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index?
> +(smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -
> EINVAL) #define smu_power_get_index(smu, src) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index?
> +(smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -
> EINVAL) #define smu_workload_get_type(smu, profile) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type?
> +(smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -
> EINVAL) #define smu_run_btc(smu) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc?
> +(smu)->ppt_funcs->run_btc((smu)) : 0) : 0) #define
> smu_get_allowed_feature_mask(smu, feature_mask, num) \
> + ((smu)->ppt_funcs? ((smu)->ppt_funcs-
> >get_allowed_feature_mask?
> +(smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask),
> +(num)) : 0) : 0)
> +
> +
> +#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
> + ((smu)->funcs->store_cc6_data ? (smu)->funcs-
> >store_cc6_data((smu),
> +(st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
> +
> +#define smu_get_dal_power_level(smu, clocks) \
> + ((smu)->funcs->get_dal_power_level ?
> +(smu)->funcs->get_dal_power_level((smu), (clocks)) : 0) #define
> smu_get_perf_level(smu, designation, level) \
> + ((smu)->funcs->get_perf_level ? (smu)->funcs-
> >get_perf_level((smu),
> +(designation), (level)) : 0) #define
> smu_get_current_shallow_sleep_clocks(smu, clocks) \
> + ((smu)->funcs->get_current_shallow_sleep_clocks ?
> +(smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
> +
> +#define smu_dpm_set_uvd_enable(smu, enable) \
> + ((smu)->ppt_funcs->dpm_set_uvd_enable ?
> +(smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0) #define
> smu_dpm_set_vce_enable(smu, enable) \
> + ((smu)->ppt_funcs->dpm_set_vce_enable ?
> +(smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
> +
> +#define smu_set_watermarks_table(smu, tab, clock_ranges) \
> + ((smu)->ppt_funcs->set_watermarks_table ?
> +(smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) :
> 0) #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> + ((smu)->ppt_funcs->get_current_clk_freq_by_table ?
> +(smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type),
> (value)) : 0) #define smu_thermal_temperature_range_update(smu, range,
> rw) \
> + ((smu)->ppt_funcs->thermal_temperature_range_update?
> +(smu)->ppt_funcs->thermal_temperature_range_update((smu), (range),
> (rw)) : 0) #define smu_get_thermal_temperature_range(smu, range) \
> + ((smu)->ppt_funcs->get_thermal_temperature_range?
> +(smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
> #define smu_register_irq_handler(smu) \
> + ((smu)->funcs->register_irq_handler ?
> +(smu)->funcs->register_irq_handler(smu) : 0)
> +
> +#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
> + ((smu)->funcs->get_dpm_ultimate_freq ?
> +(smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
> +
> +#define smu_asic_set_performance_level(smu, level) \
> + ((smu)->ppt_funcs->set_performance_level?
> +(smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
> #define smu_dump_pptable(smu) \
> + ((smu)->ppt_funcs->dump_pptable ?
> +(smu)->ppt_funcs->dump_pptable((smu)) : 0) #define
> smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
> + ((smu)->ppt_funcs->get_dpm_clk_limited ?
> +(smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level),
> +(freq)) : -EINVAL)
> +
> +#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
> + ((smu)->funcs->set_soft_freq_limited_range ?
> +(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min),
> +(max)) : -EINVAL)
> +
> +#define smu_override_pcie_parameters(smu) \
> + ((smu)->funcs->override_pcie_parameters ?
> +(smu)->funcs->override_pcie_parameters((smu)) : 0)
> +
> +#define smu_update_pcie_parameters(smu, pcie_gen_cap,
> pcie_width_cap) \
> + ((smu)->ppt_funcs->update_pcie_parameters ?
> +(smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap),
> +(pcie_width_cap)) : 0)
> +
> +#endif
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index caf8a3728541..9ab319912748 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -24,6 +24,7 @@
> #include <linux/firmware.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "atomfirmware.h"
> #include "amdgpu_atomfirmware.h"
> #include "smu_v11_0.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index 6bf942d3ceca..ea67380cd9f0 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -24,6 +24,7 @@
> #include <linux/firmware.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "atomfirmware.h"
> #include "amdgpu_atomfirmware.h"
> #include "smu_v12_0.h"
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c249df9256c7..4039efcdcb1f 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -25,6 +25,7 @@
> #include <linux/firmware.h>
> #include "amdgpu.h"
> #include "amdgpu_smu.h"
> +#include "smu_internal.h"
> #include "atomfirmware.h"
> #include "amdgpu_atomfirmware.h"
> #include "smu_v11_0.h"
> --
> 2.23.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2
[not found] ` <20191018145651.10987-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-10-19 8:00 ` Xu, Feifei
0 siblings, 0 replies; 7+ messages in thread
From: Xu, Feifei @ 2019-10-19 8:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Grodzovsky, Andrey, Quan, Evan
Acked-by: Feifei Xu <Feifei.Xu@amd.com>
Thanks,
Feifei
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Quan, Evan
Sent: Friday, October 18, 2019 10:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2
This is a quick and low risk fix. Those APIs which
are exposed to other IPs or to support sysfs/hwmon
interfaces or DAL will have lock protection. Meanwhile
no lock protection is enforced for swSMU internal used
APIs. Future optimization is needed.
V2: strip the lock protection for all swSMU internal APIs
Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 696 ++++++++++++++++--
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 -
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 163 ++--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 15 +-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 14 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 +-
12 files changed, 777 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 263265245e19..28d32725285b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
@@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 1c5c0fd76dbf..2cfb677272af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_get_current_power_state(adev) \
((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
-#define amdgpu_smu_get_current_power_state(adev) \
- ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
-
-#define amdgpu_smu_set_power_state(adev) \
- ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
-
#define amdgpu_dpm_get_pp_num_states(adev, data) \
((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c50d5f1e75e5..36f36b35000d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -211,7 +211,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
if (is_support_sw_smu(adev)) {
if (adev->smu.ppt_funcs->get_current_power_state)
- pm = amdgpu_smu_get_current_power_state(adev);
+ pm = smu_get_current_power_state(&adev->smu);
else
pm = adev->pm.dpm.user_state;
} else if (adev->powerplay.pp_funcs->get_current_power_state) {
@@ -957,7 +957,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -1004,7 +1004,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -1044,7 +1044,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
@@ -1084,7 +1084,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
@@ -1124,7 +1124,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
@@ -1164,7 +1164,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -1356,7 +1356,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
}
parameter[parameter_size] = profile_mode;
if (is_support_sw_smu(adev))
- ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
+ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
else if (adev->powerplay.pp_funcs->set_power_profile_mode)
ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
if (!ret)
@@ -2065,7 +2065,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, true);
+ smu_get_power_limit(&adev->smu, &limit, true, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
@@ -2083,7 +2083,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, false);
+ smu_get_power_limit(&adev->smu, &limit, false, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
@@ -3064,7 +3064,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
smu_handle_task(&adev->smu,
smu_dpm->dpm_level,
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ true);
} else {
if (adev->powerplay.pp_funcs->dispatch_tasks) {
if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 1352019648c0..ee9915d61cf1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -876,7 +876,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
if (!smu->funcs->get_max_sustainable_clocks_by_dc)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
+ if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
return PP_SMU_RESULT_OK;
return PP_SMU_RESULT_FAIL;
@@ -895,7 +895,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
if (!smu->ppt_funcs->get_uclk_dpm_states)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
+ if (!smu_get_uclk_dpm_states(smu,
clock_values_in_khz, num_states))
return PP_SMU_RESULT_OK;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 26cacc899dfe..0841d8c79e5b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
uint32_t sort_feature[SMU_FEATURE_COUNT];
uint64_t hw_feature_count = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
goto failed;
@@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
}
failed:
+ mutex_unlock(&smu->mutex);
+
return size;
}
@@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
uint64_t feature_2_disabled = 0;
uint64_t feature_enables = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
- return ret;
+ goto out;
feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
@@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
if (feature_2_enabled) {
ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
if (ret)
- return ret;
+ goto out;
}
if (feature_2_disabled) {
ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
if (ret)
- return ret;
+ goto out;
}
+out:
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
}
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max)
+ uint32_t *min, uint32_t *max, bool lock_needed)
{
uint32_t clock_limit;
int ret = 0;
@@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (!min && !max)
return -EINVAL;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
switch (clk_type) {
case SMU_MCLK:
@@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
*min = clock_limit / 100;
if (max)
*max = clock_limit / 100;
-
- return 0;
+ } else {
+ /*
+ * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
+ * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
+ */
+ ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
}
- /*
- * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
- * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
- */
- ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
{
int ret = 0;
+ mutex_lock(&smu->mutex);
+
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
ret = smu_dpm_set_uvd_enable(smu, gate);
@@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
break;
}
- return ret;
-}
+ mutex_unlock(&smu->mutex);
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
-{
- /* not support power state */
- return POWER_STATE_TYPE_DEFAULT;
+ return ret;
}
int smu_get_power_num_states(struct smu_context *smu,
@@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
int smu_sys_get_pp_table(struct smu_context *smu, void **table)
{
struct smu_table_context *smu_table = &smu->smu_table;
+ uint32_t powerplay_table_size;
if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
if (smu_table->hardcode_pptable)
*table = smu_table->hardcode_pptable;
else
*table = smu_table->power_play_table;
- return smu_table->power_play_table_size;
+ powerplay_table_size = smu_table->power_play_table_size;
+
+ mutex_unlock(&smu->mutex);
+
+ return powerplay_table_size;
}
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
@@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
memcpy(smu_table->hardcode_pptable, buf, size);
smu_table->power_play_table = smu_table->hardcode_pptable;
smu_table->power_play_table_size = size;
- mutex_unlock(&smu->mutex);
ret = smu_reset(smu);
if (ret)
pr_info("smu reset failed, ret = %d\n", ret);
- return ret;
-
failed:
mutex_unlock(&smu->mutex);
return ret;
@@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
if (!smu->pm_enabled)
return 0;
- mutex_lock(&smu->mutex);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
- AMD_PP_TASK_COMPLETE_INIT);
- mutex_unlock(&smu->mutex);
+ AMD_PP_TASK_COMPLETE_INIT,
+ false);
return 0;
}
@@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
if (ret)
return ret;
- ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
+ ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
if (ret)
return ret;
}
@@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct smu_context *smu)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->asic_type < CHIP_NAVI10) {
- ret = smu_load_microcode(smu);
- if (ret)
- return ret;
+ if (smu->funcs->load_microcode) {
+ ret = smu->funcs->load_microcode(smu);
+ if (ret)
+ return ret;
+ }
}
}
- ret = smu_check_fw_status(smu);
- if (ret)
- pr_err("SMC is not ready\n");
+ if (smu->funcs->check_fw_status) {
+ ret = smu->funcs->check_fw_status(smu);
+ if (ret)
+ pr_err("SMC is not ready\n");
+ }
return ret;
}
@@ -1334,8 +1354,6 @@ static int smu_resume(void *handle)
pr_info("SMU is resuming...\n");
- mutex_lock(&smu->mutex);
-
ret = smu_start_smc_engine(smu);
if (ret) {
pr_err("SMU is not ready yet!\n");
@@ -1350,13 +1368,11 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
- mutex_unlock(&smu->mutex);
-
pr_info("SMU is resumed successfully!\n");
return 0;
+
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1374,8 +1390,9 @@ int smu_display_configuration_change(struct smu_context *smu,
mutex_lock(&smu->mutex);
- smu_set_deep_sleep_dcefclk(smu,
- display_config->min_dcef_deep_sleep_set_clk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ smu->funcs->set_deep_sleep_dcefclk(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
for (index = 0; index < display_config->num_path_including_non_display; index++) {
if (display_config->displays[index].controller_id != 0)
@@ -1553,9 +1570,9 @@ static int smu_default_set_performance_level(struct smu_context *smu, enum amd_d
&soc_mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
+ smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
+ smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -1619,7 +1636,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
workload = smu->workload_setting[index];
if (smu->power_profile_mode != workload)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
}
return ret;
@@ -1627,18 +1644,22 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id)
+ enum amd_pp_task task_id,
+ bool lock_needed)
{
int ret = 0;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
ret = smu_pre_display_config_changed(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_set_cpu_power_state(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_adjust_power_state_dynamic(smu, level, false);
break;
case AMD_PP_TASK_COMPLETE_INIT:
@@ -1649,6 +1670,10 @@ int smu_handle_task(struct smu_context *smu,
break;
}
+out:
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1681,7 +1706,7 @@ int smu_switch_power_profile(struct smu_context *smu,
}
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
mutex_unlock(&smu->mutex);
@@ -1711,12 +1736,19 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
ret = smu_enable_umd_pstate(smu, &level);
- if (ret)
+ if (ret) {
+ mutex_unlock(&smu->mutex);
return ret;
+ }
ret = smu_handle_task(smu, level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
+
+ mutex_unlock(&smu->mutex);
return ret;
}
@@ -1734,7 +1766,8 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask)
+ uint32_t mask,
+ bool lock_needed)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -1744,9 +1777,15 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1764,6 +1803,8 @@ int smu_set_mp1_state(struct smu_context *smu,
if (!smu->pm_enabled)
return 0;
+ mutex_lock(&smu->mutex);
+
switch (mp1_state) {
case PP_MP1_STATE_SHUTDOWN:
msg = SMU_MSG_PrepareMp1ForShutdown;
@@ -1776,17 +1817,22 @@ int smu_set_mp1_state(struct smu_context *smu,
break;
case PP_MP1_STATE_NONE:
default:
+ mutex_unlock(&smu->mutex);
return 0;
}
/* some asics may not support those messages */
- if (smu_msg_get_index(smu, msg) < 0)
+ if (smu_msg_get_index(smu, msg) < 0) {
+ mutex_unlock(&smu->mutex);
return 0;
+ }
ret = smu_send_smc_msg(smu, msg);
if (ret)
pr_err("[PrepareMp1] Failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1806,10 +1852,14 @@ int smu_set_df_cstate(struct smu_context *smu,
if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
return 0;
+ mutex_lock(&smu->mutex);
+
ret = smu->ppt_funcs->set_df_cstate(smu, state);
if (ret)
pr_err("[SetDfCstate] failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1849,3 +1899,549 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
.rev = 0,
.funcs = &smu_ip_funcs,
};
+
+int smu_load_microcode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->load_microcode)
+ ret = smu->funcs->load_microcode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_check_fw_status(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->check_fw_status)
+ ret = smu->funcs->check_fw_status(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_gfx_cgpg)
+ ret = smu->funcs->set_gfx_cgpg(smu, enabled);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_rpm)
+ ret = smu->funcs->set_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_limit)
+ ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_power_limit)
+ ret = smu->funcs->set_power_limit(smu, limit);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->print_clk_levels)
+ ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_od_percentage)
+ ret = smu->ppt_funcs->get_od_percentage(smu, type);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_od_percentage)
+ ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->od_edit_dpm_table)
+ ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->read_sensor)
+ ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_profile_mode)
+ ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_power_profile_mode)
+ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_get_fan_control_mode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_fan_control_mode)
+ ret = smu->funcs->get_fan_control_mode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_control_mode(struct smu_context *smu, int value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_control_mode)
+ ret = smu->funcs->set_fan_control_mode(smu, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_percent)
+ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_percent)
+ ret = smu->funcs->set_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_rpm)
+ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_active_display_count)
+ ret = smu->funcs->set_active_display_count(smu, count);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_clock_by_type)
+ ret = smu->funcs->get_clock_by_type(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_high_clocks)
+ ret = smu->funcs->get_max_high_clocks(smu, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_latency)
+ ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_voltage)
+ ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
+{
+ int ret = -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->display_disable_memory_clock_switch)
+ ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_notify_smu_enable_pwe(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->notify_smu_enable_pwe)
+ ret = smu->funcs->notify_smu_enable_pwe(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_watermarks_for_clock_ranges)
+ ret = smu->funcs->set_watermarks_for_clock_ranges(smu, clock_ranges);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_xgmi_pstate)
+ ret = smu->funcs->set_xgmi_pstate(smu, pstate);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_azalia_d3_pme(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_azalia_d3_pme)
+ ret = smu->funcs->set_azalia_d3_pme(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+bool smu_baco_is_support(struct smu_context *smu)
+{
+ bool ret = false;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_is_support)
+ ret = smu->funcs->baco_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+{
+ if (smu->funcs->baco_get_state)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+ *state = smu->funcs->baco_get_state(smu);
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
+
+int smu_baco_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_reset)
+ ret = smu->funcs->baco_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_mode2_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->mode2_reset)
+ ret = smu->funcs->mode2_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_sustainable_clocks_by_dc)
+ ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_uclk_dpm_states)
+ ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+{
+ enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_current_power_state)
+ pm_state = smu->ppt_funcs->get_current_power_state(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return pm_state;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 6731fed5458e..141e48cd1c5d 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -772,8 +772,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -892,7 +890,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index cdb845f5f23e..3e3464fa2ff5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -565,18 +565,17 @@ struct smu_funcs
((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_fini_power(smu) \
((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
-#define smu_load_microcode(smu) \
- ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
-#define smu_check_fw_status(smu) \
- ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
+int smu_load_microcode(struct smu_context *smu);
+
+int smu_check_fw_status(struct smu_context *smu);
+
#define smu_setup_pptable(smu) \
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
#define smu_powergate_sdma(smu, gate) \
((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
-#define smu_set_gfx_cgpg(smu, enabled) \
- ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
@@ -610,8 +609,8 @@ struct smu_funcs
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
-#define smu_set_fan_speed_rpm(smu, speed) \
- ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
@@ -642,20 +641,22 @@ struct smu_funcs
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_set_default_od8_settings(smu) \
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
-#define smu_get_power_limit(smu, limit, def) \
- ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
-#define smu_set_power_limit(smu, limit) \
- ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed);
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
#define smu_get_current_clk_freq(smu, clk_id, value) \
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
-#define smu_print_clk_levels(smu, clk_type, buf) \
- ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
-#define smu_get_od_percentage(smu, type) \
- ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
-#define smu_set_od_percentage(smu, type, value) \
- ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
-#define smu_od_edit_dpm_table(smu, type, input, size) \
- ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
#define smu_tables_init(smu, tab) \
((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
#define smu_set_thermal_fan_table(smu) \
@@ -664,14 +665,18 @@ struct smu_funcs
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_stop_thermal_control(smu) \
((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
-#define smu_read_sensor(smu, sensor, data, size) \
- ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
#define smu_smc_read_sensor(smu, sensor, data, size) \
((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
-#define smu_get_power_profile_mode(smu, buf) \
- ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
-#define smu_set_power_profile_mode(smu, param, param_size) \
- ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed);
#define smu_pre_display_config_changed(smu) \
((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
#define smu_display_config_changed(smu) \
@@ -688,16 +693,11 @@ struct smu_funcs
((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
#define smu_set_cpu_power_state(smu) \
((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
-#define smu_get_fan_control_mode(smu) \
- ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
-#define smu_set_fan_control_mode(smu, value) \
- ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
-#define smu_get_fan_speed_percent(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
-#define smu_set_fan_speed_percent(smu, speed) \
- ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
-#define smu_get_fan_speed_rpm(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
+int smu_get_fan_control_mode(struct smu_context *smu);
+int smu_set_fan_control_mode(struct smu_context *smu, int value);
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
@@ -715,40 +715,46 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
-#define smu_set_deep_sleep_dcefclk(smu, clk) \
- ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
-#define smu_set_active_display_count(smu, count) \
- ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
-#define smu_get_clock_by_type(smu, type, clocks) \
- ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
-#define smu_get_max_high_clocks(smu, clocks) \
- ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
-#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
-#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
-#define smu_display_clock_voltage_request(smu, clock_req) \
- ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
-#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
- ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks);
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks);
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req);
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
-#define smu_notify_smu_enable_pwe(smu) \
- ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
- ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+int smu_notify_smu_enable_pwe(struct smu_context *smu);
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
#define smu_dpm_set_uvd_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
#define smu_dpm_set_vce_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
-#define smu_set_xgmi_pstate(smu, pstate) \
- ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate);
#define smu_set_watermarks_table(smu, tab, clock_ranges) \
((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -759,22 +765,18 @@ struct smu_funcs
((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
#define smu_register_irq_handler(smu) \
((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
-#define smu_set_azalia_d3_pme(smu) \
- ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+
+int smu_set_azalia_d3_pme(struct smu_context *smu);
#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
- ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
-#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
- ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
-#define smu_baco_is_support(smu) \
- ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
-#define smu_baco_get_state(smu, state) \
- ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
-#define smu_baco_reset(smu) \
- ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
-#define smu_mode2_reset(smu) \
- ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
+
+bool smu_baco_is_support(struct smu_context *smu);
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+
+int smu_baco_reset(struct smu_context *smu);
+
+int smu_mode2_reset(struct smu_context *smu);
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
#define smu_dump_pptable(smu) \
@@ -833,7 +835,8 @@ extern int smu_get_current_clocks(struct smu_context *smu,
extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id);
+ enum amd_pp_task task_id,
+ bool lock_needed);
int smu_switch_power_profile(struct smu_context *smu,
enum PP_SMC_POWER_PROFILE type,
bool en);
@@ -843,7 +846,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *value);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max);
+ uint32_t *min, uint32_t *max, bool lock_needed);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
@@ -858,10 +861,20 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask);
+ uint32_t mask,
+ bool lock_needed);
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
int smu_set_df_cstate(struct smu_context *smu,
enum pp_df_cstate state);
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks);
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states);
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b88aae9bb242..ead40b2840f9 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
int ret = 0;
uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
if (ret)
return ret;
smu->pstate_sclk = min_sclk_freq * 100;
- ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
if (ret)
return ret;
@@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
return ret;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
if (ret)
return ret;
ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
@@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
- if (!smu_display_clock_voltage_request(smu, &clock_req)) {
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
+ if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 6aedffd739db..6036f682e6f9 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
case SMU_SCLK:
/* retirve table returned paramters unit is MHz */
cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
if (!ret) {
/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
if (cur_value == max)
@@ -251,7 +251,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -269,7 +268,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
clk_type = clk_feature_map[i].clk_type;
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -435,7 +433,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
if (ret)
return ret;
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -511,7 +509,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
if (ret)
return ret;
@@ -519,7 +517,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
if (ret)
return ret;
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b68cb8badc75..caf8a3728541 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -809,8 +809,11 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
if (!table_context)
return -EINVAL;
- return smu_set_deep_sleep_dcefclk(smu,
- table_context->boot_values.dcefclk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ return smu->funcs->set_deep_sleep_dcefclk(smu,
+ table_context->boot_values.dcefclk / 100);
+
+ return 0;
}
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
@@ -1325,9 +1328,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
return 0;
- mutex_lock(&smu->mutex);
ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
- mutex_unlock(&smu->mutex);
if(clk_select == SMU_UCLK)
smu->hard_min_uclk_req_from_dal = clk_freq;
@@ -1370,12 +1371,10 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
case CHIP_NAVI12:
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
- mutex_lock(&smu->mutex);
if (enable)
ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
else
ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
- mutex_unlock(&smu->mutex);
break;
default:
break;
@@ -1491,10 +1490,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
if (!speed)
return -EINVAL;
- mutex_lock(&(smu->mutex));
ret = smu_v11_0_auto_fan_control(smu, 0);
if (ret)
- goto set_fan_speed_rpm_failed;
+ return ret;
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
@@ -1505,8 +1503,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
-set_fan_speed_rpm_failed:
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1517,11 +1513,9 @@ static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate)
{
int ret = 0;
- mutex_lock(&(smu->mutex));
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetXgmiMode,
pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1633,9 +1627,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
int ret = 0;
- mutex_lock(&smu->mutex);
ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1767,7 +1759,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0, clk_id = 0;
uint32_t param = 0;
- mutex_lock(&smu->mutex);
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) {
ret = -EINVAL;
@@ -1794,7 +1785,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index c9691d0fb523..6bf942d3ceca 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -325,8 +325,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0;
uint32_t mclk_mask, soc_mask;
- mutex_lock(&smu->mutex);
-
if (max) {
ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
NULL,
@@ -396,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index a76ffd58404e..c249df9256c7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -635,7 +635,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -653,7 +652,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level, hard_min_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1446,8 +1441,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
dpm_table = smu_dpm->dpm_context;
- mutex_lock(&smu->mutex);
-
switch (clk_type) {
case SMU_GFXCLK:
single_dpm_table = &(dpm_table->gfx_table);
@@ -1469,7 +1462,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
ret = -EINVAL;
}
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct smu_context *smu,
int feature_enabled;
PPCLK_e clk_id;
- mutex_lock(&(smu->mutex));
-
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
@@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct smu_context *smu,
}
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
set_od_failed:
- mutex_unlock(&(smu->mutex));
-
return ret;
}
@@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
}
if (type == PP_OD_COMMIT_DPM_TABLE) {
- mutex_lock(&(smu->mutex));
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
- mutex_unlock(&(smu->mutex));
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
}
return ret;
--
2.23.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2
@ 2019-10-18 14:57 Quan, Evan
[not found] ` <20191018145651.10987-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Quan, Evan @ 2019-10-18 14:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Grodzovsky, Andrey, Quan, Evan
This is a quick and low risk fix. Those APIs which
are exposed to other IPs or to support sysfs/hwmon
interfaces or DAL will have lock protection. Meanwhile
no lock protection is enforced for swSMU internal used
APIs. Future optimization is needed.
V2: strip the lock protection for all swSMU internal APIs
Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 696 ++++++++++++++++--
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 -
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 163 ++--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 15 +-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 14 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 +-
12 files changed, 777 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 263265245e19..28d32725285b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
@@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
if (is_support_sw_smu(adev)) {
ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
low ? &clk_freq : NULL,
- !low ? &clk_freq : NULL);
+ !low ? &clk_freq : NULL,
+ true);
if (ret)
return 0;
return clk_freq * 100;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 1c5c0fd76dbf..2cfb677272af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_get_current_power_state(adev) \
((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
-#define amdgpu_smu_get_current_power_state(adev) \
- ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
-
-#define amdgpu_smu_set_power_state(adev) \
- ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
-
#define amdgpu_dpm_get_pp_num_states(adev, data) \
((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c50d5f1e75e5..36f36b35000d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -211,7 +211,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
if (is_support_sw_smu(adev)) {
if (adev->smu.ppt_funcs->get_current_power_state)
- pm = amdgpu_smu_get_current_power_state(adev);
+ pm = smu_get_current_power_state(&adev->smu);
else
pm = adev->pm.dpm.user_state;
} else if (adev->powerplay.pp_funcs->get_current_power_state) {
@@ -957,7 +957,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -1004,7 +1004,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -1044,7 +1044,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
@@ -1084,7 +1084,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
@@ -1124,7 +1124,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
@@ -1164,7 +1164,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
return ret;
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
+ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -1356,7 +1356,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
}
parameter[parameter_size] = profile_mode;
if (is_support_sw_smu(adev))
- ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
+ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
else if (adev->powerplay.pp_funcs->set_power_profile_mode)
ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
if (!ret)
@@ -2065,7 +2065,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, true);
+ smu_get_power_limit(&adev->smu, &limit, true, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
@@ -2083,7 +2083,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
uint32_t limit = 0;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, false);
+ smu_get_power_limit(&adev->smu, &limit, false, true);
return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
@@ -3064,7 +3064,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
smu_handle_task(&adev->smu,
smu_dpm->dpm_level,
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ true);
} else {
if (adev->powerplay.pp_funcs->dispatch_tasks) {
if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 1352019648c0..ee9915d61cf1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -876,7 +876,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
if (!smu->funcs->get_max_sustainable_clocks_by_dc)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
+ if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
return PP_SMU_RESULT_OK;
return PP_SMU_RESULT_FAIL;
@@ -895,7 +895,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
if (!smu->ppt_funcs->get_uclk_dpm_states)
return PP_SMU_RESULT_UNSUPPORTED;
- if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
+ if (!smu_get_uclk_dpm_states(smu,
clock_values_in_khz, num_states))
return PP_SMU_RESULT_OK;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 26cacc899dfe..0841d8c79e5b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
uint32_t sort_feature[SMU_FEATURE_COUNT];
uint64_t hw_feature_count = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
goto failed;
@@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
}
failed:
+ mutex_unlock(&smu->mutex);
+
return size;
}
@@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
uint64_t feature_2_disabled = 0;
uint64_t feature_enables = 0;
+ mutex_lock(&smu->mutex);
+
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
- return ret;
+ goto out;
feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
@@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
if (feature_2_enabled) {
ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
if (ret)
- return ret;
+ goto out;
}
if (feature_2_disabled) {
ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
if (ret)
- return ret;
+ goto out;
}
+out:
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
}
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max)
+ uint32_t *min, uint32_t *max, bool lock_needed)
{
uint32_t clock_limit;
int ret = 0;
@@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (!min && !max)
return -EINVAL;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
switch (clk_type) {
case SMU_MCLK:
@@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
*min = clock_limit / 100;
if (max)
*max = clock_limit / 100;
-
- return 0;
+ } else {
+ /*
+ * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
+ * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
+ */
+ ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
}
- /*
- * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
- * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
- */
- ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
{
int ret = 0;
+ mutex_lock(&smu->mutex);
+
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
ret = smu_dpm_set_uvd_enable(smu, gate);
@@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
break;
}
- return ret;
-}
+ mutex_unlock(&smu->mutex);
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
-{
- /* not support power state */
- return POWER_STATE_TYPE_DEFAULT;
+ return ret;
}
int smu_get_power_num_states(struct smu_context *smu,
@@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
int smu_sys_get_pp_table(struct smu_context *smu, void **table)
{
struct smu_table_context *smu_table = &smu->smu_table;
+ uint32_t powerplay_table_size;
if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
if (smu_table->hardcode_pptable)
*table = smu_table->hardcode_pptable;
else
*table = smu_table->power_play_table;
- return smu_table->power_play_table_size;
+ powerplay_table_size = smu_table->power_play_table_size;
+
+ mutex_unlock(&smu->mutex);
+
+ return powerplay_table_size;
}
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
@@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
memcpy(smu_table->hardcode_pptable, buf, size);
smu_table->power_play_table = smu_table->hardcode_pptable;
smu_table->power_play_table_size = size;
- mutex_unlock(&smu->mutex);
ret = smu_reset(smu);
if (ret)
pr_info("smu reset failed, ret = %d\n", ret);
- return ret;
-
failed:
mutex_unlock(&smu->mutex);
return ret;
@@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
if (!smu->pm_enabled)
return 0;
- mutex_lock(&smu->mutex);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
- AMD_PP_TASK_COMPLETE_INIT);
- mutex_unlock(&smu->mutex);
+ AMD_PP_TASK_COMPLETE_INIT,
+ false);
return 0;
}
@@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
if (ret)
return ret;
- ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
+ ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
if (ret)
return ret;
}
@@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct smu_context *smu)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->asic_type < CHIP_NAVI10) {
- ret = smu_load_microcode(smu);
- if (ret)
- return ret;
+ if (smu->funcs->load_microcode) {
+ ret = smu->funcs->load_microcode(smu);
+ if (ret)
+ return ret;
+ }
}
}
- ret = smu_check_fw_status(smu);
- if (ret)
- pr_err("SMC is not ready\n");
+ if (smu->funcs->check_fw_status) {
+ ret = smu->funcs->check_fw_status(smu);
+ if (ret)
+ pr_err("SMC is not ready\n");
+ }
return ret;
}
@@ -1334,8 +1354,6 @@ static int smu_resume(void *handle)
pr_info("SMU is resuming...\n");
- mutex_lock(&smu->mutex);
-
ret = smu_start_smc_engine(smu);
if (ret) {
pr_err("SMU is not ready yet!\n");
@@ -1350,13 +1368,11 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
- mutex_unlock(&smu->mutex);
-
pr_info("SMU is resumed successfully!\n");
return 0;
+
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1374,8 +1390,9 @@ int smu_display_configuration_change(struct smu_context *smu,
mutex_lock(&smu->mutex);
- smu_set_deep_sleep_dcefclk(smu,
- display_config->min_dcef_deep_sleep_set_clk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ smu->funcs->set_deep_sleep_dcefclk(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
for (index = 0; index < display_config->num_path_including_non_display; index++) {
if (display_config->displays[index].controller_id != 0)
@@ -1553,9 +1570,9 @@ static int smu_default_set_performance_level(struct smu_context *smu, enum amd_d
&soc_mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
+ smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
+ smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -1619,7 +1636,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
workload = smu->workload_setting[index];
if (smu->power_profile_mode != workload)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
}
return ret;
@@ -1627,18 +1644,22 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id)
+ enum amd_pp_task task_id,
+ bool lock_needed)
{
int ret = 0;
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
ret = smu_pre_display_config_changed(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_set_cpu_power_state(smu);
if (ret)
- return ret;
+ goto out;
ret = smu_adjust_power_state_dynamic(smu, level, false);
break;
case AMD_PP_TASK_COMPLETE_INIT:
@@ -1649,6 +1670,10 @@ int smu_handle_task(struct smu_context *smu,
break;
}
+out:
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1681,7 +1706,7 @@ int smu_switch_power_profile(struct smu_context *smu,
}
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- smu_set_power_profile_mode(smu, &workload, 0);
+ smu_set_power_profile_mode(smu, &workload, 0, false);
mutex_unlock(&smu->mutex);
@@ -1711,12 +1736,19 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
+ mutex_lock(&smu->mutex);
+
ret = smu_enable_umd_pstate(smu, &level);
- if (ret)
+ if (ret) {
+ mutex_unlock(&smu->mutex);
return ret;
+ }
ret = smu_handle_task(smu, level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
+
+ mutex_unlock(&smu->mutex);
return ret;
}
@@ -1734,7 +1766,8 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask)
+ uint32_t mask,
+ bool lock_needed)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -1744,9 +1777,15 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1764,6 +1803,8 @@ int smu_set_mp1_state(struct smu_context *smu,
if (!smu->pm_enabled)
return 0;
+ mutex_lock(&smu->mutex);
+
switch (mp1_state) {
case PP_MP1_STATE_SHUTDOWN:
msg = SMU_MSG_PrepareMp1ForShutdown;
@@ -1776,17 +1817,22 @@ int smu_set_mp1_state(struct smu_context *smu,
break;
case PP_MP1_STATE_NONE:
default:
+ mutex_unlock(&smu->mutex);
return 0;
}
/* some asics may not support those messages */
- if (smu_msg_get_index(smu, msg) < 0)
+ if (smu_msg_get_index(smu, msg) < 0) {
+ mutex_unlock(&smu->mutex);
return 0;
+ }
ret = smu_send_smc_msg(smu, msg);
if (ret)
pr_err("[PrepareMp1] Failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1806,10 +1852,14 @@ int smu_set_df_cstate(struct smu_context *smu,
if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
return 0;
+ mutex_lock(&smu->mutex);
+
ret = smu->ppt_funcs->set_df_cstate(smu, state);
if (ret)
pr_err("[SetDfCstate] failed!\n");
+ mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1849,3 +1899,549 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
.rev = 0,
.funcs = &smu_ip_funcs,
};
+
+int smu_load_microcode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->load_microcode)
+ ret = smu->funcs->load_microcode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_check_fw_status(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->check_fw_status)
+ ret = smu->funcs->check_fw_status(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_gfx_cgpg)
+ ret = smu->funcs->set_gfx_cgpg(smu, enabled);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_rpm)
+ ret = smu->funcs->set_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_limit)
+ ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_power_limit)
+ ret = smu->funcs->set_power_limit(smu, limit);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->print_clk_levels)
+ ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_od_percentage)
+ ret = smu->ppt_funcs->get_od_percentage(smu, type);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_od_percentage)
+ ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->od_edit_dpm_table)
+ ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->read_sensor)
+ ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_power_profile_mode)
+ ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed)
+{
+ int ret = 0;
+
+ if (lock_needed)
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->set_power_profile_mode)
+ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
+
+ if (lock_needed)
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_get_fan_control_mode(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_fan_control_mode)
+ ret = smu->funcs->get_fan_control_mode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_control_mode(struct smu_context *smu, int value)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_control_mode)
+ ret = smu->funcs->set_fan_control_mode(smu, value);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_percent)
+ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_fan_speed_percent)
+ ret = smu->funcs->set_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_fan_speed_rpm)
+ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_active_display_count)
+ ret = smu->funcs->set_active_display_count(smu, count);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_clock_by_type)
+ ret = smu->funcs->get_clock_by_type(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_high_clocks)
+ ret = smu->funcs->get_max_high_clocks(smu, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_latency)
+ ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_clock_by_type_with_voltage)
+ ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
+{
+ int ret = -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->display_disable_memory_clock_switch)
+ ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_notify_smu_enable_pwe(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->notify_smu_enable_pwe)
+ ret = smu->funcs->notify_smu_enable_pwe(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_watermarks_for_clock_ranges)
+ ret = smu->funcs->set_watermarks_for_clock_ranges(smu, clock_ranges);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_xgmi_pstate)
+ ret = smu->funcs->set_xgmi_pstate(smu, pstate);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_set_azalia_d3_pme(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->set_azalia_d3_pme)
+ ret = smu->funcs->set_azalia_d3_pme(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+bool smu_baco_is_support(struct smu_context *smu)
+{
+ bool ret = false;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_is_support)
+ ret = smu->funcs->baco_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+{
+ if (smu->funcs->baco_get_state)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+ *state = smu->funcs->baco_get_state(smu);
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
+
+int smu_baco_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->baco_reset)
+ ret = smu->funcs->baco_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_mode2_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->mode2_reset)
+ ret = smu->funcs->mode2_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->funcs->get_max_sustainable_clocks_by_dc)
+ ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_uclk_dpm_states)
+ ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+{
+ enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->get_current_power_state)
+ pm_state = smu->ppt_funcs->get_current_power_state(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return pm_state;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 6731fed5458e..141e48cd1c5d 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -772,8 +772,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -892,7 +890,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index cdb845f5f23e..3e3464fa2ff5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -565,18 +565,17 @@ struct smu_funcs
((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_fini_power(smu) \
((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
-#define smu_load_microcode(smu) \
- ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
-#define smu_check_fw_status(smu) \
- ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
+int smu_load_microcode(struct smu_context *smu);
+
+int smu_check_fw_status(struct smu_context *smu);
+
#define smu_setup_pptable(smu) \
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
#define smu_powergate_sdma(smu, gate) \
((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
-#define smu_set_gfx_cgpg(smu, enabled) \
- ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
+int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
@@ -610,8 +609,8 @@ struct smu_funcs
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
-#define smu_set_fan_speed_rpm(smu, speed) \
- ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
+int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
@@ -642,20 +641,22 @@ struct smu_funcs
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_set_default_od8_settings(smu) \
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
-#define smu_get_power_limit(smu, limit, def) \
- ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
-#define smu_set_power_limit(smu, limit) \
- ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
+
+int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool def,
+ bool lock_needed);
+
+int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
#define smu_get_current_clk_freq(smu, clk_id, value) \
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
-#define smu_print_clk_levels(smu, clk_type, buf) \
- ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
-#define smu_get_od_percentage(smu, type) \
- ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
-#define smu_set_od_percentage(smu, type, value) \
- ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
-#define smu_od_edit_dpm_table(smu, type, input, size) \
- ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
+int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
+int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
+
+int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
#define smu_tables_init(smu, tab) \
((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
#define smu_set_thermal_fan_table(smu) \
@@ -664,14 +665,18 @@ struct smu_funcs
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_stop_thermal_control(smu) \
((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
-#define smu_read_sensor(smu, sensor, data, size) \
- ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+
+int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
#define smu_smc_read_sensor(smu, sensor, data, size) \
((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
-#define smu_get_power_profile_mode(smu, buf) \
- ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
-#define smu_set_power_profile_mode(smu, param, param_size) \
- ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
+int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
+
+int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed);
#define smu_pre_display_config_changed(smu) \
((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
#define smu_display_config_changed(smu) \
@@ -688,16 +693,11 @@ struct smu_funcs
((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
#define smu_set_cpu_power_state(smu) \
((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
-#define smu_get_fan_control_mode(smu) \
- ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
-#define smu_set_fan_control_mode(smu, value) \
- ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
-#define smu_get_fan_speed_percent(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
-#define smu_set_fan_speed_percent(smu, speed) \
- ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
-#define smu_get_fan_speed_rpm(smu, speed) \
- ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
+int smu_get_fan_control_mode(struct smu_context *smu);
+int smu_set_fan_control_mode(struct smu_context *smu, int value);
+int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
+int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
@@ -715,40 +715,46 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
-#define smu_set_deep_sleep_dcefclk(smu, clk) \
- ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
-#define smu_set_active_display_count(smu, count) \
- ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
+int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
+int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
-#define smu_get_clock_by_type(smu, type, clocks) \
- ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
-#define smu_get_max_high_clocks(smu, clocks) \
- ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
-#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
-#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
- ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
-#define smu_display_clock_voltage_request(smu, clock_req) \
- ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
-#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
- ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
+
+int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+
+int smu_get_max_high_clocks(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks);
+
+int smu_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks);
+
+int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+
+int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req);
+int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
-#define smu_notify_smu_enable_pwe(smu) \
- ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
- ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+int smu_notify_smu_enable_pwe(struct smu_context *smu);
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
#define smu_dpm_set_uvd_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
#define smu_dpm_set_vce_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
-#define smu_set_xgmi_pstate(smu, pstate) \
- ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
+
+int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate);
#define smu_set_watermarks_table(smu, tab, clock_ranges) \
((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -759,22 +765,18 @@ struct smu_funcs
((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
#define smu_register_irq_handler(smu) \
((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
-#define smu_set_azalia_d3_pme(smu) \
- ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+
+int smu_set_azalia_d3_pme(struct smu_context *smu);
#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
- ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
-#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
- ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
-#define smu_baco_is_support(smu) \
- ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
-#define smu_baco_get_state(smu, state) \
- ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
-#define smu_baco_reset(smu) \
- ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
-#define smu_mode2_reset(smu) \
- ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
+
+bool smu_baco_is_support(struct smu_context *smu);
+
+int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+
+int smu_baco_reset(struct smu_context *smu);
+
+int smu_mode2_reset(struct smu_context *smu);
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
#define smu_dump_pptable(smu) \
@@ -833,7 +835,8 @@ extern int smu_get_current_clocks(struct smu_context *smu,
extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
- enum amd_pp_task task_id);
+ enum amd_pp_task task_id,
+ bool lock_needed);
int smu_switch_power_profile(struct smu_context *smu,
enum PP_SMC_POWER_PROFILE type,
bool en);
@@ -843,7 +846,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *value);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max);
+ uint32_t *min, uint32_t *max, bool lock_needed);
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
@@ -858,10 +861,20 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask);
+ uint32_t mask,
+ bool lock_needed);
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
int smu_set_df_cstate(struct smu_context *smu,
enum pp_df_cstate state);
+int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks);
+
+int smu_get_uclk_dpm_states(struct smu_context *smu,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states);
+
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b88aae9bb242..ead40b2840f9 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
int ret = 0;
uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
if (ret)
return ret;
smu->pstate_sclk = min_sclk_freq * 100;
- ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
+ ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
if (ret)
return ret;
@@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
return ret;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
if (ret)
return ret;
ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
@@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
- if (!smu_display_clock_voltage_request(smu, &clock_req)) {
+
+ if (smu->funcs->display_clock_voltage_request)
+ ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
+ if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 6aedffd739db..6036f682e6f9 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
case SMU_SCLK:
/* retirve table returned paramters unit is MHz */
cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
if (!ret) {
/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
if (cur_value == max)
@@ -251,7 +251,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -269,7 +268,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
clk_type = clk_feature_map[i].clk_type;
- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
if (ret)
return ret;
@@ -435,7 +433,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
if (ret)
return ret;
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -511,7 +509,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
if (ret)
return ret;
@@ -519,7 +517,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
if (ret)
return ret;
- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b68cb8badc75..caf8a3728541 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -809,8 +809,11 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
if (!table_context)
return -EINVAL;
- return smu_set_deep_sleep_dcefclk(smu,
- table_context->boot_values.dcefclk / 100);
+ if (smu->funcs->set_deep_sleep_dcefclk)
+ return smu->funcs->set_deep_sleep_dcefclk(smu,
+ table_context->boot_values.dcefclk / 100);
+
+ return 0;
}
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
@@ -1325,9 +1328,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
return 0;
- mutex_lock(&smu->mutex);
ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
- mutex_unlock(&smu->mutex);
if(clk_select == SMU_UCLK)
smu->hard_min_uclk_req_from_dal = clk_freq;
@@ -1370,12 +1371,10 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
case CHIP_NAVI12:
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
- mutex_lock(&smu->mutex);
if (enable)
ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
else
ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
- mutex_unlock(&smu->mutex);
break;
default:
break;
@@ -1491,10 +1490,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
if (!speed)
return -EINVAL;
- mutex_lock(&(smu->mutex));
ret = smu_v11_0_auto_fan_control(smu, 0);
if (ret)
- goto set_fan_speed_rpm_failed;
+ return ret;
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
@@ -1505,8 +1503,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
-set_fan_speed_rpm_failed:
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1517,11 +1513,9 @@ static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate)
{
int ret = 0;
- mutex_lock(&(smu->mutex));
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetXgmiMode,
pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1633,9 +1627,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
int ret = 0;
- mutex_lock(&smu->mutex);
ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -1767,7 +1759,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0, clk_id = 0;
uint32_t param = 0;
- mutex_lock(&smu->mutex);
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) {
ret = -EINVAL;
@@ -1794,7 +1785,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index c9691d0fb523..6bf942d3ceca 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -325,8 +325,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
int ret = 0;
uint32_t mclk_mask, soc_mask;
- mutex_lock(&smu->mutex);
-
if (max) {
ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
NULL,
@@ -396,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
}
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index a76ffd58404e..c249df9256c7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -635,7 +635,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
!smu_dpm_ctx->dpm_current_power_state)
return -EINVAL;
- mutex_lock(&(smu->mutex));
switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
case SMU_STATE_UI_LABEL_BATTERY:
pm_type = POWER_STATE_TYPE_BATTERY;
@@ -653,7 +652,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&(smu->mutex));
return pm_type;
}
@@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
uint32_t soft_min_level, soft_max_level, hard_min_level;
int ret = 0;
- mutex_lock(&(smu->mutex));
-
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
break;
}
- mutex_unlock(&(smu->mutex));
return ret;
}
@@ -1446,8 +1441,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
dpm_table = smu_dpm->dpm_context;
- mutex_lock(&smu->mutex);
-
switch (clk_type) {
case SMU_GFXCLK:
single_dpm_table = &(dpm_table->gfx_table);
@@ -1469,7 +1462,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
ret = -EINVAL;
}
- mutex_unlock(&smu->mutex);
return ret;
}
@@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct smu_context *smu,
int feature_enabled;
PPCLK_e clk_id;
- mutex_lock(&(smu->mutex));
-
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
@@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct smu_context *smu,
}
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
set_od_failed:
- mutex_unlock(&(smu->mutex));
-
return ret;
}
@@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
}
if (type == PP_OD_COMMIT_DPM_TABLE) {
- mutex_lock(&(smu->mutex));
ret = smu_handle_task(smu, smu_dpm->dpm_level,
- AMD_PP_TASK_READJUST_POWER_STATE);
- mutex_unlock(&(smu->mutex));
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ false);
}
return ret;
--
2.23.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-10-21 13:42 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-21 2:47 [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2 Quan, Evan
[not found] ` <20191021024610.16569-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-21 2:47 ` [PATCH 2/3] drm/amd/powerplay: split out those internal used " Quan, Evan
[not found] ` <20191021024610.16569-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-21 13:42 ` Deucher, Alexander
2019-10-21 2:47 ` [PATCH 3/3] drm/amd/powerplay: clear the swSMU code layer Quan, Evan
2019-10-21 13:42 ` [PATCH 1/3] drm/amd/powerplay: add lock protection for swSMU APIs V2 Deucher, Alexander
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2019-10-18 14:57 Quan, Evan
[not found] ` <20191018145651.10987-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-10-19 8:00 ` Xu, Feifei
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