* [RFC 0/6] DP Phy compliace auto test.
@ 2019-10-03 15:06 Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
` (7 more replies)
0 siblings, 8 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.
Overall design:
--------------
Automate test request will come to source device as HDP short pulse
interrupt from test scope.
Read DPCD 0x201, Check for bit 1 for automated test request.
If set continue and read DPCD 0x218.
Check for bit 3 for phy test pattern, If set continue.
Get the requested test pattern through DPCD 0x248.
Compute requested voltage swing level and pre-emphasis level
from DPCD 0x206 and 0x207
Set signal level through vswing programming sequence.
Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern.
Configure the link and write the new test pattern through DPCD.
High level patch description.
-----------------------------
patch 1: drm level api added to get/set test pattern as per vesa
DP spec. This maybe useful for other driver so added in drm layer.
patch 2: vswing/preemphasis adjustment calculation is needed during
phy compliance request processing along with existing link training
process, so moved the same function in intel_dp.c.
patch 3: Parse the test scope request regarding test rquested pattern,
vswing level, preemphasis level.
patch 4: Register difnition of DP compliance register added.
patch 5: Funcion added to update the pattern in source side.
patch 6: This patch os mainly processing the request.
Currently through prototyping patch able to run DP compliance where
vswing, preemphasis and test pattern is changing fine but complete
test is under process. In parallel want to start design discussion
so sending the above patches as RFC.
Animesh Manna (6):
drm/dp: get/set phy compliance pattern.
drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
drm/i915/dp: Preparation for DP phy compliance auto test.
drm/i915/dp: Register definition for DP compliance register.
drm/i915/dp: Update the pattern as per request.
drm/i915/dp: Program vswing, pre-emphasis, test-pattern
drivers/gpu/drm/drm_dp_helper.c | 77 ++++++++
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 178 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
.../drm/i915/display/intel_dp_link_training.c | 32 ----
drivers/gpu/drm/i915/i915_reg.h | 20 ++
include/drm/drm_dp_helper.h | 28 +++
7 files changed, 307 insertions(+), 32 deletions(-)
--
2.22.0
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [RFC 1/6] drm/dp: get/set phy compliance pattern.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-03 16:24 ` [Intel-gfx] " kbuild test robot
` (2 more replies)
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
` (6 subsequent siblings)
7 siblings, 3 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
During phy complaince auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 28 ++++++++++++
2 files changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f373798d82f6..3cb7170e55f4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+
+ err = drm_dp_link_probe(aux, &data->link);
+ if (err < 0)
+ return err;
+
+ err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ &data->custom80, 10);
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_TEST_PHY_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ &data->hbr2_reset, 2);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err, i;
+ u8 test_pattern;
+
+ err = drm_dp_link_configure(aux, &data->link);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (data->link.revision < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
+ &test_pattern, 1);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->link.num_lanes; i++) {
+ err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
+ &test_pattern, 1);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ed1a985745ba..77dcf5879beb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -691,6 +691,14 @@
# define DP_TEST_COUNT_MASK 0xf
#define DP_TEST_PHY_PATTERN 0x248
+# define DP_TEST_PHY_PATTERN_NONE 0
+# define DP_TEST_PHY_PATTERN_D10_2 1
+# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
+# define DP_TEST_PHY_PATTERN_PRBS7 3
+# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
+# define DP_TEST_PHY_PATTERN_CP2520 5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
@@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
#endif
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ * 0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ * through 0x259.
+ */
+struct drm_dp_phy_test_params {
+ struct drm_dp_link link;
+ u8 phy_pattern;
+ u8 hbr2_reset[2];
+ u8 custom80[10];
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data);
#endif /* _DRM_DP_HELPER_H_ */
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-21 22:57 ` Manasi Navare
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
` (5 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
.../drm/i915/display/intel_dp_link_training.c | 32 -------------------
3 files changed, 35 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1aa39e92f0df..7d33e20dfc87 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4026,6 +4026,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
}
}
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 *link_status)
+{
+ u8 v = 0;
+ u8 p = 0;
+ int lane;
+ u8 voltage_max;
+ u8 preemph_max;
+
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+ u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+ if (this_v > v)
+ v = this_v;
+ if (this_p > p)
+ p = this_p;
+ }
+
+ voltage_max = intel_dp_voltage_max(intel_dp);
+ if (v >= voltage_max)
+ v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+ preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+ if (p >= preemph_max)
+ p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (lane = 0; lane < 4; lane++)
+ intel_dp->train_set[lane] = v | p;
+}
+
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index a194b5b6da05..8f8333afd43d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
u8 dp_train_pat);
void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 *link_status);
+void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
link_status[3], link_status[4], link_status[5]);
}
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
-{
- u8 v = 0;
- u8 p = 0;
- int lane;
- u8 voltage_max;
- u8 preemph_max;
-
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
- u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
- u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
- if (this_v > v)
- v = this_v;
- if (this_p > p)
- p = this_p;
- }
-
- voltage_max = intel_dp_voltage_max(intel_dp);
- if (v >= voltage_max)
- v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
- preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
- if (p >= preemph_max)
- p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
- for (lane = 0; lane < 4; lane++)
- intel_dp->train_set[lane] = v | p;
-}
-
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
--
2.22.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-21 23:29 ` Manasi Navare
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
` (4 subsequent siblings)
7 siblings, 1 reply; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 29 +++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 976669f01a8c..5d6d44fa2594 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1142,6 +1142,7 @@ struct intel_dp_compliance_data {
u8 video_pattern;
u16 hdisplay, vdisplay;
u8 bpc;
+ struct drm_dp_phy_test_params phytest;
};
struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7d33e20dfc87..a19141fc672e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4738,9 +4738,38 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
return test_result;
}
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ if (!drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+ DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+ return DP_TEST_NAK;
+ }
+
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ DRM_DEBUG_KMS("failed to get link status\n");
+ return DP_TEST_NAK;
+ }
+
+ intel_dp->link_mst = false;
+
+ /* retrieve vswing & pre-emphasis setting */
+ intel_get_adjust_train(intel_dp, link_status);
+
+ return DP_TEST_ACK;
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+
+ test_result = intel_dp_prepare_phytest(intel_dp);
+ if (test_result != DP_TEST_ACK)
+ DRM_ERROR("Phy test preparation failed\n");
+
return test_result;
}
--
2.22.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 4/6] drm/i915/dp: Register definition for DP compliance register.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
` (2 preceding siblings ...)
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
` (3 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefd789b9a28..38dacfddbd42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9621,6 +9621,26 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x605f0
+#define DDI_DP_COMP_CTL_B 0x615f0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+ DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x605f4
+#define DDI_DP_COMP_PAT_B 0x615f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+ DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.22.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 5/6] drm/i915/dp: Update the pattern as per request.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
` (3 preceding siblings ...)
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
` (2 subsequent siblings)
7 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
set pattern in DP_COMP_CTL.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a19141fc672e..93b1ce80c174 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4762,6 +4762,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
return DP_TEST_ACK;
}
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
+ u32 temp;
+
+ switch (data->phy_pattern) {
+ case DP_TEST_PHY_PATTERN_NONE:
+ DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+ break;
+ case DP_TEST_PHY_PATTERN_D10_2:
+ DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+ break;
+ case DP_TEST_PHY_PATTERN_ERROR_COUNT:
+ DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE |
+ DDI_DP_COMP_CTL_SCRAMBLED_0);
+ break;
+ case DP_TEST_PHY_PATTERN_PRBS7:
+ DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+ break;
+ case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+ temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+ (data->custom80[2] << 8) | (data->custom80[3]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+ temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+ (data->custom80[6] << 8) | (data->custom80[7]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+ temp = ((data->custom80[8] << 8) | data->custom80[9]);
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+ break;
+ case DP_TEST_PHY_PATTERN_CP2520:
+ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+ temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+ temp);
+ break;
+ default:
+ DRM_ERROR("Invalid Phy Test PAttern\n");
+ }
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
` (4 preceding siblings ...)
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
@ 2019-10-03 15:06 ` Animesh Manna
2019-10-21 23:47 ` Manasi Navare
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
2019-10-04 3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 1 reply; 24+ messages in thread
From: Animesh Manna @ 2019-10-03 15:06 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 93b1ce80c174..dd4c3a81c11d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
}
}
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+ ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+ dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
+ trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+ DDI_PORT_WIDTH_MASK);
+
+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+ ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE |
+ DDI_PORT_WIDTH(lane_cnt);
+ dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+ trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+ DDI_PORT_WIDTH(lane_cnt);
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+ struct drm_dp_phy_test_params *data =
+ &intel_dp->compliance.test_data.phytest;
test_result = intel_dp_prepare_phytest(intel_dp);
if (test_result != DP_TEST_ACK)
DRM_ERROR("Phy test preparation failed\n");
+ intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+ intel_dp_set_signal_levels(intel_dp);
+
+ intel_dp_phy_pattern_update(intel_dp);
+
+ intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
+
+ drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
+
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
return test_result;
}
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [RFC 1/6] drm/dp: get/set phy compliance pattern.
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
@ 2019-10-03 16:24 ` kbuild test robot
2019-10-21 23:27 ` Manasi Navare
2019-11-05 23:12 ` [Intel-gfx] " Manasi Navare
2 siblings, 0 replies; 24+ messages in thread
From: kbuild test robot @ 2019-10-03 16:24 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 24614 bytes --]
Hi Animesh,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191003]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/DP-Phy-compliace-auto-test/20191003-231902
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
include/linux/skbuff.h:893: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'head_frag' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'encapsulation' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'csum_valid' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'vlan_present' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'csum_level' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff'
include/linux/skbuff.h:893: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff'
include/net/sock.h:233: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_portpair' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_cookie' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_listener' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common'
include/net/sock.h:233: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common'
include/net/sock.h:515: warning: Function parameter or member 'sk_rx_skb_cache' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_wq_raw' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_tx_skb_cache' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock'
include/net/sock.h:515: warning: Function parameter or member 'sk_bpf_storage' not described in 'sock'
include/net/sock.h:2439: warning: Function parameter or member 'tcp_rx_skb_cache_key' not described in 'DECLARE_STATIC_KEY_FALSE'
include/net/sock.h:2439: warning: Excess function parameter 'sk' description in 'DECLARE_STATIC_KEY_FALSE'
include/net/sock.h:2439: warning: Excess function parameter 'skb' description in 'DECLARE_STATIC_KEY_FALSE'
include/linux/netdevice.h:2040: warning: Function parameter or member 'gso_partial_features' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'name_assign_type' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'mpls_ptr' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'xdp_prog' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'qdisc_hash' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device'
include/linux/netdevice.h:2040: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state'
drivers/net/phy/phylink.c:593: warning: Function parameter or member 'config' not described in 'phylink_create'
drivers/net/phy/phylink.c:593: warning: Excess function parameter 'ndev' description in 'phylink_create'
mm/util.c:1: warning: 'get_user_pages_fast' not found
mm/slab.c:4215: warning: Function parameter or member 'objp' not described in '__ksize'
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c:335: warning: Excess function parameter 'dev' description in 'amdgpu_gem_prime_export'
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c:336: warning: Excess function parameter 'dev' description in 'amdgpu_gem_prime_export'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:142: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:347: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:348: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:494: warning: Function parameter or member 'start' not described in 'amdgpu_vm_pt_first_dfs'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:546: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:546: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:546: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:546: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:546: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:823: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1285: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2823: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:378: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:379: warning: Function parameter or member 'ih' not described in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:379: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c:1: warning: no structured comments found
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1: warning: no structured comments found
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1: warning: 'pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie' not found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:132: warning: Incorrect use of kernel-doc format: * @atomic_obj
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:238: warning: Incorrect use of kernel-doc format: * gpu_info FW provided soc bounding box struct or 0 if not
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:243: warning: Function parameter or member 'soc_bounding_box' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: 'register_hpd_handlers' not found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: 'dm_pflip_high_irq' not found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: 'dm_crtc_high_irq' not found
include/drm/drm_modeset_helper_vtables.h:1053: warning: Function parameter or member 'prepare_writeback_job' not described in 'drm_connector_helper_funcs'
include/drm/drm_modeset_helper_vtables.h:1053: warning: Function parameter or member 'cleanup_writeback_job' not described in 'drm_connector_helper_funcs'
include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found
>> include/drm/drm_dp_helper.h:1508: warning: Function parameter or member 'hbr2_reset' not described in 'drm_dp_phy_test_params'
include/drm/drm_gem_shmem_helper.h:87: warning: Function parameter or member 'madv' not described in 'drm_gem_shmem_object'
include/drm/drm_gem_shmem_helper.h:87: warning: Function parameter or member 'madv_list' not described in 'drm_gem_shmem_object'
drivers/gpu/drm/i915/display/intel_dpll_mgr.h:158: warning: Enum value 'DPLL_ID_TGL_MGPLL5' not described in enum 'intel_dpll_id'
drivers/gpu/drm/i915/display/intel_dpll_mgr.h:158: warning: Enum value 'DPLL_ID_TGL_MGPLL6' not described in enum 'intel_dpll_id'
drivers/gpu/drm/i915/display/intel_dpll_mgr.h:158: warning: Excess enum value 'DPLL_ID_TGL_TCPLL5' description in 'intel_dpll_id'
drivers/gpu/drm/i915/display/intel_dpll_mgr.h:158: warning: Excess enum value 'DPLL_ID_TGL_TCPLL6' description in 'intel_dpll_id'
drivers/gpu/drm/i915/display/intel_dpll_mgr.h:342: warning: Function parameter or member 'wakeref' not described in 'intel_shared_dpll'
Error: Cannot open file drivers/gpu/drm/i915/i915_gem_batch_pool.c
Error: Cannot open file drivers/gpu/drm/i915/i915_gem_batch_pool.c
Error: Cannot open file drivers/gpu/drm/i915/i915_gem_batch_pool.c
drivers/gpu/drm/i915/i915_drv.h:1129: warning: Incorrect use of kernel-doc format: * The OA context specific information.
drivers/gpu/drm/i915/i915_drv.h:1143: warning: Incorrect use of kernel-doc format: * State of the OA buffer.
drivers/gpu/drm/i915/i915_drv.h:1154: warning: Incorrect use of kernel-doc format: * Locks reads and writes to all head/tail state
drivers/gpu/drm/i915/i915_drv.h:1176: warning: Incorrect use of kernel-doc format: * One 'aging' tail pointer and one 'aged' tail pointer ready to
drivers/gpu/drm/i915/i915_drv.h:1188: warning: Incorrect use of kernel-doc format: * Index for the aged tail ready to read() data up to.
drivers/gpu/drm/i915/i915_drv.h:1193: warning: Incorrect use of kernel-doc format: * A monotonic timestamp for when the current aging tail pointer
drivers/gpu/drm/i915/i915_drv.h:1199: warning: Incorrect use of kernel-doc format: * Although we can always read back the head pointer register,
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'pinned_ctx' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'specific_ctx_id' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'specific_ctx_id_mask' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'poll_check_timer' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'poll_wq' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'pollin' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'periodic' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'period_exponent' not described in 'i915_perf_stream'
drivers/gpu/drm/i915/i915_drv.h:1207: warning: Function parameter or member 'oa_buffer' not described in 'i915_perf_stream'
include/net/cfg80211.h:1092: warning: Function parameter or member 'txpwr' not described in 'station_parameters'
include/net/mac80211.h:4043: warning: Function parameter or member 'sta_set_txpwr' not described in 'ieee80211_ops'
include/net/mac80211.h:2006: warning: Function parameter or member 'txpwr' not described in 'ieee80211_sta'
drivers/gpu/drm/i915/i915_drv.h:1129: warning: Incorrect use of kernel-doc format: * The OA context specific information.
drivers/gpu/drm/i915/i915_drv.h:1143: warning: Incorrect use of kernel-doc format: * State of the OA buffer.
drivers/gpu/drm/i915/i915_drv.h:1154: warning: Incorrect use of kernel-doc format: * Locks reads and writes to all head/tail state
drivers/gpu/drm/i915/i915_drv.h:1176: warning: Incorrect use of kernel-doc format: * One 'aging' tail pointer and one 'aged' tail pointer ready to
drivers/gpu/drm/i915/i915_drv.h:1188: warning: Incorrect use of kernel-doc format: * Index for the aged tail ready to read() data up to.
drivers/gpu/drm/i915/i915_drv.h:1193: warning: Incorrect use of kernel-doc format: * A monotonic timestamp for when the current aging tail pointer
drivers/gpu/drm/i915/i915_drv.h:1199: warning: Incorrect use of kernel-doc format: * Although we can always read back the head pointer register,
drivers/gpu/drm/i915/i915_drv.h:1129: warning: Incorrect use of kernel-doc format: * The OA context specific information.
drivers/gpu/drm/i915/i915_drv.h:1143: warning: Incorrect use of kernel-doc format: * State of the OA buffer.
drivers/gpu/drm/i915/i915_drv.h:1154: warning: Incorrect use of kernel-doc format: * Locks reads and writes to all head/tail state
drivers/gpu/drm/i915/i915_drv.h:1176: warning: Incorrect use of kernel-doc format: * One 'aging' tail pointer and one 'aged' tail pointer ready to
drivers/gpu/drm/i915/i915_drv.h:1188: warning: Incorrect use of kernel-doc format: * Index for the aged tail ready to read() data up to.
drivers/gpu/drm/i915/i915_drv.h:1193: warning: Incorrect use of kernel-doc format: * A monotonic timestamp for when the current aging tail pointer
drivers/gpu/drm/i915/i915_drv.h:1199: warning: Incorrect use of kernel-doc format: * Although we can always read back the head pointer register,
drivers/gpu/drm/mcde/mcde_drv.c:1: warning: 'ST-Ericsson MCDE DRM Driver' not found
Documentation/admin-guide/xfs.rst:257: WARNING: Block quote ends without a blank line; unexpected unindent.
WARNING: kernel-doc 'scripts/kernel-doc -rst -enable-lineno -function Reservation Object Overview drivers/dma-buf/reservation.c' failed with return code 1
WARNING: kernel-doc 'scripts/kernel-doc -rst -enable-lineno -export drivers/dma-buf/reservation.c' failed with return code 2
WARNING: kernel-doc 'scripts/kernel-doc -rst -enable-lineno -internal include/linux/reservation.h' failed with return code 2
Documentation/trace/kprobetrace.rst:99: WARNING: Explicit markup ends without a blank line; unexpected unindent.
Documentation/translations/it_IT/process/maintainer-pgp-guide.rst:458: WARNING: Unknown target name: "nitrokey pro".
drivers/message/fusion/mptbase.c:5057: WARNING: Definition list ends without a blank line; unexpected unindent.
drivers/tty/serial/serial_core.c:1964: WARNING: Definition list ends without a blank line; unexpected unindent.
include/linux/regulator/driver.h:284: WARNING: Unknown target name: "regulator_regmap_x_voltage".
Documentation/security/keys/core.rst:1110: WARNING: Inline emphasis start-string without end-string.
Documentation/security/keys/core.rst:1110: WARNING: Inline emphasis start-string without end-string.
Documentation/security/keys/core.rst:1108: WARNING: Inline emphasis start-string without end-string.
Documentation/security/keys/core.rst:1108: WARNING: Inline emphasis start-string without end-string.
Documentation/security/keys/core.rst:1108: WARNING: Inline emphasis start-string without end-string.
include/uapi/linux/firewire-cdev.h:312: WARNING: Inline literal start-string without end-string.
drivers/firewire/core-transaction.c:606: WARNING: Inline strong start-string without end-string.
fs/seq_file.c:40: WARNING: Inline strong start-string without end-string.
fs/seq_file.c:40: WARNING: Inline strong start-string without end-string.
fs/seq_file.c:40: WARNING: Inline strong start-string without end-string.
fs/seq_file.c:40: WARNING: Inline strong start-string without end-string.
fs/posix_acl.c:636: WARNING: Inline emphasis start-string without end-string.
fs/debugfs/inode.c:399: WARNING: Inline literal start-string without end-string.
fs/debugfs/inode.c:478: WARNING: Inline literal start-string without end-string.
fs/debugfs/inode.c:510: WARNING: Inline literal start-string without end-string.
fs/debugfs/inode.c:603: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:394: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:400: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:439: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:445: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:484: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:490: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:530: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:536: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:578: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:584: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:845: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:851: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:898: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:904: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:1090: WARNING: Inline literal start-string without end-string.
fs/debugfs/file.c:1096: WARNING: Inline literal start-string without end-string.
include/linux/spi/spi.h:382: WARNING: Unexpected indentation.
include/linux/i2c.h:522: WARNING: Inline strong start-string without end-string.
drivers/ata/libata-core.c:5945: WARNING: Unknown target name: "hw".
include/linux/netdevice.h:3482: WARNING: Inline emphasis start-string without end-string.
include/linux/netdevice.h:3482: WARNING: Inline emphasis start-string without end-string.
net/core/dev.c:5008: WARNING: Unknown target name: "page_is".
Documentation/kbuild/makefiles.rst:1142: WARNING: Inline emphasis start-string without end-string.
Documentation/kbuild/makefiles.rst:1152: WARNING: Inline emphasis start-string without end-string.
Documentation/kbuild/makefiles.rst:1154: WARNING: Inline emphasis start-string without end-string.
include/linux/xarray.h:232: WARNING: Unexpected indentation.
Documentation/crypto/crypto_engine.rst:2: WARNING: Explicit markup ends without a blank line; unexpected unindent.
Documentation/index.rst:94: WARNING: toctree contains reference to nonexisting document 'virtual/index'
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:246: WARNING: Unexpected indentation.
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:249: WARNING: Block quote ends without a blank line; unexpected unindent.
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:213: WARNING: Unexpected indentation.
vim +1508 include/drm/drm_dp_helper.h
> 1508
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 7289 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for DP Phy compliace auto test.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
` (5 preceding siblings ...)
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
@ 2019-10-03 17:36 ` Patchwork
2019-10-04 3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-10-03 17:36 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliace auto test.
URL : https://patchwork.freedesktop.org/series/67546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14653
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/index.html
Known issues
------------
Here are the changes found in Patchwork_14653 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#103167])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-bsw-kefka: [DMESG-FAIL][3] ([fdo#111895]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
[fdo#111895]: https://bugs.freedesktop.org/show_bug.cgi?id=111895
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6998 -> Patchwork_14653
CI-20190529: 20190529
CI_DRM_6998: fd44976bff7ae3cdf72245ac33d92d2186e57e9b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5210: 74f55119f9920b65996535210a09147997804136 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14653: 77cab7c63700d1785248d4bd2fe16bd47133e1ac @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
77cab7c63700 drm/i915/dp: Program vswing, pre-emphasis, test-pattern
37e871ded5f0 drm/i915/dp: Update the pattern as per request.
a922ee94741a drm/i915/dp: Register definition for DP compliance register.
ee56d9460821 drm/i915/dp: Preparation for DP phy compliance auto test.
7eb9c2d46a96 drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
0c3427b6dd5d drm/dp: get/set phy compliance pattern.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.IGT: failure for DP Phy compliace auto test.
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
` (6 preceding siblings ...)
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
@ 2019-10-04 3:07 ` Patchwork
7 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-10-04 3:07 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: DP Phy compliace auto test.
URL : https://patchwork.freedesktop.org/series/67546/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6998_full -> Patchwork_14653_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14653_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14653_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14653_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@basic-small-copy:
- shard-hsw: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw5/igt@gem_mmap_gtt@basic-small-copy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw1/igt@gem_mmap_gtt@basic-small-copy.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@pm-tiling:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb5/igt@i915_pm_rpm@pm-tiling.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb1/igt@i915_pm_rpm@pm-tiling.html
Known issues
------------
Here are the changes found in Patchwork_14653_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw2/igt@gem_userptr_blits@coherency-sync.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw6/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-kbl7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-glk5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-glk9/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#109385] / [fdo#111870])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108682])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl6/igt@kms_color@pipe-a-ctm-0-75.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#103232])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#110741])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][23] -> [FAIL][24] ([fdo#105363]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [PASS][25] -> [INCOMPLETE][26] ([fdo#103540])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103167]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [fdo#110403])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#103166])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb2/igt@kms_psr@psr2_dpms.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb1/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][39] -> [INCOMPLETE][40] ([fdo#104108])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-skl: [PASS][41] -> [TIMEOUT][42] ([fdo#111732 ])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl9/igt@perf@gen8-unprivileged-single-ctx-counters.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl8/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@short-reads:
- shard-kbl: [PASS][43] -> [FAIL][44] ([fdo#103183])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-kbl4/igt@perf@short-reads.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-kbl7/igt@perf@short-reads.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109276]) +12 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb2/igt@prime_busy@hang-bsd2.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb6/igt@prime_busy@hang-bsd2.html
* igt@tools_test@tools_test:
- shard-apl: [PASS][47] -> [SKIP][48] ([fdo#109271])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl6/igt@tools_test@tools_test.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl4/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-bsd1:
- {shard-tglb}: [INCOMPLETE][49] ([fdo#111735]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb4/igt@gem_ctx_shared@q-smoketest-bsd1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb8/igt@gem_ctx_shared@q-smoketest-bsd1.html
* igt@gem_ctx_shared@q-smoketest-render:
- {shard-tglb}: [INCOMPLETE][51] ([fdo# 111852 ]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb3/igt@gem_ctx_shared@q-smoketest-render.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb4/igt@gem_ctx_shared@q-smoketest-render.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][53] ([fdo#111325]) -> [PASS][54] +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb7/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][55] ([fdo#109276]) -> [PASS][56] +10 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-kbl: [DMESG-WARN][57] ([fdo#111870]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-kbl1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [DMESG-WARN][59] ([fdo#111870]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-skl: [DMESG-WARN][61] ([fdo#111870]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-snb7/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_backlight@fade_with_suspend:
- {shard-tglb}: [INCOMPLETE][65] ([fdo#111832]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb3/igt@i915_pm_backlight@fade_with_suspend.html
* igt@kms_color@pipe-a-gamma:
- {shard-tglb}: [FAIL][67] ([fdo#104782]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb1/igt@kms_color@pipe-a-gamma.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb3/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
- shard-apl: [INCOMPLETE][69] ([fdo#103927]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [INCOMPLETE][71] ([fdo#103540]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw6/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- {shard-tglb}: [FAIL][73] ([fdo#103167]) -> [PASS][74] +8 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76] +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][77] ([fdo#103167]) -> [PASS][78] +9 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][79] ([fdo#108145]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][81] ([fdo#108145] / [fdo#110403]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant:
- {shard-tglb}: [INCOMPLETE][83] -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb1/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb5/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][85] ([fdo#109441]) -> [PASS][86] +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][87] ([fdo#99912]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw2/igt@kms_setmode@basic.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw6/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][89] ([fdo#109276]) -> [FAIL][90] ([fdo#111329])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][91] ([fdo#109276]) -> [FAIL][92] ([fdo#111330])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][93] ([fdo#111330]) -> [SKIP][94] ([fdo#109276])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb1/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb5/igt@gem_mocs_settings@mocs-rc6-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108682]: https://bugs.freedesktop.org/show_bug.cgi?id=108682
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=11
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
@ 2019-10-21 22:57 ` Manasi Navare
2019-10-22 14:04 ` Animesh Manna
0 siblings, 1 reply; 24+ messages in thread
From: Manasi Navare @ 2019-10-21 22:57 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
>
> No functional change.
You could just make it a non static function instead of moving to intel_dp.c
Manasi
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
> 3 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1aa39e92f0df..7d33e20dfc87 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4026,6 +4026,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
> }
> }
>
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status)
> +{
> + u8 v = 0;
> + u8 p = 0;
> + int lane;
> + u8 voltage_max;
> + u8 preemph_max;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++) {
> + u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> + if (this_v > v)
> + v = this_v;
> + if (this_p > p)
> + p = this_p;
> + }
> +
> + voltage_max = intel_dp_voltage_max(intel_dp);
> + if (v >= voltage_max)
> + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> + preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> + if (p >= preemph_max)
> + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> + for (lane = 0; lane < 4; lane++)
> + intel_dp->train_set[lane] = v | p;
> +}
> +
> void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index a194b5b6da05..8f8333afd43d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat);
> void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status);
> +void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> link_status[3], link_status[4], link_status[5]);
> }
>
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> - const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - u8 v = 0;
> - u8 p = 0;
> - int lane;
> - u8 voltage_max;
> - u8 preemph_max;
> -
> - for (lane = 0; lane < intel_dp->lane_count; lane++) {
> - u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> - u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> - if (this_v > v)
> - v = this_v;
> - if (this_p > p)
> - p = this_p;
> - }
> -
> - voltage_max = intel_dp_voltage_max(intel_dp);
> - if (v >= voltage_max)
> - v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> - preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> - if (p >= preemph_max)
> - p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> - for (lane = 0; lane < 4; lane++)
> - intel_dp->train_set[lane] = v | p;
> -}
> -
> static bool
> intel_dp_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 1/6] drm/dp: get/set phy compliance pattern.
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-03 16:24 ` [Intel-gfx] " kbuild test robot
@ 2019-10-21 23:27 ` Manasi Navare
2019-10-22 13:29 ` Animesh Manna
2019-11-05 23:12 ` [Intel-gfx] " Manasi Navare
2 siblings, 1 reply; 24+ messages in thread
From: Manasi Navare @ 2019-10-21 23:27 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:48PM +0530, Animesh Manna wrote:
> During phy complaince auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
> include/drm/drm_dp_helper.h | 28 ++++++++++++
> 2 files changed, 105 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f373798d82f6..3cb7170e55f4 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> return num_bpc;
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +/**
> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err;
> +
> + err = drm_dp_link_probe(aux, &data->link);
> + if (err < 0)
> + return err;
> +
> + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
Just use drm_dp_dpcd_readb
> + if (err < 0)
> + return err;
> +
> + switch (data->phy_pattern) {
> + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
> + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
> + &data->custom80, 10);
> + if (err < 0)
> + return err;
> +
> + break;
> + case DP_TEST_PHY_PATTERN_CP2520:
> + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> + &data->hbr2_reset, 2);
> + if (err < 0)
> + return err;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
> +
> +/**
> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err, i;
> + u8 test_pattern;
> +
> + err = drm_dp_link_configure(aux, &data->link);
> + if (err < 0)
> + return err;
> +
> + test_pattern = data->phy_pattern;
> + if (data->link.revision < 0x12) {
> + test_pattern = (test_pattern << 2) &
> + DP_LINK_QUAL_PATTERN_11_MASK;
> + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
> + &test_pattern, 1);
Same, just use drm_dp_dpcd_writeb
> + if (err < 0)
> + return err;
> + } else {
> + for (i = 0; i < data->link.num_lanes; i++) {
> + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
> + &test_pattern, 1);
> + if (err < 0)
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index ed1a985745ba..77dcf5879beb 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -691,6 +691,14 @@
> # define DP_TEST_COUNT_MASK 0xf
>
> #define DP_TEST_PHY_PATTERN 0x248
This should be consistent with spec name DP_PHY_TEST_PATTERN
And since the bits below are part of the 2:0 PATTERN_SEL, I would prefer
having DP_PHY_TEST_PATTERN_SEL_MASK 0x7
> +# define DP_TEST_PHY_PATTERN_NONE 0
^ 0x0
> +# define DP_TEST_PHY_PATTERN_D10_2 1
^ 0x1 (to be consistent with other bit defs in .h file)
Manasi
> +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
> +# define DP_TEST_PHY_PATTERN_PRBS7 3
> +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
> +# define DP_TEST_PHY_PATTERN_CP2520 5
> +
> +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
> @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>
> #endif
>
> +/**
> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
> + * @link: Link information.
> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
> + * 0x24A and 0x24B (sink)
> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
> + * through 0x259.
> + */
> +struct drm_dp_phy_test_params {
> + struct drm_dp_link link;
> + u8 phy_pattern;
> + u8 hbr2_reset[2];
> + u8 custom80[10];
> +};
> +
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.22.0
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test.
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
@ 2019-10-21 23:29 ` Manasi Navare
2019-10-22 14:12 ` Animesh Manna
0 siblings, 1 reply; 24+ messages in thread
From: Manasi Navare @ 2019-10-21 23:29 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:50PM +0530, Animesh Manna wrote:
> During DP phy compliance auto test mode, sink will request
> combination of different test pattern with differnt level of
> vswing, pre-emphasis. Function added to prepare for it.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
This patch looks good to me, could you add a comment for why
link_mst is set to false?
Manasi
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 29 +++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 976669f01a8c..5d6d44fa2594 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1142,6 +1142,7 @@ struct intel_dp_compliance_data {
> u8 video_pattern;
> u16 hdisplay, vdisplay;
> u8 bpc;
> + struct drm_dp_phy_test_params phytest;
> };
>
> struct intel_dp_compliance {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7d33e20dfc87..a19141fc672e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4738,9 +4738,38 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
> return test_result;
> }
>
> +static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
> +{
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
> + u8 link_status[DP_LINK_STATUS_SIZE];
> +
> + if (!drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
> + DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
> + return DP_TEST_NAK;
> + }
> +
> + if (!intel_dp_get_link_status(intel_dp, link_status)) {
> + DRM_DEBUG_KMS("failed to get link status\n");
> + return DP_TEST_NAK;
> + }
> +
> + intel_dp->link_mst = false;
> +
> + /* retrieve vswing & pre-emphasis setting */
> + intel_get_adjust_train(intel_dp, link_status);
> +
> + return DP_TEST_ACK;
> +}
> +
> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> u8 test_result = DP_TEST_NAK;
> +
> + test_result = intel_dp_prepare_phytest(intel_dp);
> + if (test_result != DP_TEST_ACK)
> + DRM_ERROR("Phy test preparation failed\n");
> +
> return test_result;
> }
>
> --
> 2.22.0
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
@ 2019-10-21 23:47 ` Manasi Navare
2019-10-22 15:07 ` Animesh Manna
0 siblings, 1 reply; 24+ messages in thread
From: Manasi Navare @ 2019-10-21 23:47 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:53PM +0530, Animesh Manna wrote:
> This patch process phy compliance request by programming requested
> vswing, pre-emphasis and test pattern.
So the design of this whole patch will need to be changed to work with the whole kms infrastructure
Basically what you are doing here is handling the HPD test request, getting the test patterns.
populating the intel_dp_compliance phytest struct and also writing the I915 regs right then and there.
This model does not fit the atomic KMS infrastructure, IMO this is how it should look like:
1. Handle the test request
2. Prepare the PHY patterns where you erad the test patterns from DPCD and populate
the intel_dp_compliance phytest struct
3. set test_active = true
4. Now in atomic_commit_tail somewhere just before enabling pipe, is where
based on if intel_dp_compliance.phytest not NULL you will need to call ddi_disable, enable,
set_signal_levels, phy_update on the other hand all teh functions that write data to the
I915 registers will need to happen here.
Clint, Jani N any thoughts here?
Regards
Manasi
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 93b1ce80c174..dd4c3a81c11d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> }
> }
>
> +static void
> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum port port = intel_dig_port->base.port;
> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> +
> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> +
> + ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
> + dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> + trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> + DDI_PORT_WIDTH_MASK);
> +
> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum port port = intel_dig_port->base.port;
> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> +
> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> +
> + ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE |
> + DDI_PORT_WIDTH(lane_cnt);
> + dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> + trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> + DDI_PORT_WIDTH(lane_cnt);
> +
> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> +}
> +
> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> u8 test_result = DP_TEST_NAK;
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
>
> test_result = intel_dp_prepare_phytest(intel_dp);
> if (test_result != DP_TEST_ACK)
> DRM_ERROR("Phy test preparation failed\n");
>
> + intel_dp_autotest_phy_ddi_disable(intel_dp);
> +
> + intel_dp_set_signal_levels(intel_dp);
> +
> + intel_dp_phy_pattern_update(intel_dp);
> +
> + intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
> +
> + drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
> +
> + /* Set test active flag here so userspace doesn't interrupt things */
> + intel_dp->compliance.test_active = 1;
> +
> return test_result;
> }
>
> --
> 2.22.0
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 1/6] drm/dp: get/set phy compliance pattern.
2019-10-21 23:27 ` Manasi Navare
@ 2019-10-22 13:29 ` Animesh Manna
0 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-22 13:29 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 4:57 AM, Manasi Navare wrote:
> On Thu, Oct 03, 2019 at 08:36:48PM +0530, Animesh Manna wrote:
>> During phy complaince auto test mode source need to read
>> requested test pattern from sink through DPCD. After processing
>> the request source need to set the pattern. So set/get method
>> added in drm layer as it is DP protocol.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
>> include/drm/drm_dp_helper.h | 28 ++++++++++++
>> 2 files changed, 105 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index f373798d82f6..3cb7170e55f4 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>> return num_bpc;
>> }
>> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>> +
>> +/**
>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data)
>> +{
>> + int err;
>> +
>> + err = drm_dp_link_probe(aux, &data->link);
>> + if (err < 0)
>> + return err;
>> +
>> + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
> Just use drm_dp_dpcd_readb
Thanks Manasi for code review.
Will add all suggested changes here.
Regards,
Animesh
>
>> + if (err < 0)
>> + return err;
>> +
>> + switch (data->phy_pattern) {
>> + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
>> + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>> + &data->custom80, 10);
>> + if (err < 0)
>> + return err;
>> +
>> + break;
>> + case DP_TEST_PHY_PATTERN_CP2520:
>> + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>> + &data->hbr2_reset, 2);
>> + if (err < 0)
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>> +
>> +/**
>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data)
>> +{
>> + int err, i;
>> + u8 test_pattern;
>> +
>> + err = drm_dp_link_configure(aux, &data->link);
>> + if (err < 0)
>> + return err;
>> +
>> + test_pattern = data->phy_pattern;
>> + if (data->link.revision < 0x12) {
>> + test_pattern = (test_pattern << 2) &
>> + DP_LINK_QUAL_PATTERN_11_MASK;
>> + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
>> + &test_pattern, 1);
> Same, just use drm_dp_dpcd_writeb
>
>> + if (err < 0)
>> + return err;
>> + } else {
>> + for (i = 0; i < data->link.num_lanes; i++) {
>> + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
>> + &test_pattern, 1);
>> + if (err < 0)
>> + return err;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index ed1a985745ba..77dcf5879beb 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -691,6 +691,14 @@
>> # define DP_TEST_COUNT_MASK 0xf
>>
>> #define DP_TEST_PHY_PATTERN 0x248
> This should be consistent with spec name DP_PHY_TEST_PATTERN
>
> And since the bits below are part of the 2:0 PATTERN_SEL, I would prefer
> having DP_PHY_TEST_PATTERN_SEL_MASK 0x7
>
>> +# define DP_TEST_PHY_PATTERN_NONE 0
> ^ 0x0
>> +# define DP_TEST_PHY_PATTERN_D10_2 1
> ^ 0x1 (to be consistent with other bit defs in .h file)
>
> Manasi
>
>> +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
>> +# define DP_TEST_PHY_PATTERN_PRBS7 3
>> +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
>> +# define DP_TEST_PHY_PATTERN_CP2520 5
>> +
>> +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
>> @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>
>> #endif
>>
>> +/**
>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>> + * @link: Link information.
>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>> + * 0x24A and 0x24B (sink)
>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>> + * through 0x259.
>> + */
>> +struct drm_dp_phy_test_params {
>> + struct drm_dp_link link;
>> + u8 phy_pattern;
>> + u8 hbr2_reset[2];
>> + u8 custom80[10];
>> +};
>> +
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data);
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data);
>> #endif /* _DRM_DP_HELPER_H_ */
>> --
>> 2.22.0
>>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
2019-10-21 22:57 ` Manasi Navare
@ 2019-10-22 14:04 ` Animesh Manna
2019-10-22 17:40 ` Manasi Navare
0 siblings, 1 reply; 24+ messages in thread
From: Animesh Manna @ 2019-10-22 14:04 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 4:27 AM, Manasi Navare wrote:
> On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
>> vswing/pre-emphasis adjustment calculation is needed in processing
>> of auto phy compliance request other than link training, so moved
>> the same function in intel_dp.c.
>>
>> No functional change.
> You could just make it a non static function instead of moving to intel_dp.c
Initially I did the same ... :)
Later I thought intel_dp_link_training.c file is mainly focused only on
link training process, start_link_train() and stop_link_train() are only
exposed.
I thought I may not be allowed to expose intel_get_adjust_train() as it
is not exclusive for link training.
Please let me know your view.
Regards,
Animesh
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test.
2019-10-21 23:29 ` Manasi Navare
@ 2019-10-22 14:12 ` Animesh Manna
0 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-22 14:12 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 4:59 AM, Manasi Navare wrote:
> On Thu, Oct 03, 2019 at 08:36:50PM +0530, Animesh Manna wrote:
>> During DP phy compliance auto test mode, sink will request
>> combination of different test pattern with differnt level of
>> vswing, pre-emphasis. Function added to prepare for it.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> This patch looks good to me, could you add a comment for why
> link_mst is set to false?
Thanks, link_mst is set to false to avoid executing mst related code
during compliance testing... will add as comment.
Regards.
Animesh
>
> Manasi
>
>> ---
>> .../drm/i915/display/intel_display_types.h | 1 +
>> drivers/gpu/drm/i915/display/intel_dp.c | 29 +++++++++++++++++++
>> 2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 976669f01a8c..5d6d44fa2594 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1142,6 +1142,7 @@ struct intel_dp_compliance_data {
>> u8 video_pattern;
>> u16 hdisplay, vdisplay;
>> u8 bpc;
>> + struct drm_dp_phy_test_params phytest;
>> };
>>
>> struct intel_dp_compliance {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 7d33e20dfc87..a19141fc672e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4738,9 +4738,38 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
>> return test_result;
>> }
>>
>> +static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
>> +{
>> + struct drm_dp_phy_test_params *data =
>> + &intel_dp->compliance.test_data.phytest;
>> + u8 link_status[DP_LINK_STATUS_SIZE];
>> +
>> + if (!drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
>> + DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
>> + return DP_TEST_NAK;
>> + }
>> +
>> + if (!intel_dp_get_link_status(intel_dp, link_status)) {
>> + DRM_DEBUG_KMS("failed to get link status\n");
>> + return DP_TEST_NAK;
>> + }
>> +
>> + intel_dp->link_mst = false;
>> +
>> + /* retrieve vswing & pre-emphasis setting */
>> + intel_get_adjust_train(intel_dp, link_status);
>> +
>> + return DP_TEST_ACK;
>> +}
>> +
>> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>> {
>> u8 test_result = DP_TEST_NAK;
>> +
>> + test_result = intel_dp_prepare_phytest(intel_dp);
>> + if (test_result != DP_TEST_ACK)
>> + DRM_ERROR("Phy test preparation failed\n");
>> +
>> return test_result;
>> }
>>
>> --
>> 2.22.0
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2019-10-21 23:47 ` Manasi Navare
@ 2019-10-22 15:07 ` Animesh Manna
2019-10-22 18:41 ` Manasi Navare
0 siblings, 1 reply; 24+ messages in thread
From: Animesh Manna @ 2019-10-22 15:07 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 5:17 AM, Manasi Navare wrote:
> On Thu, Oct 03, 2019 at 08:36:53PM +0530, Animesh Manna wrote:
>> This patch process phy compliance request by programming requested
>> vswing, pre-emphasis and test pattern.
> So the design of this whole patch will need to be changed to work with the whole kms infrastructure
> Basically what you are doing here is handling the HPD test request, getting the test patterns.
> populating the intel_dp_compliance phytest struct and also writing the I915 regs right then and there.
>
> This model does not fit the atomic KMS infrastructure, IMO this is how it should look like:
>
> 1. Handle the test request
> 2. Prepare the PHY patterns where you erad the test patterns from DPCD and populate
> the intel_dp_compliance phytest struct
> 3. set test_active = true
> 4. Now in atomic_commit_tail somewhere just before enabling pipe, is where
> based on if intel_dp_compliance.phytest not NULL you will need to call ddi_disable, enable,
> set_signal_levels, phy_update on the other hand all teh functions that write data to the
> I915 registers will need to happen here.
Got the high level view, more brainstorming will help here to finalize
the design. Hope initial patches will not much change irrespective of
the design
Do we need any drm-property here? The process of auto phy compliance
testing is general for all driver so a thought came.
Have an option to put the preparation for phy compliance request in
atomic_check.
Will wait for feedback from Jani, Clint and others.
Regards,
Animesh
>
> Clint, Jani N any thoughts here?
>
> Regards
> Manasi
>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
>> 1 file changed, 62 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 93b1ce80c174..dd4c3a81c11d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
>> }
>> }
>>
>> +static void
>> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
>> +{
>> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_device *dev = intel_dig_port->base.base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> + enum port port = intel_dig_port->base.port;
>> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
>> +
>> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
>> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
>> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
>> +
>> + ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
>> + dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
>> + trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
>> + DDI_PORT_WIDTH_MASK);
>> +
>> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
>> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
>> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
>> +}
>> +
>> +static void
>> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
>> +{
>> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_device *dev = intel_dig_port->base.base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> + enum port port = intel_dig_port->base.port;
>> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
>> +
>> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
>> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
>> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
>> +
>> + ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE |
>> + DDI_PORT_WIDTH(lane_cnt);
>> + dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
>> + trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
>> + DDI_PORT_WIDTH(lane_cnt);
>> +
>> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
>> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
>> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
>> +}
>> +
>> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
>> {
>> u8 test_result = DP_TEST_NAK;
>> + struct drm_dp_phy_test_params *data =
>> + &intel_dp->compliance.test_data.phytest;
>>
>> test_result = intel_dp_prepare_phytest(intel_dp);
>> if (test_result != DP_TEST_ACK)
>> DRM_ERROR("Phy test preparation failed\n");
>>
>> + intel_dp_autotest_phy_ddi_disable(intel_dp);
>> +
>> + intel_dp_set_signal_levels(intel_dp);
>> +
>> + intel_dp_phy_pattern_update(intel_dp);
>> +
>> + intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
>> +
>> + drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
>> +
>> + /* Set test active flag here so userspace doesn't interrupt things */
>> + intel_dp->compliance.test_active = 1;
>> +
>> return test_result;
>> }
>>
>> --
>> 2.22.0
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
2019-10-22 14:04 ` Animesh Manna
@ 2019-10-22 17:40 ` Manasi Navare
2019-10-24 11:45 ` [Intel-gfx] " Animesh Manna
0 siblings, 1 reply; 24+ messages in thread
From: Manasi Navare @ 2019-10-22 17:40 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Tue, Oct 22, 2019 at 07:34:13PM +0530, Animesh Manna wrote:
>
> On 10/22/2019 4:27 AM, Manasi Navare wrote:
> >On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
> >>vswing/pre-emphasis adjustment calculation is needed in processing
> >>of auto phy compliance request other than link training, so moved
> >>the same function in intel_dp.c.
> >>
> >>No functional change.
> >You could just make it a non static function instead of moving to intel_dp.c
>
> Initially I did the same ... :)
> Later I thought intel_dp_link_training.c file is mainly focused only on link
> training process, start_link_train() and stop_link_train() are only exposed.
> I thought I may not be allowed to expose intel_get_adjust_train() as it is
> not exclusive for link training.
> Please let me know your view.
Infact now that I look at this, i think the prepare_phy_test function should only
probably get the drm_get_phy_test_pattern and populate in the intel_dp_compliance
structure and then adjust train and all that can happen right before pattern update
which will need to happen in atomic_commit_tail.
How do you handle the regular link training sequence in the case of PHY test?
What happens to the adjust train the the regular link training clock recovery and
channel eq stages?
Manasi
>
> Regards,
> Animesh
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
2019-10-22 15:07 ` Animesh Manna
@ 2019-10-22 18:41 ` Manasi Navare
0 siblings, 0 replies; 24+ messages in thread
From: Manasi Navare @ 2019-10-22 18:41 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Tue, Oct 22, 2019 at 08:37:58PM +0530, Animesh Manna wrote:
>
> On 10/22/2019 5:17 AM, Manasi Navare wrote:
> >On Thu, Oct 03, 2019 at 08:36:53PM +0530, Animesh Manna wrote:
> >>This patch process phy compliance request by programming requested
> >>vswing, pre-emphasis and test pattern.
> >So the design of this whole patch will need to be changed to work with the whole kms infrastructure
> >Basically what you are doing here is handling the HPD test request, getting the test patterns.
> >populating the intel_dp_compliance phytest struct and also writing the I915 regs right then and there.
> >
> >This model does not fit the atomic KMS infrastructure, IMO this is how it should look like:
> >
> >1. Handle the test request
> >2. Prepare the PHY patterns where you erad the test patterns from DPCD and populate
> >the intel_dp_compliance phytest struct
> >3. set test_active = true
> >4. Now in atomic_commit_tail somewhere just before enabling pipe, is where
> >based on if intel_dp_compliance.phytest not NULL you will need to call ddi_disable, enable,
> >set_signal_levels, phy_update on the other hand all teh functions that write data to the
> >I915 registers will need to happen here.
>
> Got the high level view, more brainstorming will help here to finalize the
> design. Hope initial patches will not much change irrespective of the design
>
> Do we need any drm-property here? The process of auto phy compliance testing
> is general for all driver so a thought came.
>
No need to have any property since the control to run phy test
stays within the kernel. So we can just make use of whether the intel_dp_compliance.phytest struct
is set or not to determine calling phy test related functions in atomic_commit_tail before
enabling the pipe
Manasi
> Have an option to put the preparation for phy compliance request in
> atomic_check.
>
> Will wait for feedback from Jani, Clint and others.
>
> Regards,
> Animesh
>
> >
> >Clint, Jani N any thoughts here?
> >
> >Regards
> >Manasi
> >
> >>Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
> >> 1 file changed, 62 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >>index 93b1ce80c174..dd4c3a81c11d 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>@@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> >> }
> >> }
> >>+static void
> >>+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> >>+{
> >>+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >>+ struct drm_device *dev = intel_dig_port->base.base.dev;
> >>+ struct drm_i915_private *dev_priv = to_i915(dev);
> >>+ enum port port = intel_dig_port->base.port;
> >>+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> >>+
> >>+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> >>+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> >>+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> >>+
> >>+ ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
> >>+ dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> >>+ trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> >>+ DDI_PORT_WIDTH_MASK);
> >>+
> >>+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> >>+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> >>+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> >>+}
> >>+
> >>+static void
> >>+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> >>+{
> >>+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >>+ struct drm_device *dev = intel_dig_port->base.base.dev;
> >>+ struct drm_i915_private *dev_priv = to_i915(dev);
> >>+ enum port port = intel_dig_port->base.port;
> >>+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> >>+
> >>+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> >>+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> >>+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> >>+
> >>+ ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE |
> >>+ DDI_PORT_WIDTH(lane_cnt);
> >>+ dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> >>+ trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> >>+ DDI_PORT_WIDTH(lane_cnt);
> >>+
> >>+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> >>+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> >>+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> >>+}
> >>+
> >> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> >> {
> >> u8 test_result = DP_TEST_NAK;
> >>+ struct drm_dp_phy_test_params *data =
> >>+ &intel_dp->compliance.test_data.phytest;
> >> test_result = intel_dp_prepare_phytest(intel_dp);
> >> if (test_result != DP_TEST_ACK)
> >> DRM_ERROR("Phy test preparation failed\n");
> >>+ intel_dp_autotest_phy_ddi_disable(intel_dp);
> >>+
> >>+ intel_dp_set_signal_levels(intel_dp);
> >>+
> >>+ intel_dp_phy_pattern_update(intel_dp);
> >>+
> >>+ intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
> >>+
> >>+ drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
> >>+
> >>+ /* Set test active flag here so userspace doesn't interrupt things */
> >>+ intel_dp->compliance.test_active = 1;
> >>+
> >> return test_result;
> >> }
> >>--
> >>2.22.0
> >>
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
@ 2019-10-24 11:45 ` Animesh Manna
0 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-24 11:45 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 11:10 PM, Manasi Navare wrote:
> On Tue, Oct 22, 2019 at 07:34:13PM +0530, Animesh Manna wrote:
>> On 10/22/2019 4:27 AM, Manasi Navare wrote:
>>> On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
>>>> vswing/pre-emphasis adjustment calculation is needed in processing
>>>> of auto phy compliance request other than link training, so moved
>>>> the same function in intel_dp.c.
>>>>
>>>> No functional change.
>>> You could just make it a non static function instead of moving to intel_dp.c
>> Initially I did the same ... :)
>> Later I thought intel_dp_link_training.c file is mainly focused only on link
>> training process, start_link_train() and stop_link_train() are only exposed.
>> I thought I may not be allowed to expose intel_get_adjust_train() as it is
>> not exclusive for link training.
>> Please let me know your view.
> Infact now that I look at this, i think the prepare_phy_test function should only
> probably get the drm_get_phy_test_pattern and populate in the intel_dp_compliance
> structure and then adjust train and all that can happen right before pattern update
> which will need to happen in atomic_commit_tail.
Okay, in commit-tail we follow modeset sequence and use encoder specific
hook to do encoder specific programming.
Can you please share your thought about the right place to do DP phy
compliance specific programming.
>
> How do you handle the regular link training sequence in the case of PHY test?
In automated phy compliance testing as such there is no requirement to
do link training in between.
Do you see any need of link training in between compliance testing?
> What happens to the adjust train the the regular link training clock recovery and
> channel eq stages?
I felt adjust train calculation can be exposed from intel_dp.c/.h and same like other helper link training process(clock recovery + channel eq) can use it.
Regards,
Animesh
>
> Manasi
>
>> Regards,
>> Animesh
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
@ 2019-10-24 11:45 ` Animesh Manna
0 siblings, 0 replies; 24+ messages in thread
From: Animesh Manna @ 2019-10-24 11:45 UTC (permalink / raw)
To: Manasi Navare; +Cc: jani.nikula, intel-gfx
On 10/22/2019 11:10 PM, Manasi Navare wrote:
> On Tue, Oct 22, 2019 at 07:34:13PM +0530, Animesh Manna wrote:
>> On 10/22/2019 4:27 AM, Manasi Navare wrote:
>>> On Thu, Oct 03, 2019 at 08:36:49PM +0530, Animesh Manna wrote:
>>>> vswing/pre-emphasis adjustment calculation is needed in processing
>>>> of auto phy compliance request other than link training, so moved
>>>> the same function in intel_dp.c.
>>>>
>>>> No functional change.
>>> You could just make it a non static function instead of moving to intel_dp.c
>> Initially I did the same ... :)
>> Later I thought intel_dp_link_training.c file is mainly focused only on link
>> training process, start_link_train() and stop_link_train() are only exposed.
>> I thought I may not be allowed to expose intel_get_adjust_train() as it is
>> not exclusive for link training.
>> Please let me know your view.
> Infact now that I look at this, i think the prepare_phy_test function should only
> probably get the drm_get_phy_test_pattern and populate in the intel_dp_compliance
> structure and then adjust train and all that can happen right before pattern update
> which will need to happen in atomic_commit_tail.
Okay, in commit-tail we follow modeset sequence and use encoder specific
hook to do encoder specific programming.
Can you please share your thought about the right place to do DP phy
compliance specific programming.
>
> How do you handle the regular link training sequence in the case of PHY test?
In automated phy compliance testing as such there is no requirement to
do link training in between.
Do you see any need of link training in between compliance testing?
> What happens to the adjust train the the regular link training clock recovery and
> channel eq stages?
I felt adjust train calculation can be exposed from intel_dp.c/.h and same like other helper link training process(clock recovery + channel eq) can use it.
Regards,
Animesh
>
> Manasi
>
>> Regards,
>> Animesh
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC 1/6] drm/dp: get/set phy compliance pattern.
@ 2019-11-05 23:12 ` Manasi Navare
0 siblings, 0 replies; 24+ messages in thread
From: Manasi Navare @ 2019-11-05 23:12 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:48PM +0530, Animesh Manna wrote:
> During phy complaince auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
> include/drm/drm_dp_helper.h | 28 ++++++++++++
> 2 files changed, 105 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f373798d82f6..3cb7170e55f4 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> return num_bpc;
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +/**
> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err;
> +
> + err = drm_dp_link_probe(aux, &data->link);
Here this just reads the Sink capabilities and reads the max link rate and lane count
and stores that into the phy test link. But after talking to Clint here he pointed
out that for PHY compliance, you should be reading the TEST_LINK_RATE and TEST_LANE_COUNT
as the requested link config.
> + if (err < 0)
> + return err;
> +
> + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
> + if (err < 0)
> + return err;
> +
> + switch (data->phy_pattern) {
> + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
> + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
> + &data->custom80, 10);
> + if (err < 0)
> + return err;
> +
> + break;
> + case DP_TEST_PHY_PATTERN_CP2520:
> + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> + &data->hbr2_reset, 2);
> + if (err < 0)
> + return err;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
> +
> +/**
> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err, i;
> + u8 test_pattern;
> +
> + err = drm_dp_link_configure(aux, &data->link);
So here this function write sto the sink's DPCD registers to set the
link rate and lane count, however we havent set the display controller HW to that link rate
since we call this out of atomic modeset context.
Another reason why all this needs to happen in the context of atomic modeset
Manasi
> + if (err < 0)
> + return err;
> +
> + test_pattern = data->phy_pattern;
> + if (data->link.revision < 0x12) {
> + test_pattern = (test_pattern << 2) &
> + DP_LINK_QUAL_PATTERN_11_MASK;
> + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
> + &test_pattern, 1);
> + if (err < 0)
> + return err;
> + } else {
> + for (i = 0; i < data->link.num_lanes; i++) {
> + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
> + &test_pattern, 1);
> + if (err < 0)
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index ed1a985745ba..77dcf5879beb 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -691,6 +691,14 @@
> # define DP_TEST_COUNT_MASK 0xf
>
> #define DP_TEST_PHY_PATTERN 0x248
> +# define DP_TEST_PHY_PATTERN_NONE 0
> +# define DP_TEST_PHY_PATTERN_D10_2 1
> +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
> +# define DP_TEST_PHY_PATTERN_PRBS7 3
> +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
> +# define DP_TEST_PHY_PATTERN_CP2520 5
> +
> +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
> @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>
> #endif
>
> +/**
> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
> + * @link: Link information.
> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
> + * 0x24A and 0x24B (sink)
> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
> + * through 0x259.
> + */
> +struct drm_dp_phy_test_params {
> + struct drm_dp_link link;
> + u8 phy_pattern;
> + u8 hbr2_reset[2];
> + u8 custom80[10];
> +};
> +
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.22.0
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [RFC 1/6] drm/dp: get/set phy compliance pattern.
@ 2019-11-05 23:12 ` Manasi Navare
0 siblings, 0 replies; 24+ messages in thread
From: Manasi Navare @ 2019-11-05 23:12 UTC (permalink / raw)
To: Animesh Manna; +Cc: jani.nikula, intel-gfx
On Thu, Oct 03, 2019 at 08:36:48PM +0530, Animesh Manna wrote:
> During phy complaince auto test mode source need to read
> requested test pattern from sink through DPCD. After processing
> the request source need to set the pattern. So set/get method
> added in drm layer as it is DP protocol.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
> include/drm/drm_dp_helper.h | 28 ++++++++++++
> 2 files changed, 105 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f373798d82f6..3cb7170e55f4 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> return num_bpc;
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +/**
> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err;
> +
> + err = drm_dp_link_probe(aux, &data->link);
Here this just reads the Sink capabilities and reads the max link rate and lane count
and stores that into the phy test link. But after talking to Clint here he pointed
out that for PHY compliance, you should be reading the TEST_LINK_RATE and TEST_LANE_COUNT
as the requested link config.
> + if (err < 0)
> + return err;
> +
> + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
> + if (err < 0)
> + return err;
> +
> + switch (data->phy_pattern) {
> + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
> + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
> + &data->custom80, 10);
> + if (err < 0)
> + return err;
> +
> + break;
> + case DP_TEST_PHY_PATTERN_CP2520:
> + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
> + &data->hbr2_reset, 2);
> + if (err < 0)
> + return err;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
> +
> +/**
> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
> + * @aux: DisplayPort AUX channel
> + * @data: DP phy compliance test parameters.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data)
> +{
> + int err, i;
> + u8 test_pattern;
> +
> + err = drm_dp_link_configure(aux, &data->link);
So here this function write sto the sink's DPCD registers to set the
link rate and lane count, however we havent set the display controller HW to that link rate
since we call this out of atomic modeset context.
Another reason why all this needs to happen in the context of atomic modeset
Manasi
> + if (err < 0)
> + return err;
> +
> + test_pattern = data->phy_pattern;
> + if (data->link.revision < 0x12) {
> + test_pattern = (test_pattern << 2) &
> + DP_LINK_QUAL_PATTERN_11_MASK;
> + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
> + &test_pattern, 1);
> + if (err < 0)
> + return err;
> + } else {
> + for (i = 0; i < data->link.num_lanes; i++) {
> + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
> + &test_pattern, 1);
> + if (err < 0)
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index ed1a985745ba..77dcf5879beb 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -691,6 +691,14 @@
> # define DP_TEST_COUNT_MASK 0xf
>
> #define DP_TEST_PHY_PATTERN 0x248
> +# define DP_TEST_PHY_PATTERN_NONE 0
> +# define DP_TEST_PHY_PATTERN_D10_2 1
> +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
> +# define DP_TEST_PHY_PATTERN_PRBS7 3
> +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
> +# define DP_TEST_PHY_PATTERN_CP2520 5
> +
> +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
> @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>
> #endif
>
> +/**
> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
> + * @link: Link information.
> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
> + * 0x24A and 0x24B (sink)
> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
> + * through 0x259.
> + */
> +struct drm_dp_phy_test_params {
> + struct drm_dp_link link;
> + u8 phy_pattern;
> + u8 hbr2_reset[2];
> + u8 custom80[10];
> +};
> +
> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
> + struct drm_dp_phy_test_params *data);
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.22.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2019-11-05 23:09 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-03 16:24 ` [Intel-gfx] " kbuild test robot
2019-10-21 23:27 ` Manasi Navare
2019-10-22 13:29 ` Animesh Manna
2019-11-05 23:12 ` Manasi Navare
2019-11-05 23:12 ` [Intel-gfx] " Manasi Navare
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-10-21 22:57 ` Manasi Navare
2019-10-22 14:04 ` Animesh Manna
2019-10-22 17:40 ` Manasi Navare
2019-10-24 11:45 ` Animesh Manna
2019-10-24 11:45 ` [Intel-gfx] " Animesh Manna
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-10-21 23:29 ` Manasi Navare
2019-10-22 14:12 ` Animesh Manna
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-10-21 23:47 ` Manasi Navare
2019-10-22 15:07 ` Animesh Manna
2019-10-22 18:41 ` Manasi Navare
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
2019-10-04 3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
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