* [PATCH 1/8] drm/i915: Parametrize PFIT_PIPE
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 2/8] drm/i915: Replace some accidental I915_READ_FW()s with the normal version Ville Syrjala
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the PFIT_PIPE stuff less ugly via parametrization.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..4601416c603e 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -430,8 +430,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
if (INTEL_GEN(dev_priv) >= 4)
- pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
- PFIT_FILTER_FUZZY);
+ pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY;
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 855db888516c..fe043c37e76b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4819,6 +4819,7 @@ enum {
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
+#define PFIT_PIPE(pipe) ((pipe) << 29)
#define VERT_INTERP_DISABLE (0 << 10)
#define VERT_INTERP_BILINEAR (1 << 10)
#define VERT_INTERP_MASK (3 << 10)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/8] drm/i915: Replace some accidental I915_READ_FW()s with the normal version
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
2019-10-22 17:55 ` [PATCH 1/8] drm/i915: Parametrize PFIT_PIPE Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 3/8] drm/i915: Fix skl+ non-scaled pfit modes Ville Syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Some I915_READ_FW()s have snuck in where we don't hold the uncore lock.
Replace with the normal thing for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 236fdf122e47..85c82e3f3223 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5657,10 +5657,10 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
- I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
- I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
+ I915_WRITE(SKL_PS_VPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+ I915_WRITE(SKL_PS_HPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/8] drm/i915: Fix skl+ non-scaled pfit modes
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
2019-10-22 17:55 ` [PATCH 1/8] drm/i915: Parametrize PFIT_PIPE Ville Syrjala
2019-10-22 17:55 ` [PATCH 2/8] drm/i915: Replace some accidental I915_READ_FW()s with the normal version Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 4/8] drm/i915: Flatten a bunch of the pfit functions Ville Syrjala
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix skl_update_scaler_crtc() to deal with different scaling
modes correctly. The current implementation assumes
DRM_MODE_SCALE_FULLSCREEN. Fortunately we don't expose any
border properties currently so the code does actually end
up doing the right thing (assigning a scaler for pfit).
The code does need to be fixed before any borders are
exposed.
Also we have redundant calls to skl_update_scaler_crtc() in
dp/hdmi .compute_config() which can be nuked. They were anyway
called before we had even computed the pfit state so were
basically nonsense. The real call we need to keep is in
intel_crtc_atomic_check().
v2: Deal witrh skl_update_scaler_crtc() in intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_dp.c | 15 --------
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ----
4 files changed, 19 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 85c82e3f3223..a811e7872fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5514,28 +5514,28 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
return 0;
}
-/**
- * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
- *
- * @state: crtc's scaler state
- *
- * Return
- * 0 - scaler_usage updated successfully
- * error - requested scaling cannot be supported or other error condition
- */
-int skl_update_scaler_crtc(struct intel_crtc_state *state)
+static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
{
- const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
- bool need_scaler = false;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ int width, height;
- if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- need_scaler = true;
+ if (crtc_state->pch_pfit.enabled) {
+ u32 pfit_size = crtc_state->pch_pfit.size;
+
+ width = pfit_size >> 16;
+ height = pfit_size & 0xffff;
+ } else {
+ width = adjusted_mode->crtc_hdisplay;
+ height = adjusted_mode->crtc_vdisplay;
+ }
- return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
- &state->scaler_state.scaler_id,
- state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_vdisplay, NULL, need_scaler);
+ return skl_update_scaler(crtc_state, !crtc_state->base.active,
+ SKL_CRTC_INDEX,
+ &crtc_state->scaler_state.scaler_id,
+ crtc_state->pipe_src_w, crtc_state->pipe_src_h,
+ width, height, NULL,
+ crtc_state->pch_pfit.enabled);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 7dcb176d91b0..852f0da0b60e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -562,7 +562,6 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
-int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(const struct intel_crtc_state *crtc_state,
const struct drm_format_info *format);
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5eeafa45831a..0b38b81de508 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2245,7 +2245,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- int ret;
if (!drm_mode_is_420_only(info, adjusted_mode) ||
!intel_dp_get_colorimetry_status(intel_dp) ||
@@ -2254,13 +2253,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- /* YCBCR 420 output conversion needs a scaler */
- ret = skl_update_scaler_crtc(crtc_state);
- if (ret) {
- DRM_DEBUG_KMS("Scaler allocation for output failed\n");
- return ret;
- }
-
intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
return 0;
@@ -2327,7 +2319,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
else
ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
pipe_config);
-
if (ret)
return ret;
@@ -2343,12 +2334,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
adjusted_mode);
- if (INTEL_GEN(dev_priv) >= 9) {
- ret = skl_update_scaler_crtc(pipe_config);
- if (ret)
- return ret;
- }
-
if (HAS_GMCH(dev_priv))
intel_gmch_panel_fitting(intel_crtc, pipe_config,
conn_state->scaling_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..98688dfc2dee 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2290,12 +2290,6 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- /* YCBCR 420 output conversion needs a scaler */
- if (skl_update_scaler_crtc(config)) {
- DRM_DEBUG_KMS("Scaler allocation for output failed\n");
- return false;
- }
-
intel_pch_panel_fitting(intel_crtc, config,
DRM_MODE_SCALE_FULLSCREEN);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/8] drm/i915: Flatten a bunch of the pfit functions
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (2 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 3/8] drm/i915: Fix skl+ non-scaled pfit modes Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 5/8] drm/i915: Use drm_rect to store the pfit window pos/size Ville Syrjala
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Most of the pfit functions are of the form:
func()
{
if (pfit_enabled) {
...
}
}
Flip the pfit_enabled check around to flatten the functions.
And while we're touching all this let's do the usual
s/pipe_config/crtc_state/ replacement.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 207 +++++++++----------
drivers/gpu/drm/i915/intel_pm.c | 38 ++--
2 files changed, 119 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a811e7872fe7..6aeec01e2d24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5636,34 +5636,34 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
+ u16 uv_rgb_hphase, uv_rgb_vphase;
+ int pfit_w, pfit_h, hscale, vscale;
+ int id;
- if (crtc_state->pch_pfit.enabled) {
- u16 uv_rgb_hphase, uv_rgb_vphase;
- int pfit_w, pfit_h, hscale, vscale;
- int id;
+ if (!crtc_state->pch_pfit.enabled)
+ return;
- if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
- return;
+ if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
+ return;
- pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
- pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
+ pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
+ pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
- hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
- vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+ hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
+ vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
- uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
- uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
+ uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
+ uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
- id = scaler_state->scaler_id;
- I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
- PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
- I915_WRITE(SKL_PS_VPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
- I915_WRITE(SKL_PS_HPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
- I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
- I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
- }
+ id = scaler_state->scaler_id;
+ I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
+ PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+ I915_WRITE(SKL_PS_VPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+ I915_WRITE(SKL_PS_HPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
+ I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
+ I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
}
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -5672,19 +5672,20 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (crtc_state->pch_pfit.enabled) {
- /* Force use of hard-coded filter coefficients
- * as some pre-programmed values are broken,
- * e.g. x201.
- */
- if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
- PF_PIPE_SEL_IVB(pipe));
- else
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
- }
+ if (!crtc_state->pch_pfit.enabled)
+ return;
+
+ /* Force use of hard-coded filter coefficients
+ * as some pre-programmed values are broken,
+ * e.g. x201.
+ */
+ if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
+ PF_PIPE_SEL_IVB(pipe));
+ else
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
+ I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
}
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
@@ -6572,11 +6573,12 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
/* To avoid upsetting the power well on haswell only disable the pfit if
* it's in use. The hw state code will make sure we get this right. */
- if (old_crtc_state->pch_pfit.enabled) {
- I915_WRITE(PF_CTL(pipe), 0);
- I915_WRITE(PF_WIN_POS(pipe), 0);
- I915_WRITE(PF_WIN_SZ(pipe), 0);
- }
+ if (!old_crtc_state->pch_pfit.enabled)
+ return;
+
+ I915_WRITE(PF_CTL(pipe), 0);
+ I915_WRITE(PF_WIN_POS(pipe), 0);
+ I915_WRITE(PF_WIN_SZ(pipe), 0);
}
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
@@ -7395,39 +7397,35 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}
-static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
+static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
- u32 pixel_rate;
-
- pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
+ u32 pixel_rate = crtc_state->base.adjusted_mode.crtc_clock;
+ u32 pfit_size = crtc_state->pch_pfit.size;
+ u64 pipe_w, pipe_h, pfit_w, pfit_h;
/*
* We only use IF-ID interlacing. If we ever use
* PF-ID we'll need to adjust the pixel_rate here.
*/
- if (pipe_config->pch_pfit.enabled) {
- u64 pipe_w, pipe_h, pfit_w, pfit_h;
- u32 pfit_size = pipe_config->pch_pfit.size;
+ if (!crtc_state->pch_pfit.enabled)
+ return pixel_rate;
- pipe_w = pipe_config->pipe_src_w;
- pipe_h = pipe_config->pipe_src_h;
+ pipe_w = crtc_state->pipe_src_w;
+ pipe_h = crtc_state->pipe_src_h;
- pfit_w = (pfit_size >> 16) & 0xFFFF;
- pfit_h = pfit_size & 0xFFFF;
- if (pipe_w < pfit_w)
- pipe_w = pfit_w;
- if (pipe_h < pfit_h)
- pipe_h = pfit_h;
+ pfit_w = (pfit_size >> 16) & 0xFFFF;
+ pfit_h = pfit_size & 0xFFFF;
+ if (pipe_w < pfit_w)
+ pipe_w = pfit_w;
+ if (pipe_h < pfit_h)
+ pipe_h = pfit_h;
- if (WARN_ON(!pfit_w || !pfit_h))
- return pixel_rate;
+ if (WARN_ON(!pfit_w || !pfit_h))
+ return pixel_rate;
- pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
- pfit_w * pfit_h);
- }
-
- return pixel_rate;
+ return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
+ pfit_w * pfit_h);
}
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
@@ -8595,9 +8593,9 @@ static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
}
-static void i9xx_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
@@ -8617,8 +8615,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
return;
}
- pipe_config->gmch_pfit.control = tmp;
- pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
+ crtc_state->gmch_pfit.control = tmp;
+ crtc_state->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
}
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
@@ -8864,7 +8862,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- i9xx_get_pfit_config(crtc, pipe_config);
+ i9xx_get_pfit_config(pipe_config);
if (INTEL_GEN(dev_priv) >= 4) {
/* No way to read it out on pipes B and C */
@@ -9811,35 +9809,35 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
-static void skylake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
- u32 ps_ctrl = 0;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
int id = -1;
int i;
/* find scaler attached to this pipe */
for (i = 0; i < crtc->num_scalers; i++) {
- ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
- if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
- id = i;
- pipe_config->pch_pfit.enabled = true;
- pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
- pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
- scaler_state->scalers[i].in_use = true;
- break;
- }
+ u32 tmp;
+
+ tmp = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
+ if ((tmp & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ continue;
+
+ id = i;
+ crtc_state->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
+ crtc_state->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
+ scaler_state->scalers[i].in_use = true;
+ break;
}
scaler_state->scaler_id = id;
- if (id >= 0) {
+ if (id >= 0)
scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
- } else {
+ else
scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
- }
}
static void
@@ -9969,28 +9967,27 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
kfree(intel_fb);
}
-static void ironlake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void ironlake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
tmp = I915_READ(PF_CTL(crtc->pipe));
+ if ((tmp & PF_ENABLE) == 0)
+ return;
- if (tmp & PF_ENABLE) {
- pipe_config->pch_pfit.enabled = true;
- pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
- pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
-
- /* We currently do not free assignements of panel fitters on
- * ivb/hsw (since we don't use the higher upscaling modes which
- * differentiates them) so just WARN about this case for now. */
- if (IS_GEN(dev_priv, 7)) {
- WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
- PF_PIPE_SEL_IVB(crtc->pipe));
- }
- }
+ /*
+ * We currently do not free assignements of panel fitters on
+ * ivb/hsw (since we don't use the higher upscaling modes which
+ * differentiates them) so just WARN about this case for now.
+ */
+ WARN_ON(IS_GEN(dev_priv, 7) &&
+ (tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
+
+ crtc_state->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
+ crtc_state->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -10101,7 +10098,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- ironlake_get_pfit_config(crtc, pipe_config);
+ ironlake_get_pfit_config(pipe_config);
ret = true;
@@ -10609,9 +10606,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
power_domain_mask |= BIT_ULL(power_domain);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_get_pfit_config(crtc, pipe_config);
+ skylake_get_pfit_config(pipe_config);
else
- ironlake_get_pfit_config(crtc, pipe_config);
+ ironlake_get_pfit_config(pipe_config);
}
if (hsw_crtc_supports_ips(crtc)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 362234449087..80ea5074cabd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4101,33 +4101,29 @@ static uint_fixed_16_16_t
skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
{
uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
+ u32 src_w, src_h, dst_w, dst_h;
+ u32 pfit_size = crtc_state->pch_pfit.size;
+ uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
+ uint_fixed_16_16_t downscale_h, downscale_w;
- if (!crtc_state->base.enable)
+ if (!crtc_state->base.enable ||
+ !crtc_state->pch_pfit.enabled)
return pipe_downscale;
- if (crtc_state->pch_pfit.enabled) {
- u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
- uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
- uint_fixed_16_16_t downscale_h, downscale_w;
+ src_w = crtc_state->pipe_src_w;
+ src_h = crtc_state->pipe_src_h;
+ dst_w = pfit_size >> 16;
+ dst_h = pfit_size & 0xffff;
- src_w = crtc_state->pipe_src_w;
- src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0xffff;
-
- if (!dst_w || !dst_h)
- return pipe_downscale;
-
- fp_w_ratio = div_fixed16(src_w, dst_w);
- fp_h_ratio = div_fixed16(src_h, dst_h);
- downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
- downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
+ if (!dst_w || !dst_h)
+ return pipe_downscale;
- pipe_downscale = mul_fixed16(downscale_w, downscale_h);
- }
+ fp_w_ratio = div_fixed16(src_w, dst_w);
+ fp_h_ratio = div_fixed16(src_h, dst_h);
+ downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
+ downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
- return pipe_downscale;
+ return mul_fixed16(downscale_w, downscale_h);
}
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/8] drm/i915: Use drm_rect to store the pfit window pos/size
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (3 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 4/8] drm/i915: Flatten a bunch of the pfit functions Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 6/8] drm/i915: s/pipe_config/crtc_state/ in pfit functions Ville Syrjala
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make things a bit more abstract by replacing the pch_pfit.pos/size
raw register values with a drm_rect. Makes it slighly more convenient
to eg. compute the scaling factors.
v2: Use drm_rect_init()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 79 ++++++++++++-------
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/display/intel_panel.c | 13 ++-
drivers/gpu/drm/i915/intel_pm.c | 5 +-
4 files changed, 60 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6aeec01e2d24..38df154123d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5521,10 +5521,8 @@ static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
int width, height;
if (crtc_state->pch_pfit.enabled) {
- u32 pfit_size = crtc_state->pch_pfit.size;
-
- width = pfit_size >> 16;
- height = pfit_size & 0xffff;
+ width = drm_rect_width(&crtc_state->pch_pfit.dst);
+ height = drm_rect_height(&crtc_state->pch_pfit.dst);
} else {
width = adjusted_mode->crtc_hdisplay;
height = adjusted_mode->crtc_vdisplay;
@@ -5633,11 +5631,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
+ struct drm_rect src = {
+ .x2 = crtc_state->pipe_src_w << 16,
+ .y2 = crtc_state->pipe_src_h << 16,
+ };
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
u16 uv_rgb_hphase, uv_rgb_vphase;
- int pfit_w, pfit_h, hscale, vscale;
+ enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
+ int hscale, vscale;
int id;
if (!crtc_state->pch_pfit.enabled)
@@ -5646,11 +5653,8 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
- pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
- pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
-
- hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
- vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+ hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
+ vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -5662,15 +5666,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
I915_WRITE(SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
- I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
- I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
+ I915_WRITE(SKL_PS_WIN_POS(pipe, id), x << 16 | y);
+ I915_WRITE(SKL_PS_WIN_SZ(pipe, id), width << 16 | height);
}
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
if (!crtc_state->pch_pfit.enabled)
return;
@@ -5684,8 +5693,8 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
PF_PIPE_SEL_IVB(pipe));
else
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
+ I915_WRITE(PF_WIN_POS(pipe), x << 16 | y);
+ I915_WRITE(PF_WIN_SZ(pipe), width << 16 | height);
}
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
@@ -7400,8 +7409,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate = crtc_state->base.adjusted_mode.crtc_clock;
- u32 pfit_size = crtc_state->pch_pfit.size;
- u64 pipe_w, pipe_h, pfit_w, pfit_h;
+ unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
/*
* We only use IF-ID interlacing. If we ever use
@@ -7414,8 +7422,9 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
pipe_w = crtc_state->pipe_src_w;
pipe_h = crtc_state->pipe_src_h;
- pfit_w = (pfit_size >> 16) & 0xFFFF;
- pfit_h = pfit_size & 0xFFFF;
+ pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
+ pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
+
if (pipe_w < pfit_w)
pipe_w = pfit_w;
if (pipe_h < pfit_h)
@@ -9809,6 +9818,14 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
+static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
+ u32 pos, u32 size)
+{
+ drm_rect_init(&crtc_state->pch_pfit.dst,
+ pos >> 16, pos & 0xffff,
+ size >> 16, size & 0xffff);
+}
+
static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -9827,8 +9844,11 @@ static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
id = i;
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
- crtc_state->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
+
+ ilk_get_pfit_pos_size(crtc_state,
+ I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)),
+ I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)));
+
scaler_state->scalers[i].in_use = true;
break;
}
@@ -9986,8 +10006,10 @@ static void ironlake_get_pfit_config(struct intel_crtc_state *crtc_state)
(tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
- crtc_state->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
+
+ ilk_get_pfit_pos_size(crtc_state,
+ I915_READ(PF_WIN_POS(crtc->pipe)),
+ I915_READ(PF_WIN_SZ(crtc->pipe)));
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -12383,9 +12405,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->gmch_pfit.pgm_ratios,
pipe_config->gmch_pfit.lvds_border_bits);
else
- DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
- pipe_config->pch_pfit.pos,
- pipe_config->pch_pfit.size,
+ DRM_DEBUG_KMS("pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+ DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
enableddisabled(pipe_config->pch_pfit.enabled),
yesno(pipe_config->pch_pfit.force_thru));
@@ -13058,8 +13079,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
if (current_config->pch_pfit.enabled) {
- PIPE_CONF_CHECK_X(pch_pfit.pos);
- PIPE_CONF_CHECK_X(pch_pfit.size);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8358152e403e..ab4ec6215c22 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -902,8 +902,7 @@ struct intel_crtc_state {
/* Panel fitter placement and size for Ironlake+ */
struct {
- u32 pos;
- u32 size;
+ struct drm_rect dst;
bool enabled;
bool force_thru;
} pch_pfit;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 4601416c603e..68257b21abf5 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -179,13 +179,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
int fitting_mode)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- int x = 0, y = 0, width = 0, height = 0;
+ int x, y, width, height;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- goto done;
+ return;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
@@ -231,14 +231,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
break;
default:
- WARN(1, "bad panel fit mode: %d\n", fitting_mode);
+ MISSING_CASE(fitting_mode);
return;
}
-done:
- pipe_config->pch_pfit.pos = (x << 16) | y;
- pipe_config->pch_pfit.size = (width << 16) | height;
- pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
+ drm_rect_init(&pipe_config->pch_pfit.dst,
+ x, y, width, height);
+ pipe_config->pch_pfit.enabled = true;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 80ea5074cabd..e7ce80acdd45 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4102,7 +4102,6 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
{
uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
@@ -4112,8 +4111,8 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
src_w = crtc_state->pipe_src_w;
src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0xffff;
+ dst_w = drm_rect_width(&crtc_state->pch_pfit.dst);
+ dst_h = drm_rect_height(&crtc_state->pch_pfit.dst);
if (!dst_w || !dst_h)
return pipe_downscale;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 6/8] drm/i915: s/pipe_config/crtc_state/ in pfit functions
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (4 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 5/8] drm/i915: Use drm_rect to store the pfit window pos/size Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 7/8] drm/i915: Pass connector state to pfit calculations Ville Syrjala
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Follow the new naming convention and call the crtc state
"crtc_state", and while at it drop the redundant crtc argument.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c | 92 +++++++++++-----------
drivers/gpu/drm/i915/display/intel_panel.h | 6 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +-
7 files changed, 57 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..627cbd880224 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1265,7 +1265,6 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
@@ -1273,7 +1272,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state->scaling_mode);
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0b38b81de508..dcd6b96de9ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2244,7 +2244,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
if (!drm_mode_is_420_only(info, adjusted_mode) ||
!intel_dp_get_colorimetry_status(intel_dp) ||
@@ -2253,7 +2252,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, DRM_MODE_SCALE_FULLSCREEN);
return 0;
}
@@ -2301,7 +2300,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
enum port port = encoder->port;
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
@@ -2335,10 +2333,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(intel_crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
else
- intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 98688dfc2dee..0a7dc78db307 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2281,8 +2281,6 @@ static bool
intel_hdmi_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *config)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
-
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
return false;
@@ -2290,8 +2288,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(intel_crtc, config,
- DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(config, DRM_MODE_SCALE_FULLSCREEN);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 13841d7c455b..09493505940b 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -430,10 +430,10 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (HAS_PCH_SPLIT(dev_priv)) {
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
} else {
- intel_gmch_panel_fitting(intel_crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 68257b21abf5..35125aa97a9f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -174,23 +174,23 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
/* adjusted_mode has been preset to be the panel's fixed mode */
void
-intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *pipe_config,
+intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
int x, y, width, height;
/* Native modes don't need fitting */
- if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
- adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
- pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+ if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
+ adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
- width = pipe_config->pipe_src_w;
- height = pipe_config->pipe_src_h;
+ width = crtc_state->pipe_src_w;
+ height = crtc_state->pipe_src_h;
x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
break;
@@ -199,18 +199,18 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
/* Scale but preserve the aspect ratio */
{
u32 scaled_width = adjusted_mode->crtc_hdisplay
- * pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w
+ * crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w
* adjusted_mode->crtc_vdisplay;
if (scaled_width > scaled_height) { /* pillar */
- width = scaled_height / pipe_config->pipe_src_h;
+ width = scaled_height / crtc_state->pipe_src_h;
if (width & 1)
width++;
x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
y = 0;
height = adjusted_mode->crtc_vdisplay;
} else if (scaled_width < scaled_height) { /* letter */
- height = scaled_width / pipe_config->pipe_src_w;
+ height = scaled_width / crtc_state->pipe_src_w;
if (height & 1)
height++;
y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
@@ -235,9 +235,9 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
return;
}
- drm_rect_init(&pipe_config->pch_pfit.dst,
+ drm_rect_init(&crtc_state->pch_pfit.dst,
x, y, width, height);
- pipe_config->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.enabled = true;
}
static void
@@ -296,13 +296,13 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
return (FACTOR * ratio + FACTOR/2) / FACTOR;
}
-static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
+static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
u32 *pfit_control)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
- pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w *
+ crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w *
adjusted_mode->crtc_vdisplay;
/* 965+ is easy, it does everything in hw */
@@ -312,18 +312,18 @@ static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
else if (scaled_width < scaled_height)
*pfit_control |= PFIT_ENABLE |
PFIT_SCALING_LETTER;
- else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w)
+ else if (adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w)
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
}
-static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
+static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
u32 *pfit_control, u32 *pfit_pgm_ratios,
u32 *border)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
- pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w *
+ crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w *
adjusted_mode->crtc_vdisplay;
u32 bits;
@@ -335,11 +335,11 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
if (scaled_width > scaled_height) { /* pillar */
centre_horizontally(adjusted_mode,
scaled_height /
- pipe_config->pipe_src_h);
+ crtc_state->pipe_src_h);
*border = LVDS_BORDER_ENABLE;
- if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) {
- bits = panel_fitter_scaling(pipe_config->pipe_src_h,
+ if (crtc_state->pipe_src_h != adjusted_mode->crtc_vdisplay) {
+ bits = panel_fitter_scaling(crtc_state->pipe_src_h,
adjusted_mode->crtc_vdisplay);
*pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
@@ -351,11 +351,11 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
} else if (scaled_width < scaled_height) { /* letter */
centre_vertically(adjusted_mode,
scaled_width /
- pipe_config->pipe_src_w);
+ crtc_state->pipe_src_w);
*border = LVDS_BORDER_ENABLE;
- if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
- bits = panel_fitter_scaling(pipe_config->pipe_src_w,
+ if (crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) {
+ bits = panel_fitter_scaling(crtc_state->pipe_src_w,
adjusted_mode->crtc_hdisplay);
*pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
@@ -373,17 +373,17 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
}
}
-void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *pipe_config,
+void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode)
{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
/* Native modes don't need fitting */
- if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
- adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
+ if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
+ adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h)
goto out;
switch (fitting_mode) {
@@ -392,16 +392,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
* For centered modes, we have to calculate border widths &
* heights and modify the values programmed into the CRTC.
*/
- centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
- centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
+ centre_horizontally(adjusted_mode, crtc_state->pipe_src_w);
+ centre_vertically(adjusted_mode, crtc_state->pipe_src_h);
border = LVDS_BORDER_ENABLE;
break;
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
if (INTEL_GEN(dev_priv) >= 4)
- i965_scale_aspect(pipe_config, &pfit_control);
+ i965_scale_aspect(crtc_state, &pfit_control);
else
- i9xx_scale_aspect(pipe_config, &pfit_control,
+ i9xx_scale_aspect(crtc_state, &pfit_control,
&pfit_pgm_ratios, &border);
break;
case DRM_MODE_SCALE_FULLSCREEN:
@@ -409,8 +409,8 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
* Full scaling, even if it changes the aspect ratio.
* Fortunately this is all done for us in hw.
*/
- if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
- pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
+ if (crtc_state->pipe_src_h != adjusted_mode->crtc_vdisplay ||
+ crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) {
pfit_control |= PFIT_ENABLE;
if (INTEL_GEN(dev_priv) >= 4)
pfit_control |= PFIT_SCALING_AUTO;
@@ -429,7 +429,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
if (INTEL_GEN(dev_priv) >= 4)
- pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY;
+ pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
@@ -438,12 +438,12 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
}
/* Make sure pre-965 set dither correctly for 18bpp panels. */
- if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
+ if (INTEL_GEN(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
- pipe_config->gmch_pfit.control = pfit_control;
- pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
- pipe_config->gmch_pfit.lvds_border_bits = border;
+ crtc_state->gmch_pfit.control = pfit_control;
+ crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
+ crtc_state->gmch_pfit.lvds_border_bits = border;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index cedeea443336..e1804e6e8325 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -25,11 +25,9 @@ int intel_panel_init(struct intel_panel *panel,
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
-void intel_pch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config,
+void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode);
-void intel_gmch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config,
+void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 50064cde0724..6a20c4169a53 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -261,7 +261,6 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int ret;
@@ -273,10 +272,10 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
else
- intel_pch_panel_fitting(crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 7/8] drm/i915: Pass connector state to pfit calculations
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (5 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 6/8] drm/i915: s/pipe_config/crtc_state/ in pfit functions Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-22 17:55 ` [PATCH 8/8] drm/i915: Have pfit calculations return an error code Ville Syrjala
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass the entire connector state to intel_{gmch,pch}_panel_fitting().
For now we just need to get at .scaling_mode but in the future we'll
want access to the margin properties as well.
v2: Deal with intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++---------
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_lvds.c | 7 ++-----
drivers/gpu/drm/i915/display/intel_panel.c | 16 ++++++++++------
drivers/gpu/drm/i915/display/intel_panel.h | 4 ++--
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 ++----
7 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 627cbd880224..d252f68e5d09 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1272,7 +1272,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(pipe_config, conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dcd6b96de9ac..8ca35ba91731 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2238,9 +2238,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
static int
intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
- struct drm_connector *connector,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
+ struct drm_connector *connector = conn_state->connector;
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
@@ -2252,7 +2253,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, conn_state);
return 0;
}
@@ -2315,8 +2316,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (lspcon->active)
lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
else
- ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
- pipe_config);
+ ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
+ conn_state);
if (ret)
return ret;
@@ -2333,11 +2334,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0a7dc78db307..426dec979992 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2278,17 +2278,19 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
}
static bool
-intel_hdmi_ycbcr420_config(struct drm_connector *connector,
- struct intel_crtc_state *config)
+intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
+ struct drm_connector *connector = conn_state->connector;
+
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
return false;
}
- config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(config, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, conn_state);
return true;
}
@@ -2418,7 +2420,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->pixel_multiplier = 2;
if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
- if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
+ if (!intel_hdmi_ycbcr420_config(pipe_config, conn_state)) {
DRM_ERROR("Can't support YCBCR420 output\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 09493505940b..03e8da7797dc 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -430,12 +430,9 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (HAS_PCH_SPLIT(dev_priv)) {
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
} else {
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
-
+ intel_gmch_panel_fitting(pipe_config, conn_state);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 35125aa97a9f..2981d1751877 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -175,7 +175,7 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
/* adjusted_mode has been preset to be the panel's fixed mode */
void
intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode)
+ const struct drm_connector_state *conn_state)
{
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
@@ -187,7 +187,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return;
- switch (fitting_mode) {
+ switch (conn_state->scaling_mode) {
case DRM_MODE_SCALE_CENTER:
width = crtc_state->pipe_src_w;
height = crtc_state->pipe_src_h;
@@ -224,6 +224,10 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
}
break;
+ case DRM_MODE_SCALE_NONE:
+ WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w);
+ WARN_ON(adjusted_mode->crtc_vdisplay != crtc_state->pipe_src_h);
+ /* fall through */
case DRM_MODE_SCALE_FULLSCREEN:
x = y = 0;
width = adjusted_mode->crtc_hdisplay;
@@ -231,7 +235,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
break;
default:
- MISSING_CASE(fitting_mode);
+ MISSING_CASE(conn_state->scaling_mode);
return;
}
@@ -374,7 +378,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
}
void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode)
+ const struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -386,7 +390,7 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h)
goto out;
- switch (fitting_mode) {
+ switch (conn_state->scaling_mode) {
case DRM_MODE_SCALE_CENTER:
/*
* For centered modes, we have to calculate border widths &
@@ -422,7 +426,7 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
}
break;
default:
- WARN(1, "bad panel fit mode: %d\n", fitting_mode);
+ MISSING_CASE(conn_state->scaling_mode);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index e1804e6e8325..e2fa1543a61f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -26,9 +26,9 @@ void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode);
+ const struct drm_connector_state *conn_state);
void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode);
+ const struct drm_connector_state *conn_state);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 6a20c4169a53..9f4f7c670cc8 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -272,11 +272,9 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 8/8] drm/i915: Have pfit calculations return an error code
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (6 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 7/8] drm/i915: Pass connector state to pfit calculations Ville Syrjala
@ 2019-10-22 17:55 ` Ville Syrjala
2019-10-23 0:44 ` ✓ Fi.CI.BAT: success for drm/i915: pfit/scaler rework prep stuff Patchwork
2019-10-23 16:13 ` [Intel-gfx] " Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2019-10-22 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Change intel_{gmch,pch}_panel_fitting() to return a normal
error vs. success int. We'll need this later to validate that
the margin properties aren't misconfigured.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++-----
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++-----------
drivers/gpu/drm/i915/display/intel_lvds.c | 13 ++++++++-----
drivers/gpu/drm/i915/display/intel_panel.c | 19 +++++++++++--------
drivers/gpu/drm/i915/display/intel_panel.h | 6 +++---
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 ++++--
7 files changed, 49 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d252f68e5d09..2010ad991876 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1266,13 +1266,17 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
const struct drm_display_mode *fixed_mode =
- intel_connector->panel.fixed_mode;
+ intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->base.adjusted_mode;
+ int ret;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(pipe_config, conn_state);
+
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ca35ba91731..50cebd5bf8eb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2253,9 +2253,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, conn_state);
-
- return 0;
+ return intel_pch_panel_fitting(crtc_state, conn_state);
}
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
@@ -2334,9 +2332,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config, conn_state);
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config, conn_state);
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 426dec979992..e9ef3964be5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2277,22 +2277,25 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
return true;
}
-static bool
+static int
intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
struct drm_connector *connector = conn_state->connector;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+
+ if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
+ return 0;
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
- return false;
+ return -EINVAL;
}
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, conn_state);
-
- return true;
+ return intel_pch_panel_fitting(crtc_state, conn_state);
}
static int intel_hdmi_port_clock(int clock, int bpc)
@@ -2419,12 +2422,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
pipe_config->pixel_multiplier = 2;
- if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
- if (!intel_hdmi_ycbcr420_config(pipe_config, conn_state)) {
- DRM_ERROR("Can't support YCBCR420 output\n");
- return -EINVAL;
- }
- }
+ ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
+ if (ret)
+ return ret;
pipe_config->limited_color_range =
intel_hdmi_limited_color_range(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 03e8da7797dc..751abbc63daa 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -395,6 +395,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
unsigned int lvds_bpp;
+ int ret;
/* Should never happen!! */
if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
@@ -427,13 +428,15 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev_priv))
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(pipe_config, conn_state);
- } else {
- intel_gmch_panel_fitting(pipe_config, conn_state);
- }
+ if (HAS_GMCH(dev_priv))
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
+ else
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
/*
* XXX: It would be nice to support lower refresh rates on the
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 2981d1751877..5a8b5a747579 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -173,9 +173,8 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
}
/* adjusted_mode has been preset to be the panel's fixed mode */
-void
-intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
@@ -185,7 +184,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- return;
+ return 0;
switch (conn_state->scaling_mode) {
case DRM_MODE_SCALE_CENTER:
@@ -236,12 +235,14 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
default:
MISSING_CASE(conn_state->scaling_mode);
- return;
+ return -EINVAL;
}
drm_rect_init(&crtc_state->pch_pfit.dst,
x, y, width, height);
crtc_state->pch_pfit.enabled = true;
+
+ return 0;
}
static void
@@ -377,8 +378,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
}
}
-void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -427,7 +428,7 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
break;
default:
MISSING_CASE(conn_state->scaling_mode);
- return;
+ return -EINVAL;
}
/* 965+ wants fuzzy fitting */
@@ -448,6 +449,8 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
crtc_state->gmch_pfit.control = pfit_control;
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
crtc_state->gmch_pfit.lvds_border_bits = border;
+
+ return 0;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index e2fa1543a61f..a5c93232eb6f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -25,10 +25,10 @@ int intel_panel_init(struct intel_panel *panel,
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
-void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
+int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 9f4f7c670cc8..7b0007faa579 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -272,9 +272,11 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config, conn_state);
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config, conn_state);
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: pfit/scaler rework prep stuff
2019-10-22 17:55 [PATCH 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
` (7 preceding siblings ...)
2019-10-22 17:55 ` [PATCH 8/8] drm/i915: Have pfit calculations return an error code Ville Syrjala
@ 2019-10-23 0:44 ` Patchwork
2019-10-23 16:13 ` [Intel-gfx] " Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-10-23 0:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14934
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14934:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem:
- {fi-tgl-u2}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-tgl-u2/igt@i915_selftest@live_gem.html
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-tgl-u/igt@i915_selftest@live_gem.html
Known issues
------------
Here are the changes found in Patchwork_14934 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111045] / [fdo#111096])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111880]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u/igt@gem_sync@basic-many-each.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-tgl-u/igt@gem_sync@basic-many-each.html
* igt@i915_selftest@live_requests:
- {fi-tgl-u2}: [INCOMPLETE][7] ([fdo#112057]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u2/igt@i915_selftest@live_requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-tgl-u2/igt@i915_selftest@live_requests.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}: [DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 41)
------------------------------
Additional (1): fi-bxt-dsi
Missing (12): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-u3 fi-pnv-d510 fi-icl-y fi-icl-dsi fi-bdw-samus fi-cml-u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7155 -> Patchwork_14934
CI-20190529: 20190529
CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14934: 4318419709ea5e8134ba03123f64ec7e6d40d4c5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4318419709ea drm/i915: Have pfit calculations return an error code
e03d0a60c7a9 drm/i915: Pass connector state to pfit calculations
6a0b9bd3bfd7 drm/i915: s/pipe_config/crtc_state/ in pfit functions
6492dc5c6071 drm/i915: Use drm_rect to store the pfit window pos/size
d9f9af9a8574 drm/i915: Flatten a bunch of the pfit functions
999fc29e7186 drm/i915: Fix skl+ non-scaled pfit modes
2ce65398221d drm/i915: Replace some accidental I915_READ_FW()s with the normal version
71d6e1c4e7b7 drm/i915: Parametrize PFIT_PIPE
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: pfit/scaler rework prep stuff
@ 2019-10-23 16:13 ` Patchwork
0 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-10-23 16:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14934_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14934_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-c-cursor-size-change:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-size-change.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-size-change.html
Known issues
------------
Here are the changes found in Patchwork_14934_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolation@vcs1-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][5] -> [FAIL][6] ([fdo#111925])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_eio@in-flight-contexts-immediate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb5/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +6 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@i915_suspend@sysfs-reader.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +7 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [fdo#110403])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][29] -> [FAIL][30] ([fdo#103166])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#112080]) +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: [INCOMPLETE][37] ([fdo#103665]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_ctx_isolation@vecs0-s3.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-kbl1/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][39] ([fdo#110841]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][41] ([fdo#112080]) -> [PASS][42] +10 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][43] ([fdo#111325]) -> [PASS][44] +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [DMESG-WARN][45] ([fdo#111870]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-apl: [INCOMPLETE][49] ([fdo#103927]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl3/igt@gem_userptr_blits@unsync-unmap-cycles.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-apl5/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-context:
- {shard-tglb}: [INCOMPLETE][51] ([fdo#111832] / [fdo#111850]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-tglb6/igt@gem_workarounds@suspend-resume-context.html
* {igt@i915_pm_dc@dc6-dpms}:
- shard-iclb: [FAIL][53] ([fdo#110548]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@system-suspend:
- {shard-tglb}: [INCOMPLETE][55] ([fdo#111747] / [fdo#111850]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-tglb5/igt@i915_pm_rpm@system-suspend.html
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb4/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-iclb: [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: [FAIL][61] ([fdo#111609]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@kms_flip@dpms-vs-vblank-race.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-glk3/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][63] ([fdo#105363]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-iclb: [FAIL][65] ([fdo#103167]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- {shard-tglb}: [FAIL][67] ([fdo#103167]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][69] ([fdo#108145] / [fdo#110403]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@short-reads:
- shard-glk: [TIMEOUT][73] ([fdo#103183]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk9/igt@perf@short-reads.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-glk5/igt@perf@short-reads.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +11 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][77] ([fdo#109276]) -> [FAIL][78] ([fdo#111330]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
[fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
[fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111925]: https://bugs.freedesktop.org/show_bug.cgi?id=111925
[fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7155 -> Patchwork_14934
CI-20190529: 20190529
CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14934: 4318419709ea5e8134ba03123f64ec7e6d40d4c5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread