* [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc
@ 2019-10-22 13:34 Jani Nikula
2019-10-22 13:34 ` [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config Jani Nikula
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Jani Nikula @ 2019-10-22 13:34 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Reduce verbosity in code by renaming dsc_params member of crtc state to
simply dsc. There is enough context for this to be clear. No functional
changes.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++-----
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 68 +++++++++----------
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ba794cb9b4f..1a49266f4f57 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2234,7 +2234,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
/*
* VDSC power is needed when DSC is enabled
*/
- if (crtc_state->dsc_params.compression_enable)
+ if (crtc_state->dsc.compression_enable)
intel_display_power_get(dev_priv,
intel_dsc_power_domain(crtc_state));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8358152e403e..db66f9d623f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -986,7 +986,7 @@ struct intel_crtc_state {
bool dsc_split;
u16 compressed_bpp;
u8 slice_count;
- } dsc_params;
+ } dsc;
struct drm_dsc_config dp_dsc_cfg;
/* Forward Error correction State */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5eeafa45831a..521ce23f38ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2080,10 +2080,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc_params.compressed_bpp =
+ pipe_config->dsc.compressed_bpp =
min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
pipe_config->pipe_bpp);
- pipe_config->dsc_params.slice_count =
+ pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else {
@@ -2104,10 +2104,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
return -EINVAL;
}
- pipe_config->dsc_params.compressed_bpp = min_t(u16,
+ pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
pipe_config->pipe_bpp);
- pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
+ pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
@@ -2115,8 +2115,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* then we need to use 2 VDSC instances.
*/
if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
- if (pipe_config->dsc_params.slice_count > 1) {
- pipe_config->dsc_params.dsc_split = true;
+ if (pipe_config->dsc.slice_count > 1) {
+ pipe_config->dsc.dsc_split = true;
} else {
DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
return -EINVAL;
@@ -2128,16 +2128,16 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
"Compressed BPP = %d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc_params.compressed_bpp);
+ pipe_config->dsc.compressed_bpp);
return ret;
}
- pipe_config->dsc_params.compression_enable = true;
+ pipe_config->dsc.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc_params.compressed_bpp,
- pipe_config->dsc_params.slice_count);
+ pipe_config->dsc.compressed_bpp,
+ pipe_config->dsc.slice_count);
return 0;
}
@@ -2211,15 +2211,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
return ret;
}
- if (pipe_config->dsc_params.compression_enable) {
+ if (pipe_config->dsc.compression_enable) {
DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
- pipe_config->dsc_params.compressed_bpp);
+ pipe_config->dsc.compressed_bpp);
DRM_DEBUG_KMS("DP link rate required %i available %i\n",
intel_dp_link_required(adjusted_mode->crtc_clock,
- pipe_config->dsc_params.compressed_bpp),
+ pipe_config->dsc.compressed_bpp),
intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count));
} else {
@@ -2377,8 +2377,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->limited_color_range =
intel_dp_limited_color_range(pipe_config, conn_state);
- if (pipe_config->dsc_params.compression_enable)
- output_bpp = pipe_config->dsc_params.compressed_bpp;
+ if (pipe_config->dsc.compression_enable)
+ output_bpp = pipe_config->dsc.compressed_bpp;
else
output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
@@ -3102,7 +3102,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
{
int ret;
- if (!crtc_state->dsc_params.compression_enable)
+ if (!crtc_state->dsc.compression_enable)
return;
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 50f22abcd30e..dfbedff98ea8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -76,7 +76,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
/* Cannot enable DSC and PSR2 simultaneously */
- WARN_ON(crtc_state->dsc_params.compression_enable &&
+ WARN_ON(crtc_state->dsc.compression_enable &&
crtc_state->has_psr2);
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
@@ -623,7 +623,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
* resolution requires DSC to be enabled, priority is given to DSC
* over PSR2.
*/
- if (crtc_state->dsc_params.compression_enable) {
+ if (crtc_state->dsc.compression_enable) {
DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d4fb7f16f9f6..f41a9336476b 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -323,7 +323,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
{
struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
- u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
+ u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
u8 i = 0;
int row_index = 0;
int column_index = 0;
@@ -332,7 +332,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
- pipe_config->dsc_params.slice_count);
+ pipe_config->dsc.slice_count);
/*
* Slice Height of 8 works for all currently available panels. So start
* with that if pic_height is an integral multiple of 8.
@@ -491,7 +491,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
u32 pps_val = 0;
u32 rc_buf_thresh_dword[4];
u32 rc_range_params_dword[8];
- u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
int i = 0;
/* Populate PICTURE_PARAMETER_SET_0 registers */
@@ -514,11 +514,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
pps_val);
}
@@ -533,11 +533,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
pps_val);
}
@@ -553,11 +553,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
pps_val);
}
@@ -573,11 +573,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
pps_val);
}
@@ -593,11 +593,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
pps_val);
}
@@ -613,11 +613,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
pps_val);
}
@@ -635,11 +635,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
pps_val);
}
@@ -655,11 +655,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
pps_val);
}
@@ -675,11 +675,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
pps_val);
}
@@ -695,11 +695,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
pps_val);
}
@@ -717,11 +717,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
pps_val);
}
@@ -740,11 +740,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
* If 2 VDSC instances are needed, configure PPS for second
* VDSC
*/
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
} else {
I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
- if (crtc_state->dsc_params.dsc_split)
+ if (crtc_state->dsc.dsc_split)
I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
pps_val);
}
@@ -763,7 +763,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
- if (crtc_state->dsc_params.dsc_split) {
+ if (crtc_state->dsc.dsc_split) {
I915_WRITE(DSCC_RC_BUF_THRESH_0,
rc_buf_thresh_dword[0]);
I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
@@ -782,7 +782,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
rc_buf_thresh_dword[2]);
I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
rc_buf_thresh_dword[3]);
- if (crtc_state->dsc_params.dsc_split) {
+ if (crtc_state->dsc.dsc_split) {
I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
rc_buf_thresh_dword[0]);
I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
@@ -824,7 +824,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
rc_range_params_dword[6]);
I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
rc_range_params_dword[7]);
- if (crtc_state->dsc_params.dsc_split) {
+ if (crtc_state->dsc.dsc_split) {
I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
rc_range_params_dword[0]);
I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
@@ -859,7 +859,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
rc_range_params_dword[6]);
I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
rc_range_params_dword[7]);
- if (crtc_state->dsc_params.dsc_split) {
+ if (crtc_state->dsc.dsc_split) {
I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
rc_range_params_dword[0]);
I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
@@ -909,7 +909,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
u32 dss_ctl1_val = 0;
u32 dss_ctl2_val = 0;
- if (!crtc_state->dsc_params.compression_enable)
+ if (!crtc_state->dsc.compression_enable)
return;
/* Enable Power wells for VDSC/joining */
@@ -928,7 +928,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
}
dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
- if (crtc_state->dsc_params.dsc_split) {
+ if (crtc_state->dsc.dsc_split) {
dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
dss_ctl1_val |= JOINER_ENABLE;
}
@@ -944,7 +944,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
- if (!old_crtc_state->dsc_params.compression_enable)
+ if (!old_crtc_state->dsc.compression_enable)
return;
if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ada57eee914a..50f2a392f00e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4566,7 +4566,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
intel_dp = enc_to_intel_dp(&intel_attached_encoder(connector)->base);
crtc_state = to_intel_crtc_state(crtc->state);
seq_printf(m, "DSC_Enabled: %s\n",
- yesno(crtc_state->dsc_params.compression_enable));
+ yesno(crtc_state->dsc.compression_enable));
seq_printf(m, "DSC_Sink_Support: %s\n",
yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
seq_printf(m, "Force_DSC_Enable: %s\n",
--
2.20.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config 2019-10-22 13:34 [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Jani Nikula @ 2019-10-22 13:34 ` Jani Nikula 2019-10-22 17:24 ` Manasi Navare 2019-10-22 17:23 ` [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Manasi Navare ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Jani Nikula @ 2019-10-22 13:34 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula DSC isn't DP specific, so remove the dp_ prefix from the crtc state member name. Also moving the member under the dsc sub-struct gives us enough context to allow shortening the name to just config. No functional changes. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index db66f9d623f8..bac40482a2aa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -986,8 +986,8 @@ struct intel_crtc_state { bool dsc_split; u16 compressed_bpp; u8 slice_count; + struct drm_dsc_config config; } dsc; - struct drm_dsc_config dp_dsc_cfg; /* Forward Error correction State */ bool fec_enable; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index f41a9336476b..896b0c334f5e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -322,7 +322,7 @@ static int get_column_index_for_rc_params(u8 bits_per_component) int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config) { - struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; + struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; u16 compressed_bpp = pipe_config->dsc.compressed_bpp; u8 i = 0; int row_index = 0; @@ -485,7 +485,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 pps_val = 0; @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config 2019-10-22 13:34 ` [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config Jani Nikula @ 2019-10-22 17:24 ` Manasi Navare 2019-10-23 13:33 ` [Intel-gfx] " Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Manasi Navare @ 2019-10-22 17:24 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Tue, Oct 22, 2019 at 04:34:14PM +0300, Jani Nikula wrote: > DSC isn't DP specific, so remove the dp_ prefix from the crtc state > member name. Also moving the member under the dsc sub-struct gives us > enough context to allow shortening the name to just config. No > functional changes. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Sounds good to me and I guess works better with expanding this code to other connectors Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index db66f9d623f8..bac40482a2aa 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -986,8 +986,8 @@ struct intel_crtc_state { > bool dsc_split; > u16 compressed_bpp; > u8 slice_count; > + struct drm_dsc_config config; > } dsc; > - struct drm_dsc_config dp_dsc_cfg; > > /* Forward Error correction State */ > bool fec_enable; > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index f41a9336476b..896b0c334f5e 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -322,7 +322,7 @@ static int get_column_index_for_rc_params(u8 bits_per_component) > int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > - struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > + struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; > u16 compressed_bpp = pipe_config->dsc.compressed_bpp; > u8 i = 0; > int row_index = 0; > @@ -485,7 +485,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; > + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > enum pipe pipe = crtc->pipe; > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > u32 pps_val = 0; > @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder, > { > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; > + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; > > /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config @ 2019-10-23 13:33 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2019-10-23 13:33 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Tue, 22 Oct 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Tue, Oct 22, 2019 at 04:34:14PM +0300, Jani Nikula wrote: >> DSC isn't DP specific, so remove the dp_ prefix from the crtc state >> member name. Also moving the member under the dsc sub-struct gives us >> enough context to allow shortening the name to just config. No >> functional changes. >> >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Sounds good to me and I guess works better with expanding this code > to other connectors > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Thanks for the review, pushed both. BR, Jani. > > Manasi > >> --- >> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 6 +++--- >> 2 files changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h >> index db66f9d623f8..bac40482a2aa 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >> @@ -986,8 +986,8 @@ struct intel_crtc_state { >> bool dsc_split; >> u16 compressed_bpp; >> u8 slice_count; >> + struct drm_dsc_config config; >> } dsc; >> - struct drm_dsc_config dp_dsc_cfg; >> >> /* Forward Error correction State */ >> bool fec_enable; >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index f41a9336476b..896b0c334f5e 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -322,7 +322,7 @@ static int get_column_index_for_rc_params(u8 bits_per_component) >> int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, >> struct intel_crtc_state *pipe_config) >> { >> - struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; >> + struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; >> u16 compressed_bpp = pipe_config->dsc.compressed_bpp; >> u8 i = 0; >> int row_index = 0; >> @@ -485,7 +485,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, >> { >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> enum pipe pipe = crtc->pipe; >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> u32 pps_val = 0; >> @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder, >> { >> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); >> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); >> - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; >> >> /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config @ 2019-10-23 13:33 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2019-10-23 13:33 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Tue, 22 Oct 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Tue, Oct 22, 2019 at 04:34:14PM +0300, Jani Nikula wrote: >> DSC isn't DP specific, so remove the dp_ prefix from the crtc state >> member name. Also moving the member under the dsc sub-struct gives us >> enough context to allow shortening the name to just config. No >> functional changes. >> >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Sounds good to me and I guess works better with expanding this code > to other connectors > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Thanks for the review, pushed both. BR, Jani. > > Manasi > >> --- >> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 6 +++--- >> 2 files changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h >> index db66f9d623f8..bac40482a2aa 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >> @@ -986,8 +986,8 @@ struct intel_crtc_state { >> bool dsc_split; >> u16 compressed_bpp; >> u8 slice_count; >> + struct drm_dsc_config config; >> } dsc; >> - struct drm_dsc_config dp_dsc_cfg; >> >> /* Forward Error correction State */ >> bool fec_enable; >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index f41a9336476b..896b0c334f5e 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -322,7 +322,7 @@ static int get_column_index_for_rc_params(u8 bits_per_component) >> int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, >> struct intel_crtc_state *pipe_config) >> { >> - struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; >> + struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; >> u16 compressed_bpp = pipe_config->dsc.compressed_bpp; >> u8 i = 0; >> int row_index = 0; >> @@ -485,7 +485,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, >> { >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> enum pipe pipe = crtc->pipe; >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> u32 pps_val = 0; >> @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder, >> { >> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); >> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); >> - const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; >> >> /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc 2019-10-22 13:34 [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Jani Nikula 2019-10-22 13:34 ` [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config Jani Nikula @ 2019-10-22 17:23 ` Manasi Navare 2019-10-22 21:04 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Manasi Navare @ 2019-10-22 17:23 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Tue, Oct 22, 2019 at 04:34:13PM +0300, Jani Nikula wrote: > Reduce verbosity in code by renaming dsc_params member of crtc state to > simply dsc. There is enough context for this to be clear. No functional > changes. Makes sense to just call it dsc Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > .../drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++----- > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 68 +++++++++---------- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > 6 files changed, 55 insertions(+), 55 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 9ba794cb9b4f..1a49266f4f57 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2234,7 +2234,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, > /* > * VDSC power is needed when DSC is enabled > */ > - if (crtc_state->dsc_params.compression_enable) > + if (crtc_state->dsc.compression_enable) > intel_display_power_get(dev_priv, > intel_dsc_power_domain(crtc_state)); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8358152e403e..db66f9d623f8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -986,7 +986,7 @@ struct intel_crtc_state { > bool dsc_split; > u16 compressed_bpp; > u8 slice_count; > - } dsc_params; > + } dsc; > struct drm_dsc_config dp_dsc_cfg; > > /* Forward Error correction State */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 5eeafa45831a..521ce23f38ac 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2080,10 +2080,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > pipe_config->lane_count = limits->max_lane_count; > > if (intel_dp_is_edp(intel_dp)) { > - pipe_config->dsc_params.compressed_bpp = > + pipe_config->dsc.compressed_bpp = > min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, > pipe_config->pipe_bpp); > - pipe_config->dsc_params.slice_count = > + pipe_config->dsc.slice_count = > drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, > true); > } else { > @@ -2104,10 +2104,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); > return -EINVAL; > } > - pipe_config->dsc_params.compressed_bpp = min_t(u16, > + pipe_config->dsc.compressed_bpp = min_t(u16, > dsc_max_output_bpp >> 4, > pipe_config->pipe_bpp); > - pipe_config->dsc_params.slice_count = dsc_dp_slice_count; > + pipe_config->dsc.slice_count = dsc_dp_slice_count; > } > /* > * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate > @@ -2115,8 +2115,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > * then we need to use 2 VDSC instances. > */ > if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { > - if (pipe_config->dsc_params.slice_count > 1) { > - pipe_config->dsc_params.dsc_split = true; > + if (pipe_config->dsc.slice_count > 1) { > + pipe_config->dsc.dsc_split = true; > } else { > DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); > return -EINVAL; > @@ -2128,16 +2128,16 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " > "Compressed BPP = %d\n", > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp); > + pipe_config->dsc.compressed_bpp); > return ret; > } > > - pipe_config->dsc_params.compression_enable = true; > + pipe_config->dsc.compression_enable = true; > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > "Compressed Bpp = %d Slice Count = %d\n", > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp, > - pipe_config->dsc_params.slice_count); > + pipe_config->dsc.compressed_bpp, > + pipe_config->dsc.slice_count); > > return 0; > } > @@ -2211,15 +2211,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, > return ret; > } > > - if (pipe_config->dsc_params.compression_enable) { > + if (pipe_config->dsc.compression_enable) { > DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", > pipe_config->lane_count, pipe_config->port_clock, > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp); > + pipe_config->dsc.compressed_bpp); > > DRM_DEBUG_KMS("DP link rate required %i available %i\n", > intel_dp_link_required(adjusted_mode->crtc_clock, > - pipe_config->dsc_params.compressed_bpp), > + pipe_config->dsc.compressed_bpp), > intel_dp_max_data_rate(pipe_config->port_clock, > pipe_config->lane_count)); > } else { > @@ -2377,8 +2377,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, > pipe_config->limited_color_range = > intel_dp_limited_color_range(pipe_config, conn_state); > > - if (pipe_config->dsc_params.compression_enable) > - output_bpp = pipe_config->dsc_params.compressed_bpp; > + if (pipe_config->dsc.compression_enable) > + output_bpp = pipe_config->dsc.compressed_bpp; > else > output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); > > @@ -3102,7 +3102,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, > { > int ret; > > - if (!crtc_state->dsc_params.compression_enable) > + if (!crtc_state->dsc.compression_enable) > return; > > ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 50f22abcd30e..dfbedff98ea8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -76,7 +76,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, > const struct intel_crtc_state *crtc_state) > { > /* Cannot enable DSC and PSR2 simultaneously */ > - WARN_ON(crtc_state->dsc_params.compression_enable && > + WARN_ON(crtc_state->dsc.compression_enable && > crtc_state->has_psr2); > > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { > @@ -623,7 +623,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > * resolution requires DSC to be enabled, priority is given to DSC > * over PSR2. > */ > - if (crtc_state->dsc_params.compression_enable) { > + if (crtc_state->dsc.compression_enable) { > DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > return false; > } > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index d4fb7f16f9f6..f41a9336476b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -323,7 +323,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > - u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > + u16 compressed_bpp = pipe_config->dsc.compressed_bpp; > u8 i = 0; > int row_index = 0; > int column_index = 0; > @@ -332,7 +332,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > - pipe_config->dsc_params.slice_count); > + pipe_config->dsc.slice_count); > /* > * Slice Height of 8 works for all currently available panels. So start > * with that if pic_height is an integral multiple of 8. > @@ -491,7 +491,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > u32 pps_val = 0; > u32 rc_buf_thresh_dword[4]; > u32 rc_range_params_dword[8]; > - u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; > + u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; > int i = 0; > > /* Populate PICTURE_PARAMETER_SET_0 registers */ > @@ -514,11 +514,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), > pps_val); > } > @@ -533,11 +533,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), > pps_val); > } > @@ -553,11 +553,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), > pps_val); > } > @@ -573,11 +573,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), > pps_val); > } > @@ -593,11 +593,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), > pps_val); > } > @@ -613,11 +613,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), > pps_val); > } > @@ -635,11 +635,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), > pps_val); > } > @@ -655,11 +655,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), > pps_val); > } > @@ -675,11 +675,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), > pps_val); > } > @@ -695,11 +695,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), > pps_val); > } > @@ -717,11 +717,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), > pps_val); > } > @@ -740,11 +740,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), > pps_val); > } > @@ -763,7 +763,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); > I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); > I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(DSCC_RC_BUF_THRESH_0, > rc_buf_thresh_dword[0]); > I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, > @@ -782,7 +782,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > rc_buf_thresh_dword[2]); > I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), > rc_buf_thresh_dword[3]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), > rc_buf_thresh_dword[0]); > I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), > @@ -824,7 +824,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > rc_range_params_dword[6]); > I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, > rc_range_params_dword[7]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, > rc_range_params_dword[0]); > I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, > @@ -859,7 +859,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > rc_range_params_dword[6]); > I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), > rc_range_params_dword[7]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), > rc_range_params_dword[0]); > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), > @@ -909,7 +909,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > u32 dss_ctl1_val = 0; > u32 dss_ctl2_val = 0; > > - if (!crtc_state->dsc_params.compression_enable) > + if (!crtc_state->dsc.compression_enable) > return; > > /* Enable Power wells for VDSC/joining */ > @@ -928,7 +928,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); > } > dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; > dss_ctl1_val |= JOINER_ENABLE; > } > @@ -944,7 +944,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) > i915_reg_t dss_ctl1_reg, dss_ctl2_reg; > u32 dss_ctl1_val = 0, dss_ctl2_val = 0; > > - if (!old_crtc_state->dsc_params.compression_enable) > + if (!old_crtc_state->dsc.compression_enable) > return; > > if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index ada57eee914a..50f2a392f00e 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4566,7 +4566,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > intel_dp = enc_to_intel_dp(&intel_attached_encoder(connector)->base); > crtc_state = to_intel_crtc_state(crtc->state); > seq_printf(m, "DSC_Enabled: %s\n", > - yesno(crtc_state->dsc_params.compression_enable)); > + yesno(crtc_state->dsc.compression_enable)); > seq_printf(m, "DSC_Sink_Support: %s\n", > yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); > seq_printf(m, "Force_DSC_Enable: %s\n", > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc 2019-10-22 13:34 [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Jani Nikula 2019-10-22 13:34 ` [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config Jani Nikula 2019-10-22 17:23 ` [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Manasi Navare @ 2019-10-22 21:04 ` Patchwork 2019-10-22 21:45 ` ✓ Fi.CI.BAT: success " Patchwork 2019-10-23 13:16 ` [Intel-gfx] " Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-10-22 21:04 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc URL : https://patchwork.freedesktop.org/series/68394/ State : warning == Summary == $ dim checkpatch origin/drm-tip 884c1ae47848 drm/i915/dsc: rename crtc state dsc_params member to dsc -:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #63: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2108: + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_output_bpp >> 4, total: 0 errors, 0 warnings, 1 checks, 366 lines checked 6c8178f6862e drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc 2019-10-22 13:34 [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Jani Nikula ` (2 preceding siblings ...) 2019-10-22 21:04 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork @ 2019-10-22 21:45 ` Patchwork 2019-10-23 13:16 ` [Intel-gfx] " Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-10-22 21:45 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc URL : https://patchwork.freedesktop.org/series/68394/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155 -> Patchwork_14926 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_14926: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live_gem: - {fi-tgl-u2}: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-tgl-u2/igt@i915_selftest@live_gem.html - {fi-tgl-u}: NOTRUN -> [INCOMPLETE][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-tgl-u/igt@i915_selftest@live_gem.html * {igt@i915_selftest@live_gt_heartbeat}: - fi-whl-u: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html Known issues ------------ Here are the changes found in Patchwork_14926 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_mmap_gtt@basic-small-bo-tiledx: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html #### Possible fixes #### * igt@gem_flink_basic@basic: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724] / [fdo#112052 ]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@gem_flink_basic@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-icl-u3/igt@gem_flink_basic@basic.html * igt@gem_sync@basic-many-each: - {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u/igt@gem_sync@basic-many-each.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-tgl-u/igt@gem_sync@basic-many-each.html * igt@i915_selftest@live_requests: - {fi-tgl-u2}: [INCOMPLETE][13] ([fdo#112057]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-tgl-u2/igt@i915_selftest@live_requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-tgl-u2/igt@i915_selftest@live_requests.html * igt@vgem_basic@setversion: - fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/fi-icl-u3/igt@vgem_basic@setversion.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/fi-icl-u3/igt@vgem_basic@setversion.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880 [fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052 [fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057 [fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096 Participating hosts (52 -> 37) ------------------------------ Additional (1): fi-bxt-dsi Missing (16): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-apl-guc fi-snb-2520m fi-byt-clapper fi-gdg-551 fi-pnv-d510 fi-icl-y fi-bdw-samus fi-icl-dsi fi-skl-6700k2 Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7155 -> Patchwork_14926 CI-20190529: 20190529 CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14926: 6c8178f6862ec3b579006486819cbc225481f21e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6c8178f6862e drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config 884c1ae47848 drm/i915/dsc: rename crtc state dsc_params member to dsc == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc @ 2019-10-23 13:16 ` Patchwork 0 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-10-23 13:16 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc URL : https://patchwork.freedesktop.org/series/68394/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14926_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_14926_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-s3: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolation@vcs1-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_ctx_isolation@vcs1-s3.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#112037]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl6/igt@gem_workarounds@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl6/igt@gem_workarounds@suspend-resume.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103665]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106107]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl7/igt@kms_color@pipe-b-ctm-0-5.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_flip@flip-vs-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw6/igt@kms_flip@flip-vs-suspend.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#100368]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +7 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([fdo#111747]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl1/igt@perf@gen8-unprivileged-single-ctx-counters.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl10/igt@perf@gen8-unprivileged-single-ctx-counters.html * igt@perf_pmu@busy-no-semaphores-vcs1: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#112080]) +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@perf_pmu@busy-no-semaphores-vcs1.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: [SKIP][35] ([fdo#109276] / [fdo#112080]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_ctx_isolation@vcs1-reset.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_ctx_isolation@vcs1-reset.html * igt@gem_ctx_isolation@vecs0-s3: - shard-kbl: [INCOMPLETE][37] ([fdo#103665]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_ctx_isolation@vecs0-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-kbl7/igt@gem_ctx_isolation@vecs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [SKIP][39] ([fdo#110841]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][41] ([fdo#110854]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_exec_balancer@smoke.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [SKIP][43] ([fdo#112080]) -> [PASS][44] +14 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][45] ([fdo#111325]) -> [PASS][46] +4 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw2/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-snb: [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-apl: [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl3/igt@gem_userptr_blits@unsync-unmap-cycles.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl4/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][53] ([fdo#108566]) -> [PASS][54] +5 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl2/igt@gem_workarounds@suspend-resume-context.html * {igt@i915_pm_dc@dc6-dpms}: - shard-iclb: [FAIL][55] ([fdo#110548]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html * igt@kms_flip@dpms-vs-vblank-race: - shard-glk: [FAIL][61] ([fdo#111609]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@kms_flip@dpms-vs-vblank-race.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk3/igt@kms_flip@dpms-vs-vblank-race.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [FAIL][63] ([fdo#105363]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [FAIL][65] ([fdo#103167]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-tilingchange.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - {shard-tglb}: [FAIL][67] ([fdo#103167]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-suspend: - {shard-tglb}: [INCOMPLETE][69] ([fdo#111832] / [fdo#111850]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb4/igt@kms_frontbuffer_tracking@psr-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb4/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][71] ([fdo#108145] / [fdo#110403]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_setmode@basic: - shard-hsw: [FAIL][75] ([fdo#99912]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@kms_setmode@basic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw1/igt@kms_setmode@basic.html * igt@perf@short-reads: - shard-glk: [TIMEOUT][77] ([fdo#103183]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk9/igt@perf@short-reads.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk9/igt@perf@short-reads.html * igt@perf_pmu@busy-start-vecs0: - {shard-tglb}: [INCOMPLETE][79] ([fdo#111747]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@perf_pmu@busy-start-vecs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb1/igt@perf_pmu@busy-start-vecs0.html * igt@prime_busy@hang-bsd2: - shard-iclb: [SKIP][81] ([fdo#109276]) -> [PASS][82] +14 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@prime_busy@hang-bsd2.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@prime_busy@hang-bsd2.html #### Warnings #### * igt@gem_mocs_settings@mocs-rc6-bsd2: - shard-iclb: [SKIP][83] ([fdo#109276]) -> [FAIL][84] ([fdo#111330]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@gem_mocs_settings@mocs-rc6-bsd2.html * igt@gem_mocs_settings@mocs-settings-bsd2: - shard-iclb: [FAIL][85] ([fdo#111330]) -> [SKIP][86] ([fdo#109276]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][87] ([fdo#109349]) -> [DMESG-WARN][88] ([fdo#107724]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548 [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330 [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609 [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747 [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832 [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-skl-6260u Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7155 -> Patchwork_14926 CI-20190529: 20190529 CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14926: 6c8178f6862ec3b579006486819cbc225481f21e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc @ 2019-10-23 13:16 ` Patchwork 0 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-10-23 13:16 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc URL : https://patchwork.freedesktop.org/series/68394/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14926_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_14926_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-s3: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolation@vcs1-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_ctx_isolation@vcs1-s3.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#112037]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl6/igt@gem_workarounds@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl6/igt@gem_workarounds@suspend-resume.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103665]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106107]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl7/igt@kms_color@pipe-b-ctm-0-5.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_flip@flip-vs-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw6/igt@kms_flip@flip-vs-suspend.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#100368]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +7 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([fdo#111747]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl1/igt@perf@gen8-unprivileged-single-ctx-counters.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl10/igt@perf@gen8-unprivileged-single-ctx-counters.html * igt@perf_pmu@busy-no-semaphores-vcs1: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#112080]) +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@perf_pmu@busy-no-semaphores-vcs1.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: [SKIP][35] ([fdo#109276] / [fdo#112080]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_ctx_isolation@vcs1-reset.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_ctx_isolation@vcs1-reset.html * igt@gem_ctx_isolation@vecs0-s3: - shard-kbl: [INCOMPLETE][37] ([fdo#103665]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_ctx_isolation@vecs0-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-kbl7/igt@gem_ctx_isolation@vecs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [SKIP][39] ([fdo#110841]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][41] ([fdo#110854]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_exec_balancer@smoke.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@gem_exec_balancer@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [SKIP][43] ([fdo#112080]) -> [PASS][44] +14 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][45] ([fdo#111325]) -> [PASS][46] +4 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw2/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-snb: [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-apl: [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl3/igt@gem_userptr_blits@unsync-unmap-cycles.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl4/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][53] ([fdo#108566]) -> [PASS][54] +5 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl2/igt@gem_workarounds@suspend-resume-context.html * {igt@i915_pm_dc@dc6-dpms}: - shard-iclb: [FAIL][55] ([fdo#110548]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html * igt@kms_flip@dpms-vs-vblank-race: - shard-glk: [FAIL][61] ([fdo#111609]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@kms_flip@dpms-vs-vblank-race.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk3/igt@kms_flip@dpms-vs-vblank-race.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [FAIL][63] ([fdo#105363]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [FAIL][65] ([fdo#103167]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-tilingchange.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - {shard-tglb}: [FAIL][67] ([fdo#103167]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-suspend: - {shard-tglb}: [INCOMPLETE][69] ([fdo#111832] / [fdo#111850]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb4/igt@kms_frontbuffer_tracking@psr-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb4/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][71] ([fdo#108145] / [fdo#110403]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_setmode@basic: - shard-hsw: [FAIL][75] ([fdo#99912]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@kms_setmode@basic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw1/igt@kms_setmode@basic.html * igt@perf@short-reads: - shard-glk: [TIMEOUT][77] ([fdo#103183]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk9/igt@perf@short-reads.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-glk9/igt@perf@short-reads.html * igt@perf_pmu@busy-start-vecs0: - {shard-tglb}: [INCOMPLETE][79] ([fdo#111747]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@perf_pmu@busy-start-vecs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-tglb1/igt@perf_pmu@busy-start-vecs0.html * igt@prime_busy@hang-bsd2: - shard-iclb: [SKIP][81] ([fdo#109276]) -> [PASS][82] +14 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@prime_busy@hang-bsd2.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@prime_busy@hang-bsd2.html #### Warnings #### * igt@gem_mocs_settings@mocs-rc6-bsd2: - shard-iclb: [SKIP][83] ([fdo#109276]) -> [FAIL][84] ([fdo#111330]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb1/igt@gem_mocs_settings@mocs-rc6-bsd2.html * igt@gem_mocs_settings@mocs-settings-bsd2: - shard-iclb: [FAIL][85] ([fdo#111330]) -> [SKIP][86] ([fdo#109276]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][87] ([fdo#109349]) -> [DMESG-WARN][88] ([fdo#107724]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548 [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330 [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609 [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747 [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832 [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-skl-6260u Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7155 -> Patchwork_14926 CI-20190529: 20190529 CI_DRM_7155: 87aff128f9bafd90854e4691c3afcdf7a0e61ce2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14926: 6c8178f6862ec3b579006486819cbc225481f21e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-10-23 13:33 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-22 13:34 [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Jani Nikula 2019-10-22 13:34 ` [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config Jani Nikula 2019-10-22 17:24 ` Manasi Navare 2019-10-23 13:33 ` Jani Nikula 2019-10-23 13:33 ` [Intel-gfx] " Jani Nikula 2019-10-22 17:23 ` [PATCH 1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc Manasi Navare 2019-10-22 21:04 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork 2019-10-22 21:45 ` ✓ Fi.CI.BAT: success " Patchwork 2019-10-23 13:16 ` ✓ Fi.CI.IGT: " Patchwork 2019-10-23 13:16 ` [Intel-gfx] " Patchwork
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