From: Florian Fainelli <f.fainelli@gmail.com> To: linux-kernel@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2835 ARM ARCHITECTURE), Souvik Chakravarty <Souvik.Chakravarty@arm.com>, Jim Quinlan <james.quinlan@broadcom.com>, Sudeep Holla <Sudeep.Holla@arm.com>, Thanu Rangarajan <Thanu.Rangarajan@arm.com> Subject: [PATCH RFC 2/2] irqchip/gic: Allow the use of SGI interrupts Date: Tue, 22 Oct 2019 17:05:47 -0700 [thread overview] Message-ID: <20191023000547.7831-3-f.fainelli@gmail.com> (raw) In-Reply-To: <20191023000547.7831-1-f.fainelli@gmail.com> SGI interrupts are a convenient way for trusted firmware to target a specific set of CPUs. Update the ARM GIC code to allow the translation and mapping of SGI interrupts. Since the kernel already uses SGIs for various inter-processor interrupt activities, we specifically make sure that we do not let users of the IRQ API to even try to map those. Internal IPIs remain dispatched through handle_IPI() while public SGIs get promoted to a normal interrupt flow management. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/irqchip/irq-gic.c | 41 +++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 30ab623343d3..dcfdbaacdd64 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -385,7 +385,10 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) * Pairs with the write barrier in gic_raise_softirq */ smp_rmb(); - handle_IPI(irqnr, regs); + if (irqnr < NR_IPI) + handle_IPI(irqnr, regs); + else + handle_domain_irq(gic->domain, irqnr, regs); #endif continue; } @@ -1005,20 +1008,34 @@ static int gic_irq_domain_translate(struct irq_domain *d, if (fwspec->param_count < 3) return -EINVAL; - /* Get the interrupt number and add 16 to skip over SGIs */ - *hwirq = fwspec->param[1] + 16; - - /* - * For SPIs, we need to add 16 more to get the GIC irq - * ID number - */ - if (!fwspec->param[0]) + *hwirq = fwspec->param[1]; + switch (fwspec->param[0]) { + case 0: + /* + * For SPIs, we need to add 16 more to get the GIC irq + * ID number + */ + *hwirq += 16; + /* fall through */ + case 1: + /* Add 16 to skip over SGIs */ *hwirq += 16; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + /* Make it clear that broken DTs are... broken */ + WARN_ON(*type == IRQ_TYPE_NONE); + break; + case 2: + /* Refuse to map internal IPIs */ + if (*hwirq < NR_IPI) + return -EPERM; + + *type = IRQ_TYPE_NONE; + break; + default: + break; + } - /* Make it clear that broken DTs are... broken */ - WARN_ON(*type == IRQ_TYPE_NONE); return 0; } -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com> To: linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Thanu Rangarajan <Thanu.Rangarajan@arm.com>, Florian Fainelli <f.fainelli@gmail.com>, Souvik Chakravarty <Souvik.Chakravarty@arm.com>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, "maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE..." <bcm-kernel-feedback-list@broadcom.com>, Jim Quinlan <james.quinlan@broadcom.com>, Sudeep Holla <Sudeep.Holla@arm.com>, Thomas Gleixner <tglx@linutronix.de>, "moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org> Subject: [PATCH RFC 2/2] irqchip/gic: Allow the use of SGI interrupts Date: Tue, 22 Oct 2019 17:05:47 -0700 [thread overview] Message-ID: <20191023000547.7831-3-f.fainelli@gmail.com> (raw) In-Reply-To: <20191023000547.7831-1-f.fainelli@gmail.com> SGI interrupts are a convenient way for trusted firmware to target a specific set of CPUs. Update the ARM GIC code to allow the translation and mapping of SGI interrupts. Since the kernel already uses SGIs for various inter-processor interrupt activities, we specifically make sure that we do not let users of the IRQ API to even try to map those. Internal IPIs remain dispatched through handle_IPI() while public SGIs get promoted to a normal interrupt flow management. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/irqchip/irq-gic.c | 41 +++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 30ab623343d3..dcfdbaacdd64 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -385,7 +385,10 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) * Pairs with the write barrier in gic_raise_softirq */ smp_rmb(); - handle_IPI(irqnr, regs); + if (irqnr < NR_IPI) + handle_IPI(irqnr, regs); + else + handle_domain_irq(gic->domain, irqnr, regs); #endif continue; } @@ -1005,20 +1008,34 @@ static int gic_irq_domain_translate(struct irq_domain *d, if (fwspec->param_count < 3) return -EINVAL; - /* Get the interrupt number and add 16 to skip over SGIs */ - *hwirq = fwspec->param[1] + 16; - - /* - * For SPIs, we need to add 16 more to get the GIC irq - * ID number - */ - if (!fwspec->param[0]) + *hwirq = fwspec->param[1]; + switch (fwspec->param[0]) { + case 0: + /* + * For SPIs, we need to add 16 more to get the GIC irq + * ID number + */ + *hwirq += 16; + /* fall through */ + case 1: + /* Add 16 to skip over SGIs */ *hwirq += 16; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + /* Make it clear that broken DTs are... broken */ + WARN_ON(*type == IRQ_TYPE_NONE); + break; + case 2: + /* Refuse to map internal IPIs */ + if (*hwirq < NR_IPI) + return -EPERM; + + *type = IRQ_TYPE_NONE; + break; + default: + break; + } - /* Make it clear that broken DTs are... broken */ - WARN_ON(*type == IRQ_TYPE_NONE); return 0; } -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-23 0:06 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-23 0:05 [PATCH RFC 0/2] irqchip/gic: Allow the use of SGI interrupts Florian Fainelli 2019-10-23 0:05 ` Florian Fainelli 2019-10-23 0:05 ` [PATCH RFC 1/2] dt-bindings: Define interrupt type for " Florian Fainelli 2019-10-23 0:05 ` Florian Fainelli 2019-10-23 0:05 ` Florian Fainelli [this message] 2019-10-23 0:05 ` [PATCH RFC 2/2] irqchip/gic: Allow the use of " Florian Fainelli 2019-10-23 13:22 ` Marc Zyngier 2019-10-23 13:22 ` Marc Zyngier 2019-10-23 17:02 ` Florian Fainelli 2019-10-23 17:02 ` Florian Fainelli 2019-10-24 8:27 ` Marc Zyngier 2019-10-24 8:27 ` Marc Zyngier
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