* [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
@ 2019-10-23 11:28 ` Colin King
0 siblings, 0 replies; 6+ messages in thread
From: Colin King @ 2019-10-23 11:28 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
linux-arm-kernel, linux-clk
Cc: kernel-janitors, linux-kernel
From: Colin Ian King <colin.king@canonical.com>
The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.
Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index dcac1391767f..ef29582676f6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -1224,7 +1224,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev)
/* Enforce d1 = 0, d2 = 0 for Audio PLL */
val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
- val &= (BIT(16) & BIT(18));
+ val &= ~(BIT(16) | BIT(18));
writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
@ 2019-10-23 11:28 ` Colin King
0 siblings, 0 replies; 6+ messages in thread
From: Colin King @ 2019-10-23 11:28 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
linux-arm-kernel, linux-clk
Cc: kernel-janitors, linux-kernel
From: Colin Ian King <colin.king@canonical.com>
The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.
Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index dcac1391767f..ef29582676f6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -1224,7 +1224,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev)
/* Enforce d1 = 0, d2 = 0 for Audio PLL */
val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
- val &= (BIT(16) & BIT(18));
+ val &= ~(BIT(16) | BIT(18));
writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
@ 2019-10-23 11:28 ` Colin King
0 siblings, 0 replies; 6+ messages in thread
From: Colin King @ 2019-10-23 11:28 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
linux-arm-kernel, linux-clk
Cc: kernel-janitors, linux-kernel
From: Colin Ian King <colin.king@canonical.com>
The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.
Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index dcac1391767f..ef29582676f6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -1224,7 +1224,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev)
/* Enforce d1 = 0, d2 = 0 for Audio PLL */
val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
- val &= (BIT(16) & BIT(18));
+ val &= ~(BIT(16) | BIT(18));
writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
--
2.20.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
2019-10-23 11:28 ` Colin King
(?)
@ 2019-10-29 7:43 ` Maxime Ripard
-1 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2019-10-29 7:43 UTC (permalink / raw)
To: Colin King
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, kernel-janitors, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 587 bytes --]
On Wed, Oct 23, 2019 at 12:28:09PM +0100, Colin King wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> The zero'ing of bits 16 and 18 is incorrect. Currently the code
> is masking with the bitwise-and of BIT(16) & BIT(18) which is
> 0, so the updated value for val is always zero. Fix this by bitwise
> and-ing value with the correct mask that will zero bits 16 and 18.
>
> Addresses-Coverity: (" Suspicious &= or |= constant expression")
> Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Applied, thanks!
Maxime
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
@ 2019-10-29 7:43 ` Maxime Ripard
0 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2019-10-29 7:43 UTC (permalink / raw)
To: Colin King
Cc: Stephen Boyd, Michael Turquette, kernel-janitors, linux-kernel,
Chen-Yu Tsai, linux-clk, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 587 bytes --]
On Wed, Oct 23, 2019 at 12:28:09PM +0100, Colin King wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> The zero'ing of bits 16 and 18 is incorrect. Currently the code
> is masking with the bitwise-and of BIT(16) & BIT(18) which is
> 0, so the updated value for val is always zero. Fix this by bitwise
> and-ing value with the correct mask that will zero bits 16 and 18.
>
> Addresses-Coverity: (" Suspicious &= or |= constant expression")
> Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Applied, thanks!
Maxime
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
@ 2019-10-29 7:43 ` Maxime Ripard
0 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2019-10-29 7:43 UTC (permalink / raw)
To: Colin King
Cc: Stephen Boyd, Michael Turquette, kernel-janitors, linux-kernel,
Chen-Yu Tsai, linux-clk, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 587 bytes --]
On Wed, Oct 23, 2019 at 12:28:09PM +0100, Colin King wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> The zero'ing of bits 16 and 18 is incorrect. Currently the code
> is masking with the bitwise-and of BIT(16) & BIT(18) which is
> 0, so the updated value for val is always zero. Fix this by bitwise
> and-ing value with the correct mask that will zero bits 16 and 18.
>
> Addresses-Coverity: (" Suspicious &= or |= constant expression")
> Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
Applied, thanks!
Maxime
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-29 7:48 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-23 11:28 [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18 Colin King
2019-10-23 11:28 ` Colin King
2019-10-23 11:28 ` Colin King
2019-10-29 7:43 ` Maxime Ripard
2019-10-29 7:43 ` Maxime Ripard
2019-10-29 7:43 ` Maxime Ripard
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