From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>
Cc: Anil Varughese <aniljoy@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v2 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
Date: Wed, 23 Oct 2019 18:27:31 +0530 [thread overview]
Message-ID: <20191023125735.4713-11-kishon@ti.com> (raw)
In-Reply-To: <20191023125735.4713-1-kishon@ti.com>
Sierra SERDES IP supports upto 16 lanes (though not all of it
will be enabled in a platform). Allow Sierra driver to support a
maximum of upto 16 lanes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 82f7617b2dac..dd54a0ab89b7 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -139,7 +139,7 @@
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID 0x00007364
-#define SIERRA_MAX_LANES 4
+#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100000
static const struct reg_field macro_id_type =
@@ -197,6 +197,7 @@ struct cdns_sierra_phy {
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct clk *clk;
int nsubnodes;
+ u32 num_lanes;
bool autoconf;
};
@@ -233,6 +234,18 @@ static struct regmap_config cdns_sierra_lane_cdb_config[] = {
SIERRA_LANE_CDB_REGMAP_CONF("1"),
SIERRA_LANE_CDB_REGMAP_CONF("2"),
SIERRA_LANE_CDB_REGMAP_CONF("3"),
+ SIERRA_LANE_CDB_REGMAP_CONF("4"),
+ SIERRA_LANE_CDB_REGMAP_CONF("5"),
+ SIERRA_LANE_CDB_REGMAP_CONF("6"),
+ SIERRA_LANE_CDB_REGMAP_CONF("7"),
+ SIERRA_LANE_CDB_REGMAP_CONF("8"),
+ SIERRA_LANE_CDB_REGMAP_CONF("9"),
+ SIERRA_LANE_CDB_REGMAP_CONF("10"),
+ SIERRA_LANE_CDB_REGMAP_CONF("11"),
+ SIERRA_LANE_CDB_REGMAP_CONF("12"),
+ SIERRA_LANE_CDB_REGMAP_CONF("13"),
+ SIERRA_LANE_CDB_REGMAP_CONF("14"),
+ SIERRA_LANE_CDB_REGMAP_CONF("15"),
};
static struct regmap_config cdns_sierra_common_cdb_config = {
@@ -546,6 +559,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
}
}
+ sp->num_lanes += sp->phys[node].num_lanes;
+
gphy = devm_phy_create(dev, child, &ops);
if (IS_ERR(gphy)) {
@@ -559,6 +574,11 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
}
sp->nsubnodes = node;
+ if (sp->num_lanes > SIERRA_MAX_LANES) {
+ dev_err(dev, "Invalid lane configuration\n");
+ goto put_child2;
+ }
+
/* If more than one subnode, configure the PHY as multilink */
if (!sp->autoconf && sp->nsubnodes > 1)
regmap_field_write(sp->phy_pll_cfg_1, 0x1);
--
2.17.1
next prev parent reply other threads:[~2019-10-23 12:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 12:57 [PATCH v2 00/14] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-10-29 18:59 ` Rob Herring
2019-10-30 5:36 ` Kishon Vijay Abraham I
2019-11-05 9:40 ` Anil Joy Varughese
2019-10-23 12:57 ` [PATCH v2 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 08/14] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-10-23 12:57 ` Kishon Vijay Abraham I [this message]
2019-10-23 12:57 ` [PATCH v2 11/14] phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-10-29 6:53 ` Kishon Vijay Abraham I
2019-10-29 19:08 ` Rob Herring
2019-10-30 5:45 ` Kishon Vijay Abraham I
2019-10-30 19:26 ` Rob Herring
2019-10-31 4:41 ` Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
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